arch/arm/mach-mx5/cpu.c

   1 /*
   2  * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
   3  *
   4  * The code contained herein is licensed under the GNU General Public
   5  * License. You may obtain a copy of the GNU General Public License
   6  * Version 2 or later at the following locations:
   7  *
   8  * http://www.opensource.org/licenses/gpl-license.html
   9  * http://www.gnu.org/copyleft/gpl.html
  10  *
  11  * This file contains the CPU initialization code.
  12  */
  13
  14 #include <linux/types.h>
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/module.h>
  18 #include <mach/hardware.h>
  19 #include <asm/io.h>
  20
  21 static int cpu_silicon_rev = -1;
  22
  23 #define SI_REV 0x48
  24
  25 static void query_silicon_parameter(void)
  26 {
  27         void __iomem *rom = ioremap(MX51_IROM_BASE_ADDR, MX51_IROM_SIZE);
  28         u32 rev;
  29
  30         if (!rom) {
  31                 cpu_silicon_rev = -EINVAL;
  32                 return;
  33         }
  34
  35         rev = readl(rom + SI_REV);
  36         switch (rev) {
  37         case 0x1:
  38                 cpu_silicon_rev = MX51_CHIP_REV_1_0;
  39                 break;
  40         case 0x2:
  41                 cpu_silicon_rev = MX51_CHIP_REV_1_1;
  42                 break;
  43         case 0x10:
  44                 cpu_silicon_rev = MX51_CHIP_REV_2_0;
  45                 break;
  46         case 0x20:
  47                 cpu_silicon_rev = MX51_CHIP_REV_3_0;
  48                 break;
  49         default:
  50                 cpu_silicon_rev = 0;
  51         }
  52
  53         iounmap(rom);
  54 }
  55
  56 /*
  57  * Returns:
  58  *      the silicon revision of the cpu
  59  *      -EINVAL - not a mx51
  60  */
  61 int mx51_revision(void)
  62 {
  63         if (!cpu_is_mx51())
  64                 return -EINVAL;
  65
  66         if (cpu_silicon_rev == -1)
  67                 query_silicon_parameter();
  68
  69         return cpu_silicon_rev;
  70 }
  71 EXPORT_SYMBOL(mx51_revision);
  72
  73 static int __init post_cpu_init(void)
  74 {
  75         unsigned int reg;
  76         void __iomem *base;
  77
  78         if (!cpu_is_mx51())
  79                 return 0;
  80
  81         base = MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR);
  82         __raw_writel(0x0, base + 0x40);
  83         __raw_writel(0x0, base + 0x44);
  84         __raw_writel(0x0, base + 0x48);
  85         __raw_writel(0x0, base + 0x4C);
  86         reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
  87         __raw_writel(reg, base + 0x50);
  88
  89         base = MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR);
  90         __raw_writel(0x0, base + 0x40);
  91         __raw_writel(0x0, base + 0x44);
  92         __raw_writel(0x0, base + 0x48);
  93         __raw_writel(0x0, base + 0x4C);
  94         reg = __raw_readl(base + 0x50) & 0x00FFFFFF;
  95         __raw_writel(reg, base + 0x50);
  96
  97         return 0;
  98 }
  99
 100 postcore_initcall(post_cpu_init);