2 * arch/powerpc/platforms/pseries/xics.c
4 * Copyright 2000 IBM Corporation.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
12 #include <linux/types.h>
13 #include <linux/threads.h>
14 #include <linux/kernel.h>
15 #include <linux/irq.h>
16 #include <linux/smp.h>
17 #include <linux/interrupt.h>
18 #include <linux/init.h>
19 #include <linux/radix-tree.h>
20 #include <linux/cpu.h>
21 #include <linux/msi.h>
24 #include <asm/firmware.h>
26 #include <asm/pgtable.h>
29 #include <asm/hvcall.h>
30 #include <asm/machdep.h>
33 #include "plpar_wrappers.h"
35 static struct irq_host
*xics_host
;
38 #define XICS_IRQ_SPURIOUS 0
40 /* Want a priority other than 0. Various HW issues require this. */
41 #define DEFAULT_PRIORITY 5
44 * Mark IPIs as higher priority so we can take them inside interrupts that
45 * arent marked IRQF_DISABLED
47 #define IPI_PRIORITY 4
49 static unsigned int default_server
= 0xFF;
50 static unsigned int default_distrib_server
= 0;
51 static unsigned int interrupt_server_size
= 8;
53 /* RTAS service tokens */
54 static int ibm_get_xive
;
55 static int ibm_set_xive
;
56 static int ibm_int_on
;
57 static int ibm_int_off
;
60 /* Direct hardware low level accessors */
62 /* The part of the interrupt presentation layer that we care about */
79 static struct xics_ipl __iomem
*xics_per_cpu
[NR_CPUS
];
81 static inline unsigned int direct_xirr_info_get(void)
83 int cpu
= smp_processor_id();
85 return in_be32(&xics_per_cpu
[cpu
]->xirr
.word
);
88 static inline void direct_xirr_info_set(unsigned int value
)
90 int cpu
= smp_processor_id();
92 out_be32(&xics_per_cpu
[cpu
]->xirr
.word
, value
);
95 static inline void direct_cppr_info(u8 value
)
97 int cpu
= smp_processor_id();
99 out_8(&xics_per_cpu
[cpu
]->xirr
.bytes
[0], value
);
102 static inline void direct_qirr_info(int n_cpu
, u8 value
)
104 out_8(&xics_per_cpu
[n_cpu
]->qirr
.bytes
[0], value
);
108 /* LPAR low level accessors */
110 static inline unsigned int lpar_xirr_info_get(void)
112 unsigned long lpar_rc
;
113 unsigned long return_value
;
115 lpar_rc
= plpar_xirr(&return_value
);
116 if (lpar_rc
!= H_SUCCESS
)
117 panic(" bad return code xirr - rc = %lx \n", lpar_rc
);
118 return (unsigned int)return_value
;
121 static inline void lpar_xirr_info_set(unsigned int value
)
123 unsigned long lpar_rc
;
125 lpar_rc
= plpar_eoi(value
);
126 if (lpar_rc
!= H_SUCCESS
)
127 panic("bad return code EOI - rc = %ld, value=%x\n", lpar_rc
,
131 static inline void lpar_cppr_info(u8 value
)
133 unsigned long lpar_rc
;
135 lpar_rc
= plpar_cppr(value
);
136 if (lpar_rc
!= H_SUCCESS
)
137 panic("bad return code cppr - rc = %lx\n", lpar_rc
);
140 static inline void lpar_qirr_info(int n_cpu
, u8 value
)
142 unsigned long lpar_rc
;
144 lpar_rc
= plpar_ipi(get_hard_smp_processor_id(n_cpu
), value
);
145 if (lpar_rc
!= H_SUCCESS
)
146 panic("bad return code qirr - rc = %lx\n", lpar_rc
);
150 /* Interface to generic irq subsystem */
153 static int get_irq_server(unsigned int virq
, unsigned int strict_check
)
156 /* For the moment only implement delivery to all cpus or one cpu */
158 cpumask_t tmp
= CPU_MASK_NONE
;
160 cpumask_copy(&cpumask
, irq_to_desc(virq
)->affinity
);
161 if (!distribute_irqs
)
162 return default_server
;
164 if (!cpus_equal(cpumask
, CPU_MASK_ALL
)) {
165 cpus_and(tmp
, cpu_online_map
, cpumask
);
167 server
= first_cpu(tmp
);
169 if (server
< NR_CPUS
)
170 return get_hard_smp_processor_id(server
);
176 if (cpus_equal(cpu_online_map
, cpu_present_map
))
177 return default_distrib_server
;
179 return default_server
;
182 static int get_irq_server(unsigned int virq
, unsigned int strict_check
)
184 return default_server
;
188 static void xics_unmask_irq(unsigned int virq
)
194 pr_devel("xics: unmask virq %d\n", virq
);
196 irq
= (unsigned int)irq_map
[virq
].hwirq
;
197 pr_devel(" -> map to hwirq 0x%x\n", irq
);
198 if (irq
== XICS_IPI
|| irq
== XICS_IRQ_SPURIOUS
)
201 server
= get_irq_server(virq
, 0);
203 call_status
= rtas_call(ibm_set_xive
, 3, 1, NULL
, irq
, server
,
205 if (call_status
!= 0) {
207 "%s: ibm_set_xive irq %u server %x returned %d\n",
208 __func__
, irq
, server
, call_status
);
212 /* Now unmask the interrupt (often a no-op) */
213 call_status
= rtas_call(ibm_int_on
, 1, 1, NULL
, irq
);
214 if (call_status
!= 0) {
215 printk(KERN_ERR
"%s: ibm_int_on irq=%u returned %d\n",
216 __func__
, irq
, call_status
);
221 static unsigned int xics_startup(unsigned int virq
)
224 * The generic MSI code returns with the interrupt disabled on the
225 * card, using the MSI mask bits. Firmware doesn't appear to unmask
226 * at that level, so we do it here by hand.
228 if (irq_to_desc(virq
)->msi_desc
)
229 unmask_msi_irq(virq
);
232 xics_unmask_irq(virq
);
236 static void xics_mask_real_irq(unsigned int irq
)
243 call_status
= rtas_call(ibm_int_off
, 1, 1, NULL
, irq
);
244 if (call_status
!= 0) {
245 printk(KERN_ERR
"%s: ibm_int_off irq=%u returned %d\n",
246 __func__
, irq
, call_status
);
250 /* Have to set XIVE to 0xff to be able to remove a slot */
251 call_status
= rtas_call(ibm_set_xive
, 3, 1, NULL
, irq
,
252 default_server
, 0xff);
253 if (call_status
!= 0) {
254 printk(KERN_ERR
"%s: ibm_set_xive(0xff) irq=%u returned %d\n",
255 __func__
, irq
, call_status
);
260 static void xics_mask_irq(unsigned int virq
)
264 pr_devel("xics: mask virq %d\n", virq
);
266 irq
= (unsigned int)irq_map
[virq
].hwirq
;
267 if (irq
== XICS_IPI
|| irq
== XICS_IRQ_SPURIOUS
)
269 xics_mask_real_irq(irq
);
272 static void xics_mask_unknown_vec(unsigned int vec
)
274 printk(KERN_ERR
"Interrupt %u (real) is invalid, disabling it.\n", vec
);
275 xics_mask_real_irq(vec
);
278 static inline unsigned int xics_xirr_vector(unsigned int xirr
)
281 * The top byte is the old cppr, to be restored on EOI.
282 * The remaining 24 bits are the vector.
284 return xirr
& 0x00ffffff;
287 static unsigned int xics_get_irq_direct(void)
289 unsigned int xirr
= direct_xirr_info_get();
290 unsigned int vec
= xics_xirr_vector(xirr
);
293 if (vec
== XICS_IRQ_SPURIOUS
)
296 irq
= irq_radix_revmap_lookup(xics_host
, vec
);
297 if (likely(irq
!= NO_IRQ
))
300 /* We don't have a linux mapping, so have rtas mask it. */
301 xics_mask_unknown_vec(vec
);
303 /* We might learn about it later, so EOI it */
304 direct_xirr_info_set(xirr
);
308 static unsigned int xics_get_irq_lpar(void)
310 unsigned int xirr
= lpar_xirr_info_get();
311 unsigned int vec
= xics_xirr_vector(xirr
);
314 if (vec
== XICS_IRQ_SPURIOUS
)
317 irq
= irq_radix_revmap_lookup(xics_host
, vec
);
318 if (likely(irq
!= NO_IRQ
))
321 /* We don't have a linux mapping, so have RTAS mask it. */
322 xics_mask_unknown_vec(vec
);
324 /* We might learn about it later, so EOI it */
325 lpar_xirr_info_set(xirr
);
329 static void xics_eoi_direct(unsigned int virq
)
331 unsigned int irq
= (unsigned int)irq_map
[virq
].hwirq
;
334 direct_xirr_info_set((0xff << 24) | irq
);
337 static void xics_eoi_lpar(unsigned int virq
)
339 unsigned int irq
= (unsigned int)irq_map
[virq
].hwirq
;
342 lpar_xirr_info_set((0xff << 24) | irq
);
345 static int xics_set_affinity(unsigned int virq
, const struct cpumask
*cpumask
)
352 irq
= (unsigned int)irq_map
[virq
].hwirq
;
353 if (irq
== XICS_IPI
|| irq
== XICS_IRQ_SPURIOUS
)
356 status
= rtas_call(ibm_get_xive
, 1, 3, xics_status
, irq
);
359 printk(KERN_ERR
"%s: ibm,get-xive irq=%u returns %d\n",
360 __func__
, irq
, status
);
365 * For the moment only implement delivery to all cpus or one cpu.
366 * Get current irq_server for the given irq
368 irq_server
= get_irq_server(virq
, 1);
369 if (irq_server
== -1) {
371 cpumask_scnprintf(cpulist
, sizeof(cpulist
), cpumask
);
373 "%s: No online cpus in the mask %s for irq %d\n",
374 __func__
, cpulist
, virq
);
378 status
= rtas_call(ibm_set_xive
, 3, 1, NULL
,
379 irq
, irq_server
, xics_status
[1]);
382 printk(KERN_ERR
"%s: ibm,set-xive irq=%u returns %d\n",
383 __func__
, irq
, status
);
390 static struct irq_chip xics_pic_direct
= {
392 .startup
= xics_startup
,
393 .mask
= xics_mask_irq
,
394 .unmask
= xics_unmask_irq
,
395 .eoi
= xics_eoi_direct
,
396 .set_affinity
= xics_set_affinity
399 static struct irq_chip xics_pic_lpar
= {
401 .startup
= xics_startup
,
402 .mask
= xics_mask_irq
,
403 .unmask
= xics_unmask_irq
,
404 .eoi
= xics_eoi_lpar
,
405 .set_affinity
= xics_set_affinity
409 /* Interface to arch irq controller subsystem layer */
411 /* Points to the irq_chip we're actually using */
412 static struct irq_chip
*xics_irq_chip
;
414 static int xics_host_match(struct irq_host
*h
, struct device_node
*node
)
416 /* IBM machines have interrupt parents of various funky types for things
417 * like vdevices, events, etc... The trick we use here is to match
418 * everything here except the legacy 8259 which is compatible "chrp,iic"
420 return !of_device_is_compatible(node
, "chrp,iic");
423 static int xics_host_map(struct irq_host
*h
, unsigned int virq
,
426 pr_devel("xics: map virq %d, hwirq 0x%lx\n", virq
, hw
);
428 /* Insert the interrupt mapping into the radix tree for fast lookup */
429 irq_radix_revmap_insert(xics_host
, virq
, hw
);
431 irq_to_desc(virq
)->status
|= IRQ_LEVEL
;
432 set_irq_chip_and_handler(virq
, xics_irq_chip
, handle_fasteoi_irq
);
436 static int xics_host_xlate(struct irq_host
*h
, struct device_node
*ct
,
437 const u32
*intspec
, unsigned int intsize
,
438 irq_hw_number_t
*out_hwirq
, unsigned int *out_flags
)
441 /* Current xics implementation translates everything
442 * to level. It is not technically right for MSIs but this
443 * is irrelevant at this point. We might get smarter in the future
445 *out_hwirq
= intspec
[0];
446 *out_flags
= IRQ_TYPE_LEVEL_LOW
;
451 static struct irq_host_ops xics_host_ops
= {
452 .match
= xics_host_match
,
453 .map
= xics_host_map
,
454 .xlate
= xics_host_xlate
,
457 static void __init
xics_init_host(void)
459 if (firmware_has_feature(FW_FEATURE_LPAR
))
460 xics_irq_chip
= &xics_pic_lpar
;
462 xics_irq_chip
= &xics_pic_direct
;
464 xics_host
= irq_alloc_host(NULL
, IRQ_HOST_MAP_TREE
, 0, &xics_host_ops
,
466 BUG_ON(xics_host
== NULL
);
467 irq_set_default_host(xics_host
);
471 /* Inter-processor interrupt support */
475 * XICS only has a single IPI, so encode the messages per CPU
477 struct xics_ipi_struct
{
479 } ____cacheline_aligned
;
481 static struct xics_ipi_struct xics_ipi_message
[NR_CPUS
] __cacheline_aligned
;
483 static inline void smp_xics_do_message(int cpu
, int msg
)
485 set_bit(msg
, &xics_ipi_message
[cpu
].value
);
487 if (firmware_has_feature(FW_FEATURE_LPAR
))
488 lpar_qirr_info(cpu
, IPI_PRIORITY
);
490 direct_qirr_info(cpu
, IPI_PRIORITY
);
493 void smp_xics_message_pass(int target
, int msg
)
497 if (target
< NR_CPUS
) {
498 smp_xics_do_message(target
, msg
);
500 for_each_online_cpu(i
) {
501 if (target
== MSG_ALL_BUT_SELF
502 && i
== smp_processor_id())
504 smp_xics_do_message(i
, msg
);
509 static irqreturn_t
xics_ipi_dispatch(int cpu
)
511 WARN_ON(cpu_is_offline(cpu
));
513 mb(); /* order mmio clearing qirr */
514 while (xics_ipi_message
[cpu
].value
) {
515 if (test_and_clear_bit(PPC_MSG_CALL_FUNCTION
,
516 &xics_ipi_message
[cpu
].value
)) {
517 smp_message_recv(PPC_MSG_CALL_FUNCTION
);
519 if (test_and_clear_bit(PPC_MSG_RESCHEDULE
,
520 &xics_ipi_message
[cpu
].value
)) {
521 smp_message_recv(PPC_MSG_RESCHEDULE
);
523 if (test_and_clear_bit(PPC_MSG_CALL_FUNC_SINGLE
,
524 &xics_ipi_message
[cpu
].value
)) {
525 smp_message_recv(PPC_MSG_CALL_FUNC_SINGLE
);
527 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
528 if (test_and_clear_bit(PPC_MSG_DEBUGGER_BREAK
,
529 &xics_ipi_message
[cpu
].value
)) {
530 smp_message_recv(PPC_MSG_DEBUGGER_BREAK
);
537 static irqreturn_t
xics_ipi_action_direct(int irq
, void *dev_id
)
539 int cpu
= smp_processor_id();
541 direct_qirr_info(cpu
, 0xff);
543 return xics_ipi_dispatch(cpu
);
546 static irqreturn_t
xics_ipi_action_lpar(int irq
, void *dev_id
)
548 int cpu
= smp_processor_id();
550 lpar_qirr_info(cpu
, 0xff);
552 return xics_ipi_dispatch(cpu
);
555 static void xics_request_ipi(void)
560 ipi
= irq_create_mapping(xics_host
, XICS_IPI
);
561 BUG_ON(ipi
== NO_IRQ
);
564 * IPIs are marked IRQF_DISABLED as they must run with irqs
567 set_irq_handler(ipi
, handle_percpu_irq
);
568 if (firmware_has_feature(FW_FEATURE_LPAR
))
569 rc
= request_irq(ipi
, xics_ipi_action_lpar
,
570 IRQF_DISABLED
|IRQF_PERCPU
, "IPI", NULL
);
572 rc
= request_irq(ipi
, xics_ipi_action_direct
,
573 IRQF_DISABLED
|IRQF_PERCPU
, "IPI", NULL
);
577 int __init
smp_xics_probe(void)
581 return cpus_weight(cpu_possible_map
);
584 #endif /* CONFIG_SMP */
589 static void xics_update_irq_servers(void)
592 struct device_node
*np
;
597 /* Find the server numbers for the boot cpu. */
598 np
= of_get_cpu_node(boot_cpuid
, NULL
);
601 ireg
= of_get_property(np
, "ibm,ppc-interrupt-gserver#s", &ilen
);
607 i
= ilen
/ sizeof(int);
608 hcpuid
= get_hard_smp_processor_id(boot_cpuid
);
610 /* Global interrupt distribution server is specified in the last
611 * entry of "ibm,ppc-interrupt-gserver#s" property. Get the last
612 * entry fom this property for current boot cpu id and use it as
613 * default distribution server
615 for (j
= 0; j
< i
; j
+= 2) {
616 if (ireg
[j
] == hcpuid
) {
617 default_server
= hcpuid
;
618 default_distrib_server
= ireg
[j
+1];
625 static void __init
xics_map_one_cpu(int hw_id
, unsigned long addr
,
630 /* This may look gross but it's good enough for now, we don't quite
631 * have a hard -> linux processor id matching.
633 for_each_possible_cpu(i
) {
636 if (hw_id
== get_hard_smp_processor_id(i
)) {
637 xics_per_cpu
[i
] = ioremap(addr
, size
);
643 static void __init
xics_init_one_node(struct device_node
*np
,
649 /* This code does the theorically broken assumption that the interrupt
650 * server numbers are the same as the hard CPU numbers.
651 * This happens to be the case so far but we are playing with fire...
652 * should be fixed one of these days. -BenH.
654 ireg
= of_get_property(np
, "ibm,interrupt-server-ranges", NULL
);
656 /* Do that ever happen ? we'll know soon enough... but even good'old
657 * f80 does have that property ..
659 WARN_ON(ireg
== NULL
);
662 * set node starting index for this node
666 ireg
= of_get_property(np
, "reg", &ilen
);
668 panic("xics_init_IRQ: can't find interrupt reg property");
670 while (ilen
>= (4 * sizeof(u32
))) {
671 unsigned long addr
, size
;
673 /* XXX Use proper OF parsing code here !!! */
674 addr
= (unsigned long)*ireg
++ << 32;
678 size
= (unsigned long)*ireg
++ << 32;
682 xics_map_one_cpu(*indx
, addr
, size
);
687 void __init
xics_init_IRQ(void)
689 struct device_node
*np
;
694 ppc64_boot_msg(0x20, "XICS Init");
696 ibm_get_xive
= rtas_token("ibm,get-xive");
697 ibm_set_xive
= rtas_token("ibm,set-xive");
698 ibm_int_on
= rtas_token("ibm,int-on");
699 ibm_int_off
= rtas_token("ibm,int-off");
701 for_each_node_by_type(np
, "PowerPC-External-Interrupt-Presentation") {
703 if (firmware_has_feature(FW_FEATURE_LPAR
)) {
707 xics_init_one_node(np
, &indx
);
712 /* get the bit size of server numbers */
715 for_each_compatible_node(np
, NULL
, "ibm,ppc-xics") {
716 isize
= of_get_property(np
, "ibm,interrupt-server#-size", NULL
);
722 interrupt_server_size
= *isize
;
724 } else if (*isize
!= interrupt_server_size
) {
725 printk(KERN_WARNING
"XICS: "
726 "mismatched ibm,interrupt-server#-size\n");
727 interrupt_server_size
= max(*isize
,
728 interrupt_server_size
);
732 xics_update_irq_servers();
735 if (firmware_has_feature(FW_FEATURE_LPAR
))
736 ppc_md
.get_irq
= xics_get_irq_lpar
;
738 ppc_md
.get_irq
= xics_get_irq_direct
;
742 ppc64_boot_msg(0x21, "XICS Done");
745 /* Cpu startup, shutdown, and hotplug */
747 static void xics_set_cpu_priority(unsigned char cppr
)
749 if (firmware_has_feature(FW_FEATURE_LPAR
))
750 lpar_cppr_info(cppr
);
752 direct_cppr_info(cppr
);
756 /* Have the calling processor join or leave the specified global queue */
757 static void xics_set_cpu_giq(unsigned int gserver
, unsigned int join
)
762 if (!rtas_indicator_present(GLOBAL_INTERRUPT_QUEUE
, NULL
))
765 index
= (1UL << interrupt_server_size
) - 1 - gserver
;
767 status
= rtas_set_indicator_fast(GLOBAL_INTERRUPT_QUEUE
, index
, join
);
769 WARN(status
< 0, "set-indicator(%d, %d, %u) returned %d\n",
770 GLOBAL_INTERRUPT_QUEUE
, index
, join
, status
);
773 void xics_setup_cpu(void)
775 xics_set_cpu_priority(0xff);
777 xics_set_cpu_giq(default_distrib_server
, 1);
780 void xics_teardown_cpu(void)
782 int cpu
= smp_processor_id();
784 xics_set_cpu_priority(0);
786 /* Clear any pending IPI request */
787 if (firmware_has_feature(FW_FEATURE_LPAR
))
788 lpar_qirr_info(cpu
, 0xff);
790 direct_qirr_info(cpu
, 0xff);
793 void xics_kexec_teardown_cpu(int secondary
)
798 * we take the ipi irq but and never return so we
799 * need to EOI the IPI, but want to leave our priority 0
801 * should we check all the other interrupts too?
802 * should we be flagging idle loop instead?
803 * or creating some task to be scheduled?
806 if (firmware_has_feature(FW_FEATURE_LPAR
))
807 lpar_xirr_info_set((0x00 << 24) | XICS_IPI
);
809 direct_xirr_info_set((0x00 << 24) | XICS_IPI
);
812 * Some machines need to have at least one cpu in the GIQ,
813 * so leave the master cpu in the group.
816 xics_set_cpu_giq(default_distrib_server
, 0);
819 #ifdef CONFIG_HOTPLUG_CPU
821 /* Interrupts are disabled. */
822 void xics_migrate_irqs_away(void)
824 int cpu
= smp_processor_id(), hw_cpu
= hard_smp_processor_id();
825 unsigned int irq
, virq
;
827 /* If we used to be the default server, move to the new "boot_cpuid" */
828 if (hw_cpu
== default_server
)
829 xics_update_irq_servers();
831 /* Reject any interrupt that was queued to us... */
832 xics_set_cpu_priority(0);
834 /* Remove ourselves from the global interrupt queue */
835 xics_set_cpu_giq(default_distrib_server
, 0);
837 /* Allow IPIs again... */
838 xics_set_cpu_priority(DEFAULT_PRIORITY
);
841 struct irq_desc
*desc
;
846 /* We cant set affinity on ISA interrupts */
847 if (virq
< NUM_ISA_INTERRUPTS
)
849 if (irq_map
[virq
].host
!= xics_host
)
851 irq
= (unsigned int)irq_map
[virq
].hwirq
;
852 /* We need to get IPIs still. */
853 if (irq
== XICS_IPI
|| irq
== XICS_IRQ_SPURIOUS
)
855 desc
= irq_to_desc(virq
);
857 /* We only need to migrate enabled IRQS */
858 if (desc
== NULL
|| desc
->chip
== NULL
859 || desc
->action
== NULL
860 || desc
->chip
->set_affinity
== NULL
)
863 spin_lock_irqsave(&desc
->lock
, flags
);
865 status
= rtas_call(ibm_get_xive
, 1, 3, xics_status
, irq
);
867 printk(KERN_ERR
"%s: ibm,get-xive irq=%u returns %d\n",
868 __func__
, irq
, status
);
873 * We only support delivery to all cpus or to one cpu.
874 * The irq has to be migrated only in the single cpu
877 if (xics_status
[0] != hw_cpu
)
880 printk(KERN_WARNING
"IRQ %u affinity broken off cpu %u\n",
883 /* Reset affinity to all cpus */
884 cpumask_setall(irq_to_desc(virq
)->affinity
);
885 desc
->chip
->set_affinity(virq
, cpu_all_mask
);
887 spin_unlock_irqrestore(&desc
->lock
, flags
);