2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 1999, 2000, 01, 06 Ralf Baechle
7 * Copyright (C) 1995, 1996 Paul M. Antoine
8 * Copyright (C) 1998 Ulf Carlsson
9 * Copyright (C) 1999 Silicon Graphics, Inc.
10 * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
11 * Copyright (C) 2000, 01 MIPS Technologies, Inc.
12 * Copyright (C) 2002, 2003, 2004, 2005, 2007 Maciej W. Rozycki
14 #include <linux/bug.h>
15 #include <linux/compiler.h>
16 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/sched.h>
20 #include <linux/smp.h>
21 #include <linux/spinlock.h>
22 #include <linux/kallsyms.h>
23 #include <linux/bootmem.h>
24 #include <linux/interrupt.h>
25 #include <linux/ptrace.h>
26 #include <linux/kgdb.h>
27 #include <linux/kdebug.h>
28 #include <linux/notifier.h>
29 #include <linux/kdb.h>
31 #include <asm/bootinfo.h>
32 #include <asm/branch.h>
33 #include <asm/break.h>
38 #include <asm/fpu_emulator.h>
39 #include <asm/mipsregs.h>
40 #include <asm/mipsmtregs.h>
41 #include <asm/module.h>
42 #include <asm/pgtable.h>
43 #include <asm/ptrace.h>
44 #include <asm/sections.h>
45 #include <asm/system.h>
46 #include <asm/tlbdebug.h>
47 #include <asm/traps.h>
48 #include <asm/uaccess.h>
49 #include <asm/watch.h>
50 #include <asm/mmu_context.h>
51 #include <asm/types.h>
52 #include <asm/stacktrace.h>
56 extern void check_wait(void);
57 extern asmlinkage
void r4k_wait(void);
58 extern asmlinkage
void rollback_handle_int(void);
59 extern asmlinkage
void handle_int(void);
60 extern asmlinkage
void handle_tlbm(void);
61 extern asmlinkage
void handle_tlbl(void);
62 extern asmlinkage
void handle_tlbs(void);
63 extern asmlinkage
void handle_adel(void);
64 extern asmlinkage
void handle_ades(void);
65 extern asmlinkage
void handle_ibe(void);
66 extern asmlinkage
void handle_dbe(void);
67 extern asmlinkage
void handle_sys(void);
68 extern asmlinkage
void handle_bp(void);
69 extern asmlinkage
void handle_ri(void);
70 extern asmlinkage
void handle_ri_rdhwr_vivt(void);
71 extern asmlinkage
void handle_ri_rdhwr(void);
72 extern asmlinkage
void handle_cpu(void);
73 extern asmlinkage
void handle_ov(void);
74 extern asmlinkage
void handle_tr(void);
75 extern asmlinkage
void handle_fpe(void);
76 extern asmlinkage
void handle_mdmx(void);
77 extern asmlinkage
void handle_watch(void);
78 extern asmlinkage
void handle_mt(void);
79 extern asmlinkage
void handle_dsp(void);
80 extern asmlinkage
void handle_mcheck(void);
81 extern asmlinkage
void handle_reserved(void);
83 extern int fpu_emulator_cop1Handler(struct pt_regs
*xcp
,
84 struct mips_fpu_struct
*ctx
, int has_fpu
);
86 void (*board_be_init
)(void);
87 int (*board_be_handler
)(struct pt_regs
*regs
, int is_fixup
);
88 void (*board_nmi_handler_setup
)(void);
89 void (*board_ejtag_handler_setup
)(void);
90 void (*board_bind_eic_interrupt
)(int irq
, int regset
);
93 static void show_raw_backtrace(unsigned long reg29
)
95 unsigned long *sp
= (unsigned long *)(reg29
& ~3);
98 printk("Call Trace:");
99 #ifdef CONFIG_KALLSYMS
102 while (!kstack_end(sp
)) {
103 unsigned long __user
*p
=
104 (unsigned long __user
*)(unsigned long)sp
++;
105 if (__get_user(addr
, p
)) {
106 printk(" (Bad stack address)");
109 if (__kernel_text_address(addr
))
115 #ifdef CONFIG_KALLSYMS
117 static int __init
set_raw_show_trace(char *str
)
122 __setup("raw_show_trace", set_raw_show_trace
);
125 static void show_backtrace(struct task_struct
*task
, const struct pt_regs
*regs
)
127 unsigned long sp
= regs
->regs
[29];
128 unsigned long ra
= regs
->regs
[31];
129 unsigned long pc
= regs
->cp0_epc
;
131 if (raw_show_trace
|| !__kernel_text_address(pc
)) {
132 show_raw_backtrace(sp
);
135 printk("Call Trace:\n");
138 pc
= unwind_stack(task
, &sp
, pc
, &ra
);
144 * This routine abuses get_user()/put_user() to reference pointers
145 * with at least a bit of error checking ...
147 static void show_stacktrace(struct task_struct
*task
,
148 const struct pt_regs
*regs
)
150 const int field
= 2 * sizeof(unsigned long);
153 unsigned long __user
*sp
= (unsigned long __user
*)regs
->regs
[29];
157 while ((unsigned long) sp
& (PAGE_SIZE
- 1)) {
158 if (i
&& ((i
% (64 / field
)) == 0))
165 if (__get_user(stackdata
, sp
++)) {
166 printk(" (Bad stack address)");
170 printk(" %0*lx", field
, stackdata
);
174 show_backtrace(task
, regs
);
177 void show_stack(struct task_struct
*task
, unsigned long *sp
)
181 regs
.regs
[29] = (unsigned long)sp
;
185 if (task
&& task
!= current
) {
186 regs
.regs
[29] = task
->thread
.reg29
;
188 regs
.cp0_epc
= task
->thread
.reg31
;
189 #ifdef CONFIG_KGDB_KDB
190 } else if (atomic_read(&kgdb_active
) != -1 &&
192 memcpy(®s
, kdb_current_regs
, sizeof(regs
));
193 #endif /* CONFIG_KGDB_KDB */
195 prepare_frametrace(®s
);
198 show_stacktrace(task
, ®s
);
202 * The architecture-independent dump_stack generator
204 void dump_stack(void)
208 prepare_frametrace(®s
);
209 show_backtrace(current
, ®s
);
212 EXPORT_SYMBOL(dump_stack
);
214 static void show_code(unsigned int __user
*pc
)
217 unsigned short __user
*pc16
= NULL
;
221 if ((unsigned long)pc
& 1)
222 pc16
= (unsigned short __user
*)((unsigned long)pc
& ~1);
223 for(i
= -3 ; i
< 6 ; i
++) {
225 if (pc16
? __get_user(insn
, pc16
+ i
) : __get_user(insn
, pc
+ i
)) {
226 printk(" (Bad address in epc)\n");
229 printk("%c%0*x%c", (i
?' ':'<'), pc16
? 4 : 8, insn
, (i
?' ':'>'));
233 static void __show_regs(const struct pt_regs
*regs
)
235 const int field
= 2 * sizeof(unsigned long);
236 unsigned int cause
= regs
->cp0_cause
;
239 printk("Cpu %d\n", smp_processor_id());
242 * Saved main processor registers
244 for (i
= 0; i
< 32; ) {
248 printk(" %0*lx", field
, 0UL);
249 else if (i
== 26 || i
== 27)
250 printk(" %*s", field
, "");
252 printk(" %0*lx", field
, regs
->regs
[i
]);
259 #ifdef CONFIG_CPU_HAS_SMARTMIPS
260 printk("Acx : %0*lx\n", field
, regs
->acx
);
262 printk("Hi : %0*lx\n", field
, regs
->hi
);
263 printk("Lo : %0*lx\n", field
, regs
->lo
);
266 * Saved cp0 registers
268 printk("epc : %0*lx %pS\n", field
, regs
->cp0_epc
,
269 (void *) regs
->cp0_epc
);
270 printk(" %s\n", print_tainted());
271 printk("ra : %0*lx %pS\n", field
, regs
->regs
[31],
272 (void *) regs
->regs
[31]);
274 printk("Status: %08x ", (uint32_t) regs
->cp0_status
);
276 if (current_cpu_data
.isa_level
== MIPS_CPU_ISA_I
) {
277 if (regs
->cp0_status
& ST0_KUO
)
279 if (regs
->cp0_status
& ST0_IEO
)
281 if (regs
->cp0_status
& ST0_KUP
)
283 if (regs
->cp0_status
& ST0_IEP
)
285 if (regs
->cp0_status
& ST0_KUC
)
287 if (regs
->cp0_status
& ST0_IEC
)
290 if (regs
->cp0_status
& ST0_KX
)
292 if (regs
->cp0_status
& ST0_SX
)
294 if (regs
->cp0_status
& ST0_UX
)
296 switch (regs
->cp0_status
& ST0_KSU
) {
301 printk("SUPERVISOR ");
310 if (regs
->cp0_status
& ST0_ERL
)
312 if (regs
->cp0_status
& ST0_EXL
)
314 if (regs
->cp0_status
& ST0_IE
)
319 printk("Cause : %08x\n", cause
);
321 cause
= (cause
& CAUSEF_EXCCODE
) >> CAUSEB_EXCCODE
;
322 if (1 <= cause
&& cause
<= 5)
323 printk("BadVA : %0*lx\n", field
, regs
->cp0_badvaddr
);
325 printk("PrId : %08x (%s)\n", read_c0_prid(),
330 * FIXME: really the generic show_regs should take a const pointer argument.
332 void show_regs(struct pt_regs
*regs
)
334 __show_regs((struct pt_regs
*)regs
);
337 void show_registers(const struct pt_regs
*regs
)
339 const int field
= 2 * sizeof(unsigned long);
343 printk("Process %s (pid: %d, threadinfo=%p, task=%p, tls=%0*lx)\n",
344 current
->comm
, current
->pid
, current_thread_info(), current
,
345 field
, current_thread_info()->tp_value
);
346 if (cpu_has_userlocal
) {
349 tls
= read_c0_userlocal();
350 if (tls
!= current_thread_info()->tp_value
)
351 printk("*HwTLS: %0*lx\n", field
, tls
);
354 show_stacktrace(current
, regs
);
355 show_code((unsigned int __user
*) regs
->cp0_epc
);
359 static DEFINE_SPINLOCK(die_lock
);
361 void __noreturn
die(const char * str
, struct pt_regs
* regs
)
363 static int die_counter
;
365 #ifdef CONFIG_MIPS_MT_SMTC
366 unsigned long dvpret
= dvpe();
367 #endif /* CONFIG_MIPS_MT_SMTC */
369 notify_die(DIE_OOPS
, str
, (struct pt_regs
*)regs
, SIGSEGV
, 0, 0);
372 spin_lock_irq(&die_lock
);
374 #ifdef CONFIG_MIPS_MT_SMTC
375 mips_mt_regdump(dvpret
);
376 #endif /* CONFIG_MIPS_MT_SMTC */
378 if (notify_die(DIE_OOPS
, str
, regs
, 0, current
->thread
.trap_no
, SIGSEGV
) == NOTIFY_STOP
)
381 printk("%s[#%d]:\n", str
, ++die_counter
);
382 show_registers(regs
);
383 add_taint(TAINT_DIE
);
384 spin_unlock_irq(&die_lock
);
387 panic("Fatal exception in interrupt");
390 printk(KERN_EMERG
"Fatal exception: panic in 5 seconds\n");
392 panic("Fatal exception");
398 extern struct exception_table_entry __start___dbe_table
[];
399 extern struct exception_table_entry __stop___dbe_table
[];
402 " .section __dbe_table, \"a\"\n"
405 /* Given an address, look for it in the exception tables. */
406 static const struct exception_table_entry
*search_dbe_tables(unsigned long addr
)
408 const struct exception_table_entry
*e
;
410 e
= search_extable(__start___dbe_table
, __stop___dbe_table
- 1, addr
);
412 e
= search_module_dbetables(addr
);
416 asmlinkage
void do_be(struct pt_regs
*regs
)
418 const int field
= 2 * sizeof(unsigned long);
419 const struct exception_table_entry
*fixup
= NULL
;
420 int data
= regs
->cp0_cause
& 4;
421 int action
= MIPS_BE_FATAL
;
423 /* XXX For now. Fixme, this searches the wrong table ... */
424 if (data
&& !user_mode(regs
))
425 fixup
= search_dbe_tables(exception_epc(regs
));
428 action
= MIPS_BE_FIXUP
;
430 if (board_be_handler
)
431 action
= board_be_handler(regs
, fixup
!= NULL
);
434 case MIPS_BE_DISCARD
:
438 regs
->cp0_epc
= fixup
->nextinsn
;
447 * Assume it would be too dangerous to continue ...
449 printk(KERN_ALERT
"%s bus error, epc == %0*lx, ra == %0*lx\n",
450 data
? "Data" : "Instruction",
451 field
, regs
->cp0_epc
, field
, regs
->regs
[31]);
452 if (notify_die(DIE_OOPS
, "bus error", regs
, SIGBUS
, 0, 0)
456 die_if_kernel("Oops", regs
);
457 force_sig(SIGBUS
, current
);
461 * ll/sc, rdhwr, sync emulation
464 #define OPCODE 0xfc000000
465 #define BASE 0x03e00000
466 #define RT 0x001f0000
467 #define OFFSET 0x0000ffff
468 #define LL 0xc0000000
469 #define SC 0xe0000000
470 #define SPEC0 0x00000000
471 #define SPEC3 0x7c000000
472 #define RD 0x0000f800
473 #define FUNC 0x0000003f
474 #define SYNC 0x0000000f
475 #define RDHWR 0x0000003b
478 * The ll_bit is cleared by r*_switch.S
482 struct task_struct
*ll_task
;
484 static inline int simulate_ll(struct pt_regs
*regs
, unsigned int opcode
)
486 unsigned long value
, __user
*vaddr
;
490 * analyse the ll instruction that just caused a ri exception
491 * and put the referenced address to addr.
494 /* sign extend offset */
495 offset
= opcode
& OFFSET
;
499 vaddr
= (unsigned long __user
*)
500 ((unsigned long)(regs
->regs
[(opcode
& BASE
) >> 21]) + offset
);
502 if ((unsigned long)vaddr
& 3)
504 if (get_user(value
, vaddr
))
509 if (ll_task
== NULL
|| ll_task
== current
) {
518 regs
->regs
[(opcode
& RT
) >> 16] = value
;
523 static inline int simulate_sc(struct pt_regs
*regs
, unsigned int opcode
)
525 unsigned long __user
*vaddr
;
530 * analyse the sc instruction that just caused a ri exception
531 * and put the referenced address to addr.
534 /* sign extend offset */
535 offset
= opcode
& OFFSET
;
539 vaddr
= (unsigned long __user
*)
540 ((unsigned long)(regs
->regs
[(opcode
& BASE
) >> 21]) + offset
);
541 reg
= (opcode
& RT
) >> 16;
543 if ((unsigned long)vaddr
& 3)
548 if (ll_bit
== 0 || ll_task
!= current
) {
556 if (put_user(regs
->regs
[reg
], vaddr
))
565 * ll uses the opcode of lwc0 and sc uses the opcode of swc0. That is both
566 * opcodes are supposed to result in coprocessor unusable exceptions if
567 * executed on ll/sc-less processors. That's the theory. In practice a
568 * few processors such as NEC's VR4100 throw reserved instruction exceptions
569 * instead, so we're doing the emulation thing in both exception handlers.
571 static int simulate_llsc(struct pt_regs
*regs
, unsigned int opcode
)
573 if ((opcode
& OPCODE
) == LL
)
574 return simulate_ll(regs
, opcode
);
575 if ((opcode
& OPCODE
) == SC
)
576 return simulate_sc(regs
, opcode
);
578 return -1; /* Must be something else ... */
582 * Simulate trapping 'rdhwr' instructions to provide user accessible
583 * registers not implemented in hardware.
585 static int simulate_rdhwr(struct pt_regs
*regs
, unsigned int opcode
)
587 struct thread_info
*ti
= task_thread_info(current
);
589 if ((opcode
& OPCODE
) == SPEC3
&& (opcode
& FUNC
) == RDHWR
) {
590 int rd
= (opcode
& RD
) >> 11;
591 int rt
= (opcode
& RT
) >> 16;
593 case 0: /* CPU number */
594 regs
->regs
[rt
] = smp_processor_id();
596 case 1: /* SYNCI length */
597 regs
->regs
[rt
] = min(current_cpu_data
.dcache
.linesz
,
598 current_cpu_data
.icache
.linesz
);
600 case 2: /* Read count register */
601 regs
->regs
[rt
] = read_c0_count();
603 case 3: /* Count register resolution */
604 switch (current_cpu_data
.cputype
) {
614 regs
->regs
[rt
] = ti
->tp_value
;
625 static int simulate_sync(struct pt_regs
*regs
, unsigned int opcode
)
627 if ((opcode
& OPCODE
) == SPEC0
&& (opcode
& FUNC
) == SYNC
)
630 return -1; /* Must be something else ... */
633 asmlinkage
void do_ov(struct pt_regs
*regs
)
637 die_if_kernel("Integer overflow", regs
);
639 info
.si_code
= FPE_INTOVF
;
640 info
.si_signo
= SIGFPE
;
642 info
.si_addr
= (void __user
*) regs
->cp0_epc
;
643 force_sig_info(SIGFPE
, &info
, current
);
647 * XXX Delayed fp exceptions when doing a lazy ctx switch XXX
649 asmlinkage
void do_fpe(struct pt_regs
*regs
, unsigned long fcr31
)
653 if (notify_die(DIE_FP
, "FP exception", regs
, SIGFPE
, 0, 0)
656 die_if_kernel("FP exception in kernel code", regs
);
658 if (fcr31
& FPU_CSR_UNI_X
) {
662 * Unimplemented operation exception. If we've got the full
663 * software emulator on-board, let's use it...
665 * Force FPU to dump state into task/thread context. We're
666 * moving a lot of data here for what is probably a single
667 * instruction, but the alternative is to pre-decode the FP
668 * register operands before invoking the emulator, which seems
669 * a bit extreme for what should be an infrequent event.
671 /* Ensure 'resume' not overwrite saved fp context again. */
674 /* Run the emulator */
675 sig
= fpu_emulator_cop1Handler(regs
, ¤t
->thread
.fpu
, 1);
678 * We can't allow the emulated instruction to leave any of
679 * the cause bit set in $fcr31.
681 current
->thread
.fpu
.fcr31
&= ~FPU_CSR_ALL_X
;
683 /* Restore the hardware register state */
684 own_fpu(1); /* Using the FPU again. */
686 /* If something went wrong, signal */
688 force_sig(sig
, current
);
691 } else if (fcr31
& FPU_CSR_INV_X
)
692 info
.si_code
= FPE_FLTINV
;
693 else if (fcr31
& FPU_CSR_DIV_X
)
694 info
.si_code
= FPE_FLTDIV
;
695 else if (fcr31
& FPU_CSR_OVF_X
)
696 info
.si_code
= FPE_FLTOVF
;
697 else if (fcr31
& FPU_CSR_UDF_X
)
698 info
.si_code
= FPE_FLTUND
;
699 else if (fcr31
& FPU_CSR_INE_X
)
700 info
.si_code
= FPE_FLTRES
;
702 info
.si_code
= __SI_FAULT
;
703 info
.si_signo
= SIGFPE
;
705 info
.si_addr
= (void __user
*) regs
->cp0_epc
;
706 force_sig_info(SIGFPE
, &info
, current
);
709 static void do_trap_or_bp(struct pt_regs
*regs
, unsigned int code
,
715 #ifdef CONFIG_KGDB_LOW_LEVEL_TRAP
716 if (kgdb_ll_trap(DIE_TRAP
, str
, regs
, code
, 0, 0) == NOTIFY_STOP
)
718 #endif /* CONFIG_KGDB_LOW_LEVEL_TRAP */
720 if (notify_die(DIE_TRAP
, str
, regs
, code
, 0, 0) == NOTIFY_STOP
)
724 * A short test says that IRIX 5.3 sends SIGTRAP for all trap
725 * insns, even for trap and break codes that indicate arithmetic
726 * failures. Weird ...
727 * But should we continue the brokenness??? --macro
732 scnprintf(b
, sizeof(b
), "%s instruction in kernel code", str
);
733 die_if_kernel(b
, regs
);
734 if (code
== BRK_DIVZERO
)
735 info
.si_code
= FPE_INTDIV
;
737 info
.si_code
= FPE_INTOVF
;
738 info
.si_signo
= SIGFPE
;
740 info
.si_addr
= (void __user
*) regs
->cp0_epc
;
741 force_sig_info(SIGFPE
, &info
, current
);
744 die_if_kernel("Kernel bug detected", regs
);
745 force_sig(SIGTRAP
, current
);
749 * Address errors may be deliberately induced by the FPU
750 * emulator to retake control of the CPU after executing the
751 * instruction in the delay slot of an emulated branch.
753 * Terminate if exception was recognized as a delay slot return
754 * otherwise handle as normal.
756 if (do_dsemulret(regs
))
759 die_if_kernel("Math emu break/trap", regs
);
760 force_sig(SIGTRAP
, current
);
763 scnprintf(b
, sizeof(b
), "%s instruction in kernel code", str
);
764 die_if_kernel(b
, regs
);
765 force_sig(SIGTRAP
, current
);
769 asmlinkage
void do_bp(struct pt_regs
*regs
)
771 unsigned int opcode
, bcode
;
773 if (__get_user(opcode
, (unsigned int __user
*) exception_epc(regs
)))
777 * There is the ancient bug in the MIPS assemblers that the break
778 * code starts left to bit 16 instead to bit 6 in the opcode.
779 * Gas is bug-compatible, but not always, grrr...
780 * We handle both cases with a simple heuristics. --macro
782 bcode
= ((opcode
>> 6) & ((1 << 20) - 1));
783 if (bcode
>= (1 << 10))
786 do_trap_or_bp(regs
, bcode
, "Break");
790 force_sig(SIGSEGV
, current
);
793 asmlinkage
void do_tr(struct pt_regs
*regs
)
795 unsigned int opcode
, tcode
= 0;
797 if (__get_user(opcode
, (unsigned int __user
*) exception_epc(regs
)))
800 /* Immediate versions don't provide a code. */
801 if (!(opcode
& OPCODE
))
802 tcode
= ((opcode
>> 6) & ((1 << 10) - 1));
804 do_trap_or_bp(regs
, tcode
, "Trap");
808 force_sig(SIGSEGV
, current
);
811 asmlinkage
void do_ri(struct pt_regs
*regs
)
813 unsigned int __user
*epc
= (unsigned int __user
*)exception_epc(regs
);
814 unsigned long old_epc
= regs
->cp0_epc
;
815 unsigned int opcode
= 0;
818 if (notify_die(DIE_RI
, "RI Fault", regs
, SIGSEGV
, 0, 0)
822 die_if_kernel("Reserved instruction in kernel code", regs
);
824 if (unlikely(compute_return_epc(regs
) < 0))
827 if (unlikely(get_user(opcode
, epc
) < 0))
830 if (!cpu_has_llsc
&& status
< 0)
831 status
= simulate_llsc(regs
, opcode
);
834 status
= simulate_rdhwr(regs
, opcode
);
837 status
= simulate_sync(regs
, opcode
);
842 if (unlikely(status
> 0)) {
843 regs
->cp0_epc
= old_epc
; /* Undo skip-over. */
844 force_sig(status
, current
);
849 * MIPS MT processors may have fewer FPU contexts than CPU threads. If we've
850 * emulated more than some threshold number of instructions, force migration to
851 * a "CPU" that has FP support.
853 static void mt_ase_fp_affinity(void)
855 #ifdef CONFIG_MIPS_MT_FPAFF
856 if (mt_fpemul_threshold
> 0 &&
857 ((current
->thread
.emulated_fp
++ > mt_fpemul_threshold
))) {
859 * If there's no FPU present, or if the application has already
860 * restricted the allowed set to exclude any CPUs with FPUs,
861 * we'll skip the procedure.
863 if (cpus_intersects(current
->cpus_allowed
, mt_fpu_cpumask
)) {
866 current
->thread
.user_cpus_allowed
867 = current
->cpus_allowed
;
868 cpus_and(tmask
, current
->cpus_allowed
,
870 set_cpus_allowed_ptr(current
, &tmask
);
871 set_thread_flag(TIF_FPUBOUND
);
874 #endif /* CONFIG_MIPS_MT_FPAFF */
878 * No lock; only written during early bootup by CPU 0.
880 static RAW_NOTIFIER_HEAD(cu2_chain
);
882 int __ref
register_cu2_notifier(struct notifier_block
*nb
)
884 return raw_notifier_chain_register(&cu2_chain
, nb
);
887 int cu2_notifier_call_chain(unsigned long val
, void *v
)
889 return raw_notifier_call_chain(&cu2_chain
, val
, v
);
892 static int default_cu2_call(struct notifier_block
*nfb
, unsigned long action
,
895 struct pt_regs
*regs
= data
;
899 die_if_kernel("Unhandled kernel unaligned access or invalid "
900 "instruction", regs
);
904 force_sig(SIGILL
, current
);
910 static struct notifier_block default_cu2_notifier
= {
911 .notifier_call
= default_cu2_call
,
912 .priority
= 0x80000000, /* Run last */
915 asmlinkage
void do_cpu(struct pt_regs
*regs
)
917 unsigned int __user
*epc
;
918 unsigned long old_epc
;
922 unsigned long __maybe_unused flags
;
924 die_if_kernel("do_cpu invoked from kernel context!", regs
);
926 cpid
= (regs
->cp0_cause
>> CAUSEB_CE
) & 3;
930 epc
= (unsigned int __user
*)exception_epc(regs
);
931 old_epc
= regs
->cp0_epc
;
935 if (unlikely(compute_return_epc(regs
) < 0))
938 if (unlikely(get_user(opcode
, epc
) < 0))
941 if (!cpu_has_llsc
&& status
< 0)
942 status
= simulate_llsc(regs
, opcode
);
945 status
= simulate_rdhwr(regs
, opcode
);
950 if (unlikely(status
> 0)) {
951 regs
->cp0_epc
= old_epc
; /* Undo skip-over. */
952 force_sig(status
, current
);
958 if (used_math()) /* Using the FPU again. */
960 else { /* First time FPU user. */
965 if (!raw_cpu_has_fpu
) {
967 sig
= fpu_emulator_cop1Handler(regs
,
968 ¤t
->thread
.fpu
, 0);
970 force_sig(sig
, current
);
972 mt_ase_fp_affinity();
978 raw_notifier_call_chain(&cu2_chain
, CU2_EXCEPTION
, regs
);
985 force_sig(SIGILL
, current
);
988 asmlinkage
void do_mdmx(struct pt_regs
*regs
)
990 force_sig(SIGILL
, current
);
994 * Called with interrupts disabled.
996 asmlinkage
void do_watch(struct pt_regs
*regs
)
1001 * Clear WP (bit 22) bit of cause register so we don't loop
1004 cause
= read_c0_cause();
1005 cause
&= ~(1 << 22);
1006 write_c0_cause(cause
);
1009 * If the current thread has the watch registers loaded, save
1010 * their values and send SIGTRAP. Otherwise another thread
1011 * left the registers set, clear them and continue.
1013 if (test_tsk_thread_flag(current
, TIF_LOAD_WATCH
)) {
1014 mips_read_watch_registers();
1016 force_sig(SIGTRAP
, current
);
1018 mips_clear_watch_registers();
1023 asmlinkage
void do_mcheck(struct pt_regs
*regs
)
1025 const int field
= 2 * sizeof(unsigned long);
1026 int multi_match
= regs
->cp0_status
& ST0_TS
;
1031 printk("Index : %0x\n", read_c0_index());
1032 printk("Pagemask: %0x\n", read_c0_pagemask());
1033 printk("EntryHi : %0*lx\n", field
, read_c0_entryhi());
1034 printk("EntryLo0: %0*lx\n", field
, read_c0_entrylo0());
1035 printk("EntryLo1: %0*lx\n", field
, read_c0_entrylo1());
1040 show_code((unsigned int __user
*) regs
->cp0_epc
);
1043 * Some chips may have other causes of machine check (e.g. SB1
1046 panic("Caught Machine Check exception - %scaused by multiple "
1047 "matching entries in the TLB.",
1048 (multi_match
) ? "" : "not ");
1051 asmlinkage
void do_mt(struct pt_regs
*regs
)
1055 subcode
= (read_vpe_c0_vpecontrol() & VPECONTROL_EXCPT
)
1056 >> VPECONTROL_EXCPT_SHIFT
;
1059 printk(KERN_DEBUG
"Thread Underflow\n");
1062 printk(KERN_DEBUG
"Thread Overflow\n");
1065 printk(KERN_DEBUG
"Invalid YIELD Qualifier\n");
1068 printk(KERN_DEBUG
"Gating Storage Exception\n");
1071 printk(KERN_DEBUG
"YIELD Scheduler Exception\n");
1074 printk(KERN_DEBUG
"Gating Storage Schedulier Exception\n");
1077 printk(KERN_DEBUG
"*** UNKNOWN THREAD EXCEPTION %d ***\n",
1081 die_if_kernel("MIPS MT Thread exception in kernel", regs
);
1083 force_sig(SIGILL
, current
);
1087 asmlinkage
void do_dsp(struct pt_regs
*regs
)
1090 panic("Unexpected DSP exception\n");
1092 force_sig(SIGILL
, current
);
1095 asmlinkage
void do_reserved(struct pt_regs
*regs
)
1098 * Game over - no way to handle this if it ever occurs. Most probably
1099 * caused by a new unknown cpu type or after another deadly
1100 * hard/software error.
1103 panic("Caught reserved exception %ld - should not happen.",
1104 (regs
->cp0_cause
& 0x7f) >> 2);
1107 static int __initdata l1parity
= 1;
1108 static int __init
nol1parity(char *s
)
1113 __setup("nol1par", nol1parity
);
1114 static int __initdata l2parity
= 1;
1115 static int __init
nol2parity(char *s
)
1120 __setup("nol2par", nol2parity
);
1123 * Some MIPS CPUs can enable/disable for cache parity detection, but do
1124 * it different ways.
1126 static inline void parity_protection_init(void)
1128 switch (current_cpu_type()) {
1134 #define ERRCTL_PE 0x80000000
1135 #define ERRCTL_L2P 0x00800000
1136 unsigned long errctl
;
1137 unsigned int l1parity_present
, l2parity_present
;
1139 errctl
= read_c0_ecc();
1140 errctl
&= ~(ERRCTL_PE
|ERRCTL_L2P
);
1142 /* probe L1 parity support */
1143 write_c0_ecc(errctl
| ERRCTL_PE
);
1144 back_to_back_c0_hazard();
1145 l1parity_present
= (read_c0_ecc() & ERRCTL_PE
);
1147 /* probe L2 parity support */
1148 write_c0_ecc(errctl
|ERRCTL_L2P
);
1149 back_to_back_c0_hazard();
1150 l2parity_present
= (read_c0_ecc() & ERRCTL_L2P
);
1152 if (l1parity_present
&& l2parity_present
) {
1154 errctl
|= ERRCTL_PE
;
1155 if (l1parity
^ l2parity
)
1156 errctl
|= ERRCTL_L2P
;
1157 } else if (l1parity_present
) {
1159 errctl
|= ERRCTL_PE
;
1160 } else if (l2parity_present
) {
1162 errctl
|= ERRCTL_L2P
;
1164 /* No parity available */
1167 printk(KERN_INFO
"Writing ErrCtl register=%08lx\n", errctl
);
1169 write_c0_ecc(errctl
);
1170 back_to_back_c0_hazard();
1171 errctl
= read_c0_ecc();
1172 printk(KERN_INFO
"Readback ErrCtl register=%08lx\n", errctl
);
1174 if (l1parity_present
)
1175 printk(KERN_INFO
"Cache parity protection %sabled\n",
1176 (errctl
& ERRCTL_PE
) ? "en" : "dis");
1178 if (l2parity_present
) {
1179 if (l1parity_present
&& l1parity
)
1180 errctl
^= ERRCTL_L2P
;
1181 printk(KERN_INFO
"L2 cache parity protection %sabled\n",
1182 (errctl
& ERRCTL_L2P
) ? "en" : "dis");
1188 write_c0_ecc(0x80000000);
1189 back_to_back_c0_hazard();
1190 /* Set the PE bit (bit 31) in the c0_errctl register. */
1191 printk(KERN_INFO
"Cache parity protection %sabled\n",
1192 (read_c0_ecc() & 0x80000000) ? "en" : "dis");
1196 /* Clear the DE bit (bit 16) in the c0_status register. */
1197 printk(KERN_INFO
"Enable cache parity protection for "
1198 "MIPS 20KC/25KF CPUs.\n");
1199 clear_c0_status(ST0_DE
);
1206 asmlinkage
void cache_parity_error(void)
1208 const int field
= 2 * sizeof(unsigned long);
1209 unsigned int reg_val
;
1211 /* For the moment, report the problem and hang. */
1212 printk("Cache error exception:\n");
1213 printk("cp0_errorepc == %0*lx\n", field
, read_c0_errorepc());
1214 reg_val
= read_c0_cacheerr();
1215 printk("c0_cacheerr == %08x\n", reg_val
);
1217 printk("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
1218 reg_val
& (1<<30) ? "secondary" : "primary",
1219 reg_val
& (1<<31) ? "data" : "insn");
1220 printk("Error bits: %s%s%s%s%s%s%s\n",
1221 reg_val
& (1<<29) ? "ED " : "",
1222 reg_val
& (1<<28) ? "ET " : "",
1223 reg_val
& (1<<26) ? "EE " : "",
1224 reg_val
& (1<<25) ? "EB " : "",
1225 reg_val
& (1<<24) ? "EI " : "",
1226 reg_val
& (1<<23) ? "E1 " : "",
1227 reg_val
& (1<<22) ? "E0 " : "");
1228 printk("IDX: 0x%08x\n", reg_val
& ((1<<22)-1));
1230 #if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
1231 if (reg_val
& (1<<22))
1232 printk("DErrAddr0: 0x%0*lx\n", field
, read_c0_derraddr0());
1234 if (reg_val
& (1<<23))
1235 printk("DErrAddr1: 0x%0*lx\n", field
, read_c0_derraddr1());
1238 panic("Can't handle the cache error!");
1242 * SDBBP EJTAG debug exception handler.
1243 * We skip the instruction and return to the next instruction.
1245 void ejtag_exception_handler(struct pt_regs
*regs
)
1247 const int field
= 2 * sizeof(unsigned long);
1248 unsigned long depc
, old_epc
;
1251 printk(KERN_DEBUG
"SDBBP EJTAG debug exception - not handled yet, just ignored!\n");
1252 depc
= read_c0_depc();
1253 debug
= read_c0_debug();
1254 printk(KERN_DEBUG
"c0_depc = %0*lx, DEBUG = %08x\n", field
, depc
, debug
);
1255 if (debug
& 0x80000000) {
1257 * In branch delay slot.
1258 * We cheat a little bit here and use EPC to calculate the
1259 * debug return address (DEPC). EPC is restored after the
1262 old_epc
= regs
->cp0_epc
;
1263 regs
->cp0_epc
= depc
;
1264 __compute_return_epc(regs
);
1265 depc
= regs
->cp0_epc
;
1266 regs
->cp0_epc
= old_epc
;
1269 write_c0_depc(depc
);
1272 printk(KERN_DEBUG
"\n\n----- Enable EJTAG single stepping ----\n\n");
1273 write_c0_debug(debug
| 0x100);
1278 * NMI exception handler.
1280 NORET_TYPE
void ATTRIB_NORET
nmi_exception_handler(struct pt_regs
*regs
)
1283 printk("NMI taken!!!!\n");
1287 #define VECTORSPACING 0x100 /* for EI/VI mode */
1289 unsigned long ebase
;
1290 unsigned long exception_handlers
[32];
1291 unsigned long vi_handlers
[64];
1293 void __init
*set_except_vector(int n
, void *addr
)
1295 unsigned long handler
= (unsigned long) addr
;
1296 unsigned long old_handler
= exception_handlers
[n
];
1298 exception_handlers
[n
] = handler
;
1299 if (n
== 0 && cpu_has_divec
) {
1300 unsigned long jump_mask
= ~((1 << 28) - 1);
1301 u32
*buf
= (u32
*)(ebase
+ 0x200);
1302 unsigned int k0
= 26;
1303 if ((handler
& jump_mask
) == ((ebase
+ 0x200) & jump_mask
)) {
1304 uasm_i_j(&buf
, handler
& ~jump_mask
);
1307 UASM_i_LA(&buf
, k0
, handler
);
1308 uasm_i_jr(&buf
, k0
);
1311 local_flush_icache_range(ebase
+ 0x200, (unsigned long)buf
);
1313 return (void *)old_handler
;
1316 static asmlinkage
void do_default_vi(void)
1318 show_regs(get_irq_regs());
1319 panic("Caught unexpected vectored interrupt.");
1322 static void *set_vi_srs_handler(int n
, vi_handler_t addr
, int srs
)
1324 unsigned long handler
;
1325 unsigned long old_handler
= vi_handlers
[n
];
1326 int srssets
= current_cpu_data
.srsets
;
1330 BUG_ON(!cpu_has_veic
&& !cpu_has_vint
);
1333 handler
= (unsigned long) do_default_vi
;
1336 handler
= (unsigned long) addr
;
1337 vi_handlers
[n
] = (unsigned long) addr
;
1339 b
= (unsigned char *)(ebase
+ 0x200 + n
*VECTORSPACING
);
1342 panic("Shadow register set %d not supported", srs
);
1345 if (board_bind_eic_interrupt
)
1346 board_bind_eic_interrupt(n
, srs
);
1347 } else if (cpu_has_vint
) {
1348 /* SRSMap is only defined if shadow sets are implemented */
1350 change_c0_srsmap(0xf << n
*4, srs
<< n
*4);
1355 * If no shadow set is selected then use the default handler
1356 * that does normal register saving and a standard interrupt exit
1359 extern char except_vec_vi
, except_vec_vi_lui
;
1360 extern char except_vec_vi_ori
, except_vec_vi_end
;
1361 extern char rollback_except_vec_vi
;
1362 char *vec_start
= (cpu_wait
== r4k_wait
) ?
1363 &rollback_except_vec_vi
: &except_vec_vi
;
1364 #ifdef CONFIG_MIPS_MT_SMTC
1366 * We need to provide the SMTC vectored interrupt handler
1367 * not only with the address of the handler, but with the
1368 * Status.IM bit to be masked before going there.
1370 extern char except_vec_vi_mori
;
1371 const int mori_offset
= &except_vec_vi_mori
- vec_start
;
1372 #endif /* CONFIG_MIPS_MT_SMTC */
1373 const int handler_len
= &except_vec_vi_end
- vec_start
;
1374 const int lui_offset
= &except_vec_vi_lui
- vec_start
;
1375 const int ori_offset
= &except_vec_vi_ori
- vec_start
;
1377 if (handler_len
> VECTORSPACING
) {
1379 * Sigh... panicing won't help as the console
1380 * is probably not configured :(
1382 panic("VECTORSPACING too small");
1385 memcpy(b
, vec_start
, handler_len
);
1386 #ifdef CONFIG_MIPS_MT_SMTC
1387 BUG_ON(n
> 7); /* Vector index %d exceeds SMTC maximum. */
1389 w
= (u32
*)(b
+ mori_offset
);
1390 *w
= (*w
& 0xffff0000) | (0x100 << n
);
1391 #endif /* CONFIG_MIPS_MT_SMTC */
1392 w
= (u32
*)(b
+ lui_offset
);
1393 *w
= (*w
& 0xffff0000) | (((u32
)handler
>> 16) & 0xffff);
1394 w
= (u32
*)(b
+ ori_offset
);
1395 *w
= (*w
& 0xffff0000) | ((u32
)handler
& 0xffff);
1396 local_flush_icache_range((unsigned long)b
,
1397 (unsigned long)(b
+handler_len
));
1401 * In other cases jump directly to the interrupt handler
1403 * It is the handlers responsibility to save registers if required
1404 * (eg hi/lo) and return from the exception using "eret"
1407 *w
++ = 0x08000000 | (((u32
)handler
>> 2) & 0x03fffff); /* j handler */
1409 local_flush_icache_range((unsigned long)b
,
1410 (unsigned long)(b
+8));
1413 return (void *)old_handler
;
1416 void *set_vi_handler(int n
, vi_handler_t addr
)
1418 return set_vi_srs_handler(n
, addr
, 0);
1421 extern void cpu_cache_init(void);
1422 extern void tlb_init(void);
1423 extern void flush_tlb_handlers(void);
1428 int cp0_compare_irq
;
1429 int cp0_compare_irq_shift
;
1432 * Performance counter IRQ or -1 if shared with timer
1434 int cp0_perfcount_irq
;
1435 EXPORT_SYMBOL_GPL(cp0_perfcount_irq
);
1437 static int __cpuinitdata noulri
;
1439 static int __init
ulri_disable(char *s
)
1441 pr_info("Disabling ulri\n");
1446 __setup("noulri", ulri_disable
);
1448 void __cpuinit
per_cpu_trap_init(void)
1450 unsigned int cpu
= smp_processor_id();
1451 unsigned int status_set
= ST0_CU0
;
1452 #ifdef CONFIG_MIPS_MT_SMTC
1453 int secondaryTC
= 0;
1454 int bootTC
= (cpu
== 0);
1457 * Only do per_cpu_trap_init() for first TC of Each VPE.
1458 * Note that this hack assumes that the SMTC init code
1459 * assigns TCs consecutively and in ascending order.
1462 if (((read_c0_tcbind() & TCBIND_CURTC
) != 0) &&
1463 ((read_c0_tcbind() & TCBIND_CURVPE
) == cpu_data
[cpu
- 1].vpe_id
))
1465 #endif /* CONFIG_MIPS_MT_SMTC */
1468 * Disable coprocessors and select 32-bit or 64-bit addressing
1469 * and the 16/32 or 32/32 FPR register model. Reset the BEV
1470 * flag that some firmware may have left set and the TS bit (for
1471 * IP27). Set XX for ISA IV code to work.
1474 status_set
|= ST0_FR
|ST0_KX
|ST0_SX
|ST0_UX
;
1476 if (current_cpu_data
.isa_level
== MIPS_CPU_ISA_IV
)
1477 status_set
|= ST0_XX
;
1479 status_set
|= ST0_MX
;
1481 change_c0_status(ST0_CU
|ST0_MX
|ST0_RE
|ST0_FR
|ST0_BEV
|ST0_TS
|ST0_KX
|ST0_SX
|ST0_UX
,
1484 if (cpu_has_mips_r2
) {
1485 unsigned int enable
= 0x0000000f | cpu_hwrena_impl_bits
;
1487 if (!noulri
&& cpu_has_userlocal
)
1488 enable
|= (1 << 29);
1490 write_c0_hwrena(enable
);
1493 #ifdef CONFIG_MIPS_MT_SMTC
1495 #endif /* CONFIG_MIPS_MT_SMTC */
1497 if (cpu_has_veic
|| cpu_has_vint
) {
1498 unsigned long sr
= set_c0_status(ST0_BEV
);
1499 write_c0_ebase(ebase
);
1500 write_c0_status(sr
);
1501 /* Setting vector spacing enables EI/VI mode */
1502 change_c0_intctl(0x3e0, VECTORSPACING
);
1504 if (cpu_has_divec
) {
1505 if (cpu_has_mipsmt
) {
1506 unsigned int vpflags
= dvpe();
1507 set_c0_cause(CAUSEF_IV
);
1510 set_c0_cause(CAUSEF_IV
);
1514 * Before R2 both interrupt numbers were fixed to 7, so on R2 only:
1516 * o read IntCtl.IPTI to determine the timer interrupt
1517 * o read IntCtl.IPPCI to determine the performance counter interrupt
1519 if (cpu_has_mips_r2
) {
1520 cp0_compare_irq_shift
= CAUSEB_TI
- CAUSEB_IP
;
1521 cp0_compare_irq
= (read_c0_intctl() >> INTCTLB_IPTI
) & 7;
1522 cp0_perfcount_irq
= (read_c0_intctl() >> INTCTLB_IPPCI
) & 7;
1523 if (cp0_perfcount_irq
== cp0_compare_irq
)
1524 cp0_perfcount_irq
= -1;
1526 cp0_compare_irq
= CP0_LEGACY_COMPARE_IRQ
;
1527 cp0_compare_irq_shift
= cp0_compare_irq
;
1528 cp0_perfcount_irq
= -1;
1531 #ifdef CONFIG_MIPS_MT_SMTC
1533 #endif /* CONFIG_MIPS_MT_SMTC */
1535 cpu_data
[cpu
].asid_cache
= ASID_FIRST_VERSION
;
1536 TLBMISS_HANDLER_SETUP();
1538 atomic_inc(&init_mm
.mm_count
);
1539 current
->active_mm
= &init_mm
;
1540 BUG_ON(current
->mm
);
1541 enter_lazy_tlb(&init_mm
, current
);
1543 #ifdef CONFIG_MIPS_MT_SMTC
1545 #endif /* CONFIG_MIPS_MT_SMTC */
1548 #ifdef CONFIG_MIPS_MT_SMTC
1549 } else if (!secondaryTC
) {
1551 * First TC in non-boot VPE must do subset of tlb_init()
1552 * for MMU countrol registers.
1554 write_c0_pagemask(PM_DEFAULT_MASK
);
1557 #endif /* CONFIG_MIPS_MT_SMTC */
1560 /* Install CPU exception handler */
1561 void __init
set_handler(unsigned long offset
, void *addr
, unsigned long size
)
1563 memcpy((void *)(ebase
+ offset
), addr
, size
);
1564 local_flush_icache_range(ebase
+ offset
, ebase
+ offset
+ size
);
1567 static char panic_null_cerr
[] __cpuinitdata
=
1568 "Trying to set NULL cache error exception handler";
1571 * Install uncached CPU exception handler.
1572 * This is suitable only for the cache error exception which is the only
1573 * exception handler that is being run uncached.
1575 void __cpuinit
set_uncached_handler(unsigned long offset
, void *addr
,
1578 unsigned long uncached_ebase
= CKSEG1ADDR(ebase
);
1581 panic(panic_null_cerr
);
1583 memcpy((void *)(uncached_ebase
+ offset
), addr
, size
);
1586 static int __initdata rdhwr_noopt
;
1587 static int __init
set_rdhwr_noopt(char *str
)
1593 __setup("rdhwr_noopt", set_rdhwr_noopt
);
1595 void __init
trap_init(void)
1597 extern char except_vec3_generic
, except_vec3_r4000
;
1598 extern char except_vec4
;
1603 rollback
= (cpu_wait
== r4k_wait
);
1605 #if defined(CONFIG_KGDB)
1606 if (kgdb_early_setup
)
1607 return; /* Already done */
1610 if (cpu_has_veic
|| cpu_has_vint
) {
1611 unsigned long size
= 0x200 + VECTORSPACING
*64;
1612 ebase
= (unsigned long)
1613 __alloc_bootmem(size
, 1 << fls(size
), 0);
1616 if (cpu_has_mips_r2
)
1617 ebase
+= (read_c0_ebase() & 0x3ffff000);
1620 per_cpu_trap_init();
1623 * Copy the generic exception handlers to their final destination.
1624 * This will be overriden later as suitable for a particular
1627 set_handler(0x180, &except_vec3_generic
, 0x80);
1630 * Setup default vectors
1632 for (i
= 0; i
<= 31; i
++)
1633 set_except_vector(i
, handle_reserved
);
1636 * Copy the EJTAG debug exception vector handler code to it's final
1639 if (cpu_has_ejtag
&& board_ejtag_handler_setup
)
1640 board_ejtag_handler_setup();
1643 * Only some CPUs have the watch exceptions.
1646 set_except_vector(23, handle_watch
);
1649 * Initialise interrupt handlers
1651 if (cpu_has_veic
|| cpu_has_vint
) {
1652 int nvec
= cpu_has_veic
? 64 : 8;
1653 for (i
= 0; i
< nvec
; i
++)
1654 set_vi_handler(i
, NULL
);
1656 else if (cpu_has_divec
)
1657 set_handler(0x200, &except_vec4
, 0x8);
1660 * Some CPUs can enable/disable for cache parity detection, but does
1661 * it different ways.
1663 parity_protection_init();
1666 * The Data Bus Errors / Instruction Bus Errors are signaled
1667 * by external hardware. Therefore these two exceptions
1668 * may have board specific handlers.
1673 set_except_vector(0, rollback
? rollback_handle_int
: handle_int
);
1674 set_except_vector(1, handle_tlbm
);
1675 set_except_vector(2, handle_tlbl
);
1676 set_except_vector(3, handle_tlbs
);
1678 set_except_vector(4, handle_adel
);
1679 set_except_vector(5, handle_ades
);
1681 set_except_vector(6, handle_ibe
);
1682 set_except_vector(7, handle_dbe
);
1684 set_except_vector(8, handle_sys
);
1685 set_except_vector(9, handle_bp
);
1686 set_except_vector(10, rdhwr_noopt
? handle_ri
:
1687 (cpu_has_vtag_icache
?
1688 handle_ri_rdhwr_vivt
: handle_ri_rdhwr
));
1689 set_except_vector(11, handle_cpu
);
1690 set_except_vector(12, handle_ov
);
1691 set_except_vector(13, handle_tr
);
1693 if (current_cpu_type() == CPU_R6000
||
1694 current_cpu_type() == CPU_R6000A
) {
1696 * The R6000 is the only R-series CPU that features a machine
1697 * check exception (similar to the R4000 cache error) and
1698 * unaligned ldc1/sdc1 exception. The handlers have not been
1699 * written yet. Well, anyway there is no R6000 machine on the
1700 * current list of targets for Linux/MIPS.
1701 * (Duh, crap, there is someone with a triple R6k machine)
1703 //set_except_vector(14, handle_mc);
1704 //set_except_vector(15, handle_ndc);
1708 if (board_nmi_handler_setup
)
1709 board_nmi_handler_setup();
1711 if (cpu_has_fpu
&& !cpu_has_nofpuex
)
1712 set_except_vector(15, handle_fpe
);
1714 set_except_vector(22, handle_mdmx
);
1717 set_except_vector(24, handle_mcheck
);
1720 set_except_vector(25, handle_mt
);
1722 set_except_vector(26, handle_dsp
);
1725 /* Special exception: R4[04]00 uses also the divec space. */
1726 memcpy((void *)(ebase
+ 0x180), &except_vec3_r4000
, 0x100);
1727 else if (cpu_has_4kex
)
1728 memcpy((void *)(ebase
+ 0x180), &except_vec3_generic
, 0x80);
1730 memcpy((void *)(ebase
+ 0x080), &except_vec3_generic
, 0x80);
1732 local_flush_icache_range(ebase
, ebase
+ 0x400);
1733 flush_tlb_handlers();
1735 sort_extable(__start___dbe_table
, __stop___dbe_table
);
1737 register_cu2_notifier(&default_cu2_notifier
);