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[PATCH] Char: timers cleanup
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / char / synclinkmp.c
blobef93d055bdd79dc64ba7889b64e87e2a67f3c597
1 /*
2 * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
3 *
4 * Device driver for Microgate SyncLink Multiport
5 * high speed multiprotocol serial adapter.
6 *
7 * written by Paul Fulghum for Microgate Corporation
8 * paulkf@microgate.com
9 *
10 * Microgate and SyncLink are trademarks of Microgate Corporation
11 *
12 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
13 * This code is released under the GNU General Public License (GPL)
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
25 * OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
29 #if defined(__i386__)
30 # define BREAKPOINT() asm(" int $3");
31 #else
32 # define BREAKPOINT() { }
33 #endif
34
35 #define MAX_DEVICES 12
36
37 #include <linux/module.h>
38 #include <linux/errno.h>
39 #include <linux/signal.h>
40 #include <linux/sched.h>
41 #include <linux/timer.h>
42 #include <linux/interrupt.h>
43 #include <linux/pci.h>
44 #include <linux/tty.h>
45 #include <linux/tty_flip.h>
46 #include <linux/serial.h>
47 #include <linux/major.h>
48 #include <linux/string.h>
49 #include <linux/fcntl.h>
50 #include <linux/ptrace.h>
51 #include <linux/ioport.h>
52 #include <linux/mm.h>
53 #include <linux/slab.h>
54 #include <linux/netdevice.h>
55 #include <linux/vmalloc.h>
56 #include <linux/init.h>
57 #include <linux/delay.h>
58 #include <linux/ioctl.h>
59
60 #include <asm/system.h>
61 #include <asm/io.h>
62 #include <asm/irq.h>
63 #include <asm/dma.h>
64 #include <linux/bitops.h>
65 #include <asm/types.h>
66 #include <linux/termios.h>
67 #include <linux/workqueue.h>
68 #include <linux/hdlc.h>
69
70 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE))
71 #define SYNCLINK_GENERIC_HDLC 1
72 #else
73 #define SYNCLINK_GENERIC_HDLC 0
74 #endif
75
76 #define GET_USER(error,value,addr) error = get_user(value,addr)
77 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
78 #define PUT_USER(error,value,addr) error = put_user(value,addr)
79 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
80
81 #include <asm/uaccess.h>
82
83 #include "linux/synclink.h"
84
85 static MGSL_PARAMS default_params = {
86 MGSL_MODE_HDLC, /* unsigned long mode */
87 0, /* unsigned char loopback; */
88 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
89 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
90 0, /* unsigned long clock_speed; */
91 0xff, /* unsigned char addr_filter; */
92 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
93 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
94 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
95 9600, /* unsigned long data_rate; */
96 8, /* unsigned char data_bits; */
97 1, /* unsigned char stop_bits; */
98 ASYNC_PARITY_NONE /* unsigned char parity; */
99 };
100
101 /* size in bytes of DMA data buffers */
102 #define SCABUFSIZE 1024
103 #define SCA_MEM_SIZE 0x40000
104 #define SCA_BASE_SIZE 512
105 #define SCA_REG_SIZE 16
106 #define SCA_MAX_PORTS 4
107 #define SCAMAXDESC 128
108
109 #define BUFFERLISTSIZE 4096
110
111 /* SCA-I style DMA buffer descriptor */
112 typedef struct _SCADESC
113 {
114 u16 next; /* lower l6 bits of next descriptor addr */
115 u16 buf_ptr; /* lower 16 bits of buffer addr */
116 u8 buf_base; /* upper 8 bits of buffer addr */
117 u8 pad1;
118 u16 length; /* length of buffer */
119 u8 status; /* status of buffer */
120 u8 pad2;
121 } SCADESC, *PSCADESC;
122
123 typedef struct _SCADESC_EX
124 {
125 /* device driver bookkeeping section */
126 char *virt_addr; /* virtual address of data buffer */
127 u16 phys_entry; /* lower 16-bits of physical address of this descriptor */
128 } SCADESC_EX, *PSCADESC_EX;
129
130 /* The queue of BH actions to be performed */
131
132 #define BH_RECEIVE 1
133 #define BH_TRANSMIT 2
134 #define BH_STATUS 4
135
136 #define IO_PIN_SHUTDOWN_LIMIT 100
137
138 #define RELEVANT_IFLAG(iflag) (iflag & (IGNBRK|BRKINT|IGNPAR|PARMRK|INPCK))
139
140 struct _input_signal_events {
141 int ri_up;
142 int ri_down;
143 int dsr_up;
144 int dsr_down;
145 int dcd_up;
146 int dcd_down;
147 int cts_up;
148 int cts_down;
149 };
150
151 /*
152 * Device instance data structure
153 */
154 typedef struct _synclinkmp_info {
155 void *if_ptr; /* General purpose pointer (used by SPPP) */
156 int magic;
157 int flags;
158 int count; /* count of opens */
159 int line;
160 unsigned short close_delay;
161 unsigned short closing_wait; /* time to wait before closing */
162
163 struct mgsl_icount icount;
164
165 struct tty_struct *tty;
166 int timeout;
167 int x_char; /* xon/xoff character */
168 int blocked_open; /* # of blocked opens */
169 u16 read_status_mask1; /* break detection (SR1 indications) */
170 u16 read_status_mask2; /* parity/framing/overun (SR2 indications) */
171 unsigned char ignore_status_mask1; /* break detection (SR1 indications) */
172 unsigned char ignore_status_mask2; /* parity/framing/overun (SR2 indications) */
173 unsigned char *tx_buf;
174 int tx_put;
175 int tx_get;
176 int tx_count;
177
178 wait_queue_head_t open_wait;
179 wait_queue_head_t close_wait;
180
181 wait_queue_head_t status_event_wait_q;
182 wait_queue_head_t event_wait_q;
183 struct timer_list tx_timer; /* HDLC transmit timeout timer */
184 struct _synclinkmp_info *next_device; /* device list link */
185 struct timer_list status_timer; /* input signal status check timer */
186
187 spinlock_t lock; /* spinlock for synchronizing with ISR */
188 struct work_struct task; /* task structure for scheduling bh */
189
190 u32 max_frame_size; /* as set by device config */
191
192 u32 pending_bh;
193
194 int bh_running; /* Protection from multiple */
195 int isr_overflow;
196 int bh_requested;
197
198 int dcd_chkcount; /* check counts to prevent */
199 int cts_chkcount; /* too many IRQs if a signal */
200 int dsr_chkcount; /* is floating */
201 int ri_chkcount;
202
203 char *buffer_list; /* virtual address of Rx & Tx buffer lists */
204 unsigned long buffer_list_phys;
205
206 unsigned int rx_buf_count; /* count of total allocated Rx buffers */
207 SCADESC *rx_buf_list; /* list of receive buffer entries */
208 SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
209 unsigned int current_rx_buf;
210
211 unsigned int tx_buf_count; /* count of total allocated Tx buffers */
212 SCADESC *tx_buf_list; /* list of transmit buffer entries */
213 SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
214 unsigned int last_tx_buf;
215
216 unsigned char *tmp_rx_buf;
217 unsigned int tmp_rx_buf_count;
218
219 int rx_enabled;
220 int rx_overflow;
221
222 int tx_enabled;
223 int tx_active;
224 u32 idle_mode;
225
226 unsigned char ie0_value;
227 unsigned char ie1_value;
228 unsigned char ie2_value;
229 unsigned char ctrlreg_value;
230 unsigned char old_signals;
231
232 char device_name[25]; /* device instance name */
233
234 int port_count;
235 int adapter_num;
236 int port_num;
237
238 struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
239
240 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
241
242 unsigned int irq_level; /* interrupt level */
243 unsigned long irq_flags;
244 int irq_requested; /* nonzero if IRQ requested */
245
246 MGSL_PARAMS params; /* communications parameters */
247
248 unsigned char serial_signals; /* current serial signal states */
249
250 int irq_occurred; /* for diagnostics use */
251 unsigned int init_error; /* Initialization startup error */
252
253 u32 last_mem_alloc;
254 unsigned char* memory_base; /* shared memory address (PCI only) */
255 u32 phys_memory_base;
256 int shared_mem_requested;
257
258 unsigned char* sca_base; /* HD64570 SCA Memory address */
259 u32 phys_sca_base;
260 u32 sca_offset;
261 int sca_base_requested;
262
263 unsigned char* lcr_base; /* local config registers (PCI only) */
264 u32 phys_lcr_base;
265 u32 lcr_offset;
266 int lcr_mem_requested;
267
268 unsigned char* statctrl_base; /* status/control register memory */
269 u32 phys_statctrl_base;
270 u32 statctrl_offset;
271 int sca_statctrl_requested;
272
273 u32 misc_ctrl_value;
274 char flag_buf[MAX_ASYNC_BUFFER_SIZE];
275 char char_buf[MAX_ASYNC_BUFFER_SIZE];
276 BOOLEAN drop_rts_on_tx_done;
277
278 struct _input_signal_events input_signal_events;
279
280 /* SPPP/Cisco HDLC device parts */
281 int netcount;
282 int dosyncppp;
283 spinlock_t netlock;
284
285 #if SYNCLINK_GENERIC_HDLC
286 struct net_device *netdev;
287 #endif
288
289 } SLMP_INFO;
290
291 #define MGSL_MAGIC 0x5401
292
293 /*
294 * define serial signal status change macros
295 */
296 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) /* indicates change in DCD */
297 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) /* indicates change in RI */
298 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) /* indicates change in CTS */
299 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) /* change in DSR */
300
301 /* Common Register macros */
302 #define LPR 0x00
303 #define PABR0 0x02
304 #define PABR1 0x03
305 #define WCRL 0x04
306 #define WCRM 0x05
307 #define WCRH 0x06
308 #define DPCR 0x08
309 #define DMER 0x09
310 #define ISR0 0x10
311 #define ISR1 0x11
312 #define ISR2 0x12
313 #define IER0 0x14
314 #define IER1 0x15
315 #define IER2 0x16
316 #define ITCR 0x18
317 #define INTVR 0x1a
318 #define IMVR 0x1c
319
320 /* MSCI Register macros */
321 #define TRB 0x20
322 #define TRBL 0x20
323 #define TRBH 0x21
324 #define SR0 0x22
325 #define SR1 0x23
326 #define SR2 0x24
327 #define SR3 0x25
328 #define FST 0x26
329 #define IE0 0x28
330 #define IE1 0x29
331 #define IE2 0x2a
332 #define FIE 0x2b
333 #define CMD 0x2c
334 #define MD0 0x2e
335 #define MD1 0x2f
336 #define MD2 0x30
337 #define CTL 0x31
338 #define SA0 0x32
339 #define SA1 0x33
340 #define IDL 0x34
341 #define TMC 0x35
342 #define RXS 0x36
343 #define TXS 0x37
344 #define TRC0 0x38
345 #define TRC1 0x39
346 #define RRC 0x3a
347 #define CST0 0x3c
348 #define CST1 0x3d
349
350 /* Timer Register Macros */
351 #define TCNT 0x60
352 #define TCNTL 0x60
353 #define TCNTH 0x61
354 #define TCONR 0x62
355 #define TCONRL 0x62
356 #define TCONRH 0x63
357 #define TMCS 0x64
358 #define TEPR 0x65
359
360 /* DMA Controller Register macros */
361 #define DARL 0x80
362 #define DARH 0x81
363 #define DARB 0x82
364 #define BAR 0x80
365 #define BARL 0x80
366 #define BARH 0x81
367 #define BARB 0x82
368 #define SAR 0x84
369 #define SARL 0x84
370 #define SARH 0x85
371 #define SARB 0x86
372 #define CPB 0x86
373 #define CDA 0x88
374 #define CDAL 0x88
375 #define CDAH 0x89
376 #define EDA 0x8a
377 #define EDAL 0x8a
378 #define EDAH 0x8b
379 #define BFL 0x8c
380 #define BFLL 0x8c
381 #define BFLH 0x8d
382 #define BCR 0x8e
383 #define BCRL 0x8e
384 #define BCRH 0x8f
385 #define DSR 0x90
386 #define DMR 0x91
387 #define FCT 0x93
388 #define DIR 0x94
389 #define DCMD 0x95
390
391 /* combine with timer or DMA register address */
392 #define TIMER0 0x00
393 #define TIMER1 0x08
394 #define TIMER2 0x10
395 #define TIMER3 0x18
396 #define RXDMA 0x00
397 #define TXDMA 0x20
398
399 /* SCA Command Codes */
400 #define NOOP 0x00
401 #define TXRESET 0x01
402 #define TXENABLE 0x02
403 #define TXDISABLE 0x03
404 #define TXCRCINIT 0x04
405 #define TXCRCEXCL 0x05
406 #define TXEOM 0x06
407 #define TXABORT 0x07
408 #define MPON 0x08
409 #define TXBUFCLR 0x09
410 #define RXRESET 0x11
411 #define RXENABLE 0x12
412 #define RXDISABLE 0x13
413 #define RXCRCINIT 0x14
414 #define RXREJECT 0x15
415 #define SEARCHMP 0x16
416 #define RXCRCEXCL 0x17
417 #define RXCRCCALC 0x18
418 #define CHRESET 0x21
419 #define HUNT 0x31
420
421 /* DMA command codes */
422 #define SWABORT 0x01
423 #define FEICLEAR 0x02
424
425 /* IE0 */
426 #define TXINTE BIT7
427 #define RXINTE BIT6
428 #define TXRDYE BIT1
429 #define RXRDYE BIT0
430
431 /* IE1 & SR1 */
432 #define UDRN BIT7
433 #define IDLE BIT6
434 #define SYNCD BIT4
435 #define FLGD BIT4
436 #define CCTS BIT3
437 #define CDCD BIT2
438 #define BRKD BIT1
439 #define ABTD BIT1
440 #define GAPD BIT1
441 #define BRKE BIT0
442 #define IDLD BIT0
443
444 /* IE2 & SR2 */
445 #define EOM BIT7
446 #define PMP BIT6
447 #define SHRT BIT6
448 #define PE BIT5
449 #define ABT BIT5
450 #define FRME BIT4
451 #define RBIT BIT4
452 #define OVRN BIT3
453 #define CRCE BIT2
454
455
456 /*
457 * Global linked list of SyncLink devices
458 */
459 static SLMP_INFO *synclinkmp_device_list = NULL;
460 static int synclinkmp_adapter_count = -1;
461 static int synclinkmp_device_count = 0;
462
463 /*
464 * Set this param to non-zero to load eax with the
465 * .text section address and breakpoint on module load.
466 * This is useful for use with gdb and add-symbol-file command.
467 */
468 static int break_on_load=0;
469
470 /*
471 * Driver major number, defaults to zero to get auto
472 * assigned major number. May be forced as module parameter.
473 */
474 static int ttymajor=0;
475
476 /*
477 * Array of user specified options for ISA adapters.
478 */
479 static int debug_level = 0;
480 static int maxframe[MAX_DEVICES] = {0,};
481 static int dosyncppp[MAX_DEVICES] = {0,};
482
483 module_param(break_on_load, bool, 0);
484 module_param(ttymajor, int, 0);
485 module_param(debug_level, int, 0);
486 module_param_array(maxframe, int, NULL, 0);
487 module_param_array(dosyncppp, int, NULL, 0);
488
489 static char *driver_name = "SyncLink MultiPort driver";
490 static char *driver_version = "$Revision: 4.38 $";
491
492 static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
493 static void synclinkmp_remove_one(struct pci_dev *dev);
494
495 static struct pci_device_id synclinkmp_pci_tbl[] = {
496 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
497 { 0, }, /* terminate list */
498 };
499 MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
500
501 MODULE_LICENSE("GPL");
502
503 static struct pci_driver synclinkmp_pci_driver = {
504 .name = "synclinkmp",
505 .id_table = synclinkmp_pci_tbl,
506 .probe = synclinkmp_init_one,
507 .remove = __devexit_p(synclinkmp_remove_one),
508 };
509
510
511 static struct tty_driver *serial_driver;
512
513 /* number of characters left in xmit buffer before we ask for more */
514 #define WAKEUP_CHARS 256
515
516
517 /* tty callbacks */
518
519 static int open(struct tty_struct *tty, struct file * filp);
520 static void close(struct tty_struct *tty, struct file * filp);
521 static void hangup(struct tty_struct *tty);
522 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
523
524 static int write(struct tty_struct *tty, const unsigned char *buf, int count);
525 static void put_char(struct tty_struct *tty, unsigned char ch);
526 static void send_xchar(struct tty_struct *tty, char ch);
527 static void wait_until_sent(struct tty_struct *tty, int timeout);
528 static int write_room(struct tty_struct *tty);
529 static void flush_chars(struct tty_struct *tty);
530 static void flush_buffer(struct tty_struct *tty);
531 static void tx_hold(struct tty_struct *tty);
532 static void tx_release(struct tty_struct *tty);
533
534 static int ioctl(struct tty_struct *tty, struct file *file, unsigned int cmd, unsigned long arg);
535 static int read_proc(char *page, char **start, off_t off, int count,int *eof, void *data);
536 static int chars_in_buffer(struct tty_struct *tty);
537 static void throttle(struct tty_struct * tty);
538 static void unthrottle(struct tty_struct * tty);
539 static void set_break(struct tty_struct *tty, int break_state);
540
541 #if SYNCLINK_GENERIC_HDLC
542 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
543 static void hdlcdev_tx_done(SLMP_INFO *info);
544 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
545 static int hdlcdev_init(SLMP_INFO *info);
546 static void hdlcdev_exit(SLMP_INFO *info);
547 #endif
548
549 /* ioctl handlers */
550
551 static int get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
552 static int get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
553 static int set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
554 static int get_txidle(SLMP_INFO *info, int __user *idle_mode);
555 static int set_txidle(SLMP_INFO *info, int idle_mode);
556 static int tx_enable(SLMP_INFO *info, int enable);
557 static int tx_abort(SLMP_INFO *info);
558 static int rx_enable(SLMP_INFO *info, int enable);
559 static int modem_input_wait(SLMP_INFO *info,int arg);
560 static int wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
561 static int tiocmget(struct tty_struct *tty, struct file *file);
562 static int tiocmset(struct tty_struct *tty, struct file *file,
563 unsigned int set, unsigned int clear);
564 static void set_break(struct tty_struct *tty, int break_state);
565
566 static void add_device(SLMP_INFO *info);
567 static void device_init(int adapter_num, struct pci_dev *pdev);
568 static int claim_resources(SLMP_INFO *info);
569 static void release_resources(SLMP_INFO *info);
570
571 static int startup(SLMP_INFO *info);
572 static int block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
573 static void shutdown(SLMP_INFO *info);
574 static void program_hw(SLMP_INFO *info);
575 static void change_params(SLMP_INFO *info);
576
577 static int init_adapter(SLMP_INFO *info);
578 static int register_test(SLMP_INFO *info);
579 static int irq_test(SLMP_INFO *info);
580 static int loopback_test(SLMP_INFO *info);
581 static int adapter_test(SLMP_INFO *info);
582 static int memory_test(SLMP_INFO *info);
583
584 static void reset_adapter(SLMP_INFO *info);
585 static void reset_port(SLMP_INFO *info);
586 static void async_mode(SLMP_INFO *info);
587 static void hdlc_mode(SLMP_INFO *info);
588
589 static void rx_stop(SLMP_INFO *info);
590 static void rx_start(SLMP_INFO *info);
591 static void rx_reset_buffers(SLMP_INFO *info);
592 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
593 static int rx_get_frame(SLMP_INFO *info);
594
595 static void tx_start(SLMP_INFO *info);
596 static void tx_stop(SLMP_INFO *info);
597 static void tx_load_fifo(SLMP_INFO *info);
598 static void tx_set_idle(SLMP_INFO *info);
599 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
600
601 static void get_signals(SLMP_INFO *info);
602 static void set_signals(SLMP_INFO *info);
603 static void enable_loopback(SLMP_INFO *info, int enable);
604 static void set_rate(SLMP_INFO *info, u32 data_rate);
605
606 static int bh_action(SLMP_INFO *info);
607 static void bh_handler(struct work_struct *work);
608 static void bh_receive(SLMP_INFO *info);
609 static void bh_transmit(SLMP_INFO *info);
610 static void bh_status(SLMP_INFO *info);
611 static void isr_timer(SLMP_INFO *info);
612 static void isr_rxint(SLMP_INFO *info);
613 static void isr_rxrdy(SLMP_INFO *info);
614 static void isr_txint(SLMP_INFO *info);
615 static void isr_txrdy(SLMP_INFO *info);
616 static void isr_rxdmaok(SLMP_INFO *info);
617 static void isr_rxdmaerror(SLMP_INFO *info);
618 static void isr_txdmaok(SLMP_INFO *info);
619 static void isr_txdmaerror(SLMP_INFO *info);
620 static void isr_io_pin(SLMP_INFO *info, u16 status);
621
622 static int alloc_dma_bufs(SLMP_INFO *info);
623 static void free_dma_bufs(SLMP_INFO *info);
624 static int alloc_buf_list(SLMP_INFO *info);
625 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
626 static int alloc_tmp_rx_buf(SLMP_INFO *info);
627 static void free_tmp_rx_buf(SLMP_INFO *info);
628
629 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
630 static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
631 static void tx_timeout(unsigned long context);
632 static void status_timeout(unsigned long context);
633
634 static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
635 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
636 static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
637 static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
638 static unsigned char read_status_reg(SLMP_INFO * info);
639 static void write_control_reg(SLMP_INFO * info);
640
641
642 static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
643 static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
644 static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
645
646 static u32 misc_ctrl_value = 0x007e4040;
647 static u32 lcr1_brdr_value = 0x00800028;
648
649 static u32 read_ahead_count = 8;
650
651 /* DPCR, DMA Priority Control
652 *
653 * 07..05 Not used, must be 0
654 * 04 BRC, bus release condition: 0=all transfers complete
655 * 1=release after 1 xfer on all channels
656 * 03 CCC, channel change condition: 0=every cycle
657 * 1=after each channel completes all xfers
658 * 02..00 PR<2..0>, priority 100=round robin
659 *
660 * 00000100 = 0x00
661 */
662 static unsigned char dma_priority = 0x04;
663
664 // Number of bytes that can be written to shared RAM
665 // in a single write operation
666 static u32 sca_pci_load_interval = 64;
667
668 /*
669 * 1st function defined in .text section. Calling this function in
670 * init_module() followed by a breakpoint allows a remote debugger
671 * (gdb) to get the .text address for the add-symbol-file command.
672 * This allows remote debugging of dynamically loadable modules.
673 */
674 static void* synclinkmp_get_text_ptr(void);
675 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
676
677 static inline int sanity_check(SLMP_INFO *info,
678 char *name, const char *routine)
679 {
680 #ifdef SANITY_CHECK
681 static const char *badmagic =
682 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
683 static const char *badinfo =
684 "Warning: null synclinkmp_struct for (%s) in %s\n";
685
686 if (!info) {
687 printk(badinfo, name, routine);
688 return 1;
689 }
690 if (info->magic != MGSL_MAGIC) {
691 printk(badmagic, name, routine);
692 return 1;
693 }
694 #else
695 if (!info)
696 return 1;
697 #endif
698 return 0;
699 }
700
701 /**
702 * line discipline callback wrappers
703 *
704 * The wrappers maintain line discipline references
705 * while calling into the line discipline.
706 *
707 * ldisc_receive_buf - pass receive data to line discipline
708 */
709
710 static void ldisc_receive_buf(struct tty_struct *tty,
711 const __u8 *data, char *flags, int count)
712 {
713 struct tty_ldisc *ld;
714 if (!tty)
715 return;
716 ld = tty_ldisc_ref(tty);
717 if (ld) {
718 if (ld->receive_buf)
719 ld->receive_buf(tty, data, flags, count);
720 tty_ldisc_deref(ld);
721 }
722 }
723
724 /* tty callbacks */
725
726 /* Called when a port is opened. Init and enable port.
727 */
728 static int open(struct tty_struct *tty, struct file *filp)
729 {
730 SLMP_INFO *info;
731 int retval, line;
732 unsigned long flags;
733
734 line = tty->index;
735 if ((line < 0) || (line >= synclinkmp_device_count)) {
736 printk("%s(%d): open with invalid line #%d.\n",
737 __FILE__,__LINE__,line);
738 return -ENODEV;
739 }
740
741 info = synclinkmp_device_list;
742 while(info && info->line != line)
743 info = info->next_device;
744 if (sanity_check(info, tty->name, "open"))
745 return -ENODEV;
746 if ( info->init_error ) {
747 printk("%s(%d):%s device is not allocated, init error=%d\n",
748 __FILE__,__LINE__,info->device_name,info->init_error);
749 return -ENODEV;
750 }
751
752 tty->driver_data = info;
753 info->tty = tty;
754
755 if (debug_level >= DEBUG_LEVEL_INFO)
756 printk("%s(%d):%s open(), old ref count = %d\n",
757 __FILE__,__LINE__,tty->driver->name, info->count);
758
759 /* If port is closing, signal caller to try again */
760 if (tty_hung_up_p(filp) || info->flags & ASYNC_CLOSING){
761 if (info->flags & ASYNC_CLOSING)
762 interruptible_sleep_on(&info->close_wait);
763 retval = ((info->flags & ASYNC_HUP_NOTIFY) ?
764 -EAGAIN : -ERESTARTSYS);
765 goto cleanup;
766 }
767
768 info->tty->low_latency = (info->flags & ASYNC_LOW_LATENCY) ? 1 : 0;
769
770 spin_lock_irqsave(&info->netlock, flags);
771 if (info->netcount) {
772 retval = -EBUSY;
773 spin_unlock_irqrestore(&info->netlock, flags);
774 goto cleanup;
775 }
776 info->count++;
777 spin_unlock_irqrestore(&info->netlock, flags);
778
779 if (info->count == 1) {
780 /* 1st open on this device, init hardware */
781 retval = startup(info);
782 if (retval < 0)
783 goto cleanup;
784 }
785
786 retval = block_til_ready(tty, filp, info);
787 if (retval) {
788 if (debug_level >= DEBUG_LEVEL_INFO)
789 printk("%s(%d):%s block_til_ready() returned %d\n",
790 __FILE__,__LINE__, info->device_name, retval);
791 goto cleanup;
792 }
793
794 if (debug_level >= DEBUG_LEVEL_INFO)
795 printk("%s(%d):%s open() success\n",
796 __FILE__,__LINE__, info->device_name);
797 retval = 0;
798
799 cleanup:
800 if (retval) {
801 if (tty->count == 1)
802 info->tty = NULL; /* tty layer will release tty struct */
803 if(info->count)
804 info->count--;
805 }
806
807 return retval;
808 }
809
810 /* Called when port is closed. Wait for remaining data to be
811 * sent. Disable port and free resources.
812 */
813 static void close(struct tty_struct *tty, struct file *filp)
814 {
815 SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
816
817 if (sanity_check(info, tty->name, "close"))
818 return;
819
820 if (debug_level >= DEBUG_LEVEL_INFO)
821 printk("%s(%d):%s close() entry, count=%d\n",
822 __FILE__,__LINE__, info->device_name, info->count);
823
824 if (!info->count)
825 return;
826
827 if (tty_hung_up_p(filp))
828 goto cleanup;
829
830 if ((tty->count == 1) && (info->count != 1)) {
831 /*
832 * tty->count is 1 and the tty structure will be freed.
833 * info->count should be one in this case.
834 * if it's not, correct it so that the port is shutdown.
835 */
836 printk("%s(%d):%s close: bad refcount; tty->count is 1, "
837 "info->count is %d\n",
838 __FILE__,__LINE__, info->device_name, info->count);
839 info->count = 1;
840 }
841
842 info->count--;
843
844 /* if at least one open remaining, leave hardware active */
845 if (info->count)
846 goto cleanup;
847
848 info->flags |= ASYNC_CLOSING;
849
850 /* set tty->closing to notify line discipline to
851 * only process XON/XOFF characters. Only the N_TTY
852 * discipline appears to use this (ppp does not).
853 */
854 tty->closing = 1;
855
856 /* wait for transmit data to clear all layers */
857
858 if (info->closing_wait != ASYNC_CLOSING_WAIT_NONE) {
859 if (debug_level >= DEBUG_LEVEL_INFO)
860 printk("%s(%d):%s close() calling tty_wait_until_sent\n",
861 __FILE__,__LINE__, info->device_name );
862 tty_wait_until_sent(tty, info->closing_wait);
863 }
864
865 if (info->flags & ASYNC_INITIALIZED)
866 wait_until_sent(tty, info->timeout);
867
868 if (tty->driver->flush_buffer)
869 tty->driver->flush_buffer(tty);
870
871 tty_ldisc_flush(tty);
872
873 shutdown(info);
874
875 tty->closing = 0;
876 info->tty = NULL;
877
878 if (info->blocked_open) {
879 if (info->close_delay) {
880 msleep_interruptible(jiffies_to_msecs(info->close_delay));
881 }
882 wake_up_interruptible(&info->open_wait);
883 }
884
885 info->flags &= ~(ASYNC_NORMAL_ACTIVE|ASYNC_CLOSING);
886
887 wake_up_interruptible(&info->close_wait);
888
889 cleanup:
890 if (debug_level >= DEBUG_LEVEL_INFO)
891 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
892 tty->driver->name, info->count);
893 }
894
895 /* Called by tty_hangup() when a hangup is signaled.
896 * This is the same as closing all open descriptors for the port.
897 */
898 static void hangup(struct tty_struct *tty)
899 {
900 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
901
902 if (debug_level >= DEBUG_LEVEL_INFO)
903 printk("%s(%d):%s hangup()\n",
904 __FILE__,__LINE__, info->device_name );
905
906 if (sanity_check(info, tty->name, "hangup"))
907 return;
908
909 flush_buffer(tty);
910 shutdown(info);
911
912 info->count = 0;
913 info->flags &= ~ASYNC_NORMAL_ACTIVE;
914 info->tty = NULL;
915
916 wake_up_interruptible(&info->open_wait);
917 }
918
919 /* Set new termios settings
920 */
921 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
922 {
923 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
924 unsigned long flags;
925
926 if (debug_level >= DEBUG_LEVEL_INFO)
927 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
928 tty->driver->name );
929
930 /* just return if nothing has changed */
931 if ((tty->termios->c_cflag == old_termios->c_cflag)
932 && (RELEVANT_IFLAG(tty->termios->c_iflag)
933 == RELEVANT_IFLAG(old_termios->c_iflag)))
934 return;
935
936 change_params(info);
937
938 /* Handle transition to B0 status */
939 if (old_termios->c_cflag & CBAUD &&
940 !(tty->termios->c_cflag & CBAUD)) {
941 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
942 spin_lock_irqsave(&info->lock,flags);
943 set_signals(info);
944 spin_unlock_irqrestore(&info->lock,flags);
945 }
946
947 /* Handle transition away from B0 status */
948 if (!(old_termios->c_cflag & CBAUD) &&
949 tty->termios->c_cflag & CBAUD) {
950 info->serial_signals |= SerialSignal_DTR;
951 if (!(tty->termios->c_cflag & CRTSCTS) ||
952 !test_bit(TTY_THROTTLED, &tty->flags)) {
953 info->serial_signals |= SerialSignal_RTS;
954 }
955 spin_lock_irqsave(&info->lock,flags);
956 set_signals(info);
957 spin_unlock_irqrestore(&info->lock,flags);
958 }
959
960 /* Handle turning off CRTSCTS */
961 if (old_termios->c_cflag & CRTSCTS &&
962 !(tty->termios->c_cflag & CRTSCTS)) {
963 tty->hw_stopped = 0;
964 tx_release(tty);
965 }
966 }
967
968 /* Send a block of data
969 *
970 * Arguments:
971 *
972 * tty pointer to tty information structure
973 * buf pointer to buffer containing send data
974 * count size of send data in bytes
975 *
976 * Return Value: number of characters written
977 */
978 static int write(struct tty_struct *tty,
979 const unsigned char *buf, int count)
980 {
981 int c, ret = 0;
982 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
983 unsigned long flags;
984
985 if (debug_level >= DEBUG_LEVEL_INFO)
986 printk("%s(%d):%s write() count=%d\n",
987 __FILE__,__LINE__,info->device_name,count);
988
989 if (sanity_check(info, tty->name, "write"))
990 goto cleanup;
991
992 if (!info->tx_buf)
993 goto cleanup;
994
995 if (info->params.mode == MGSL_MODE_HDLC) {
996 if (count > info->max_frame_size) {
997 ret = -EIO;
998 goto cleanup;
999 }
1000 if (info->tx_active)
1001 goto cleanup;
1002 if (info->tx_count) {
1003 /* send accumulated data from send_char() calls */
1004 /* as frame and wait before accepting more data. */
1005 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1006 goto start;
1007 }
1008 ret = info->tx_count = count;
1009 tx_load_dma_buffer(info, buf, count);
1010 goto start;
1011 }
1012
1013 for (;;) {
1014 c = min_t(int, count,
1015 min(info->max_frame_size - info->tx_count - 1,
1016 info->max_frame_size - info->tx_put));
1017 if (c <= 0)
1018 break;
1019
1020 memcpy(info->tx_buf + info->tx_put, buf, c);
1021
1022 spin_lock_irqsave(&info->lock,flags);
1023 info->tx_put += c;
1024 if (info->tx_put >= info->max_frame_size)
1025 info->tx_put -= info->max_frame_size;
1026 info->tx_count += c;
1027 spin_unlock_irqrestore(&info->lock,flags);
1028
1029 buf += c;
1030 count -= c;
1031 ret += c;
1032 }
1033
1034 if (info->params.mode == MGSL_MODE_HDLC) {
1035 if (count) {
1036 ret = info->tx_count = 0;
1037 goto cleanup;
1038 }
1039 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
1040 }
1041 start:
1042 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
1043 spin_lock_irqsave(&info->lock,flags);
1044 if (!info->tx_active)
1045 tx_start(info);
1046 spin_unlock_irqrestore(&info->lock,flags);
1047 }
1048
1049 cleanup:
1050 if (debug_level >= DEBUG_LEVEL_INFO)
1051 printk( "%s(%d):%s write() returning=%d\n",
1052 __FILE__,__LINE__,info->device_name,ret);
1053 return ret;
1054 }
1055
1056 /* Add a character to the transmit buffer.
1057 */
1058 static void put_char(struct tty_struct *tty, unsigned char ch)
1059 {
1060 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1061 unsigned long flags;
1062
1063 if ( debug_level >= DEBUG_LEVEL_INFO ) {
1064 printk( "%s(%d):%s put_char(%d)\n",
1065 __FILE__,__LINE__,info->device_name,ch);
1066 }
1067
1068 if (sanity_check(info, tty->name, "put_char"))
1069 return;
1070
1071 if (!info->tx_buf)
1072 return;
1073
1074 spin_lock_irqsave(&info->lock,flags);
1075
1076 if ( (info->params.mode != MGSL_MODE_HDLC) ||
1077 !info->tx_active ) {
1078
1079 if (info->tx_count < info->max_frame_size - 1) {
1080 info->tx_buf[info->tx_put++] = ch;
1081 if (info->tx_put >= info->max_frame_size)
1082 info->tx_put -= info->max_frame_size;
1083 info->tx_count++;
1084 }
1085 }
1086
1087 spin_unlock_irqrestore(&info->lock,flags);
1088 }
1089
1090 /* Send a high-priority XON/XOFF character
1091 */
1092 static void send_xchar(struct tty_struct *tty, char ch)
1093 {
1094 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1095 unsigned long flags;
1096
1097 if (debug_level >= DEBUG_LEVEL_INFO)
1098 printk("%s(%d):%s send_xchar(%d)\n",
1099 __FILE__,__LINE__, info->device_name, ch );
1100
1101 if (sanity_check(info, tty->name, "send_xchar"))
1102 return;
1103
1104 info->x_char = ch;
1105 if (ch) {
1106 /* Make sure transmit interrupts are on */
1107 spin_lock_irqsave(&info->lock,flags);
1108 if (!info->tx_enabled)
1109 tx_start(info);
1110 spin_unlock_irqrestore(&info->lock,flags);
1111 }
1112 }
1113
1114 /* Wait until the transmitter is empty.
1115 */
1116 static void wait_until_sent(struct tty_struct *tty, int timeout)
1117 {
1118 SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1119 unsigned long orig_jiffies, char_time;
1120
1121 if (!info )
1122 return;
1123
1124 if (debug_level >= DEBUG_LEVEL_INFO)
1125 printk("%s(%d):%s wait_until_sent() entry\n",
1126 __FILE__,__LINE__, info->device_name );
1127
1128 if (sanity_check(info, tty->name, "wait_until_sent"))
1129 return;
1130
1131 if (!(info->flags & ASYNC_INITIALIZED))
1132 goto exit;
1133
1134 orig_jiffies = jiffies;
1135
1136 /* Set check interval to 1/5 of estimated time to
1137 * send a character, and make it at least 1. The check
1138 * interval should also be less than the timeout.
1139 * Note: use tight timings here to satisfy the NIST-PCTS.
1140 */
1141
1142 if ( info->params.data_rate ) {
1143 char_time = info->timeout/(32 * 5);
1144 if (!char_time)
1145 char_time++;
1146 } else
1147 char_time = 1;
1148
1149 if (timeout)
1150 char_time = min_t(unsigned long, char_time, timeout);
1151
1152 if ( info->params.mode == MGSL_MODE_HDLC ) {
1153 while (info->tx_active) {
1154 msleep_interruptible(jiffies_to_msecs(char_time));
1155 if (signal_pending(current))
1156 break;
1157 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1158 break;
1159 }
1160 } else {
1161 //TODO: determine if there is something similar to USC16C32
1162 // TXSTATUS_ALL_SENT status
1163 while ( info->tx_active && info->tx_enabled) {
1164 msleep_interruptible(jiffies_to_msecs(char_time));
1165 if (signal_pending(current))
1166 break;
1167 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1168 break;
1169 }
1170 }
1171
1172 exit:
1173 if (debug_level >= DEBUG_LEVEL_INFO)
1174 printk("%s(%d):%s wait_until_sent() exit\n",
1175 __FILE__,__LINE__, info->device_name );
1176 }
1177
1178 /* Return the count of free bytes in transmit buffer
1179 */
1180 static int write_room(struct tty_struct *tty)
1181 {
1182 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1183 int ret;
1184
1185 if (sanity_check(info, tty->name, "write_room"))
1186 return 0;
1187
1188 if (info->params.mode == MGSL_MODE_HDLC) {
1189 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1190 } else {
1191 ret = info->max_frame_size - info->tx_count - 1;
1192 if (ret < 0)
1193 ret = 0;
1194 }
1195
1196 if (debug_level >= DEBUG_LEVEL_INFO)
1197 printk("%s(%d):%s write_room()=%d\n",
1198 __FILE__, __LINE__, info->device_name, ret);
1199
1200 return ret;
1201 }
1202
1203 /* enable transmitter and send remaining buffered characters
1204 */
1205 static void flush_chars(struct tty_struct *tty)
1206 {
1207 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1208 unsigned long flags;
1209
1210 if ( debug_level >= DEBUG_LEVEL_INFO )
1211 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1212 __FILE__,__LINE__,info->device_name,info->tx_count);
1213
1214 if (sanity_check(info, tty->name, "flush_chars"))
1215 return;
1216
1217 if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1218 !info->tx_buf)
1219 return;
1220
1221 if ( debug_level >= DEBUG_LEVEL_INFO )
1222 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1223 __FILE__,__LINE__,info->device_name );
1224
1225 spin_lock_irqsave(&info->lock,flags);
1226
1227 if (!info->tx_active) {
1228 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1229 info->tx_count ) {
1230 /* operating in synchronous (frame oriented) mode */
1231 /* copy data from circular tx_buf to */
1232 /* transmit DMA buffer. */
1233 tx_load_dma_buffer(info,
1234 info->tx_buf,info->tx_count);
1235 }
1236 tx_start(info);
1237 }
1238
1239 spin_unlock_irqrestore(&info->lock,flags);
1240 }
1241
1242 /* Discard all data in the send buffer
1243 */
1244 static void flush_buffer(struct tty_struct *tty)
1245 {
1246 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1247 unsigned long flags;
1248
1249 if (debug_level >= DEBUG_LEVEL_INFO)
1250 printk("%s(%d):%s flush_buffer() entry\n",
1251 __FILE__,__LINE__, info->device_name );
1252
1253 if (sanity_check(info, tty->name, "flush_buffer"))
1254 return;
1255
1256 spin_lock_irqsave(&info->lock,flags);
1257 info->tx_count = info->tx_put = info->tx_get = 0;
1258 del_timer(&info->tx_timer);
1259 spin_unlock_irqrestore(&info->lock,flags);
1260
1261 tty_wakeup(tty);
1262 }
1263
1264 /* throttle (stop) transmitter
1265 */
1266 static void tx_hold(struct tty_struct *tty)
1267 {
1268 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1269 unsigned long flags;
1270
1271 if (sanity_check(info, tty->name, "tx_hold"))
1272 return;
1273
1274 if ( debug_level >= DEBUG_LEVEL_INFO )
1275 printk("%s(%d):%s tx_hold()\n",
1276 __FILE__,__LINE__,info->device_name);
1277
1278 spin_lock_irqsave(&info->lock,flags);
1279 if (info->tx_enabled)
1280 tx_stop(info);
1281 spin_unlock_irqrestore(&info->lock,flags);
1282 }
1283
1284 /* release (start) transmitter
1285 */
1286 static void tx_release(struct tty_struct *tty)
1287 {
1288 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1289 unsigned long flags;
1290
1291 if (sanity_check(info, tty->name, "tx_release"))
1292 return;
1293
1294 if ( debug_level >= DEBUG_LEVEL_INFO )
1295 printk("%s(%d):%s tx_release()\n",
1296 __FILE__,__LINE__,info->device_name);
1297
1298 spin_lock_irqsave(&info->lock,flags);
1299 if (!info->tx_enabled)
1300 tx_start(info);
1301 spin_unlock_irqrestore(&info->lock,flags);
1302 }
1303
1304 /* Service an IOCTL request
1305 *
1306 * Arguments:
1307 *
1308 * tty pointer to tty instance data
1309 * file pointer to associated file object for device
1310 * cmd IOCTL command code
1311 * arg command argument/context
1312 *
1313 * Return Value: 0 if success, otherwise error code
1314 */
1315 static int ioctl(struct tty_struct *tty, struct file *file,
1316 unsigned int cmd, unsigned long arg)
1317 {
1318 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1319 int error;
1320 struct mgsl_icount cnow; /* kernel counter temps */
1321 struct serial_icounter_struct __user *p_cuser; /* user space */
1322 unsigned long flags;
1323 void __user *argp = (void __user *)arg;
1324
1325 if (debug_level >= DEBUG_LEVEL_INFO)
1326 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1327 info->device_name, cmd );
1328
1329 if (sanity_check(info, tty->name, "ioctl"))
1330 return -ENODEV;
1331
1332 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1333 (cmd != TIOCMIWAIT) && (cmd != TIOCGICOUNT)) {
1334 if (tty->flags & (1 << TTY_IO_ERROR))
1335 return -EIO;
1336 }
1337
1338 switch (cmd) {
1339 case MGSL_IOCGPARAMS:
1340 return get_params(info, argp);
1341 case MGSL_IOCSPARAMS:
1342 return set_params(info, argp);
1343 case MGSL_IOCGTXIDLE:
1344 return get_txidle(info, argp);
1345 case MGSL_IOCSTXIDLE:
1346 return set_txidle(info, (int)arg);
1347 case MGSL_IOCTXENABLE:
1348 return tx_enable(info, (int)arg);
1349 case MGSL_IOCRXENABLE:
1350 return rx_enable(info, (int)arg);
1351 case MGSL_IOCTXABORT:
1352 return tx_abort(info);
1353 case MGSL_IOCGSTATS:
1354 return get_stats(info, argp);
1355 case MGSL_IOCWAITEVENT:
1356 return wait_mgsl_event(info, argp);
1357 case MGSL_IOCLOOPTXDONE:
1358 return 0; // TODO: Not supported, need to document
1359 /* Wait for modem input (DCD,RI,DSR,CTS) change
1360 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1361 */
1362 case TIOCMIWAIT:
1363 return modem_input_wait(info,(int)arg);
1364
1365 /*
1366 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1367 * Return: write counters to the user passed counter struct
1368 * NB: both 1->0 and 0->1 transitions are counted except for
1369 * RI where only 0->1 is counted.
1370 */
1371 case TIOCGICOUNT:
1372 spin_lock_irqsave(&info->lock,flags);
1373 cnow = info->icount;
1374 spin_unlock_irqrestore(&info->lock,flags);
1375 p_cuser = argp;
1376 PUT_USER(error,cnow.cts, &p_cuser->cts);
1377 if (error) return error;
1378 PUT_USER(error,cnow.dsr, &p_cuser->dsr);
1379 if (error) return error;
1380 PUT_USER(error,cnow.rng, &p_cuser->rng);
1381 if (error) return error;
1382 PUT_USER(error,cnow.dcd, &p_cuser->dcd);
1383 if (error) return error;
1384 PUT_USER(error,cnow.rx, &p_cuser->rx);
1385 if (error) return error;
1386 PUT_USER(error,cnow.tx, &p_cuser->tx);
1387 if (error) return error;
1388 PUT_USER(error,cnow.frame, &p_cuser->frame);
1389 if (error) return error;
1390 PUT_USER(error,cnow.overrun, &p_cuser->overrun);
1391 if (error) return error;
1392 PUT_USER(error,cnow.parity, &p_cuser->parity);
1393 if (error) return error;
1394 PUT_USER(error,cnow.brk, &p_cuser->brk);
1395 if (error) return error;
1396 PUT_USER(error,cnow.buf_overrun, &p_cuser->buf_overrun);
1397 if (error) return error;
1398 return 0;
1399 default:
1400 return -ENOIOCTLCMD;
1401 }
1402 return 0;
1403 }
1404
1405 /*
1406 * /proc fs routines....
1407 */
1408
1409 static inline int line_info(char *buf, SLMP_INFO *info)
1410 {
1411 char stat_buf[30];
1412 int ret;
1413 unsigned long flags;
1414
1415 ret = sprintf(buf, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1416 "\tIRQ=%d MaxFrameSize=%u\n",
1417 info->device_name,
1418 info->phys_sca_base,
1419 info->phys_memory_base,
1420 info->phys_statctrl_base,
1421 info->phys_lcr_base,
1422 info->irq_level,
1423 info->max_frame_size );
1424
1425 /* output current serial signal states */
1426 spin_lock_irqsave(&info->lock,flags);
1427 get_signals(info);
1428 spin_unlock_irqrestore(&info->lock,flags);
1429
1430 stat_buf[0] = 0;
1431 stat_buf[1] = 0;
1432 if (info->serial_signals & SerialSignal_RTS)
1433 strcat(stat_buf, "|RTS");
1434 if (info->serial_signals & SerialSignal_CTS)
1435 strcat(stat_buf, "|CTS");
1436 if (info->serial_signals & SerialSignal_DTR)
1437 strcat(stat_buf, "|DTR");
1438 if (info->serial_signals & SerialSignal_DSR)
1439 strcat(stat_buf, "|DSR");
1440 if (info->serial_signals & SerialSignal_DCD)
1441 strcat(stat_buf, "|CD");
1442 if (info->serial_signals & SerialSignal_RI)
1443 strcat(stat_buf, "|RI");
1444
1445 if (info->params.mode == MGSL_MODE_HDLC) {
1446 ret += sprintf(buf+ret, "\tHDLC txok:%d rxok:%d",
1447 info->icount.txok, info->icount.rxok);
1448 if (info->icount.txunder)
1449 ret += sprintf(buf+ret, " txunder:%d", info->icount.txunder);
1450 if (info->icount.txabort)
1451 ret += sprintf(buf+ret, " txabort:%d", info->icount.txabort);
1452 if (info->icount.rxshort)
1453 ret += sprintf(buf+ret, " rxshort:%d", info->icount.rxshort);
1454 if (info->icount.rxlong)
1455 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxlong);
1456 if (info->icount.rxover)
1457 ret += sprintf(buf+ret, " rxover:%d", info->icount.rxover);
1458 if (info->icount.rxcrc)
1459 ret += sprintf(buf+ret, " rxlong:%d", info->icount.rxcrc);
1460 } else {
1461 ret += sprintf(buf+ret, "\tASYNC tx:%d rx:%d",
1462 info->icount.tx, info->icount.rx);
1463 if (info->icount.frame)
1464 ret += sprintf(buf+ret, " fe:%d", info->icount.frame);
1465 if (info->icount.parity)
1466 ret += sprintf(buf+ret, " pe:%d", info->icount.parity);
1467 if (info->icount.brk)
1468 ret += sprintf(buf+ret, " brk:%d", info->icount.brk);
1469 if (info->icount.overrun)
1470 ret += sprintf(buf+ret, " oe:%d", info->icount.overrun);
1471 }
1472
1473 /* Append serial signal status to end */
1474 ret += sprintf(buf+ret, " %s\n", stat_buf+1);
1475
1476 ret += sprintf(buf+ret, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1477 info->tx_active,info->bh_requested,info->bh_running,
1478 info->pending_bh);
1479
1480 return ret;
1481 }
1482
1483 /* Called to print information about devices
1484 */
1485 int read_proc(char *page, char **start, off_t off, int count,
1486 int *eof, void *data)
1487 {
1488 int len = 0, l;
1489 off_t begin = 0;
1490 SLMP_INFO *info;
1491
1492 len += sprintf(page, "synclinkmp driver:%s\n", driver_version);
1493
1494 info = synclinkmp_device_list;
1495 while( info ) {
1496 l = line_info(page + len, info);
1497 len += l;
1498 if (len+begin > off+count)
1499 goto done;
1500 if (len+begin < off) {
1501 begin += len;
1502 len = 0;
1503 }
1504 info = info->next_device;
1505 }
1506
1507 *eof = 1;
1508 done:
1509 if (off >= len+begin)
1510 return 0;
1511 *start = page + (off-begin);
1512 return ((count < begin+len-off) ? count : begin+len-off);
1513 }
1514
1515 /* Return the count of bytes in transmit buffer
1516 */
1517 static int chars_in_buffer(struct tty_struct *tty)
1518 {
1519 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1520
1521 if (sanity_check(info, tty->name, "chars_in_buffer"))
1522 return 0;
1523
1524 if (debug_level >= DEBUG_LEVEL_INFO)
1525 printk("%s(%d):%s chars_in_buffer()=%d\n",
1526 __FILE__, __LINE__, info->device_name, info->tx_count);
1527
1528 return info->tx_count;
1529 }
1530
1531 /* Signal remote device to throttle send data (our receive data)
1532 */
1533 static void throttle(struct tty_struct * tty)
1534 {
1535 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1536 unsigned long flags;
1537
1538 if (debug_level >= DEBUG_LEVEL_INFO)
1539 printk("%s(%d):%s throttle() entry\n",
1540 __FILE__,__LINE__, info->device_name );
1541
1542 if (sanity_check(info, tty->name, "throttle"))
1543 return;
1544
1545 if (I_IXOFF(tty))
1546 send_xchar(tty, STOP_CHAR(tty));
1547
1548 if (tty->termios->c_cflag & CRTSCTS) {
1549 spin_lock_irqsave(&info->lock,flags);
1550 info->serial_signals &= ~SerialSignal_RTS;
1551 set_signals(info);
1552 spin_unlock_irqrestore(&info->lock,flags);
1553 }
1554 }
1555
1556 /* Signal remote device to stop throttling send data (our receive data)
1557 */
1558 static void unthrottle(struct tty_struct * tty)
1559 {
1560 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
1561 unsigned long flags;
1562
1563 if (debug_level >= DEBUG_LEVEL_INFO)
1564 printk("%s(%d):%s unthrottle() entry\n",
1565 __FILE__,__LINE__, info->device_name );
1566
1567 if (sanity_check(info, tty->name, "unthrottle"))
1568 return;
1569
1570 if (I_IXOFF(tty)) {
1571 if (info->x_char)
1572 info->x_char = 0;
1573 else
1574 send_xchar(tty, START_CHAR(tty));
1575 }
1576
1577 if (tty->termios->c_cflag & CRTSCTS) {
1578 spin_lock_irqsave(&info->lock,flags);
1579 info->serial_signals |= SerialSignal_RTS;
1580 set_signals(info);
1581 spin_unlock_irqrestore(&info->lock,flags);
1582 }
1583 }
1584
1585 /* set or clear transmit break condition
1586 * break_state -1=set break condition, 0=clear
1587 */
1588 static void set_break(struct tty_struct *tty, int break_state)
1589 {
1590 unsigned char RegValue;
1591 SLMP_INFO * info = (SLMP_INFO *)tty->driver_data;
1592 unsigned long flags;
1593
1594 if (debug_level >= DEBUG_LEVEL_INFO)
1595 printk("%s(%d):%s set_break(%d)\n",
1596 __FILE__,__LINE__, info->device_name, break_state);
1597
1598 if (sanity_check(info, tty->name, "set_break"))
1599 return;
1600
1601 spin_lock_irqsave(&info->lock,flags);
1602 RegValue = read_reg(info, CTL);
1603 if (break_state == -1)
1604 RegValue |= BIT3;
1605 else
1606 RegValue &= ~BIT3;
1607 write_reg(info, CTL, RegValue);
1608 spin_unlock_irqrestore(&info->lock,flags);
1609 }
1610
1611 #if SYNCLINK_GENERIC_HDLC
1612
1613 /**
1614 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1615 * set encoding and frame check sequence (FCS) options
1616 *
1617 * dev pointer to network device structure
1618 * encoding serial encoding setting
1619 * parity FCS setting
1620 *
1621 * returns 0 if success, otherwise error code
1622 */
1623 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1624 unsigned short parity)
1625 {
1626 SLMP_INFO *info = dev_to_port(dev);
1627 unsigned char new_encoding;
1628 unsigned short new_crctype;
1629
1630 /* return error if TTY interface open */
1631 if (info->count)
1632 return -EBUSY;
1633
1634 switch (encoding)
1635 {
1636 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1637 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1638 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1639 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1640 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1641 default: return -EINVAL;
1642 }
1643
1644 switch (parity)
1645 {
1646 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1647 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1648 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1649 default: return -EINVAL;
1650 }
1651
1652 info->params.encoding = new_encoding;
1653 info->params.crc_type = new_crctype;
1654
1655 /* if network interface up, reprogram hardware */
1656 if (info->netcount)
1657 program_hw(info);
1658
1659 return 0;
1660 }
1661
1662 /**
1663 * called by generic HDLC layer to send frame
1664 *
1665 * skb socket buffer containing HDLC frame
1666 * dev pointer to network device structure
1667 *
1668 * returns 0 if success, otherwise error code
1669 */
1670 static int hdlcdev_xmit(struct sk_buff *skb, struct net_device *dev)
1671 {
1672 SLMP_INFO *info = dev_to_port(dev);
1673 struct net_device_stats *stats = hdlc_stats(dev);
1674 unsigned long flags;
1675
1676 if (debug_level >= DEBUG_LEVEL_INFO)
1677 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1678
1679 /* stop sending until this frame completes */
1680 netif_stop_queue(dev);
1681
1682 /* copy data to device buffers */
1683 info->tx_count = skb->len;
1684 tx_load_dma_buffer(info, skb->data, skb->len);
1685
1686 /* update network statistics */
1687 stats->tx_packets++;
1688 stats->tx_bytes += skb->len;
1689
1690 /* done with socket buffer, so free it */
1691 dev_kfree_skb(skb);
1692
1693 /* save start time for transmit timeout detection */
1694 dev->trans_start = jiffies;
1695
1696 /* start hardware transmitter if necessary */
1697 spin_lock_irqsave(&info->lock,flags);
1698 if (!info->tx_active)
1699 tx_start(info);
1700 spin_unlock_irqrestore(&info->lock,flags);
1701
1702 return 0;
1703 }
1704
1705 /**
1706 * called by network layer when interface enabled
1707 * claim resources and initialize hardware
1708 *
1709 * dev pointer to network device structure
1710 *
1711 * returns 0 if success, otherwise error code
1712 */
1713 static int hdlcdev_open(struct net_device *dev)
1714 {
1715 SLMP_INFO *info = dev_to_port(dev);
1716 int rc;
1717 unsigned long flags;
1718
1719 if (debug_level >= DEBUG_LEVEL_INFO)
1720 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1721
1722 /* generic HDLC layer open processing */
1723 if ((rc = hdlc_open(dev)))
1724 return rc;
1725
1726 /* arbitrate between network and tty opens */
1727 spin_lock_irqsave(&info->netlock, flags);
1728 if (info->count != 0 || info->netcount != 0) {
1729 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1730 spin_unlock_irqrestore(&info->netlock, flags);
1731 return -EBUSY;
1732 }
1733 info->netcount=1;
1734 spin_unlock_irqrestore(&info->netlock, flags);
1735
1736 /* claim resources and init adapter */
1737 if ((rc = startup(info)) != 0) {
1738 spin_lock_irqsave(&info->netlock, flags);
1739 info->netcount=0;
1740 spin_unlock_irqrestore(&info->netlock, flags);
1741 return rc;
1742 }
1743
1744 /* assert DTR and RTS, apply hardware settings */
1745 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
1746 program_hw(info);
1747
1748 /* enable network layer transmit */
1749 dev->trans_start = jiffies;
1750 netif_start_queue(dev);
1751
1752 /* inform generic HDLC layer of current DCD status */
1753 spin_lock_irqsave(&info->lock, flags);
1754 get_signals(info);
1755 spin_unlock_irqrestore(&info->lock, flags);
1756 if (info->serial_signals & SerialSignal_DCD)
1757 netif_carrier_on(dev);
1758 else
1759 netif_carrier_off(dev);
1760 return 0;
1761 }
1762
1763 /**
1764 * called by network layer when interface is disabled
1765 * shutdown hardware and release resources
1766 *
1767 * dev pointer to network device structure
1768 *
1769 * returns 0 if success, otherwise error code
1770 */
1771 static int hdlcdev_close(struct net_device *dev)
1772 {
1773 SLMP_INFO *info = dev_to_port(dev);
1774 unsigned long flags;
1775
1776 if (debug_level >= DEBUG_LEVEL_INFO)
1777 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1778
1779 netif_stop_queue(dev);
1780
1781 /* shutdown adapter and release resources */
1782 shutdown(info);
1783
1784 hdlc_close(dev);
1785
1786 spin_lock_irqsave(&info->netlock, flags);
1787 info->netcount=0;
1788 spin_unlock_irqrestore(&info->netlock, flags);
1789
1790 return 0;
1791 }
1792
1793 /**
1794 * called by network layer to process IOCTL call to network device
1795 *
1796 * dev pointer to network device structure
1797 * ifr pointer to network interface request structure
1798 * cmd IOCTL command code
1799 *
1800 * returns 0 if success, otherwise error code
1801 */
1802 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1803 {
1804 const size_t size = sizeof(sync_serial_settings);
1805 sync_serial_settings new_line;
1806 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1807 SLMP_INFO *info = dev_to_port(dev);
1808 unsigned int flags;
1809
1810 if (debug_level >= DEBUG_LEVEL_INFO)
1811 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1812
1813 /* return error if TTY interface open */
1814 if (info->count)
1815 return -EBUSY;
1816
1817 if (cmd != SIOCWANDEV)
1818 return hdlc_ioctl(dev, ifr, cmd);
1819
1820 switch(ifr->ifr_settings.type) {
1821 case IF_GET_IFACE: /* return current sync_serial_settings */
1822
1823 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1824 if (ifr->ifr_settings.size < size) {
1825 ifr->ifr_settings.size = size; /* data size wanted */
1826 return -ENOBUFS;
1827 }
1828
1829 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1830 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1831 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1832 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1833
1834 switch (flags){
1835 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1836 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1837 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1838 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1839 default: new_line.clock_type = CLOCK_DEFAULT;
1840 }
1841
1842 new_line.clock_rate = info->params.clock_speed;
1843 new_line.loopback = info->params.loopback ? 1:0;
1844
1845 if (copy_to_user(line, &new_line, size))
1846 return -EFAULT;
1847 return 0;
1848
1849 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1850
1851 if(!capable(CAP_NET_ADMIN))
1852 return -EPERM;
1853 if (copy_from_user(&new_line, line, size))
1854 return -EFAULT;
1855
1856 switch (new_line.clock_type)
1857 {
1858 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1859 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1860 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1861 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1862 case CLOCK_DEFAULT: flags = info->params.flags &
1863 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1864 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1865 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1866 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1867 default: return -EINVAL;
1868 }
1869
1870 if (new_line.loopback != 0 && new_line.loopback != 1)
1871 return -EINVAL;
1872
1873 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1874 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1875 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1876 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1877 info->params.flags |= flags;
1878
1879 info->params.loopback = new_line.loopback;
1880
1881 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1882 info->params.clock_speed = new_line.clock_rate;
1883 else
1884 info->params.clock_speed = 0;
1885
1886 /* if network interface up, reprogram hardware */
1887 if (info->netcount)
1888 program_hw(info);
1889 return 0;
1890
1891 default:
1892 return hdlc_ioctl(dev, ifr, cmd);
1893 }
1894 }
1895
1896 /**
1897 * called by network layer when transmit timeout is detected
1898 *
1899 * dev pointer to network device structure
1900 */
1901 static void hdlcdev_tx_timeout(struct net_device *dev)
1902 {
1903 SLMP_INFO *info = dev_to_port(dev);
1904 struct net_device_stats *stats = hdlc_stats(dev);
1905 unsigned long flags;
1906
1907 if (debug_level >= DEBUG_LEVEL_INFO)
1908 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1909
1910 stats->tx_errors++;
1911 stats->tx_aborted_errors++;
1912
1913 spin_lock_irqsave(&info->lock,flags);
1914 tx_stop(info);
1915 spin_unlock_irqrestore(&info->lock,flags);
1916
1917 netif_wake_queue(dev);
1918 }
1919
1920 /**
1921 * called by device driver when transmit completes
1922 * reenable network layer transmit if stopped
1923 *
1924 * info pointer to device instance information
1925 */
1926 static void hdlcdev_tx_done(SLMP_INFO *info)
1927 {
1928 if (netif_queue_stopped(info->netdev))
1929 netif_wake_queue(info->netdev);
1930 }
1931
1932 /**
1933 * called by device driver when frame received
1934 * pass frame to network layer
1935 *
1936 * info pointer to device instance information
1937 * buf pointer to buffer contianing frame data
1938 * size count of data bytes in buf
1939 */
1940 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1941 {
1942 struct sk_buff *skb = dev_alloc_skb(size);
1943 struct net_device *dev = info->netdev;
1944 struct net_device_stats *stats = hdlc_stats(dev);
1945
1946 if (debug_level >= DEBUG_LEVEL_INFO)
1947 printk("hdlcdev_rx(%s)\n",dev->name);
1948
1949 if (skb == NULL) {
1950 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n", dev->name);
1951 stats->rx_dropped++;
1952 return;
1953 }
1954
1955 memcpy(skb_put(skb, size),buf,size);
1956
1957 skb->protocol = hdlc_type_trans(skb, info->netdev);
1958
1959 stats->rx_packets++;
1960 stats->rx_bytes += size;
1961
1962 netif_rx(skb);
1963
1964 info->netdev->last_rx = jiffies;
1965 }
1966
1967 /**
1968 * called by device driver when adding device instance
1969 * do generic HDLC initialization
1970 *
1971 * info pointer to device instance information
1972 *
1973 * returns 0 if success, otherwise error code
1974 */
1975 static int hdlcdev_init(SLMP_INFO *info)
1976 {
1977 int rc;
1978 struct net_device *dev;
1979 hdlc_device *hdlc;
1980
1981 /* allocate and initialize network and HDLC layer objects */
1982
1983 if (!(dev = alloc_hdlcdev(info))) {
1984 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1985 return -ENOMEM;
1986 }
1987
1988 /* for network layer reporting purposes only */
1989 dev->mem_start = info->phys_sca_base;
1990 dev->mem_end = info->phys_sca_base + SCA_BASE_SIZE - 1;
1991 dev->irq = info->irq_level;
1992
1993 /* network layer callbacks and settings */
1994 dev->do_ioctl = hdlcdev_ioctl;
1995 dev->open = hdlcdev_open;
1996 dev->stop = hdlcdev_close;
1997 dev->tx_timeout = hdlcdev_tx_timeout;
1998 dev->watchdog_timeo = 10*HZ;
1999 dev->tx_queue_len = 50;
2000
2001 /* generic HDLC layer callbacks and settings */
2002 hdlc = dev_to_hdlc(dev);
2003 hdlc->attach = hdlcdev_attach;
2004 hdlc->xmit = hdlcdev_xmit;
2005
2006 /* register objects with HDLC layer */
2007 if ((rc = register_hdlc_device(dev))) {
2008 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
2009 free_netdev(dev);
2010 return rc;
2011 }
2012
2013 info->netdev = dev;
2014 return 0;
2015 }
2016
2017 /**
2018 * called by device driver when removing device instance
2019 * do generic HDLC cleanup
2020 *
2021 * info pointer to device instance information
2022 */
2023 static void hdlcdev_exit(SLMP_INFO *info)
2024 {
2025 unregister_hdlc_device(info->netdev);
2026 free_netdev(info->netdev);
2027 info->netdev = NULL;
2028 }
2029
2030 #endif /* CONFIG_HDLC */
2031
2032
2033 /* Return next bottom half action to perform.
2034 * Return Value: BH action code or 0 if nothing to do.
2035 */
2036 int bh_action(SLMP_INFO *info)
2037 {
2038 unsigned long flags;
2039 int rc = 0;
2040
2041 spin_lock_irqsave(&info->lock,flags);
2042
2043 if (info->pending_bh & BH_RECEIVE) {
2044 info->pending_bh &= ~BH_RECEIVE;
2045 rc = BH_RECEIVE;
2046 } else if (info->pending_bh & BH_TRANSMIT) {
2047 info->pending_bh &= ~BH_TRANSMIT;
2048 rc = BH_TRANSMIT;
2049 } else if (info->pending_bh & BH_STATUS) {
2050 info->pending_bh &= ~BH_STATUS;
2051 rc = BH_STATUS;
2052 }
2053
2054 if (!rc) {
2055 /* Mark BH routine as complete */
2056 info->bh_running = 0;
2057 info->bh_requested = 0;
2058 }
2059
2060 spin_unlock_irqrestore(&info->lock,flags);
2061
2062 return rc;
2063 }
2064
2065 /* Perform bottom half processing of work items queued by ISR.
2066 */
2067 void bh_handler(struct work_struct *work)
2068 {
2069 SLMP_INFO *info = container_of(work, SLMP_INFO, task);
2070 int action;
2071
2072 if (!info)
2073 return;
2074
2075 if ( debug_level >= DEBUG_LEVEL_BH )
2076 printk( "%s(%d):%s bh_handler() entry\n",
2077 __FILE__,__LINE__,info->device_name);
2078
2079 info->bh_running = 1;
2080
2081 while((action = bh_action(info)) != 0) {
2082
2083 /* Process work item */
2084 if ( debug_level >= DEBUG_LEVEL_BH )
2085 printk( "%s(%d):%s bh_handler() work item action=%d\n",
2086 __FILE__,__LINE__,info->device_name, action);
2087
2088 switch (action) {
2089
2090 case BH_RECEIVE:
2091 bh_receive(info);
2092 break;
2093 case BH_TRANSMIT:
2094 bh_transmit(info);
2095 break;
2096 case BH_STATUS:
2097 bh_status(info);
2098 break;
2099 default:
2100 /* unknown work item ID */
2101 printk("%s(%d):%s Unknown work item ID=%08X!\n",
2102 __FILE__,__LINE__,info->device_name,action);
2103 break;
2104 }
2105 }
2106
2107 if ( debug_level >= DEBUG_LEVEL_BH )
2108 printk( "%s(%d):%s bh_handler() exit\n",
2109 __FILE__,__LINE__,info->device_name);
2110 }
2111
2112 void bh_receive(SLMP_INFO *info)
2113 {
2114 if ( debug_level >= DEBUG_LEVEL_BH )
2115 printk( "%s(%d):%s bh_receive()\n",
2116 __FILE__,__LINE__,info->device_name);
2117
2118 while( rx_get_frame(info) );
2119 }
2120
2121 void bh_transmit(SLMP_INFO *info)
2122 {
2123 struct tty_struct *tty = info->tty;
2124
2125 if ( debug_level >= DEBUG_LEVEL_BH )
2126 printk( "%s(%d):%s bh_transmit() entry\n",
2127 __FILE__,__LINE__,info->device_name);
2128
2129 if (tty)
2130 tty_wakeup(tty);
2131 }
2132
2133 void bh_status(SLMP_INFO *info)
2134 {
2135 if ( debug_level >= DEBUG_LEVEL_BH )
2136 printk( "%s(%d):%s bh_status() entry\n",
2137 __FILE__,__LINE__,info->device_name);
2138
2139 info->ri_chkcount = 0;
2140 info->dsr_chkcount = 0;
2141 info->dcd_chkcount = 0;
2142 info->cts_chkcount = 0;
2143 }
2144
2145 void isr_timer(SLMP_INFO * info)
2146 {
2147 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2148
2149 /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2150 write_reg(info, IER2, 0);
2151
2152 /* TMCS, Timer Control/Status Register
2153 *
2154 * 07 CMF, Compare match flag (read only) 1=match
2155 * 06 ECMI, CMF Interrupt Enable: 0=disabled
2156 * 05 Reserved, must be 0
2157 * 04 TME, Timer Enable
2158 * 03..00 Reserved, must be 0
2159 *
2160 * 0000 0000
2161 */
2162 write_reg(info, (unsigned char)(timer + TMCS), 0);
2163
2164 info->irq_occurred = TRUE;
2165
2166 if ( debug_level >= DEBUG_LEVEL_ISR )
2167 printk("%s(%d):%s isr_timer()\n",
2168 __FILE__,__LINE__,info->device_name);
2169 }
2170
2171 void isr_rxint(SLMP_INFO * info)
2172 {
2173 struct tty_struct *tty = info->tty;
2174 struct mgsl_icount *icount = &info->icount;
2175 unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2176 unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2177
2178 /* clear status bits */
2179 if (status)
2180 write_reg(info, SR1, status);
2181
2182 if (status2)
2183 write_reg(info, SR2, status2);
2184
2185 if ( debug_level >= DEBUG_LEVEL_ISR )
2186 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2187 __FILE__,__LINE__,info->device_name,status,status2);
2188
2189 if (info->params.mode == MGSL_MODE_ASYNC) {
2190 if (status & BRKD) {
2191 icount->brk++;
2192
2193 /* process break detection if tty control
2194 * is not set to ignore it
2195 */
2196 if ( tty ) {
2197 if (!(status & info->ignore_status_mask1)) {
2198 if (info->read_status_mask1 & BRKD) {
2199 tty_insert_flip_char(tty, 0, TTY_BREAK);
2200 if (info->flags & ASYNC_SAK)
2201 do_SAK(tty);
2202 }
2203 }
2204 }
2205 }
2206 }
2207 else {
2208 if (status & (FLGD|IDLD)) {
2209 if (status & FLGD)
2210 info->icount.exithunt++;
2211 else if (status & IDLD)
2212 info->icount.rxidle++;
2213 wake_up_interruptible(&info->event_wait_q);
2214 }
2215 }
2216
2217 if (status & CDCD) {
2218 /* simulate a common modem status change interrupt
2219 * for our handler
2220 */
2221 get_signals( info );
2222 isr_io_pin(info,
2223 MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2224 }
2225 }
2226
2227 /*
2228 * handle async rx data interrupts
2229 */
2230 void isr_rxrdy(SLMP_INFO * info)
2231 {
2232 u16 status;
2233 unsigned char DataByte;
2234 struct tty_struct *tty = info->tty;
2235 struct mgsl_icount *icount = &info->icount;
2236
2237 if ( debug_level >= DEBUG_LEVEL_ISR )
2238 printk("%s(%d):%s isr_rxrdy\n",
2239 __FILE__,__LINE__,info->device_name);
2240
2241 while((status = read_reg(info,CST0)) & BIT0)
2242 {
2243 int flag = 0;
2244 int over = 0;
2245 DataByte = read_reg(info,TRB);
2246
2247 icount->rx++;
2248
2249 if ( status & (PE + FRME + OVRN) ) {
2250 printk("%s(%d):%s rxerr=%04X\n",
2251 __FILE__,__LINE__,info->device_name,status);
2252
2253 /* update error statistics */
2254 if (status & PE)
2255 icount->parity++;
2256 else if (status & FRME)
2257 icount->frame++;
2258 else if (status & OVRN)
2259 icount->overrun++;
2260
2261 /* discard char if tty control flags say so */
2262 if (status & info->ignore_status_mask2)
2263 continue;
2264
2265 status &= info->read_status_mask2;
2266
2267 if ( tty ) {
2268 if (status & PE)
2269 flag = TTY_PARITY;
2270 else if (status & FRME)
2271 flag = TTY_FRAME;
2272 if (status & OVRN) {
2273 /* Overrun is special, since it's
2274 * reported immediately, and doesn't
2275 * affect the current character
2276 */
2277 over = 1;
2278 }
2279 }
2280 } /* end of if (error) */
2281
2282 if ( tty ) {
2283 tty_insert_flip_char(tty, DataByte, flag);
2284 if (over)
2285 tty_insert_flip_char(tty, 0, TTY_OVERRUN);
2286 }
2287 }
2288
2289 if ( debug_level >= DEBUG_LEVEL_ISR ) {
2290 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2291 __FILE__,__LINE__,info->device_name,
2292 icount->rx,icount->brk,icount->parity,
2293 icount->frame,icount->overrun);
2294 }
2295
2296 if ( tty )
2297 tty_flip_buffer_push(tty);
2298 }
2299
2300 static void isr_txeom(SLMP_INFO * info, unsigned char status)
2301 {
2302 if ( debug_level >= DEBUG_LEVEL_ISR )
2303 printk("%s(%d):%s isr_txeom status=%02x\n",
2304 __FILE__,__LINE__,info->device_name,status);
2305
2306 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2307 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2308 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2309
2310 if (status & UDRN) {
2311 write_reg(info, CMD, TXRESET);
2312 write_reg(info, CMD, TXENABLE);
2313 } else
2314 write_reg(info, CMD, TXBUFCLR);
2315
2316 /* disable and clear tx interrupts */
2317 info->ie0_value &= ~TXRDYE;
2318 info->ie1_value &= ~(IDLE + UDRN);
2319 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2320 write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2321
2322 if ( info->tx_active ) {
2323 if (info->params.mode != MGSL_MODE_ASYNC) {
2324 if (status & UDRN)
2325 info->icount.txunder++;
2326 else if (status & IDLE)
2327 info->icount.txok++;
2328 }
2329
2330 info->tx_active = 0;
2331 info->tx_count = info->tx_put = info->tx_get = 0;
2332
2333 del_timer(&info->tx_timer);
2334
2335 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2336 info->serial_signals &= ~SerialSignal_RTS;
2337 info->drop_rts_on_tx_done = 0;
2338 set_signals(info);
2339 }
2340
2341 #if SYNCLINK_GENERIC_HDLC
2342 if (info->netcount)
2343 hdlcdev_tx_done(info);
2344 else
2345 #endif
2346 {
2347 if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2348 tx_stop(info);
2349 return;
2350 }
2351 info->pending_bh |= BH_TRANSMIT;
2352 }
2353 }
2354 }
2355
2356
2357 /*
2358 * handle tx status interrupts
2359 */
2360 void isr_txint(SLMP_INFO * info)
2361 {
2362 unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2363
2364 /* clear status bits */
2365 write_reg(info, SR1, status);
2366
2367 if ( debug_level >= DEBUG_LEVEL_ISR )
2368 printk("%s(%d):%s isr_txint status=%02x\n",
2369 __FILE__,__LINE__,info->device_name,status);
2370
2371 if (status & (UDRN + IDLE))
2372 isr_txeom(info, status);
2373
2374 if (status & CCTS) {
2375 /* simulate a common modem status change interrupt
2376 * for our handler
2377 */
2378 get_signals( info );
2379 isr_io_pin(info,
2380 MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2381
2382 }
2383 }
2384
2385 /*
2386 * handle async tx data interrupts
2387 */
2388 void isr_txrdy(SLMP_INFO * info)
2389 {
2390 if ( debug_level >= DEBUG_LEVEL_ISR )
2391 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2392 __FILE__,__LINE__,info->device_name,info->tx_count);
2393
2394 if (info->params.mode != MGSL_MODE_ASYNC) {
2395 /* disable TXRDY IRQ, enable IDLE IRQ */
2396 info->ie0_value &= ~TXRDYE;
2397 info->ie1_value |= IDLE;
2398 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2399 return;
2400 }
2401
2402 if (info->tty && (info->tty->stopped || info->tty->hw_stopped)) {
2403 tx_stop(info);
2404 return;
2405 }
2406
2407 if ( info->tx_count )
2408 tx_load_fifo( info );
2409 else {
2410 info->tx_active = 0;
2411 info->ie0_value &= ~TXRDYE;
2412 write_reg(info, IE0, info->ie0_value);
2413 }
2414
2415 if (info->tx_count < WAKEUP_CHARS)
2416 info->pending_bh |= BH_TRANSMIT;
2417 }
2418
2419 void isr_rxdmaok(SLMP_INFO * info)
2420 {
2421 /* BIT7 = EOT (end of transfer)
2422 * BIT6 = EOM (end of message/frame)
2423 */
2424 unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2425
2426 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2427 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2428
2429 if ( debug_level >= DEBUG_LEVEL_ISR )
2430 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2431 __FILE__,__LINE__,info->device_name,status);
2432
2433 info->pending_bh |= BH_RECEIVE;
2434 }
2435
2436 void isr_rxdmaerror(SLMP_INFO * info)
2437 {
2438 /* BIT5 = BOF (buffer overflow)
2439 * BIT4 = COF (counter overflow)
2440 */
2441 unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2442
2443 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2444 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2445
2446 if ( debug_level >= DEBUG_LEVEL_ISR )
2447 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2448 __FILE__,__LINE__,info->device_name,status);
2449
2450 info->rx_overflow = TRUE;
2451 info->pending_bh |= BH_RECEIVE;
2452 }
2453
2454 void isr_txdmaok(SLMP_INFO * info)
2455 {
2456 unsigned char status_reg1 = read_reg(info, SR1);
2457
2458 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2459 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2460 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2461
2462 if ( debug_level >= DEBUG_LEVEL_ISR )
2463 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2464 __FILE__,__LINE__,info->device_name,status_reg1);
2465
2466 /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2467 write_reg16(info, TRC0, 0);
2468 info->ie0_value |= TXRDYE;
2469 write_reg(info, IE0, info->ie0_value);
2470 }
2471
2472 void isr_txdmaerror(SLMP_INFO * info)
2473 {
2474 /* BIT5 = BOF (buffer overflow)
2475 * BIT4 = COF (counter overflow)
2476 */
2477 unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2478
2479 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2480 write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2481
2482 if ( debug_level >= DEBUG_LEVEL_ISR )
2483 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2484 __FILE__,__LINE__,info->device_name,status);
2485 }
2486
2487 /* handle input serial signal changes
2488 */
2489 void isr_io_pin( SLMP_INFO *info, u16 status )
2490 {
2491 struct mgsl_icount *icount;
2492
2493 if ( debug_level >= DEBUG_LEVEL_ISR )
2494 printk("%s(%d):isr_io_pin status=%04X\n",
2495 __FILE__,__LINE__,status);
2496
2497 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2498 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2499 icount = &info->icount;
2500 /* update input line counters */
2501 if (status & MISCSTATUS_RI_LATCHED) {
2502 icount->rng++;
2503 if ( status & SerialSignal_RI )
2504 info->input_signal_events.ri_up++;
2505 else
2506 info->input_signal_events.ri_down++;
2507 }
2508 if (status & MISCSTATUS_DSR_LATCHED) {
2509 icount->dsr++;
2510 if ( status & SerialSignal_DSR )
2511 info->input_signal_events.dsr_up++;
2512 else
2513 info->input_signal_events.dsr_down++;
2514 }
2515 if (status & MISCSTATUS_DCD_LATCHED) {
2516 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2517 info->ie1_value &= ~CDCD;
2518 write_reg(info, IE1, info->ie1_value);
2519 }
2520 icount->dcd++;
2521 if (status & SerialSignal_DCD) {
2522 info->input_signal_events.dcd_up++;
2523 } else
2524 info->input_signal_events.dcd_down++;
2525 #if SYNCLINK_GENERIC_HDLC
2526 if (info->netcount) {
2527 if (status & SerialSignal_DCD)
2528 netif_carrier_on(info->netdev);
2529 else
2530 netif_carrier_off(info->netdev);
2531 }
2532 #endif
2533 }
2534 if (status & MISCSTATUS_CTS_LATCHED)
2535 {
2536 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2537 info->ie1_value &= ~CCTS;
2538 write_reg(info, IE1, info->ie1_value);
2539 }
2540 icount->cts++;
2541 if ( status & SerialSignal_CTS )
2542 info->input_signal_events.cts_up++;
2543 else
2544 info->input_signal_events.cts_down++;
2545 }
2546 wake_up_interruptible(&info->status_event_wait_q);
2547 wake_up_interruptible(&info->event_wait_q);
2548
2549 if ( (info->flags & ASYNC_CHECK_CD) &&
2550 (status & MISCSTATUS_DCD_LATCHED) ) {
2551 if ( debug_level >= DEBUG_LEVEL_ISR )
2552 printk("%s CD now %s...", info->device_name,
2553 (status & SerialSignal_DCD) ? "on" : "off");
2554 if (status & SerialSignal_DCD)
2555 wake_up_interruptible(&info->open_wait);
2556 else {
2557 if ( debug_level >= DEBUG_LEVEL_ISR )
2558 printk("doing serial hangup...");
2559 if (info->tty)
2560 tty_hangup(info->tty);
2561 }
2562 }
2563
2564 if ( (info->flags & ASYNC_CTS_FLOW) &&
2565 (status & MISCSTATUS_CTS_LATCHED) ) {
2566 if ( info->tty ) {
2567 if (info->tty->hw_stopped) {
2568 if (status & SerialSignal_CTS) {
2569 if ( debug_level >= DEBUG_LEVEL_ISR )
2570 printk("CTS tx start...");
2571 info->tty->hw_stopped = 0;
2572 tx_start(info);
2573 info->pending_bh |= BH_TRANSMIT;
2574 return;
2575 }
2576 } else {
2577 if (!(status & SerialSignal_CTS)) {
2578 if ( debug_level >= DEBUG_LEVEL_ISR )
2579 printk("CTS tx stop...");
2580 info->tty->hw_stopped = 1;
2581 tx_stop(info);
2582 }
2583 }
2584 }
2585 }
2586 }
2587
2588 info->pending_bh |= BH_STATUS;
2589 }
2590
2591 /* Interrupt service routine entry point.
2592 *
2593 * Arguments:
2594 * irq interrupt number that caused interrupt
2595 * dev_id device ID supplied during interrupt registration
2596 * regs interrupted processor context
2597 */
2598 static irqreturn_t synclinkmp_interrupt(int irq, void *dev_id)
2599 {
2600 SLMP_INFO * info;
2601 unsigned char status, status0, status1=0;
2602 unsigned char dmastatus, dmastatus0, dmastatus1=0;
2603 unsigned char timerstatus0, timerstatus1=0;
2604 unsigned char shift;
2605 unsigned int i;
2606 unsigned short tmp;
2607
2608 if ( debug_level >= DEBUG_LEVEL_ISR )
2609 printk("%s(%d): synclinkmp_interrupt(%d)entry.\n",
2610 __FILE__,__LINE__,irq);
2611
2612 info = (SLMP_INFO *)dev_id;
2613 if (!info)
2614 return IRQ_NONE;
2615
2616 spin_lock(&info->lock);
2617
2618 for(;;) {
2619
2620 /* get status for SCA0 (ports 0-1) */
2621 tmp = read_reg16(info, ISR0); /* get ISR0 and ISR1 in one read */
2622 status0 = (unsigned char)tmp;
2623 dmastatus0 = (unsigned char)(tmp>>8);
2624 timerstatus0 = read_reg(info, ISR2);
2625
2626 if ( debug_level >= DEBUG_LEVEL_ISR )
2627 printk("%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2628 __FILE__,__LINE__,info->device_name,
2629 status0,dmastatus0,timerstatus0);
2630
2631 if (info->port_count == 4) {
2632 /* get status for SCA1 (ports 2-3) */
2633 tmp = read_reg16(info->port_array[2], ISR0);
2634 status1 = (unsigned char)tmp;
2635 dmastatus1 = (unsigned char)(tmp>>8);
2636 timerstatus1 = read_reg(info->port_array[2], ISR2);
2637
2638 if ( debug_level >= DEBUG_LEVEL_ISR )
2639 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2640 __FILE__,__LINE__,info->device_name,
2641 status1,dmastatus1,timerstatus1);
2642 }
2643
2644 if (!status0 && !dmastatus0 && !timerstatus0 &&
2645 !status1 && !dmastatus1 && !timerstatus1)
2646 break;
2647
2648 for(i=0; i < info->port_count ; i++) {
2649 if (info->port_array[i] == NULL)
2650 continue;
2651 if (i < 2) {
2652 status = status0;
2653 dmastatus = dmastatus0;
2654 } else {
2655 status = status1;
2656 dmastatus = dmastatus1;
2657 }
2658
2659 shift = i & 1 ? 4 :0;
2660
2661 if (status & BIT0 << shift)
2662 isr_rxrdy(info->port_array[i]);
2663 if (status & BIT1 << shift)
2664 isr_txrdy(info->port_array[i]);
2665 if (status & BIT2 << shift)
2666 isr_rxint(info->port_array[i]);
2667 if (status & BIT3 << shift)
2668 isr_txint(info->port_array[i]);
2669
2670 if (dmastatus & BIT0 << shift)
2671 isr_rxdmaerror(info->port_array[i]);
2672 if (dmastatus & BIT1 << shift)
2673 isr_rxdmaok(info->port_array[i]);
2674 if (dmastatus & BIT2 << shift)
2675 isr_txdmaerror(info->port_array[i]);
2676 if (dmastatus & BIT3 << shift)
2677 isr_txdmaok(info->port_array[i]);
2678 }
2679
2680 if (timerstatus0 & (BIT5 | BIT4))
2681 isr_timer(info->port_array[0]);
2682 if (timerstatus0 & (BIT7 | BIT6))
2683 isr_timer(info->port_array[1]);
2684 if (timerstatus1 & (BIT5 | BIT4))
2685 isr_timer(info->port_array[2]);
2686 if (timerstatus1 & (BIT7 | BIT6))
2687 isr_timer(info->port_array[3]);
2688 }
2689
2690 for(i=0; i < info->port_count ; i++) {
2691 SLMP_INFO * port = info->port_array[i];
2692
2693 /* Request bottom half processing if there's something
2694 * for it to do and the bh is not already running.
2695 *
2696 * Note: startup adapter diags require interrupts.
2697 * do not request bottom half processing if the
2698 * device is not open in a normal mode.
2699 */
2700 if ( port && (port->count || port->netcount) &&
2701 port->pending_bh && !port->bh_running &&
2702 !port->bh_requested ) {
2703 if ( debug_level >= DEBUG_LEVEL_ISR )
2704 printk("%s(%d):%s queueing bh task.\n",
2705 __FILE__,__LINE__,port->device_name);
2706 schedule_work(&port->task);
2707 port->bh_requested = 1;
2708 }
2709 }
2710
2711 spin_unlock(&info->lock);
2712
2713 if ( debug_level >= DEBUG_LEVEL_ISR )
2714 printk("%s(%d):synclinkmp_interrupt(%d)exit.\n",
2715 __FILE__,__LINE__,irq);
2716 return IRQ_HANDLED;
2717 }
2718
2719 /* Initialize and start device.
2720 */
2721 static int startup(SLMP_INFO * info)
2722 {
2723 if ( debug_level >= DEBUG_LEVEL_INFO )
2724 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2725
2726 if (info->flags & ASYNC_INITIALIZED)
2727 return 0;
2728
2729 if (!info->tx_buf) {
2730 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2731 if (!info->tx_buf) {
2732 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2733 __FILE__,__LINE__,info->device_name);
2734 return -ENOMEM;
2735 }
2736 }
2737
2738 info->pending_bh = 0;
2739
2740 memset(&info->icount, 0, sizeof(info->icount));
2741
2742 /* program hardware for current parameters */
2743 reset_port(info);
2744
2745 change_params(info);
2746
2747 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
2748
2749 if (info->tty)
2750 clear_bit(TTY_IO_ERROR, &info->tty->flags);
2751
2752 info->flags |= ASYNC_INITIALIZED;
2753
2754 return 0;
2755 }
2756
2757 /* Called by close() and hangup() to shutdown hardware
2758 */
2759 static void shutdown(SLMP_INFO * info)
2760 {
2761 unsigned long flags;
2762
2763 if (!(info->flags & ASYNC_INITIALIZED))
2764 return;
2765
2766 if (debug_level >= DEBUG_LEVEL_INFO)
2767 printk("%s(%d):%s synclinkmp_shutdown()\n",
2768 __FILE__,__LINE__, info->device_name );
2769
2770 /* clear status wait queue because status changes */
2771 /* can't happen after shutting down the hardware */
2772 wake_up_interruptible(&info->status_event_wait_q);
2773 wake_up_interruptible(&info->event_wait_q);
2774
2775 del_timer(&info->tx_timer);
2776 del_timer(&info->status_timer);
2777
2778 kfree(info->tx_buf);
2779 info->tx_buf = NULL;
2780
2781 spin_lock_irqsave(&info->lock,flags);
2782
2783 reset_port(info);
2784
2785 if (!info->tty || info->tty->termios->c_cflag & HUPCL) {
2786 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
2787 set_signals(info);
2788 }
2789
2790 spin_unlock_irqrestore(&info->lock,flags);
2791
2792 if (info->tty)
2793 set_bit(TTY_IO_ERROR, &info->tty->flags);
2794
2795 info->flags &= ~ASYNC_INITIALIZED;
2796 }
2797
2798 static void program_hw(SLMP_INFO *info)
2799 {
2800 unsigned long flags;
2801
2802 spin_lock_irqsave(&info->lock,flags);
2803
2804 rx_stop(info);
2805 tx_stop(info);
2806
2807 info->tx_count = info->tx_put = info->tx_get = 0;
2808
2809 if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2810 hdlc_mode(info);
2811 else
2812 async_mode(info);
2813
2814 set_signals(info);
2815
2816 info->dcd_chkcount = 0;
2817 info->cts_chkcount = 0;
2818 info->ri_chkcount = 0;
2819 info->dsr_chkcount = 0;
2820
2821 info->ie1_value |= (CDCD|CCTS);
2822 write_reg(info, IE1, info->ie1_value);
2823
2824 get_signals(info);
2825
2826 if (info->netcount || (info->tty && info->tty->termios->c_cflag & CREAD) )
2827 rx_start(info);
2828
2829 spin_unlock_irqrestore(&info->lock,flags);
2830 }
2831
2832 /* Reconfigure adapter based on new parameters
2833 */
2834 static void change_params(SLMP_INFO *info)
2835 {
2836 unsigned cflag;
2837 int bits_per_char;
2838
2839 if (!info->tty || !info->tty->termios)
2840 return;
2841
2842 if (debug_level >= DEBUG_LEVEL_INFO)
2843 printk("%s(%d):%s change_params()\n",
2844 __FILE__,__LINE__, info->device_name );
2845
2846 cflag = info->tty->termios->c_cflag;
2847
2848 /* if B0 rate (hangup) specified then negate DTR and RTS */
2849 /* otherwise assert DTR and RTS */
2850 if (cflag & CBAUD)
2851 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
2852 else
2853 info->serial_signals &= ~(SerialSignal_RTS + SerialSignal_DTR);
2854
2855 /* byte size and parity */
2856
2857 switch (cflag & CSIZE) {
2858 case CS5: info->params.data_bits = 5; break;
2859 case CS6: info->params.data_bits = 6; break;
2860 case CS7: info->params.data_bits = 7; break;
2861 case CS8: info->params.data_bits = 8; break;
2862 /* Never happens, but GCC is too dumb to figure it out */
2863 default: info->params.data_bits = 7; break;
2864 }
2865
2866 if (cflag & CSTOPB)
2867 info->params.stop_bits = 2;
2868 else
2869 info->params.stop_bits = 1;
2870
2871 info->params.parity = ASYNC_PARITY_NONE;
2872 if (cflag & PARENB) {
2873 if (cflag & PARODD)
2874 info->params.parity = ASYNC_PARITY_ODD;
2875 else
2876 info->params.parity = ASYNC_PARITY_EVEN;
2877 #ifdef CMSPAR
2878 if (cflag & CMSPAR)
2879 info->params.parity = ASYNC_PARITY_SPACE;
2880 #endif
2881 }
2882
2883 /* calculate number of jiffies to transmit a full
2884 * FIFO (32 bytes) at specified data rate
2885 */
2886 bits_per_char = info->params.data_bits +
2887 info->params.stop_bits + 1;
2888
2889 /* if port data rate is set to 460800 or less then
2890 * allow tty settings to override, otherwise keep the
2891 * current data rate.
2892 */
2893 if (info->params.data_rate <= 460800) {
2894 info->params.data_rate = tty_get_baud_rate(info->tty);
2895 }
2896
2897 if ( info->params.data_rate ) {
2898 info->timeout = (32*HZ*bits_per_char) /
2899 info->params.data_rate;
2900 }
2901 info->timeout += HZ/50; /* Add .02 seconds of slop */
2902
2903 if (cflag & CRTSCTS)
2904 info->flags |= ASYNC_CTS_FLOW;
2905 else
2906 info->flags &= ~ASYNC_CTS_FLOW;
2907
2908 if (cflag & CLOCAL)
2909 info->flags &= ~ASYNC_CHECK_CD;
2910 else
2911 info->flags |= ASYNC_CHECK_CD;
2912
2913 /* process tty input control flags */
2914
2915 info->read_status_mask2 = OVRN;
2916 if (I_INPCK(info->tty))
2917 info->read_status_mask2 |= PE | FRME;
2918 if (I_BRKINT(info->tty) || I_PARMRK(info->tty))
2919 info->read_status_mask1 |= BRKD;
2920 if (I_IGNPAR(info->tty))
2921 info->ignore_status_mask2 |= PE | FRME;
2922 if (I_IGNBRK(info->tty)) {
2923 info->ignore_status_mask1 |= BRKD;
2924 /* If ignoring parity and break indicators, ignore
2925 * overruns too. (For real raw support).
2926 */
2927 if (I_IGNPAR(info->tty))
2928 info->ignore_status_mask2 |= OVRN;
2929 }
2930
2931 program_hw(info);
2932 }
2933
2934 static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2935 {
2936 int err;
2937
2938 if (debug_level >= DEBUG_LEVEL_INFO)
2939 printk("%s(%d):%s get_params()\n",
2940 __FILE__,__LINE__, info->device_name);
2941
2942 if (!user_icount) {
2943 memset(&info->icount, 0, sizeof(info->icount));
2944 } else {
2945 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2946 if (err)
2947 return -EFAULT;
2948 }
2949
2950 return 0;
2951 }
2952
2953 static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2954 {
2955 int err;
2956 if (debug_level >= DEBUG_LEVEL_INFO)
2957 printk("%s(%d):%s get_params()\n",
2958 __FILE__,__LINE__, info->device_name);
2959
2960 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2961 if (err) {
2962 if ( debug_level >= DEBUG_LEVEL_INFO )
2963 printk( "%s(%d):%s get_params() user buffer copy failed\n",
2964 __FILE__,__LINE__,info->device_name);
2965 return -EFAULT;
2966 }
2967
2968 return 0;
2969 }
2970
2971 static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2972 {
2973 unsigned long flags;
2974 MGSL_PARAMS tmp_params;
2975 int err;
2976
2977 if (debug_level >= DEBUG_LEVEL_INFO)
2978 printk("%s(%d):%s set_params\n",
2979 __FILE__,__LINE__,info->device_name );
2980 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2981 if (err) {
2982 if ( debug_level >= DEBUG_LEVEL_INFO )
2983 printk( "%s(%d):%s set_params() user buffer copy failed\n",
2984 __FILE__,__LINE__,info->device_name);
2985 return -EFAULT;
2986 }
2987
2988 spin_lock_irqsave(&info->lock,flags);
2989 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2990 spin_unlock_irqrestore(&info->lock,flags);
2991
2992 change_params(info);
2993
2994 return 0;
2995 }
2996
2997 static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
2998 {
2999 int err;
3000
3001 if (debug_level >= DEBUG_LEVEL_INFO)
3002 printk("%s(%d):%s get_txidle()=%d\n",
3003 __FILE__,__LINE__, info->device_name, info->idle_mode);
3004
3005 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
3006 if (err) {
3007 if ( debug_level >= DEBUG_LEVEL_INFO )
3008 printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
3009 __FILE__,__LINE__,info->device_name);
3010 return -EFAULT;
3011 }
3012
3013 return 0;
3014 }
3015
3016 static int set_txidle(SLMP_INFO * info, int idle_mode)
3017 {
3018 unsigned long flags;
3019
3020 if (debug_level >= DEBUG_LEVEL_INFO)
3021 printk("%s(%d):%s set_txidle(%d)\n",
3022 __FILE__,__LINE__,info->device_name, idle_mode );
3023
3024 spin_lock_irqsave(&info->lock,flags);
3025 info->idle_mode = idle_mode;
3026 tx_set_idle( info );
3027 spin_unlock_irqrestore(&info->lock,flags);
3028 return 0;
3029 }
3030
3031 static int tx_enable(SLMP_INFO * info, int enable)
3032 {
3033 unsigned long flags;
3034
3035 if (debug_level >= DEBUG_LEVEL_INFO)
3036 printk("%s(%d):%s tx_enable(%d)\n",
3037 __FILE__,__LINE__,info->device_name, enable);
3038
3039 spin_lock_irqsave(&info->lock,flags);
3040 if ( enable ) {
3041 if ( !info->tx_enabled ) {
3042 tx_start(info);
3043 }
3044 } else {
3045 if ( info->tx_enabled )
3046 tx_stop(info);
3047 }
3048 spin_unlock_irqrestore(&info->lock,flags);
3049 return 0;
3050 }
3051
3052 /* abort send HDLC frame
3053 */
3054 static int tx_abort(SLMP_INFO * info)
3055 {
3056 unsigned long flags;
3057
3058 if (debug_level >= DEBUG_LEVEL_INFO)
3059 printk("%s(%d):%s tx_abort()\n",
3060 __FILE__,__LINE__,info->device_name);
3061
3062 spin_lock_irqsave(&info->lock,flags);
3063 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
3064 info->ie1_value &= ~UDRN;
3065 info->ie1_value |= IDLE;
3066 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
3067 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
3068
3069 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
3070 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
3071
3072 write_reg(info, CMD, TXABORT);
3073 }
3074 spin_unlock_irqrestore(&info->lock,flags);
3075 return 0;
3076 }
3077
3078 static int rx_enable(SLMP_INFO * info, int enable)
3079 {
3080 unsigned long flags;
3081
3082 if (debug_level >= DEBUG_LEVEL_INFO)
3083 printk("%s(%d):%s rx_enable(%d)\n",
3084 __FILE__,__LINE__,info->device_name,enable);
3085
3086 spin_lock_irqsave(&info->lock,flags);
3087 if ( enable ) {
3088 if ( !info->rx_enabled )
3089 rx_start(info);
3090 } else {
3091 if ( info->rx_enabled )
3092 rx_stop(info);
3093 }
3094 spin_unlock_irqrestore(&info->lock,flags);
3095 return 0;
3096 }
3097
3098 /* wait for specified event to occur
3099 */
3100 static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
3101 {
3102 unsigned long flags;
3103 int s;
3104 int rc=0;
3105 struct mgsl_icount cprev, cnow;
3106 int events;
3107 int mask;
3108 struct _input_signal_events oldsigs, newsigs;
3109 DECLARE_WAITQUEUE(wait, current);
3110
3111 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3112 if (rc) {
3113 return -EFAULT;
3114 }
3115
3116 if (debug_level >= DEBUG_LEVEL_INFO)
3117 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3118 __FILE__,__LINE__,info->device_name,mask);
3119
3120 spin_lock_irqsave(&info->lock,flags);
3121
3122 /* return immediately if state matches requested events */
3123 get_signals(info);
3124 s = info->serial_signals;
3125
3126 events = mask &
3127 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3128 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3129 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3130 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3131 if (events) {
3132 spin_unlock_irqrestore(&info->lock,flags);
3133 goto exit;
3134 }
3135
3136 /* save current irq counts */
3137 cprev = info->icount;
3138 oldsigs = info->input_signal_events;
3139
3140 /* enable hunt and idle irqs if needed */
3141 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3142 unsigned char oldval = info->ie1_value;
3143 unsigned char newval = oldval +
3144 (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3145 (mask & MgslEvent_IdleReceived ? IDLD:0);
3146 if ( oldval != newval ) {
3147 info->ie1_value = newval;
3148 write_reg(info, IE1, info->ie1_value);
3149 }
3150 }
3151
3152 set_current_state(TASK_INTERRUPTIBLE);
3153 add_wait_queue(&info->event_wait_q, &wait);
3154
3155 spin_unlock_irqrestore(&info->lock,flags);
3156
3157 for(;;) {
3158 schedule();
3159 if (signal_pending(current)) {
3160 rc = -ERESTARTSYS;
3161 break;
3162 }
3163
3164 /* get current irq counts */
3165 spin_lock_irqsave(&info->lock,flags);
3166 cnow = info->icount;
3167 newsigs = info->input_signal_events;
3168 set_current_state(TASK_INTERRUPTIBLE);
3169 spin_unlock_irqrestore(&info->lock,flags);
3170
3171 /* if no change, wait aborted for some reason */
3172 if (newsigs.dsr_up == oldsigs.dsr_up &&
3173 newsigs.dsr_down == oldsigs.dsr_down &&
3174 newsigs.dcd_up == oldsigs.dcd_up &&
3175 newsigs.dcd_down == oldsigs.dcd_down &&
3176 newsigs.cts_up == oldsigs.cts_up &&
3177 newsigs.cts_down == oldsigs.cts_down &&
3178 newsigs.ri_up == oldsigs.ri_up &&
3179 newsigs.ri_down == oldsigs.ri_down &&
3180 cnow.exithunt == cprev.exithunt &&
3181 cnow.rxidle == cprev.rxidle) {
3182 rc = -EIO;
3183 break;
3184 }
3185
3186 events = mask &
3187 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
3188 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3189 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
3190 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3191 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
3192 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3193 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
3194 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
3195 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
3196 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
3197 if (events)
3198 break;
3199
3200 cprev = cnow;
3201 oldsigs = newsigs;
3202 }
3203
3204 remove_wait_queue(&info->event_wait_q, &wait);
3205 set_current_state(TASK_RUNNING);
3206
3207
3208 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3209 spin_lock_irqsave(&info->lock,flags);
3210 if (!waitqueue_active(&info->event_wait_q)) {
3211 /* disable enable exit hunt mode/idle rcvd IRQs */
3212 info->ie1_value &= ~(FLGD|IDLD);
3213 write_reg(info, IE1, info->ie1_value);
3214 }
3215 spin_unlock_irqrestore(&info->lock,flags);
3216 }
3217 exit:
3218 if ( rc == 0 )
3219 PUT_USER(rc, events, mask_ptr);
3220
3221 return rc;
3222 }
3223
3224 static int modem_input_wait(SLMP_INFO *info,int arg)
3225 {
3226 unsigned long flags;
3227 int rc;
3228 struct mgsl_icount cprev, cnow;
3229 DECLARE_WAITQUEUE(wait, current);
3230
3231 /* save current irq counts */
3232 spin_lock_irqsave(&info->lock,flags);
3233 cprev = info->icount;
3234 add_wait_queue(&info->status_event_wait_q, &wait);
3235 set_current_state(TASK_INTERRUPTIBLE);
3236 spin_unlock_irqrestore(&info->lock,flags);
3237
3238 for(;;) {
3239 schedule();
3240 if (signal_pending(current)) {
3241 rc = -ERESTARTSYS;
3242 break;
3243 }
3244
3245 /* get new irq counts */
3246 spin_lock_irqsave(&info->lock,flags);
3247 cnow = info->icount;
3248 set_current_state(TASK_INTERRUPTIBLE);
3249 spin_unlock_irqrestore(&info->lock,flags);
3250
3251 /* if no change, wait aborted for some reason */
3252 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3253 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3254 rc = -EIO;
3255 break;
3256 }
3257
3258 /* check for change in caller specified modem input */
3259 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3260 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3261 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3262 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3263 rc = 0;
3264 break;
3265 }
3266
3267 cprev = cnow;
3268 }
3269 remove_wait_queue(&info->status_event_wait_q, &wait);
3270 set_current_state(TASK_RUNNING);
3271 return rc;
3272 }
3273
3274 /* return the state of the serial control and status signals
3275 */
3276 static int tiocmget(struct tty_struct *tty, struct file *file)
3277 {
3278 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3279 unsigned int result;
3280 unsigned long flags;
3281
3282 spin_lock_irqsave(&info->lock,flags);
3283 get_signals(info);
3284 spin_unlock_irqrestore(&info->lock,flags);
3285
3286 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS:0) +
3287 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR:0) +
3288 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR:0) +
3289 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG:0) +
3290 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR:0) +
3291 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS:0);
3292
3293 if (debug_level >= DEBUG_LEVEL_INFO)
3294 printk("%s(%d):%s tiocmget() value=%08X\n",
3295 __FILE__,__LINE__, info->device_name, result );
3296 return result;
3297 }
3298
3299 /* set modem control signals (DTR/RTS)
3300 */
3301 static int tiocmset(struct tty_struct *tty, struct file *file,
3302 unsigned int set, unsigned int clear)
3303 {
3304 SLMP_INFO *info = (SLMP_INFO *)tty->driver_data;
3305 unsigned long flags;
3306
3307 if (debug_level >= DEBUG_LEVEL_INFO)
3308 printk("%s(%d):%s tiocmset(%x,%x)\n",
3309 __FILE__,__LINE__,info->device_name, set, clear);
3310
3311 if (set & TIOCM_RTS)
3312 info->serial_signals |= SerialSignal_RTS;
3313 if (set & TIOCM_DTR)
3314 info->serial_signals |= SerialSignal_DTR;
3315 if (clear & TIOCM_RTS)
3316 info->serial_signals &= ~SerialSignal_RTS;
3317 if (clear & TIOCM_DTR)
3318 info->serial_signals &= ~SerialSignal_DTR;
3319
3320 spin_lock_irqsave(&info->lock,flags);
3321 set_signals(info);
3322 spin_unlock_irqrestore(&info->lock,flags);
3323
3324 return 0;
3325 }
3326
3327
3328
3329 /* Block the current process until the specified port is ready to open.
3330 */
3331 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3332 SLMP_INFO *info)
3333 {
3334 DECLARE_WAITQUEUE(wait, current);
3335 int retval;
3336 int do_clocal = 0, extra_count = 0;
3337 unsigned long flags;
3338
3339 if (debug_level >= DEBUG_LEVEL_INFO)
3340 printk("%s(%d):%s block_til_ready()\n",
3341 __FILE__,__LINE__, tty->driver->name );
3342
3343 if (filp->f_flags & O_NONBLOCK || tty->flags & (1 << TTY_IO_ERROR)){
3344 /* nonblock mode is set or port is not enabled */
3345 /* just verify that callout device is not active */
3346 info->flags |= ASYNC_NORMAL_ACTIVE;
3347 return 0;
3348 }
3349
3350 if (tty->termios->c_cflag & CLOCAL)
3351 do_clocal = 1;
3352
3353 /* Wait for carrier detect and the line to become
3354 * free (i.e., not in use by the callout). While we are in
3355 * this loop, info->count is dropped by one, so that
3356 * close() knows when to free things. We restore it upon
3357 * exit, either normal or abnormal.
3358 */
3359
3360 retval = 0;
3361 add_wait_queue(&info->open_wait, &wait);
3362
3363 if (debug_level >= DEBUG_LEVEL_INFO)
3364 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3365 __FILE__,__LINE__, tty->driver->name, info->count );
3366
3367 spin_lock_irqsave(&info->lock, flags);
3368 if (!tty_hung_up_p(filp)) {
3369 extra_count = 1;
3370 info->count--;
3371 }
3372 spin_unlock_irqrestore(&info->lock, flags);
3373 info->blocked_open++;
3374
3375 while (1) {
3376 if ((tty->termios->c_cflag & CBAUD)) {
3377 spin_lock_irqsave(&info->lock,flags);
3378 info->serial_signals |= SerialSignal_RTS + SerialSignal_DTR;
3379 set_signals(info);
3380 spin_unlock_irqrestore(&info->lock,flags);
3381 }
3382
3383 set_current_state(TASK_INTERRUPTIBLE);
3384
3385 if (tty_hung_up_p(filp) || !(info->flags & ASYNC_INITIALIZED)){
3386 retval = (info->flags & ASYNC_HUP_NOTIFY) ?
3387 -EAGAIN : -ERESTARTSYS;
3388 break;
3389 }
3390
3391 spin_lock_irqsave(&info->lock,flags);
3392 get_signals(info);
3393 spin_unlock_irqrestore(&info->lock,flags);
3394
3395 if (!(info->flags & ASYNC_CLOSING) &&
3396 (do_clocal || (info->serial_signals & SerialSignal_DCD)) ) {
3397 break;
3398 }
3399
3400 if (signal_pending(current)) {
3401 retval = -ERESTARTSYS;
3402 break;
3403 }
3404
3405 if (debug_level >= DEBUG_LEVEL_INFO)
3406 printk("%s(%d):%s block_til_ready() count=%d\n",
3407 __FILE__,__LINE__, tty->driver->name, info->count );
3408
3409 schedule();
3410 }
3411
3412 set_current_state(TASK_RUNNING);
3413 remove_wait_queue(&info->open_wait, &wait);
3414
3415 if (extra_count)
3416 info->count++;
3417 info->blocked_open--;
3418
3419 if (debug_level >= DEBUG_LEVEL_INFO)
3420 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3421 __FILE__,__LINE__, tty->driver->name, info->count );
3422
3423 if (!retval)
3424 info->flags |= ASYNC_NORMAL_ACTIVE;
3425
3426 return retval;
3427 }
3428
3429 int alloc_dma_bufs(SLMP_INFO *info)
3430 {
3431 unsigned short BuffersPerFrame;
3432 unsigned short BufferCount;
3433
3434 // Force allocation to start at 64K boundary for each port.
3435 // This is necessary because *all* buffer descriptors for a port
3436 // *must* be in the same 64K block. All descriptors on a port
3437 // share a common 'base' address (upper 8 bits of 24 bits) programmed
3438 // into the CBP register.
3439 info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3440
3441 /* Calculate the number of DMA buffers necessary to hold the */
3442 /* largest allowable frame size. Note: If the max frame size is */
3443 /* not an even multiple of the DMA buffer size then we need to */
3444 /* round the buffer count per frame up one. */
3445
3446 BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3447 if ( info->max_frame_size % SCABUFSIZE )
3448 BuffersPerFrame++;
3449
3450 /* calculate total number of data buffers (SCABUFSIZE) possible
3451 * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3452 * for the descriptor list (BUFFERLISTSIZE).
3453 */
3454 BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3455
3456 /* limit number of buffers to maximum amount of descriptors */
3457 if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3458 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3459
3460 /* use enough buffers to transmit one max size frame */
3461 info->tx_buf_count = BuffersPerFrame + 1;
3462
3463 /* never use more than half the available buffers for transmit */
3464 if (info->tx_buf_count > (BufferCount/2))
3465 info->tx_buf_count = BufferCount/2;
3466
3467 if (info->tx_buf_count > SCAMAXDESC)
3468 info->tx_buf_count = SCAMAXDESC;
3469
3470 /* use remaining buffers for receive */
3471 info->rx_buf_count = BufferCount - info->tx_buf_count;
3472
3473 if (info->rx_buf_count > SCAMAXDESC)
3474 info->rx_buf_count = SCAMAXDESC;
3475
3476 if ( debug_level >= DEBUG_LEVEL_INFO )
3477 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3478 __FILE__,__LINE__, info->device_name,
3479 info->tx_buf_count,info->rx_buf_count);
3480
3481 if ( alloc_buf_list( info ) < 0 ||
3482 alloc_frame_bufs(info,
3483 info->rx_buf_list,
3484 info->rx_buf_list_ex,
3485 info->rx_buf_count) < 0 ||
3486 alloc_frame_bufs(info,
3487 info->tx_buf_list,
3488 info->tx_buf_list_ex,
3489 info->tx_buf_count) < 0 ||
3490 alloc_tmp_rx_buf(info) < 0 ) {
3491 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3492 __FILE__,__LINE__, info->device_name);
3493 return -ENOMEM;
3494 }
3495
3496 rx_reset_buffers( info );
3497
3498 return 0;
3499 }
3500
3501 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3502 */
3503 int alloc_buf_list(SLMP_INFO *info)
3504 {
3505 unsigned int i;
3506
3507 /* build list in adapter shared memory */
3508 info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3509 info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3510 info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3511
3512 memset(info->buffer_list, 0, BUFFERLISTSIZE);
3513
3514 /* Save virtual address pointers to the receive and */
3515 /* transmit buffer lists. (Receive 1st). These pointers will */
3516 /* be used by the processor to access the lists. */
3517 info->rx_buf_list = (SCADESC *)info->buffer_list;
3518
3519 info->tx_buf_list = (SCADESC *)info->buffer_list;
3520 info->tx_buf_list += info->rx_buf_count;
3521
3522 /* Build links for circular buffer entry lists (tx and rx)
3523 *
3524 * Note: links are physical addresses read by the SCA device
3525 * to determine the next buffer entry to use.
3526 */
3527
3528 for ( i = 0; i < info->rx_buf_count; i++ ) {
3529 /* calculate and store physical address of this buffer entry */
3530 info->rx_buf_list_ex[i].phys_entry =
3531 info->buffer_list_phys + (i * sizeof(SCABUFSIZE));
3532
3533 /* calculate and store physical address of */
3534 /* next entry in cirular list of entries */
3535 info->rx_buf_list[i].next = info->buffer_list_phys;
3536 if ( i < info->rx_buf_count - 1 )
3537 info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3538
3539 info->rx_buf_list[i].length = SCABUFSIZE;
3540 }
3541
3542 for ( i = 0; i < info->tx_buf_count; i++ ) {
3543 /* calculate and store physical address of this buffer entry */
3544 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3545 ((info->rx_buf_count + i) * sizeof(SCADESC));
3546
3547 /* calculate and store physical address of */
3548 /* next entry in cirular list of entries */
3549
3550 info->tx_buf_list[i].next = info->buffer_list_phys +
3551 info->rx_buf_count * sizeof(SCADESC);
3552
3553 if ( i < info->tx_buf_count - 1 )
3554 info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3555 }
3556
3557 return 0;
3558 }
3559
3560 /* Allocate the frame DMA buffers used by the specified buffer list.
3561 */
3562 int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3563 {
3564 int i;
3565 unsigned long phys_addr;
3566
3567 for ( i = 0; i < count; i++ ) {
3568 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3569 phys_addr = info->port_array[0]->last_mem_alloc;
3570 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3571
3572 buf_list[i].buf_ptr = (unsigned short)phys_addr;
3573 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3574 }
3575
3576 return 0;
3577 }
3578
3579 void free_dma_bufs(SLMP_INFO *info)
3580 {
3581 info->buffer_list = NULL;
3582 info->rx_buf_list = NULL;
3583 info->tx_buf_list = NULL;
3584 }
3585
3586 /* allocate buffer large enough to hold max_frame_size.
3587 * This buffer is used to pass an assembled frame to the line discipline.
3588 */
3589 int alloc_tmp_rx_buf(SLMP_INFO *info)
3590 {
3591 info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3592 if (info->tmp_rx_buf == NULL)
3593 return -ENOMEM;
3594 return 0;
3595 }
3596
3597 void free_tmp_rx_buf(SLMP_INFO *info)
3598 {
3599 kfree(info->tmp_rx_buf);
3600 info->tmp_rx_buf = NULL;
3601 }
3602
3603 int claim_resources(SLMP_INFO *info)
3604 {
3605 if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3606 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3607 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3608 info->init_error = DiagStatus_AddressConflict;
3609 goto errout;
3610 }
3611 else
3612 info->shared_mem_requested = 1;
3613
3614 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3615 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3616 __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3617 info->init_error = DiagStatus_AddressConflict;
3618 goto errout;
3619 }
3620 else
3621 info->lcr_mem_requested = 1;
3622
3623 if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3624 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3625 __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3626 info->init_error = DiagStatus_AddressConflict;
3627 goto errout;
3628 }
3629 else
3630 info->sca_base_requested = 1;
3631
3632 if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3633 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3634 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3635 info->init_error = DiagStatus_AddressConflict;
3636 goto errout;
3637 }
3638 else
3639 info->sca_statctrl_requested = 1;
3640
3641 info->memory_base = ioremap(info->phys_memory_base,SCA_MEM_SIZE);
3642 if (!info->memory_base) {
3643 printk( "%s(%d):%s Cant map shared memory, MemAddr=%08X\n",
3644 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3645 info->init_error = DiagStatus_CantAssignPciResources;
3646 goto errout;
3647 }
3648
3649 info->lcr_base = ioremap(info->phys_lcr_base,PAGE_SIZE);
3650 if (!info->lcr_base) {
3651 printk( "%s(%d):%s Cant map LCR memory, MemAddr=%08X\n",
3652 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3653 info->init_error = DiagStatus_CantAssignPciResources;
3654 goto errout;
3655 }
3656 info->lcr_base += info->lcr_offset;
3657
3658 info->sca_base = ioremap(info->phys_sca_base,PAGE_SIZE);
3659 if (!info->sca_base) {
3660 printk( "%s(%d):%s Cant map SCA memory, MemAddr=%08X\n",
3661 __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3662 info->init_error = DiagStatus_CantAssignPciResources;
3663 goto errout;
3664 }
3665 info->sca_base += info->sca_offset;
3666
3667 info->statctrl_base = ioremap(info->phys_statctrl_base,PAGE_SIZE);
3668 if (!info->statctrl_base) {
3669 printk( "%s(%d):%s Cant map SCA Status/Control memory, MemAddr=%08X\n",
3670 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3671 info->init_error = DiagStatus_CantAssignPciResources;
3672 goto errout;
3673 }
3674 info->statctrl_base += info->statctrl_offset;
3675
3676 if ( !memory_test(info) ) {
3677 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3678 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3679 info->init_error = DiagStatus_MemoryError;
3680 goto errout;
3681 }
3682
3683 return 0;
3684
3685 errout:
3686 release_resources( info );
3687 return -ENODEV;
3688 }
3689
3690 void release_resources(SLMP_INFO *info)
3691 {
3692 if ( debug_level >= DEBUG_LEVEL_INFO )
3693 printk( "%s(%d):%s release_resources() entry\n",
3694 __FILE__,__LINE__,info->device_name );
3695
3696 if ( info->irq_requested ) {
3697 free_irq(info->irq_level, info);
3698 info->irq_requested = 0;
3699 }
3700
3701 if ( info->shared_mem_requested ) {
3702 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3703 info->shared_mem_requested = 0;
3704 }
3705 if ( info->lcr_mem_requested ) {
3706 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3707 info->lcr_mem_requested = 0;
3708 }
3709 if ( info->sca_base_requested ) {
3710 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3711 info->sca_base_requested = 0;
3712 }
3713 if ( info->sca_statctrl_requested ) {
3714 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3715 info->sca_statctrl_requested = 0;
3716 }
3717
3718 if (info->memory_base){
3719 iounmap(info->memory_base);
3720 info->memory_base = NULL;
3721 }
3722
3723 if (info->sca_base) {
3724 iounmap(info->sca_base - info->sca_offset);
3725 info->sca_base=NULL;
3726 }
3727
3728 if (info->statctrl_base) {
3729 iounmap(info->statctrl_base - info->statctrl_offset);
3730 info->statctrl_base=NULL;
3731 }
3732
3733 if (info->lcr_base){
3734 iounmap(info->lcr_base - info->lcr_offset);
3735 info->lcr_base = NULL;
3736 }
3737
3738 if ( debug_level >= DEBUG_LEVEL_INFO )
3739 printk( "%s(%d):%s release_resources() exit\n",
3740 __FILE__,__LINE__,info->device_name );
3741 }
3742
3743 /* Add the specified device instance data structure to the
3744 * global linked list of devices and increment the device count.
3745 */
3746 void add_device(SLMP_INFO *info)
3747 {
3748 info->next_device = NULL;
3749 info->line = synclinkmp_device_count;
3750 sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3751
3752 if (info->line < MAX_DEVICES) {
3753 if (maxframe[info->line])
3754 info->max_frame_size = maxframe[info->line];
3755 info->dosyncppp = dosyncppp[info->line];
3756 }
3757
3758 synclinkmp_device_count++;
3759
3760 if ( !synclinkmp_device_list )
3761 synclinkmp_device_list = info;
3762 else {
3763 SLMP_INFO *current_dev = synclinkmp_device_list;
3764 while( current_dev->next_device )
3765 current_dev = current_dev->next_device;
3766 current_dev->next_device = info;
3767 }
3768
3769 if ( info->max_frame_size < 4096 )
3770 info->max_frame_size = 4096;
3771 else if ( info->max_frame_size > 65535 )
3772 info->max_frame_size = 65535;
3773
3774 printk( "SyncLink MultiPort %s: "
3775 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3776 info->device_name,
3777 info->phys_sca_base,
3778 info->phys_memory_base,
3779 info->phys_statctrl_base,
3780 info->phys_lcr_base,
3781 info->irq_level,
3782 info->max_frame_size );
3783
3784 #if SYNCLINK_GENERIC_HDLC
3785 hdlcdev_init(info);
3786 #endif
3787 }
3788
3789 /* Allocate and initialize a device instance structure
3790 *
3791 * Return Value: pointer to SLMP_INFO if success, otherwise NULL
3792 */
3793 static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3794 {
3795 SLMP_INFO *info;
3796
3797 info = kmalloc(sizeof(SLMP_INFO),
3798 GFP_KERNEL);
3799
3800 if (!info) {
3801 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3802 __FILE__,__LINE__, adapter_num, port_num);
3803 } else {
3804 memset(info, 0, sizeof(SLMP_INFO));
3805 info->magic = MGSL_MAGIC;
3806 INIT_WORK(&info->task, bh_handler);
3807 info->max_frame_size = 4096;
3808 info->close_delay = 5*HZ/10;
3809 info->closing_wait = 30*HZ;
3810 init_waitqueue_head(&info->open_wait);
3811 init_waitqueue_head(&info->close_wait);
3812 init_waitqueue_head(&info->status_event_wait_q);
3813 init_waitqueue_head(&info->event_wait_q);
3814 spin_lock_init(&info->netlock);
3815 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3816 info->idle_mode = HDLC_TXIDLE_FLAGS;
3817 info->adapter_num = adapter_num;
3818 info->port_num = port_num;
3819
3820 /* Copy configuration info to device instance data */
3821 info->irq_level = pdev->irq;
3822 info->phys_lcr_base = pci_resource_start(pdev,0);
3823 info->phys_sca_base = pci_resource_start(pdev,2);
3824 info->phys_memory_base = pci_resource_start(pdev,3);
3825 info->phys_statctrl_base = pci_resource_start(pdev,4);
3826
3827 /* Because veremap only works on page boundaries we must map
3828 * a larger area than is actually implemented for the LCR
3829 * memory range. We map a full page starting at the page boundary.
3830 */
3831 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
3832 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3833
3834 info->sca_offset = info->phys_sca_base & (PAGE_SIZE-1);
3835 info->phys_sca_base &= ~(PAGE_SIZE-1);
3836
3837 info->statctrl_offset = info->phys_statctrl_base & (PAGE_SIZE-1);
3838 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3839
3840 info->bus_type = MGSL_BUS_TYPE_PCI;
3841 info->irq_flags = IRQF_SHARED;
3842
3843 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3844 setup_timer(&info->status_timer, status_timeout,
3845 (unsigned long)info);
3846
3847 /* Store the PCI9050 misc control register value because a flaw
3848 * in the PCI9050 prevents LCR registers from being read if
3849 * BIOS assigns an LCR base address with bit 7 set.
3850 *
3851 * Only the misc control register is accessed for which only
3852 * write access is needed, so set an initial value and change
3853 * bits to the device instance data as we write the value
3854 * to the actual misc control register.
3855 */
3856 info->misc_ctrl_value = 0x087e4546;
3857
3858 /* initial port state is unknown - if startup errors
3859 * occur, init_error will be set to indicate the
3860 * problem. Once the port is fully initialized,
3861 * this value will be set to 0 to indicate the
3862 * port is available.
3863 */
3864 info->init_error = -1;
3865 }
3866
3867 return info;
3868 }
3869
3870 void device_init(int adapter_num, struct pci_dev *pdev)
3871 {
3872 SLMP_INFO *port_array[SCA_MAX_PORTS];
3873 int port;
3874
3875 /* allocate device instances for up to SCA_MAX_PORTS devices */
3876 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3877 port_array[port] = alloc_dev(adapter_num,port,pdev);
3878 if( port_array[port] == NULL ) {
3879 for ( --port; port >= 0; --port )
3880 kfree(port_array[port]);
3881 return;
3882 }
3883 }
3884
3885 /* give copy of port_array to all ports and add to device list */
3886 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3887 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3888 add_device( port_array[port] );
3889 spin_lock_init(&port_array[port]->lock);
3890 }
3891
3892 /* Allocate and claim adapter resources */
3893 if ( !claim_resources(port_array[0]) ) {
3894
3895 alloc_dma_bufs(port_array[0]);
3896
3897 /* copy resource information from first port to others */
3898 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3899 port_array[port]->lock = port_array[0]->lock;
3900 port_array[port]->irq_level = port_array[0]->irq_level;
3901 port_array[port]->memory_base = port_array[0]->memory_base;
3902 port_array[port]->sca_base = port_array[0]->sca_base;
3903 port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3904 port_array[port]->lcr_base = port_array[0]->lcr_base;
3905 alloc_dma_bufs(port_array[port]);
3906 }
3907
3908 if ( request_irq(port_array[0]->irq_level,
3909 synclinkmp_interrupt,
3910 port_array[0]->irq_flags,
3911 port_array[0]->device_name,
3912 port_array[0]) < 0 ) {
3913 printk( "%s(%d):%s Cant request interrupt, IRQ=%d\n",
3914 __FILE__,__LINE__,
3915 port_array[0]->device_name,
3916 port_array[0]->irq_level );
3917 }
3918 else {
3919 port_array[0]->irq_requested = 1;
3920 adapter_test(port_array[0]);
3921 }
3922 }
3923 }
3924
3925 static const struct tty_operations ops = {
3926 .open = open,
3927 .close = close,
3928 .write = write,
3929 .put_char = put_char,
3930 .flush_chars = flush_chars,
3931 .write_room = write_room,
3932 .chars_in_buffer = chars_in_buffer,
3933 .flush_buffer = flush_buffer,
3934 .ioctl = ioctl,
3935 .throttle = throttle,
3936 .unthrottle = unthrottle,
3937 .send_xchar = send_xchar,
3938 .break_ctl = set_break,
3939 .wait_until_sent = wait_until_sent,
3940 .read_proc = read_proc,
3941 .set_termios = set_termios,
3942 .stop = tx_hold,
3943 .start = tx_release,
3944 .hangup = hangup,
3945 .tiocmget = tiocmget,
3946 .tiocmset = tiocmset,
3947 };
3948
3949 static void synclinkmp_cleanup(void)
3950 {
3951 int rc;
3952 SLMP_INFO *info;
3953 SLMP_INFO *tmp;
3954
3955 printk("Unloading %s %s\n", driver_name, driver_version);
3956
3957 if (serial_driver) {
3958 if ((rc = tty_unregister_driver(serial_driver)))
3959 printk("%s(%d) failed to unregister tty driver err=%d\n",
3960 __FILE__,__LINE__,rc);
3961 put_tty_driver(serial_driver);
3962 }
3963
3964 /* reset devices */
3965 info = synclinkmp_device_list;
3966 while(info) {
3967 reset_port(info);
3968 info = info->next_device;
3969 }
3970
3971 /* release devices */
3972 info = synclinkmp_device_list;
3973 while(info) {
3974 #if SYNCLINK_GENERIC_HDLC
3975 hdlcdev_exit(info);
3976 #endif
3977 free_dma_bufs(info);
3978 free_tmp_rx_buf(info);
3979 if ( info->port_num == 0 ) {
3980 if (info->sca_base)
3981 write_reg(info, LPR, 1); /* set low power mode */
3982 release_resources(info);
3983 }
3984 tmp = info;
3985 info = info->next_device;
3986 kfree(tmp);
3987 }
3988
3989 pci_unregister_driver(&synclinkmp_pci_driver);
3990 }
3991
3992 /* Driver initialization entry point.
3993 */
3994
3995 static int __init synclinkmp_init(void)
3996 {
3997 int rc;
3998
3999 if (break_on_load) {
4000 synclinkmp_get_text_ptr();
4001 BREAKPOINT();
4002 }
4003
4004 printk("%s %s\n", driver_name, driver_version);
4005
4006 if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
4007 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
4008 return rc;
4009 }
4010
4011 serial_driver = alloc_tty_driver(128);
4012 if (!serial_driver) {
4013 rc = -ENOMEM;
4014 goto error;
4015 }
4016
4017 /* Initialize the tty_driver structure */
4018
4019 serial_driver->owner = THIS_MODULE;
4020 serial_driver->driver_name = "synclinkmp";
4021 serial_driver->name = "ttySLM";
4022 serial_driver->major = ttymajor;
4023 serial_driver->minor_start = 64;
4024 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
4025 serial_driver->subtype = SERIAL_TYPE_NORMAL;
4026 serial_driver->init_termios = tty_std_termios;
4027 serial_driver->init_termios.c_cflag =
4028 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
4029 serial_driver->init_termios.c_ispeed = 9600;
4030 serial_driver->init_termios.c_ospeed = 9600;
4031 serial_driver->flags = TTY_DRIVER_REAL_RAW;
4032 tty_set_operations(serial_driver, &ops);
4033 if ((rc = tty_register_driver(serial_driver)) < 0) {
4034 printk("%s(%d):Couldn't register serial driver\n",
4035 __FILE__,__LINE__);
4036 put_tty_driver(serial_driver);
4037 serial_driver = NULL;
4038 goto error;
4039 }
4040
4041 printk("%s %s, tty major#%d\n",
4042 driver_name, driver_version,
4043 serial_driver->major);
4044
4045 return 0;
4046
4047 error:
4048 synclinkmp_cleanup();
4049 return rc;
4050 }
4051
4052 static void __exit synclinkmp_exit(void)
4053 {
4054 synclinkmp_cleanup();
4055 }
4056
4057 module_init(synclinkmp_init);
4058 module_exit(synclinkmp_exit);
4059
4060 /* Set the port for internal loopback mode.
4061 * The TxCLK and RxCLK signals are generated from the BRG and
4062 * the TxD is looped back to the RxD internally.
4063 */
4064 void enable_loopback(SLMP_INFO *info, int enable)
4065 {
4066 if (enable) {
4067 /* MD2 (Mode Register 2)
4068 * 01..00 CNCT<1..0> Channel Connection 11=Local Loopback
4069 */
4070 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4071
4072 /* degate external TxC clock source */
4073 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4074 write_control_reg(info);
4075
4076 /* RXS/TXS (Rx/Tx clock source)
4077 * 07 Reserved, must be 0
4078 * 06..04 Clock Source, 100=BRG
4079 * 03..00 Clock Divisor, 0000=1
4080 */
4081 write_reg(info, RXS, 0x40);
4082 write_reg(info, TXS, 0x40);
4083
4084 } else {
4085 /* MD2 (Mode Register 2)
4086 * 01..00 CNCT<1..0> Channel connection, 0=normal
4087 */
4088 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4089
4090 /* RXS/TXS (Rx/Tx clock source)
4091 * 07 Reserved, must be 0
4092 * 06..04 Clock Source, 000=RxC/TxC Pin
4093 * 03..00 Clock Divisor, 0000=1
4094 */
4095 write_reg(info, RXS, 0x00);
4096 write_reg(info, TXS, 0x00);
4097 }
4098
4099 /* set LinkSpeed if available, otherwise default to 2Mbps */
4100 if (info->params.clock_speed)
4101 set_rate(info, info->params.clock_speed);
4102 else
4103 set_rate(info, 3686400);
4104 }
4105
4106 /* Set the baud rate register to the desired speed
4107 *
4108 * data_rate data rate of clock in bits per second
4109 * A data rate of 0 disables the AUX clock.
4110 */
4111 void set_rate( SLMP_INFO *info, u32 data_rate )
4112 {
4113 u32 TMCValue;
4114 unsigned char BRValue;
4115 u32 Divisor=0;
4116
4117 /* fBRG = fCLK/(TMC * 2^BR)
4118 */
4119 if (data_rate != 0) {
4120 Divisor = 14745600/data_rate;
4121 if (!Divisor)
4122 Divisor = 1;
4123
4124 TMCValue = Divisor;
4125
4126 BRValue = 0;
4127 if (TMCValue != 1 && TMCValue != 2) {
4128 /* BRValue of 0 provides 50/50 duty cycle *only* when
4129 * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4130 * 50/50 duty cycle.
4131 */
4132 BRValue = 1;
4133 TMCValue >>= 1;
4134 }
4135
4136 /* while TMCValue is too big for TMC register, divide
4137 * by 2 and increment BR exponent.
4138 */
4139 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4140 TMCValue >>= 1;
4141
4142 write_reg(info, TXS,
4143 (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4144 write_reg(info, RXS,
4145 (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4146 write_reg(info, TMC, (unsigned char)TMCValue);
4147 }
4148 else {
4149 write_reg(info, TXS,0);
4150 write_reg(info, RXS,0);
4151 write_reg(info, TMC, 0);
4152 }
4153 }
4154
4155 /* Disable receiver
4156 */
4157 void rx_stop(SLMP_INFO *info)
4158 {
4159 if (debug_level >= DEBUG_LEVEL_ISR)
4160 printk("%s(%d):%s rx_stop()\n",
4161 __FILE__,__LINE__, info->device_name );
4162
4163 write_reg(info, CMD, RXRESET);
4164
4165 info->ie0_value &= ~RXRDYE;
4166 write_reg(info, IE0, info->ie0_value); /* disable Rx data interrupts */
4167
4168 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4169 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4170 write_reg(info, RXDMA + DIR, 0); /* disable Rx DMA interrupts */
4171
4172 info->rx_enabled = 0;
4173 info->rx_overflow = 0;
4174 }
4175
4176 /* enable the receiver
4177 */
4178 void rx_start(SLMP_INFO *info)
4179 {
4180 int i;
4181
4182 if (debug_level >= DEBUG_LEVEL_ISR)
4183 printk("%s(%d):%s rx_start()\n",
4184 __FILE__,__LINE__, info->device_name );
4185
4186 write_reg(info, CMD, RXRESET);
4187
4188 if ( info->params.mode == MGSL_MODE_HDLC ) {
4189 /* HDLC, disabe IRQ on rxdata */
4190 info->ie0_value &= ~RXRDYE;
4191 write_reg(info, IE0, info->ie0_value);
4192
4193 /* Reset all Rx DMA buffers and program rx dma */
4194 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4195 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4196
4197 for (i = 0; i < info->rx_buf_count; i++) {
4198 info->rx_buf_list[i].status = 0xff;
4199
4200 // throttle to 4 shared memory writes at a time to prevent
4201 // hogging local bus (keep latency time for DMA requests low).
4202 if (!(i % 4))
4203 read_status_reg(info);
4204 }
4205 info->current_rx_buf = 0;
4206
4207 /* set current/1st descriptor address */
4208 write_reg16(info, RXDMA + CDA,
4209 info->rx_buf_list_ex[0].phys_entry);
4210
4211 /* set new last rx descriptor address */
4212 write_reg16(info, RXDMA + EDA,
4213 info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4214
4215 /* set buffer length (shared by all rx dma data buffers) */
4216 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4217
4218 write_reg(info, RXDMA + DIR, 0x60); /* enable Rx DMA interrupts (EOM/BOF) */
4219 write_reg(info, RXDMA + DSR, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */
4220 } else {
4221 /* async, enable IRQ on rxdata */
4222 info->ie0_value |= RXRDYE;
4223 write_reg(info, IE0, info->ie0_value);
4224 }
4225
4226 write_reg(info, CMD, RXENABLE);
4227
4228 info->rx_overflow = FALSE;
4229 info->rx_enabled = 1;
4230 }
4231
4232 /* Enable the transmitter and send a transmit frame if
4233 * one is loaded in the DMA buffers.
4234 */
4235 void tx_start(SLMP_INFO *info)
4236 {
4237 if (debug_level >= DEBUG_LEVEL_ISR)
4238 printk("%s(%d):%s tx_start() tx_count=%d\n",
4239 __FILE__,__LINE__, info->device_name,info->tx_count );
4240
4241 if (!info->tx_enabled ) {
4242 write_reg(info, CMD, TXRESET);
4243 write_reg(info, CMD, TXENABLE);
4244 info->tx_enabled = TRUE;
4245 }
4246
4247 if ( info->tx_count ) {
4248
4249 /* If auto RTS enabled and RTS is inactive, then assert */
4250 /* RTS and set a flag indicating that the driver should */
4251 /* negate RTS when the transmission completes. */
4252
4253 info->drop_rts_on_tx_done = 0;
4254
4255 if (info->params.mode != MGSL_MODE_ASYNC) {
4256
4257 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4258 get_signals( info );
4259 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4260 info->serial_signals |= SerialSignal_RTS;
4261 set_signals( info );
4262 info->drop_rts_on_tx_done = 1;
4263 }
4264 }
4265
4266 write_reg16(info, TRC0,
4267 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4268
4269 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4270 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4271
4272 /* set TX CDA (current descriptor address) */
4273 write_reg16(info, TXDMA + CDA,
4274 info->tx_buf_list_ex[0].phys_entry);
4275
4276 /* set TX EDA (last descriptor address) */
4277 write_reg16(info, TXDMA + EDA,
4278 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4279
4280 /* enable underrun IRQ */
4281 info->ie1_value &= ~IDLE;
4282 info->ie1_value |= UDRN;
4283 write_reg(info, IE1, info->ie1_value);
4284 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4285
4286 write_reg(info, TXDMA + DIR, 0x40); /* enable Tx DMA interrupts (EOM) */
4287 write_reg(info, TXDMA + DSR, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */
4288
4289 mod_timer(&info->tx_timer, jiffies +
4290 msecs_to_jiffies(5000));
4291 }
4292 else {
4293 tx_load_fifo(info);
4294 /* async, enable IRQ on txdata */
4295 info->ie0_value |= TXRDYE;
4296 write_reg(info, IE0, info->ie0_value);
4297 }
4298
4299 info->tx_active = 1;
4300 }
4301 }
4302
4303 /* stop the transmitter and DMA
4304 */
4305 void tx_stop( SLMP_INFO *info )
4306 {
4307 if (debug_level >= DEBUG_LEVEL_ISR)
4308 printk("%s(%d):%s tx_stop()\n",
4309 __FILE__,__LINE__, info->device_name );
4310
4311 del_timer(&info->tx_timer);
4312
4313 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4314 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4315
4316 write_reg(info, CMD, TXRESET);
4317
4318 info->ie1_value &= ~(UDRN + IDLE);
4319 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
4320 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
4321
4322 info->ie0_value &= ~TXRDYE;
4323 write_reg(info, IE0, info->ie0_value); /* disable tx data interrupts */
4324
4325 info->tx_enabled = 0;
4326 info->tx_active = 0;
4327 }
4328
4329 /* Fill the transmit FIFO until the FIFO is full or
4330 * there is no more data to load.
4331 */
4332 void tx_load_fifo(SLMP_INFO *info)
4333 {
4334 u8 TwoBytes[2];
4335
4336 /* do nothing is now tx data available and no XON/XOFF pending */
4337
4338 if ( !info->tx_count && !info->x_char )
4339 return;
4340
4341 /* load the Transmit FIFO until FIFOs full or all data sent */
4342
4343 while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4344
4345 /* there is more space in the transmit FIFO and */
4346 /* there is more data in transmit buffer */
4347
4348 if ( (info->tx_count > 1) && !info->x_char ) {
4349 /* write 16-bits */
4350 TwoBytes[0] = info->tx_buf[info->tx_get++];
4351 if (info->tx_get >= info->max_frame_size)
4352 info->tx_get -= info->max_frame_size;
4353 TwoBytes[1] = info->tx_buf[info->tx_get++];
4354 if (info->tx_get >= info->max_frame_size)
4355 info->tx_get -= info->max_frame_size;
4356
4357 write_reg16(info, TRB, *((u16 *)TwoBytes));
4358
4359 info->tx_count -= 2;
4360 info->icount.tx += 2;
4361 } else {
4362 /* only 1 byte left to transmit or 1 FIFO slot left */
4363
4364 if (info->x_char) {
4365 /* transmit pending high priority char */
4366 write_reg(info, TRB, info->x_char);
4367 info->x_char = 0;
4368 } else {
4369 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4370 if (info->tx_get >= info->max_frame_size)
4371 info->tx_get -= info->max_frame_size;
4372 info->tx_count--;
4373 }
4374 info->icount.tx++;
4375 }
4376 }
4377 }
4378
4379 /* Reset a port to a known state
4380 */
4381 void reset_port(SLMP_INFO *info)
4382 {
4383 if (info->sca_base) {
4384
4385 tx_stop(info);
4386 rx_stop(info);
4387
4388 info->serial_signals &= ~(SerialSignal_DTR + SerialSignal_RTS);
4389 set_signals(info);
4390
4391 /* disable all port interrupts */
4392 info->ie0_value = 0;
4393 info->ie1_value = 0;
4394 info->ie2_value = 0;
4395 write_reg(info, IE0, info->ie0_value);
4396 write_reg(info, IE1, info->ie1_value);
4397 write_reg(info, IE2, info->ie2_value);
4398
4399 write_reg(info, CMD, CHRESET);
4400 }
4401 }
4402
4403 /* Reset all the ports to a known state.
4404 */
4405 void reset_adapter(SLMP_INFO *info)
4406 {
4407 int i;
4408
4409 for ( i=0; i < SCA_MAX_PORTS; ++i) {
4410 if (info->port_array[i])
4411 reset_port(info->port_array[i]);
4412 }
4413 }
4414
4415 /* Program port for asynchronous communications.
4416 */
4417 void async_mode(SLMP_INFO *info)
4418 {
4419
4420 unsigned char RegValue;
4421
4422 tx_stop(info);
4423 rx_stop(info);
4424
4425 /* MD0, Mode Register 0
4426 *
4427 * 07..05 PRCTL<2..0>, Protocol Mode, 000=async
4428 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4429 * 03 Reserved, must be 0
4430 * 02 CRCCC, CRC Calculation, 0=disabled
4431 * 01..00 STOP<1..0> Stop bits (00=1,10=2)
4432 *
4433 * 0000 0000
4434 */
4435 RegValue = 0x00;
4436 if (info->params.stop_bits != 1)
4437 RegValue |= BIT1;
4438 write_reg(info, MD0, RegValue);
4439
4440 /* MD1, Mode Register 1
4441 *
4442 * 07..06 BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4443 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4444 * 03..02 RXCHR<1..0>, rx char size
4445 * 01..00 PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4446 *
4447 * 0100 0000
4448 */
4449 RegValue = 0x40;
4450 switch (info->params.data_bits) {
4451 case 7: RegValue |= BIT4 + BIT2; break;
4452 case 6: RegValue |= BIT5 + BIT3; break;
4453 case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4454 }
4455 if (info->params.parity != ASYNC_PARITY_NONE) {
4456 RegValue |= BIT1;
4457 if (info->params.parity == ASYNC_PARITY_ODD)
4458 RegValue |= BIT0;
4459 }
4460 write_reg(info, MD1, RegValue);
4461
4462 /* MD2, Mode Register 2
4463 *
4464 * 07..02 Reserved, must be 0
4465 * 01..00 CNCT<1..0> Channel connection, 00=normal 11=local loopback
4466 *
4467 * 0000 0000
4468 */
4469 RegValue = 0x00;
4470 if (info->params.loopback)
4471 RegValue |= (BIT1 + BIT0);
4472 write_reg(info, MD2, RegValue);
4473
4474 /* RXS, Receive clock source
4475 *
4476 * 07 Reserved, must be 0
4477 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4478 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4479 */
4480 RegValue=BIT6;
4481 write_reg(info, RXS, RegValue);
4482
4483 /* TXS, Transmit clock source
4484 *
4485 * 07 Reserved, must be 0
4486 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4487 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4488 */
4489 RegValue=BIT6;
4490 write_reg(info, TXS, RegValue);
4491
4492 /* Control Register
4493 *
4494 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4495 */
4496 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4497 write_control_reg(info);
4498
4499 tx_set_idle(info);
4500
4501 /* RRC Receive Ready Control 0
4502 *
4503 * 07..05 Reserved, must be 0
4504 * 04..00 RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4505 */
4506 write_reg(info, RRC, 0x00);
4507
4508 /* TRC0 Transmit Ready Control 0
4509 *
4510 * 07..05 Reserved, must be 0
4511 * 04..00 TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4512 */
4513 write_reg(info, TRC0, 0x10);
4514
4515 /* TRC1 Transmit Ready Control 1
4516 *
4517 * 07..05 Reserved, must be 0
4518 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4519 */
4520 write_reg(info, TRC1, 0x1e);
4521
4522 /* CTL, MSCI control register
4523 *
4524 * 07..06 Reserved, set to 0
4525 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4526 * 04 IDLC, idle control, 0=mark 1=idle register
4527 * 03 BRK, break, 0=off 1 =on (async)
4528 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4529 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4530 * 00 RTS, RTS output control, 0=active 1=inactive
4531 *
4532 * 0001 0001
4533 */
4534 RegValue = 0x10;
4535 if (!(info->serial_signals & SerialSignal_RTS))
4536 RegValue |= 0x01;
4537 write_reg(info, CTL, RegValue);
4538
4539 /* enable status interrupts */
4540 info->ie0_value |= TXINTE + RXINTE;
4541 write_reg(info, IE0, info->ie0_value);
4542
4543 /* enable break detect interrupt */
4544 info->ie1_value = BRKD;
4545 write_reg(info, IE1, info->ie1_value);
4546
4547 /* enable rx overrun interrupt */
4548 info->ie2_value = OVRN;
4549 write_reg(info, IE2, info->ie2_value);
4550
4551 set_rate( info, info->params.data_rate * 16 );
4552 }
4553
4554 /* Program the SCA for HDLC communications.
4555 */
4556 void hdlc_mode(SLMP_INFO *info)
4557 {
4558 unsigned char RegValue;
4559 u32 DpllDivisor;
4560
4561 // Can't use DPLL because SCA outputs recovered clock on RxC when
4562 // DPLL mode selected. This causes output contention with RxC receiver.
4563 // Use of DPLL would require external hardware to disable RxC receiver
4564 // when DPLL mode selected.
4565 info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4566
4567 /* disable DMA interrupts */
4568 write_reg(info, TXDMA + DIR, 0);
4569 write_reg(info, RXDMA + DIR, 0);
4570
4571 /* MD0, Mode Register 0
4572 *
4573 * 07..05 PRCTL<2..0>, Protocol Mode, 100=HDLC
4574 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4575 * 03 Reserved, must be 0
4576 * 02 CRCCC, CRC Calculation, 1=enabled
4577 * 01 CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4578 * 00 CRC0, CRC initial value, 1 = all 1s
4579 *
4580 * 1000 0001
4581 */
4582 RegValue = 0x81;
4583 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4584 RegValue |= BIT4;
4585 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4586 RegValue |= BIT4;
4587 if (info->params.crc_type == HDLC_CRC_16_CCITT)
4588 RegValue |= BIT2 + BIT1;
4589 write_reg(info, MD0, RegValue);
4590
4591 /* MD1, Mode Register 1
4592 *
4593 * 07..06 ADDRS<1..0>, Address detect, 00=no addr check
4594 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits
4595 * 03..02 RXCHR<1..0>, rx char size, 00=8 bits
4596 * 01..00 PMPM<1..0>, Parity mode, 00=no parity
4597 *
4598 * 0000 0000
4599 */
4600 RegValue = 0x00;
4601 write_reg(info, MD1, RegValue);
4602
4603 /* MD2, Mode Register 2
4604 *
4605 * 07 NRZFM, 0=NRZ, 1=FM
4606 * 06..05 CODE<1..0> Encoding, 00=NRZ
4607 * 04..03 DRATE<1..0> DPLL Divisor, 00=8
4608 * 02 Reserved, must be 0
4609 * 01..00 CNCT<1..0> Channel connection, 0=normal
4610 *
4611 * 0000 0000
4612 */
4613 RegValue = 0x00;
4614 switch(info->params.encoding) {
4615 case HDLC_ENCODING_NRZI: RegValue |= BIT5; break;
4616 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4617 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4618 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break; /* aka Manchester */
4619 #if 0
4620 case HDLC_ENCODING_NRZB: /* not supported */
4621 case HDLC_ENCODING_NRZI_MARK: /* not supported */
4622 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: /* not supported */
4623 #endif
4624 }
4625 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4626 DpllDivisor = 16;
4627 RegValue |= BIT3;
4628 } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4629 DpllDivisor = 8;
4630 } else {
4631 DpllDivisor = 32;
4632 RegValue |= BIT4;
4633 }
4634 write_reg(info, MD2, RegValue);
4635
4636
4637 /* RXS, Receive clock source
4638 *
4639 * 07 Reserved, must be 0
4640 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4641 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4642 */
4643 RegValue=0;
4644 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4645 RegValue |= BIT6;
4646 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4647 RegValue |= BIT6 + BIT5;
4648 write_reg(info, RXS, RegValue);
4649
4650 /* TXS, Transmit clock source
4651 *
4652 * 07 Reserved, must be 0
4653 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4654 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4655 */
4656 RegValue=0;
4657 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4658 RegValue |= BIT6;
4659 if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4660 RegValue |= BIT6 + BIT5;
4661 write_reg(info, TXS, RegValue);
4662
4663 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4664 set_rate(info, info->params.clock_speed * DpllDivisor);
4665 else
4666 set_rate(info, info->params.clock_speed);
4667
4668 /* GPDATA (General Purpose I/O Data Register)
4669 *
4670 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4671 */
4672 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4673 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4674 else
4675 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4676 write_control_reg(info);
4677
4678 /* RRC Receive Ready Control 0
4679 *
4680 * 07..05 Reserved, must be 0
4681 * 04..00 RRC<4..0> Rx FIFO trigger active
4682 */
4683 write_reg(info, RRC, rx_active_fifo_level);
4684
4685 /* TRC0 Transmit Ready Control 0
4686 *
4687 * 07..05 Reserved, must be 0
4688 * 04..00 TRC<4..0> Tx FIFO trigger active
4689 */
4690 write_reg(info, TRC0, tx_active_fifo_level);
4691
4692 /* TRC1 Transmit Ready Control 1
4693 *
4694 * 07..05 Reserved, must be 0
4695 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4696 */
4697 write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4698
4699 /* DMR, DMA Mode Register
4700 *
4701 * 07..05 Reserved, must be 0
4702 * 04 TMOD, Transfer Mode: 1=chained-block
4703 * 03 Reserved, must be 0
4704 * 02 NF, Number of Frames: 1=multi-frame
4705 * 01 CNTE, Frame End IRQ Counter enable: 0=disabled
4706 * 00 Reserved, must be 0
4707 *
4708 * 0001 0100
4709 */
4710 write_reg(info, TXDMA + DMR, 0x14);
4711 write_reg(info, RXDMA + DMR, 0x14);
4712
4713 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4714 write_reg(info, RXDMA + CPB,
4715 (unsigned char)(info->buffer_list_phys >> 16));
4716
4717 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4718 write_reg(info, TXDMA + CPB,
4719 (unsigned char)(info->buffer_list_phys >> 16));
4720
4721 /* enable status interrupts. other code enables/disables
4722 * the individual sources for these two interrupt classes.
4723 */
4724 info->ie0_value |= TXINTE + RXINTE;
4725 write_reg(info, IE0, info->ie0_value);
4726
4727 /* CTL, MSCI control register
4728 *
4729 * 07..06 Reserved, set to 0
4730 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4731 * 04 IDLC, idle control, 0=mark 1=idle register
4732 * 03 BRK, break, 0=off 1 =on (async)
4733 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4734 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4735 * 00 RTS, RTS output control, 0=active 1=inactive
4736 *
4737 * 0001 0001
4738 */
4739 RegValue = 0x10;
4740 if (!(info->serial_signals & SerialSignal_RTS))
4741 RegValue |= 0x01;
4742 write_reg(info, CTL, RegValue);
4743
4744 /* preamble not supported ! */
4745
4746 tx_set_idle(info);
4747 tx_stop(info);
4748 rx_stop(info);
4749
4750 set_rate(info, info->params.clock_speed);
4751
4752 if (info->params.loopback)
4753 enable_loopback(info,1);
4754 }
4755
4756 /* Set the transmit HDLC idle mode
4757 */
4758 void tx_set_idle(SLMP_INFO *info)
4759 {
4760 unsigned char RegValue = 0xff;
4761
4762 /* Map API idle mode to SCA register bits */
4763 switch(info->idle_mode) {
4764 case HDLC_TXIDLE_FLAGS: RegValue = 0x7e; break;
4765 case HDLC_TXIDLE_ALT_ZEROS_ONES: RegValue = 0xaa; break;
4766 case HDLC_TXIDLE_ZEROS: RegValue = 0x00; break;
4767 case HDLC_TXIDLE_ONES: RegValue = 0xff; break;
4768 case HDLC_TXIDLE_ALT_MARK_SPACE: RegValue = 0xaa; break;
4769 case HDLC_TXIDLE_SPACE: RegValue = 0x00; break;
4770 case HDLC_TXIDLE_MARK: RegValue = 0xff; break;
4771 }
4772
4773 write_reg(info, IDL, RegValue);
4774 }
4775
4776 /* Query the adapter for the state of the V24 status (input) signals.
4777 */
4778 void get_signals(SLMP_INFO *info)
4779 {
4780 u16 status = read_reg(info, SR3);
4781 u16 gpstatus = read_status_reg(info);
4782 u16 testbit;
4783
4784 /* clear all serial signals except DTR and RTS */
4785 info->serial_signals &= SerialSignal_DTR + SerialSignal_RTS;
4786
4787 /* set serial signal bits to reflect MISR */
4788
4789 if (!(status & BIT3))
4790 info->serial_signals |= SerialSignal_CTS;
4791
4792 if ( !(status & BIT2))
4793 info->serial_signals |= SerialSignal_DCD;
4794
4795 testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4796 if (!(gpstatus & testbit))
4797 info->serial_signals |= SerialSignal_RI;
4798
4799 testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4800 if (!(gpstatus & testbit))
4801 info->serial_signals |= SerialSignal_DSR;
4802 }
4803
4804 /* Set the state of DTR and RTS based on contents of
4805 * serial_signals member of device context.
4806 */
4807 void set_signals(SLMP_INFO *info)
4808 {
4809 unsigned char RegValue;
4810 u16 EnableBit;
4811
4812 RegValue = read_reg(info, CTL);
4813 if (info->serial_signals & SerialSignal_RTS)
4814 RegValue &= ~BIT0;
4815 else
4816 RegValue |= BIT0;
4817 write_reg(info, CTL, RegValue);
4818
4819 // Port 0..3 DTR is ctrl reg <1,3,5,7>
4820 EnableBit = BIT1 << (info->port_num*2);
4821 if (info->serial_signals & SerialSignal_DTR)
4822 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4823 else
4824 info->port_array[0]->ctrlreg_value |= EnableBit;
4825 write_control_reg(info);
4826 }
4827
4828 /*******************/
4829 /* DMA Buffer Code */
4830 /*******************/
4831
4832 /* Set the count for all receive buffers to SCABUFSIZE
4833 * and set the current buffer to the first buffer. This effectively
4834 * makes all buffers free and discards any data in buffers.
4835 */
4836 void rx_reset_buffers(SLMP_INFO *info)
4837 {
4838 rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4839 }
4840
4841 /* Free the buffers used by a received frame
4842 *
4843 * info pointer to device instance data
4844 * first index of 1st receive buffer of frame
4845 * last index of last receive buffer of frame
4846 */
4847 void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4848 {
4849 int done = 0;
4850
4851 while(!done) {
4852 /* reset current buffer for reuse */
4853 info->rx_buf_list[first].status = 0xff;
4854
4855 if (first == last) {
4856 done = 1;
4857 /* set new last rx descriptor address */
4858 write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4859 }
4860
4861 first++;
4862 if (first == info->rx_buf_count)
4863 first = 0;
4864 }
4865
4866 /* set current buffer to next buffer after last buffer of frame */
4867 info->current_rx_buf = first;
4868 }
4869
4870 /* Return a received frame from the receive DMA buffers.
4871 * Only frames received without errors are returned.
4872 *
4873 * Return Value: 1 if frame returned, otherwise 0
4874 */
4875 int rx_get_frame(SLMP_INFO *info)
4876 {
4877 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
4878 unsigned short status;
4879 unsigned int framesize = 0;
4880 int ReturnCode = 0;
4881 unsigned long flags;
4882 struct tty_struct *tty = info->tty;
4883 unsigned char addr_field = 0xff;
4884 SCADESC *desc;
4885 SCADESC_EX *desc_ex;
4886
4887 CheckAgain:
4888 /* assume no frame returned, set zero length */
4889 framesize = 0;
4890 addr_field = 0xff;
4891
4892 /*
4893 * current_rx_buf points to the 1st buffer of the next available
4894 * receive frame. To find the last buffer of the frame look for
4895 * a non-zero status field in the buffer entries. (The status
4896 * field is set by the 16C32 after completing a receive frame.
4897 */
4898 StartIndex = EndIndex = info->current_rx_buf;
4899
4900 for ( ;; ) {
4901 desc = &info->rx_buf_list[EndIndex];
4902 desc_ex = &info->rx_buf_list_ex[EndIndex];
4903
4904 if (desc->status == 0xff)
4905 goto Cleanup; /* current desc still in use, no frames available */
4906
4907 if (framesize == 0 && info->params.addr_filter != 0xff)
4908 addr_field = desc_ex->virt_addr[0];
4909
4910 framesize += desc->length;
4911
4912 /* Status != 0 means last buffer of frame */
4913 if (desc->status)
4914 break;
4915
4916 EndIndex++;
4917 if (EndIndex == info->rx_buf_count)
4918 EndIndex = 0;
4919
4920 if (EndIndex == info->current_rx_buf) {
4921 /* all buffers have been 'used' but none mark */
4922 /* the end of a frame. Reset buffers and receiver. */
4923 if ( info->rx_enabled ){
4924 spin_lock_irqsave(&info->lock,flags);
4925 rx_start(info);
4926 spin_unlock_irqrestore(&info->lock,flags);
4927 }
4928 goto Cleanup;
4929 }
4930
4931 }
4932
4933 /* check status of receive frame */
4934
4935 /* frame status is byte stored after frame data
4936 *
4937 * 7 EOM (end of msg), 1 = last buffer of frame
4938 * 6 Short Frame, 1 = short frame
4939 * 5 Abort, 1 = frame aborted
4940 * 4 Residue, 1 = last byte is partial
4941 * 3 Overrun, 1 = overrun occurred during frame reception
4942 * 2 CRC, 1 = CRC error detected
4943 *
4944 */
4945 status = desc->status;
4946
4947 /* ignore CRC bit if not using CRC (bit is undefined) */
4948 /* Note:CRC is not save to data buffer */
4949 if (info->params.crc_type == HDLC_CRC_NONE)
4950 status &= ~BIT2;
4951
4952 if (framesize == 0 ||
4953 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4954 /* discard 0 byte frames, this seems to occur sometime
4955 * when remote is idling flags.
4956 */
4957 rx_free_frame_buffers(info, StartIndex, EndIndex);
4958 goto CheckAgain;
4959 }
4960
4961 if (framesize < 2)
4962 status |= BIT6;
4963
4964 if (status & (BIT6+BIT5+BIT3+BIT2)) {
4965 /* received frame has errors,
4966 * update counts and mark frame size as 0
4967 */
4968 if (status & BIT6)
4969 info->icount.rxshort++;
4970 else if (status & BIT5)
4971 info->icount.rxabort++;
4972 else if (status & BIT3)
4973 info->icount.rxover++;
4974 else
4975 info->icount.rxcrc++;
4976
4977 framesize = 0;
4978 #if SYNCLINK_GENERIC_HDLC
4979 {
4980 struct net_device_stats *stats = hdlc_stats(info->netdev);
4981 stats->rx_errors++;
4982 stats->rx_frame_errors++;
4983 }
4984 #endif
4985 }
4986
4987 if ( debug_level >= DEBUG_LEVEL_BH )
4988 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4989 __FILE__,__LINE__,info->device_name,status,framesize);
4990
4991 if ( debug_level >= DEBUG_LEVEL_DATA )
4992 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
4993 min_t(int, framesize,SCABUFSIZE),0);
4994
4995 if (framesize) {
4996 if (framesize > info->max_frame_size)
4997 info->icount.rxlong++;
4998 else {
4999 /* copy dma buffer(s) to contiguous intermediate buffer */
5000 int copy_count = framesize;
5001 int index = StartIndex;
5002 unsigned char *ptmp = info->tmp_rx_buf;
5003 info->tmp_rx_buf_count = framesize;
5004
5005 info->icount.rxok++;
5006
5007 while(copy_count) {
5008 int partial_count = min(copy_count,SCABUFSIZE);
5009 memcpy( ptmp,
5010 info->rx_buf_list_ex[index].virt_addr,
5011 partial_count );
5012 ptmp += partial_count;
5013 copy_count -= partial_count;
5014
5015 if ( ++index == info->rx_buf_count )
5016 index = 0;
5017 }
5018
5019 #if SYNCLINK_GENERIC_HDLC
5020 if (info->netcount)
5021 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
5022 else
5023 #endif
5024 ldisc_receive_buf(tty,info->tmp_rx_buf,
5025 info->flag_buf, framesize);
5026 }
5027 }
5028 /* Free the buffers used by this frame. */
5029 rx_free_frame_buffers( info, StartIndex, EndIndex );
5030
5031 ReturnCode = 1;
5032
5033 Cleanup:
5034 if ( info->rx_enabled && info->rx_overflow ) {
5035 /* Receiver is enabled, but needs to restarted due to
5036 * rx buffer overflow. If buffers are empty, restart receiver.
5037 */
5038 if (info->rx_buf_list[EndIndex].status == 0xff) {
5039 spin_lock_irqsave(&info->lock,flags);
5040 rx_start(info);
5041 spin_unlock_irqrestore(&info->lock,flags);
5042 }
5043 }
5044
5045 return ReturnCode;
5046 }
5047
5048 /* load the transmit DMA buffer with data
5049 */
5050 void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
5051 {
5052 unsigned short copy_count;
5053 unsigned int i = 0;
5054 SCADESC *desc;
5055 SCADESC_EX *desc_ex;
5056
5057 if ( debug_level >= DEBUG_LEVEL_DATA )
5058 trace_block(info,buf, min_t(int, count,SCABUFSIZE), 1);
5059
5060 /* Copy source buffer to one or more DMA buffers, starting with
5061 * the first transmit dma buffer.
5062 */
5063 for(i=0;;)
5064 {
5065 copy_count = min_t(unsigned short,count,SCABUFSIZE);
5066
5067 desc = &info->tx_buf_list[i];
5068 desc_ex = &info->tx_buf_list_ex[i];
5069
5070 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5071
5072 desc->length = copy_count;
5073 desc->status = 0;
5074
5075 buf += copy_count;
5076 count -= copy_count;
5077
5078 if (!count)
5079 break;
5080
5081 i++;
5082 if (i >= info->tx_buf_count)
5083 i = 0;
5084 }
5085
5086 info->tx_buf_list[i].status = 0x81; /* set EOM and EOT status */
5087 info->last_tx_buf = ++i;
5088 }
5089
5090 int register_test(SLMP_INFO *info)
5091 {
5092 static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5093 static unsigned int count = ARRAY_SIZE(testval);
5094 unsigned int i;
5095 int rc = TRUE;
5096 unsigned long flags;
5097
5098 spin_lock_irqsave(&info->lock,flags);
5099 reset_port(info);
5100
5101 /* assume failure */
5102 info->init_error = DiagStatus_AddressFailure;
5103
5104 /* Write bit patterns to various registers but do it out of */
5105 /* sync, then read back and verify values. */
5106
5107 for (i = 0 ; i < count ; i++) {
5108 write_reg(info, TMC, testval[i]);
5109 write_reg(info, IDL, testval[(i+1)%count]);
5110 write_reg(info, SA0, testval[(i+2)%count]);
5111 write_reg(info, SA1, testval[(i+3)%count]);
5112
5113 if ( (read_reg(info, TMC) != testval[i]) ||
5114 (read_reg(info, IDL) != testval[(i+1)%count]) ||
5115 (read_reg(info, SA0) != testval[(i+2)%count]) ||
5116 (read_reg(info, SA1) != testval[(i+3)%count]) )
5117 {
5118 rc = FALSE;
5119 break;
5120 }
5121 }
5122
5123 reset_port(info);
5124 spin_unlock_irqrestore(&info->lock,flags);
5125
5126 return rc;
5127 }
5128
5129 int irq_test(SLMP_INFO *info)
5130 {
5131 unsigned long timeout;
5132 unsigned long flags;
5133
5134 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5135
5136 spin_lock_irqsave(&info->lock,flags);
5137 reset_port(info);
5138
5139 /* assume failure */
5140 info->init_error = DiagStatus_IrqFailure;
5141 info->irq_occurred = FALSE;
5142
5143 /* setup timer0 on SCA0 to interrupt */
5144
5145 /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5146 write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5147
5148 write_reg(info, (unsigned char)(timer + TEPR), 0); /* timer expand prescale */
5149 write_reg16(info, (unsigned char)(timer + TCONR), 1); /* timer constant */
5150
5151
5152 /* TMCS, Timer Control/Status Register
5153 *
5154 * 07 CMF, Compare match flag (read only) 1=match
5155 * 06 ECMI, CMF Interrupt Enable: 1=enabled
5156 * 05 Reserved, must be 0
5157 * 04 TME, Timer Enable
5158 * 03..00 Reserved, must be 0
5159 *
5160 * 0101 0000
5161 */
5162 write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5163
5164 spin_unlock_irqrestore(&info->lock,flags);
5165
5166 timeout=100;
5167 while( timeout-- && !info->irq_occurred ) {
5168 msleep_interruptible(10);
5169 }
5170
5171 spin_lock_irqsave(&info->lock,flags);
5172 reset_port(info);
5173 spin_unlock_irqrestore(&info->lock,flags);
5174
5175 return info->irq_occurred;
5176 }
5177
5178 /* initialize individual SCA device (2 ports)
5179 */
5180 static int sca_init(SLMP_INFO *info)
5181 {
5182 /* set wait controller to single mem partition (low), no wait states */
5183 write_reg(info, PABR0, 0); /* wait controller addr boundary 0 */
5184 write_reg(info, PABR1, 0); /* wait controller addr boundary 1 */
5185 write_reg(info, WCRL, 0); /* wait controller low range */
5186 write_reg(info, WCRM, 0); /* wait controller mid range */
5187 write_reg(info, WCRH, 0); /* wait controller high range */
5188
5189 /* DPCR, DMA Priority Control
5190 *
5191 * 07..05 Not used, must be 0
5192 * 04 BRC, bus release condition: 0=all transfers complete
5193 * 03 CCC, channel change condition: 0=every cycle
5194 * 02..00 PR<2..0>, priority 100=round robin
5195 *
5196 * 00000100 = 0x04
5197 */
5198 write_reg(info, DPCR, dma_priority);
5199
5200 /* DMA Master Enable, BIT7: 1=enable all channels */
5201 write_reg(info, DMER, 0x80);
5202
5203 /* enable all interrupt classes */
5204 write_reg(info, IER0, 0xff); /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5205 write_reg(info, IER1, 0xff); /* DMIB,DMIA (channels 0-3) */
5206 write_reg(info, IER2, 0xf0); /* TIRQ (timers 0-3) */
5207
5208 /* ITCR, interrupt control register
5209 * 07 IPC, interrupt priority, 0=MSCI->DMA
5210 * 06..05 IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5211 * 04 VOS, Vector Output, 0=unmodified vector
5212 * 03..00 Reserved, must be 0
5213 */
5214 write_reg(info, ITCR, 0);
5215
5216 return TRUE;
5217 }
5218
5219 /* initialize adapter hardware
5220 */
5221 int init_adapter(SLMP_INFO *info)
5222 {
5223 int i;
5224
5225 /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5226 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5227 u32 readval;
5228
5229 info->misc_ctrl_value |= BIT30;
5230 *MiscCtrl = info->misc_ctrl_value;
5231
5232 /*
5233 * Force at least 170ns delay before clearing
5234 * reset bit. Each read from LCR takes at least
5235 * 30ns so 10 times for 300ns to be safe.
5236 */
5237 for(i=0;i<10;i++)
5238 readval = *MiscCtrl;
5239
5240 info->misc_ctrl_value &= ~BIT30;
5241 *MiscCtrl = info->misc_ctrl_value;
5242
5243 /* init control reg (all DTRs off, all clksel=input) */
5244 info->ctrlreg_value = 0xaa;
5245 write_control_reg(info);
5246
5247 {
5248 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5249 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5250
5251 switch(read_ahead_count)
5252 {
5253 case 16:
5254 lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5255 break;
5256 case 8:
5257 lcr1_brdr_value |= BIT5 + BIT4;
5258 break;
5259 case 4:
5260 lcr1_brdr_value |= BIT5 + BIT3;
5261 break;
5262 case 0:
5263 lcr1_brdr_value |= BIT5;
5264 break;
5265 }
5266
5267 *LCR1BRDR = lcr1_brdr_value;
5268 *MiscCtrl = misc_ctrl_value;
5269 }
5270
5271 sca_init(info->port_array[0]);
5272 sca_init(info->port_array[2]);
5273
5274 return TRUE;
5275 }
5276
5277 /* Loopback an HDLC frame to test the hardware
5278 * interrupt and DMA functions.
5279 */
5280 int loopback_test(SLMP_INFO *info)
5281 {
5282 #define TESTFRAMESIZE 20
5283
5284 unsigned long timeout;
5285 u16 count = TESTFRAMESIZE;
5286 unsigned char buf[TESTFRAMESIZE];
5287 int rc = FALSE;
5288 unsigned long flags;
5289
5290 struct tty_struct *oldtty = info->tty;
5291 u32 speed = info->params.clock_speed;
5292
5293 info->params.clock_speed = 3686400;
5294 info->tty = NULL;
5295
5296 /* assume failure */
5297 info->init_error = DiagStatus_DmaFailure;
5298
5299 /* build and send transmit frame */
5300 for (count = 0; count < TESTFRAMESIZE;++count)
5301 buf[count] = (unsigned char)count;
5302
5303 memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5304
5305 /* program hardware for HDLC and enabled receiver */
5306 spin_lock_irqsave(&info->lock,flags);
5307 hdlc_mode(info);
5308 enable_loopback(info,1);
5309 rx_start(info);
5310 info->tx_count = count;
5311 tx_load_dma_buffer(info,buf,count);
5312 tx_start(info);
5313 spin_unlock_irqrestore(&info->lock,flags);
5314
5315 /* wait for receive complete */
5316 /* Set a timeout for waiting for interrupt. */
5317 for ( timeout = 100; timeout; --timeout ) {
5318 msleep_interruptible(10);
5319
5320 if (rx_get_frame(info)) {
5321 rc = TRUE;
5322 break;
5323 }
5324 }
5325
5326 /* verify received frame length and contents */
5327 if (rc == TRUE &&
5328 ( info->tmp_rx_buf_count != count ||
5329 memcmp(buf, info->tmp_rx_buf,count))) {
5330 rc = FALSE;
5331 }
5332
5333 spin_lock_irqsave(&info->lock,flags);
5334 reset_adapter(info);
5335 spin_unlock_irqrestore(&info->lock,flags);
5336
5337 info->params.clock_speed = speed;
5338 info->tty = oldtty;
5339
5340 return rc;
5341 }
5342
5343 /* Perform diagnostics on hardware
5344 */
5345 int adapter_test( SLMP_INFO *info )
5346 {
5347 unsigned long flags;
5348 if ( debug_level >= DEBUG_LEVEL_INFO )
5349 printk( "%s(%d):Testing device %s\n",
5350 __FILE__,__LINE__,info->device_name );
5351
5352 spin_lock_irqsave(&info->lock,flags);
5353 init_adapter(info);
5354 spin_unlock_irqrestore(&info->lock,flags);
5355
5356 info->port_array[0]->port_count = 0;
5357
5358 if ( register_test(info->port_array[0]) &&
5359 register_test(info->port_array[1])) {
5360
5361 info->port_array[0]->port_count = 2;
5362
5363 if ( register_test(info->port_array[2]) &&
5364 register_test(info->port_array[3]) )
5365 info->port_array[0]->port_count += 2;
5366 }
5367 else {
5368 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5369 __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5370 return -ENODEV;
5371 }
5372
5373 if ( !irq_test(info->port_array[0]) ||
5374 !irq_test(info->port_array[1]) ||
5375 (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5376 (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5377 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5378 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5379 return -ENODEV;
5380 }
5381
5382 if (!loopback_test(info->port_array[0]) ||
5383 !loopback_test(info->port_array[1]) ||
5384 (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5385 (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5386 printk( "%s(%d):DMA test failure for device %s\n",
5387 __FILE__,__LINE__,info->device_name);
5388 return -ENODEV;
5389 }
5390
5391 if ( debug_level >= DEBUG_LEVEL_INFO )
5392 printk( "%s(%d):device %s passed diagnostics\n",
5393 __FILE__,__LINE__,info->device_name );
5394
5395 info->port_array[0]->init_error = 0;
5396 info->port_array[1]->init_error = 0;
5397 if ( info->port_count > 2 ) {
5398 info->port_array[2]->init_error = 0;
5399 info->port_array[3]->init_error = 0;
5400 }
5401
5402 return 0;
5403 }
5404
5405 /* Test the shared memory on a PCI adapter.
5406 */
5407 int memory_test(SLMP_INFO *info)
5408 {
5409 static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5410 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5411 unsigned long count = ARRAY_SIZE(testval);
5412 unsigned long i;
5413 unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5414 unsigned long * addr = (unsigned long *)info->memory_base;
5415
5416 /* Test data lines with test pattern at one location. */
5417
5418 for ( i = 0 ; i < count ; i++ ) {
5419 *addr = testval[i];
5420 if ( *addr != testval[i] )
5421 return FALSE;
5422 }
5423
5424 /* Test address lines with incrementing pattern over */
5425 /* entire address range. */
5426
5427 for ( i = 0 ; i < limit ; i++ ) {
5428 *addr = i * 4;
5429 addr++;
5430 }
5431
5432 addr = (unsigned long *)info->memory_base;
5433
5434 for ( i = 0 ; i < limit ; i++ ) {
5435 if ( *addr != i * 4 )
5436 return FALSE;
5437 addr++;
5438 }
5439
5440 memset( info->memory_base, 0, SCA_MEM_SIZE );
5441 return TRUE;
5442 }
5443
5444 /* Load data into PCI adapter shared memory.
5445 *
5446 * The PCI9050 releases control of the local bus
5447 * after completing the current read or write operation.
5448 *
5449 * While the PCI9050 write FIFO not empty, the
5450 * PCI9050 treats all of the writes as a single transaction
5451 * and does not release the bus. This causes DMA latency problems
5452 * at high speeds when copying large data blocks to the shared memory.
5453 *
5454 * This function breaks a write into multiple transations by
5455 * interleaving a read which flushes the write FIFO and 'completes'
5456 * the write transation. This allows any pending DMA request to gain control
5457 * of the local bus in a timely fasion.
5458 */
5459 void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5460 {
5461 /* A load interval of 16 allows for 4 32-bit writes at */
5462 /* 136ns each for a maximum latency of 542ns on the local bus.*/
5463
5464 unsigned short interval = count / sca_pci_load_interval;
5465 unsigned short i;
5466
5467 for ( i = 0 ; i < interval ; i++ )
5468 {
5469 memcpy(dest, src, sca_pci_load_interval);
5470 read_status_reg(info);
5471 dest += sca_pci_load_interval;
5472 src += sca_pci_load_interval;
5473 }
5474
5475 memcpy(dest, src, count % sca_pci_load_interval);
5476 }
5477
5478 void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5479 {
5480 int i;
5481 int linecount;
5482 if (xmit)
5483 printk("%s tx data:\n",info->device_name);
5484 else
5485 printk("%s rx data:\n",info->device_name);
5486
5487 while(count) {
5488 if (count > 16)
5489 linecount = 16;
5490 else
5491 linecount = count;
5492
5493 for(i=0;i<linecount;i++)
5494 printk("%02X ",(unsigned char)data[i]);
5495 for(;i<17;i++)
5496 printk(" ");
5497 for(i=0;i<linecount;i++) {
5498 if (data[i]>=040 && data[i]<=0176)
5499 printk("%c",data[i]);
5500 else
5501 printk(".");
5502 }
5503 printk("\n");
5504
5505 data += linecount;
5506 count -= linecount;
5507 }
5508 } /* end of trace_block() */
5509
5510 /* called when HDLC frame times out
5511 * update stats and do tx completion processing
5512 */
5513 void tx_timeout(unsigned long context)
5514 {
5515 SLMP_INFO *info = (SLMP_INFO*)context;
5516 unsigned long flags;
5517
5518 if ( debug_level >= DEBUG_LEVEL_INFO )
5519 printk( "%s(%d):%s tx_timeout()\n",
5520 __FILE__,__LINE__,info->device_name);
5521 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5522 info->icount.txtimeout++;
5523 }
5524 spin_lock_irqsave(&info->lock,flags);
5525 info->tx_active = 0;
5526 info->tx_count = info->tx_put = info->tx_get = 0;
5527
5528 spin_unlock_irqrestore(&info->lock,flags);
5529
5530 #if SYNCLINK_GENERIC_HDLC
5531 if (info->netcount)
5532 hdlcdev_tx_done(info);
5533 else
5534 #endif
5535 bh_transmit(info);
5536 }
5537
5538 /* called to periodically check the DSR/RI modem signal input status
5539 */
5540 void status_timeout(unsigned long context)
5541 {
5542 u16 status = 0;
5543 SLMP_INFO *info = (SLMP_INFO*)context;
5544 unsigned long flags;
5545 unsigned char delta;
5546
5547
5548 spin_lock_irqsave(&info->lock,flags);
5549 get_signals(info);
5550 spin_unlock_irqrestore(&info->lock,flags);
5551
5552 /* check for DSR/RI state change */
5553
5554 delta = info->old_signals ^ info->serial_signals;
5555 info->old_signals = info->serial_signals;
5556
5557 if (delta & SerialSignal_DSR)
5558 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5559
5560 if (delta & SerialSignal_RI)
5561 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5562
5563 if (delta & SerialSignal_DCD)
5564 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5565
5566 if (delta & SerialSignal_CTS)
5567 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5568
5569 if (status)
5570 isr_io_pin(info,status);
5571
5572 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
5573 }
5574
5575
5576 /* Register Access Routines -
5577 * All registers are memory mapped
5578 */
5579 #define CALC_REGADDR() \
5580 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5581 if (info->port_num > 1) \
5582 RegAddr += 256; /* port 0-1 SCA0, 2-3 SCA1 */ \
5583 if ( info->port_num & 1) { \
5584 if (Addr > 0x7f) \
5585 RegAddr += 0x40; /* DMA access */ \
5586 else if (Addr > 0x1f && Addr < 0x60) \
5587 RegAddr += 0x20; /* MSCI access */ \
5588 }
5589
5590
5591 unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5592 {
5593 CALC_REGADDR();
5594 return *RegAddr;
5595 }
5596 void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5597 {
5598 CALC_REGADDR();
5599 *RegAddr = Value;
5600 }
5601
5602 u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5603 {
5604 CALC_REGADDR();
5605 return *((u16 *)RegAddr);
5606 }
5607
5608 void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5609 {
5610 CALC_REGADDR();
5611 *((u16 *)RegAddr) = Value;
5612 }
5613
5614 unsigned char read_status_reg(SLMP_INFO * info)
5615 {
5616 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5617 return *RegAddr;
5618 }
5619
5620 void write_control_reg(SLMP_INFO * info)
5621 {
5622 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5623 *RegAddr = info->port_array[0]->ctrlreg_value;
5624 }
5625
5626
5627 static int __devinit synclinkmp_init_one (struct pci_dev *dev,
5628 const struct pci_device_id *ent)
5629 {
5630 if (pci_enable_device(dev)) {
5631 printk("error enabling pci device %p\n", dev);
5632 return -EIO;
5633 }
5634 device_init( ++synclinkmp_adapter_count, dev );
5635 return 0;
5636 }
5637
5638 static void __devexit synclinkmp_remove_one (struct pci_dev *dev)
5639 {
5640 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree