arch/arm/mach-ux500/platsmp.c

   1 /*
   2  * Copyright (C) 2002 ARM Ltd.
   3  * Copyright (C) 2008 STMicroelctronics.
   4  * Copyright (C) 2009 ST-Ericsson.
   5  * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
   6  *
   7  * This file is based on arm realview platform
   8  *
   9  * This program is free software; you can redistribute it and/or modify
  10  * it under the terms of the GNU General Public License version 2 as
  11  * published by the Free Software Foundation.
  12  */
  13 #include <linux/init.h>
  14 #include <linux/errno.h>
  15 #include <linux/delay.h>
  16 #include <linux/device.h>
  17 #include <linux/smp.h>
  18 #include <linux/io.h>
  19
  20 #include <asm/cacheflush.h>
  21 #include <asm/smp_scu.h>
  22 #include <mach/hardware.h>
  23
  24 /*
  25  * control for which core is the next to come out of the secondary
  26  * boot "holding pen"
  27  */
  28 volatile int pen_release = -1;
  29
  30 /*
  31  * Write pen_release in a way that is guaranteed to be visible to all
  32  * observers, irrespective of whether they're taking part in coherency
  33  * or not.  This is necessary for the hotplug code to work reliably.
  34  */
  35 static void write_pen_release(int val)
  36 {
  37         pen_release = val;
  38         smp_wmb();
  39         __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
  40         outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
  41 }
  42
  43 static DEFINE_SPINLOCK(boot_lock);
  44
  45 void __cpuinit platform_secondary_init(unsigned int cpu)
  46 {
  47         /*
  48          * if any interrupts are already enabled for the primary
  49          * core (e.g. timer irq), then they will not have been enabled
  50          * for us: do so
  51          */
  52         gic_secondary_init(0);
  53
  54         /*
  55          * let the primary processor know we're out of the
  56          * pen, then head off into the C entry point
  57          */
  58         write_pen_release(-1);
  59
  60         /*
  61          * Synchronise with the boot thread.
  62          */
  63         spin_lock(&boot_lock);
  64         spin_unlock(&boot_lock);
  65 }
  66
  67 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
  68 {
  69         unsigned long timeout;
  70
  71         /*
  72          * set synchronisation state between this boot processor
  73          * and the secondary one
  74          */
  75         spin_lock(&boot_lock);
  76
  77         /*
  78          * The secondary processor is waiting to be released from
  79          * the holding pen - release it, then wait for it to flag
  80          * that it has been released by resetting pen_release.
  81          */
  82         write_pen_release(cpu);
  83
  84         smp_cross_call(cpumask_of(cpu), 1);
  85
  86         timeout = jiffies + (1 * HZ);
  87         while (time_before(jiffies, timeout)) {
  88                 if (pen_release == -1)
  89                         break;
  90         }
  91
  92         /*
  93          * now the secondary core is starting up let it run its
  94          * calibrations, then wait for it to finish
  95          */
  96         spin_unlock(&boot_lock);
  97
  98         return pen_release != -1 ? -ENOSYS : 0;
  99 }
 100
 101 static void __init wakeup_secondary(void)
 102 {
 103         /*
 104          * write the address of secondary startup into the backup ram register
 105          * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the
 106          * backup ram register at offset 0x1FF0, which is what boot rom code
 107          * is waiting for. This would wake up the secondary core from WFE
 108          */
 109 #define U8500_CPU1_JUMPADDR_OFFSET 0x1FF4
 110         __raw_writel(virt_to_phys(u8500_secondary_startup),
 111                 __io_address(UX500_BACKUPRAM0_BASE) +
 112                 U8500_CPU1_JUMPADDR_OFFSET);
 113
 114 #define U8500_CPU1_WAKEMAGIC_OFFSET 0x1FF0
 115         __raw_writel(0xA1FEED01,
 116                 __io_address(UX500_BACKUPRAM0_BASE) +
 117                 U8500_CPU1_WAKEMAGIC_OFFSET);
 118
 119         /* make sure write buffer is drained */
 120         mb();
 121 }
 122
 123 /*
 124  * Initialise the CPU possible map early - this describes the CPUs
 125  * which may be present or become present in the system.
 126  */
 127 void __init smp_init_cpus(void)
 128 {
 129         unsigned int i, ncores;
 130
 131         ncores = scu_get_core_count(__io_address(UX500_SCU_BASE));
 132
 133         /* sanity check */
 134         if (ncores > NR_CPUS) {
 135                 printk(KERN_WARNING
 136                        "U8500: no. of cores (%d) greater than configured "
 137                        "maximum of %d - clipping\n",
 138                        ncores, NR_CPUS);
 139                 ncores = NR_CPUS;
 140         }
 141
 142         for (i = 0; i < ncores; i++)
 143                 set_cpu_possible(i, true);
 144 }
 145
 146 void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 147 {
 148         int i;
 149
 150         /*
 151          * Initialise the present map, which describes the set of CPUs
 152          * actually populated at the present time.
 153          */
 154         for (i = 0; i < max_cpus; i++)
 155                 set_cpu_present(i, true);
 156
 157         scu_enable(__io_address(UX500_SCU_BASE));
 158         wakeup_secondary();
 159 }