2 * linux/arch/arm/mach-pxa/pxa25x.c
4 * Author: Nicolas Pitre
5 * Created: Jun 15, 2001
6 * Copyright: MontaVista Software Inc.
8 * Code specific to PXA21x/25x/26x variants.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 * Since this file should be linked before any other machine specific file,
15 * the __initcall() here will be executed first. This serves as default
16 * initialization stuff for PXA machines which can be overridden later if
19 #include <linux/module.h>
20 #include <linux/kernel.h>
21 #include <linux/init.h>
22 #include <linux/platform_device.h>
23 #include <linux/suspend.h>
24 #include <linux/sysdev.h>
26 #include <asm/mach/map.h>
27 #include <mach/hardware.h>
28 #include <mach/irqs.h>
29 #include <mach/gpio.h>
30 #include <mach/pxa25x.h>
31 #include <mach/reset.h>
34 #include <mach/smemc.h>
41 * Various clock factors driven by the CCCR register.
44 /* Crystal Frequency to Memory Frequency Multiplier (L) */
45 static unsigned char L_clk_mult
[32] = { 0, 27, 32, 36, 40, 45, 0, };
47 /* Memory Frequency to Run Mode Frequency Multiplier (M) */
48 static unsigned char M_clk_mult
[4] = { 0, 1, 2, 4 };
50 /* Run Mode Frequency to Turbo Mode Frequency Multiplier (N) */
51 /* Note: we store the value N * 2 here. */
52 static unsigned char N2_clk_mult
[8] = { 0, 0, 2, 3, 4, 0, 6, 0 };
55 #define BASE_CLK 3686400
58 * Get the clock frequency as reflected by CCCR and the turbo flag.
59 * We assume these values have been applied via a fcs.
60 * If info is not 0 we also display the current settings.
62 unsigned int pxa25x_get_clk_frequency_khz(int info
)
64 unsigned long cccr
, turbo
;
65 unsigned int l
, L
, m
, M
, n2
, N
;
68 asm( "mrc\tp14, 0, %0, c6, c0, 0" : "=r" (turbo
) );
70 l
= L_clk_mult
[(cccr
>> 0) & 0x1f];
71 m
= M_clk_mult
[(cccr
>> 5) & 0x03];
72 n2
= N2_clk_mult
[(cccr
>> 7) & 0x07];
81 printk( KERN_INFO
"Memory clock: %d.%02dMHz (*%d)\n",
82 L
/ 1000000, (L
% 1000000) / 10000, l
);
84 printk( KERN_INFO
"Run Mode clock: %d.%02dMHz (*%d)\n",
85 M
/ 1000000, (M
% 1000000) / 10000, m
);
87 printk( KERN_INFO
"Turbo Mode clock: %d.%02dMHz (*%d.%d, %sactive)\n",
88 N
/ 1000000, (N
% 1000000) / 10000, n2
/ 2, (n2
% 2) * 5,
89 (turbo
& 1) ? "" : "in" );
92 return (turbo
& 1) ? (N
/1000) : (M
/1000);
95 static unsigned long clk_pxa25x_mem_getrate(struct clk
*clk
)
97 return L_clk_mult
[(CCCR
>> 0) & 0x1f] * BASE_CLK
;
100 static const struct clkops clk_pxa25x_mem_ops
= {
101 .enable
= clk_dummy_enable
,
102 .disable
= clk_dummy_disable
,
103 .getrate
= clk_pxa25x_mem_getrate
,
106 static const struct clkops clk_pxa25x_lcd_ops
= {
107 .enable
= clk_pxa2xx_cken_enable
,
108 .disable
= clk_pxa2xx_cken_disable
,
109 .getrate
= clk_pxa25x_mem_getrate
,
112 static unsigned long gpio12_config_32k
[] = {
116 static unsigned long gpio12_config_gpio
[] = {
120 static void clk_gpio12_enable(struct clk
*clk
)
122 pxa2xx_mfp_config(gpio12_config_32k
, 1);
125 static void clk_gpio12_disable(struct clk
*clk
)
127 pxa2xx_mfp_config(gpio12_config_gpio
, 1);
130 static const struct clkops clk_pxa25x_gpio12_ops
= {
131 .enable
= clk_gpio12_enable
,
132 .disable
= clk_gpio12_disable
,
135 static unsigned long gpio11_config_3m6
[] = {
139 static unsigned long gpio11_config_gpio
[] = {
143 static void clk_gpio11_enable(struct clk
*clk
)
145 pxa2xx_mfp_config(gpio11_config_3m6
, 1);
148 static void clk_gpio11_disable(struct clk
*clk
)
150 pxa2xx_mfp_config(gpio11_config_gpio
, 1);
153 static const struct clkops clk_pxa25x_gpio11_ops
= {
154 .enable
= clk_gpio11_enable
,
155 .disable
= clk_gpio11_disable
,
159 * 3.6864MHz -> OST, GPIO, SSP, PWM, PLLs (95.842MHz, 147.456MHz)
160 * 95.842MHz -> MMC 19.169MHz, I2C 31.949MHz, FICP 47.923MHz, USB 47.923MHz
161 * 147.456MHz -> UART 14.7456MHz, AC97 12.288MHz, I2S 5.672MHz (allegedly)
165 * PXA 2xx clock declarations.
167 static DEFINE_PXA2_CKEN(pxa25x_hwuart
, HWUART
, 14745600, 1);
168 static DEFINE_PXA2_CKEN(pxa25x_ffuart
, FFUART
, 14745600, 1);
169 static DEFINE_PXA2_CKEN(pxa25x_btuart
, BTUART
, 14745600, 1);
170 static DEFINE_PXA2_CKEN(pxa25x_stuart
, STUART
, 14745600, 1);
171 static DEFINE_PXA2_CKEN(pxa25x_usb
, USB
, 47923000, 5);
172 static DEFINE_PXA2_CKEN(pxa25x_mmc
, MMC
, 19169000, 0);
173 static DEFINE_PXA2_CKEN(pxa25x_i2c
, I2C
, 31949000, 0);
174 static DEFINE_PXA2_CKEN(pxa25x_ssp
, SSP
, 3686400, 0);
175 static DEFINE_PXA2_CKEN(pxa25x_nssp
, NSSP
, 3686400, 0);
176 static DEFINE_PXA2_CKEN(pxa25x_assp
, ASSP
, 3686400, 0);
177 static DEFINE_PXA2_CKEN(pxa25x_pwm0
, PWM0
, 3686400, 0);
178 static DEFINE_PXA2_CKEN(pxa25x_pwm1
, PWM1
, 3686400, 0);
179 static DEFINE_PXA2_CKEN(pxa25x_ac97
, AC97
, 24576000, 0);
180 static DEFINE_PXA2_CKEN(pxa25x_i2s
, I2S
, 14745600, 0);
181 static DEFINE_PXA2_CKEN(pxa25x_ficp
, FICP
, 47923000, 0);
183 static DEFINE_CK(pxa25x_lcd
, LCD
, &clk_pxa25x_lcd_ops
);
184 static DEFINE_CLK(pxa25x_gpio11
, &clk_pxa25x_gpio11_ops
, 3686400, 0);
185 static DEFINE_CLK(pxa25x_gpio12
, &clk_pxa25x_gpio12_ops
, 32768, 0);
186 static DEFINE_CLK(pxa25x_mem
, &clk_pxa25x_mem_ops
, 0, 0);
188 static struct clk_lookup pxa25x_clkregs
[] = {
189 INIT_CLKREG(&clk_pxa25x_lcd
, "pxa2xx-fb", NULL
),
190 INIT_CLKREG(&clk_pxa25x_ffuart
, "pxa2xx-uart.0", NULL
),
191 INIT_CLKREG(&clk_pxa25x_btuart
, "pxa2xx-uart.1", NULL
),
192 INIT_CLKREG(&clk_pxa25x_stuart
, "pxa2xx-uart.2", NULL
),
193 INIT_CLKREG(&clk_pxa25x_usb
, "pxa25x-udc", NULL
),
194 INIT_CLKREG(&clk_pxa25x_mmc
, "pxa2xx-mci.0", NULL
),
195 INIT_CLKREG(&clk_pxa25x_i2c
, "pxa2xx-i2c.0", NULL
),
196 INIT_CLKREG(&clk_pxa25x_ssp
, "pxa25x-ssp.0", NULL
),
197 INIT_CLKREG(&clk_pxa25x_nssp
, "pxa25x-nssp.1", NULL
),
198 INIT_CLKREG(&clk_pxa25x_assp
, "pxa25x-nssp.2", NULL
),
199 INIT_CLKREG(&clk_pxa25x_pwm0
, "pxa25x-pwm.0", NULL
),
200 INIT_CLKREG(&clk_pxa25x_pwm1
, "pxa25x-pwm.1", NULL
),
201 INIT_CLKREG(&clk_pxa25x_i2s
, "pxa2xx-i2s", NULL
),
202 INIT_CLKREG(&clk_pxa25x_stuart
, "pxa2xx-ir", "UARTCLK"),
203 INIT_CLKREG(&clk_pxa25x_ficp
, "pxa2xx-ir", "FICPCLK"),
204 INIT_CLKREG(&clk_pxa25x_ac97
, NULL
, "AC97CLK"),
205 INIT_CLKREG(&clk_pxa25x_gpio11
, NULL
, "GPIO11_CLK"),
206 INIT_CLKREG(&clk_pxa25x_gpio12
, NULL
, "GPIO12_CLK"),
207 INIT_CLKREG(&clk_pxa25x_mem
, "pxa2xx-pcmcia", NULL
),
210 static struct clk_lookup pxa25x_hwuart_clkreg
=
211 INIT_CLKREG(&clk_pxa25x_hwuart
, "pxa2xx-uart.3", NULL
);
215 #define SAVE(x) sleep_save[SLEEP_SAVE_##x] = x
216 #define RESTORE(x) x = sleep_save[SLEEP_SAVE_##x]
219 * List of global PXA peripheral registers to preserve.
220 * More ones like CP and general purpose register values are preserved
221 * with the stack pointer in sleep.S.
229 static void pxa25x_cpu_pm_save(unsigned long *sleep_save
)
234 static void pxa25x_cpu_pm_restore(unsigned long *sleep_save
)
239 static void pxa25x_cpu_pm_enter(suspend_state_t state
)
241 /* Clear reset status */
242 RCSR
= RCSR_HWR
| RCSR_WDR
| RCSR_SMR
| RCSR_GPR
;
246 pxa25x_cpu_suspend(PWRMODE_SLEEP
);
251 static int pxa25x_cpu_pm_prepare(void)
253 /* set resume return address */
254 PSPR
= virt_to_phys(pxa_cpu_resume
);
258 static void pxa25x_cpu_pm_finish(void)
260 /* ensure not to come back here if it wasn't intended */
264 static struct pxa_cpu_pm_fns pxa25x_cpu_pm_fns
= {
265 .save_count
= SLEEP_SAVE_COUNT
,
266 .valid
= suspend_valid_only_mem
,
267 .save
= pxa25x_cpu_pm_save
,
268 .restore
= pxa25x_cpu_pm_restore
,
269 .enter
= pxa25x_cpu_pm_enter
,
270 .prepare
= pxa25x_cpu_pm_prepare
,
271 .finish
= pxa25x_cpu_pm_finish
,
274 static void __init
pxa25x_init_pm(void)
276 pxa_cpu_pm_fns
= &pxa25x_cpu_pm_fns
;
279 static inline void pxa25x_init_pm(void) {}
282 /* PXA25x: supports wakeup from GPIO0..GPIO15 and RTC alarm
285 static int pxa25x_set_wake(unsigned int irq
, unsigned int on
)
287 int gpio
= IRQ_TO_GPIO(irq
);
290 if (gpio
>= 0 && gpio
< 85)
291 return gpio_set_wake(gpio
, on
);
293 if (irq
== IRQ_RTCAlrm
) {
309 void __init
pxa25x_init_irq(void)
311 pxa_init_irq(32, pxa25x_set_wake
);
312 pxa_init_gpio(IRQ_GPIO_2_x
, 2, 84, pxa25x_set_wake
);
315 #ifdef CONFIG_CPU_PXA26x
316 void __init
pxa26x_init_irq(void)
318 pxa_init_irq(32, pxa25x_set_wake
);
319 pxa_init_gpio(IRQ_GPIO_2_x
, 2, 89, pxa25x_set_wake
);
323 static struct map_desc pxa25x_io_desc
[] __initdata
= {
325 .virtual = SMEMC_VIRT
,
326 .pfn
= __phys_to_pfn(PXA2XX_SMEMC_BASE
),
327 .length
= 0x00200000,
332 void __init
pxa25x_map_io(void)
335 iotable_init(ARRAY_AND_SIZE(pxa25x_io_desc
));
336 pxa25x_get_clk_frequency_khz(1);
339 static struct platform_device
*pxa25x_devices
[] __initdata
= {
351 static struct sys_device pxa25x_sysdev
[] = {
353 .cls
= &pxa_irq_sysclass
,
355 .cls
= &pxa2xx_mfp_sysclass
,
357 .cls
= &pxa_gpio_sysclass
,
359 .cls
= &pxa2xx_clock_sysclass
,
363 static int __init
pxa25x_init(void)
367 if (cpu_is_pxa25x()) {
371 clkdev_add_table(pxa25x_clkregs
, ARRAY_SIZE(pxa25x_clkregs
));
373 if ((ret
= pxa_init_dma(IRQ_DMA
, 16)))
378 for (i
= 0; i
< ARRAY_SIZE(pxa25x_sysdev
); i
++) {
379 ret
= sysdev_register(&pxa25x_sysdev
[i
]);
381 pr_err("failed to register sysdev[%d]\n", i
);
384 ret
= platform_add_devices(pxa25x_devices
,
385 ARRAY_SIZE(pxa25x_devices
));
390 /* Only add HWUART for PXA255/26x; PXA210/250 do not have it. */
392 clkdev_add(&pxa25x_hwuart_clkreg
);
397 postcore_initcall(pxa25x_init
);