arch/arm/mach-ep93xx/core.c

   1 /*
   2  * arch/arm/mach-ep93xx/core.c
   3  * Core routines for Cirrus EP93xx chips.
   4  *
   5  * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
   6  *
   7  * Thanks go to Michael Burian and Ray Lehtiniemi for their key
   8  * role in the ep93xx linux community.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or (at
  13  * your option) any later version.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/spinlock.h>
  19 #include <linux/sched.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/serial.h>
  22 #include <linux/tty.h>
  23 #include <linux/bitops.h>
  24 #include <linux/serial.h>
  25 #include <linux/serial_8250.h>
  26 #include <linux/serial_core.h>
  27 #include <linux/device.h>
  28 #include <linux/mm.h>
  29 #include <linux/time.h>
  30 #include <linux/timex.h>
  31 #include <linux/delay.h>
  32 #include <linux/termios.h>
  33 #include <linux/amba/bus.h>
  34 #include <linux/amba/serial.h>
  35
  36 #include <asm/types.h>
  37 #include <asm/setup.h>
  38 #include <asm/memory.h>
  39 #include <asm/hardware.h>
  40 #include <asm/irq.h>
  41 #include <asm/system.h>
  42 #include <asm/tlbflush.h>
  43 #include <asm/pgtable.h>
  44 #include <asm/io.h>
  45
  46 #include <asm/mach/map.h>
  47 #include <asm/mach/time.h>
  48 #include <asm/mach/irq.h>
  49 #include <asm/arch/gpio.h>
  50
  51 #include <asm/hardware/vic.h>
  52
  53
  54 /*************************************************************************
  55  * Static I/O mappings that are needed for all EP93xx platforms
  56  *************************************************************************/
  57 static struct map_desc ep93xx_io_desc[] __initdata = {
  58         {
  59                 .virtual        = EP93XX_AHB_VIRT_BASE,
  60                 .pfn            = __phys_to_pfn(EP93XX_AHB_PHYS_BASE),
  61                 .length         = EP93XX_AHB_SIZE,
  62                 .type           = MT_DEVICE,
  63         }, {
  64                 .virtual        = EP93XX_APB_VIRT_BASE,
  65                 .pfn            = __phys_to_pfn(EP93XX_APB_PHYS_BASE),
  66                 .length         = EP93XX_APB_SIZE,
  67                 .type           = MT_DEVICE,
  68         },
  69 };
  70
  71 void __init ep93xx_map_io(void)
  72 {
  73         iotable_init(ep93xx_io_desc, ARRAY_SIZE(ep93xx_io_desc));
  74 }
  75
  76
  77 /*************************************************************************
  78  * Timer handling for EP93xx
  79  *************************************************************************
  80  * The ep93xx has four internal timers.  Timers 1, 2 (both 16 bit) and
  81  * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
  82  * an interrupt on underflow.  Timer 4 (40 bit) counts down at 983.04 kHz,
  83  * is free-running, and can't generate interrupts.
  84  *
  85  * The 508 kHz timers are ideal for use for the timer interrupt, as the
  86  * most common values of HZ divide 508 kHz nicely.  We pick one of the 16
  87  * bit timers (timer 1) since we don't need more than 16 bits of reload
  88  * value as long as HZ >= 8.
  89  *
  90  * The higher clock rate of timer 4 makes it a better choice than the
  91  * other timers for use in gettimeoffset(), while the fact that it can't
  92  * generate interrupts means we don't have to worry about not being able
  93  * to use this timer for something else.  We also use timer 4 for keeping
  94  * track of lost jiffies.
  95  */
  96 static unsigned int last_jiffy_time;
  97
  98 #define TIMER4_TICKS_PER_JIFFY          ((CLOCK_TICK_RATE + (HZ/2)) / HZ)
  99
 100 static int ep93xx_timer_interrupt(int irq, void *dev_id)
 101 {
 102         write_seqlock(&xtime_lock);
 103
 104         __raw_writel(1, EP93XX_TIMER1_CLEAR);
 105         while ((signed long)
 106                 (__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time)
 107                                                 >= TIMER4_TICKS_PER_JIFFY) {
 108                 last_jiffy_time += TIMER4_TICKS_PER_JIFFY;
 109                 timer_tick();
 110         }
 111
 112         write_sequnlock(&xtime_lock);
 113
 114         return IRQ_HANDLED;
 115 }
 116
 117 static struct irqaction ep93xx_timer_irq = {
 118         .name           = "ep93xx timer",
 119         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 120         .handler        = ep93xx_timer_interrupt,
 121 };
 122
 123 static void __init ep93xx_timer_init(void)
 124 {
 125         /* Enable periodic HZ timer.  */
 126         __raw_writel(0x48, EP93XX_TIMER1_CONTROL);
 127         __raw_writel((508469 / HZ) - 1, EP93XX_TIMER1_LOAD);
 128         __raw_writel(0xc8, EP93XX_TIMER1_CONTROL);
 129
 130         /* Enable lost jiffy timer.  */
 131         __raw_writel(0x100, EP93XX_TIMER4_VALUE_HIGH);
 132
 133         setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);
 134 }
 135
 136 static unsigned long ep93xx_gettimeoffset(void)
 137 {
 138         int offset;
 139
 140         offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time;
 141
 142         /* Calculate (1000000 / 983040) * offset.  */
 143         return offset + (53 * offset / 3072);
 144 }
 145
 146 struct sys_timer ep93xx_timer = {
 147         .init           = ep93xx_timer_init,
 148         .offset         = ep93xx_gettimeoffset,
 149 };
 150
 151
 152 /*************************************************************************
 153  * GPIO handling for EP93xx
 154  *************************************************************************/
 155 static unsigned char gpio_int_unmasked[3];
 156 static unsigned char gpio_int_enabled[3];
 157 static unsigned char gpio_int_type1[3];
 158 static unsigned char gpio_int_type2[3];
 159
 160 static void update_gpio_int_params(int abf)
 161 {
 162         if (abf == 0) {
 163                 __raw_writeb(0, EP93XX_GPIO_A_INT_ENABLE);
 164                 __raw_writeb(gpio_int_type2[0], EP93XX_GPIO_A_INT_TYPE2);
 165                 __raw_writeb(gpio_int_type1[0], EP93XX_GPIO_A_INT_TYPE1);
 166                 __raw_writeb(gpio_int_unmasked[0] & gpio_int_enabled[0], EP93XX_GPIO_A_INT_ENABLE);
 167         } else if (abf == 1) {
 168                 __raw_writeb(0, EP93XX_GPIO_B_INT_ENABLE);
 169                 __raw_writeb(gpio_int_type2[1], EP93XX_GPIO_B_INT_TYPE2);
 170                 __raw_writeb(gpio_int_type1[1], EP93XX_GPIO_B_INT_TYPE1);
 171                 __raw_writeb(gpio_int_unmasked[1] & gpio_int_enabled[1], EP93XX_GPIO_B_INT_ENABLE);
 172         } else if (abf == 2) {
 173                 __raw_writeb(0, EP93XX_GPIO_F_INT_ENABLE);
 174                 __raw_writeb(gpio_int_type2[2], EP93XX_GPIO_F_INT_TYPE2);
 175                 __raw_writeb(gpio_int_type1[2], EP93XX_GPIO_F_INT_TYPE1);
 176                 __raw_writeb(gpio_int_unmasked[2] & gpio_int_enabled[2], EP93XX_GPIO_F_INT_ENABLE);
 177         } else {
 178                 BUG();
 179         }
 180 }
 181
 182
 183 static unsigned char data_register_offset[8] = {
 184         0x00, 0x04, 0x08, 0x0c, 0x20, 0x30, 0x38, 0x40,
 185 };
 186
 187 static unsigned char data_direction_register_offset[8] = {
 188         0x10, 0x14, 0x18, 0x1c, 0x24, 0x34, 0x3c, 0x44,
 189 };
 190
 191 void gpio_line_config(int line, int direction)
 192 {
 193         unsigned int data_direction_register;
 194         unsigned long flags;
 195         unsigned char v;
 196
 197         data_direction_register =
 198                 EP93XX_GPIO_REG(data_direction_register_offset[line >> 3]);
 199
 200         local_irq_save(flags);
 201         if (direction == GPIO_OUT) {
 202                 if (line >= 0 && line < 16) {
 203                         /* Port A/B.  */
 204                         gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
 205                         update_gpio_int_params(line >> 3);
 206                 } else if (line >= 40 && line < 48) {
 207                         /* Port F.  */
 208                         gpio_int_unmasked[2] &= ~(1 << (line & 7));
 209                         update_gpio_int_params(2);
 210                 }
 211
 212                 v = __raw_readb(data_direction_register);
 213                 v |= 1 << (line & 7);
 214                 __raw_writeb(v, data_direction_register);
 215         } else if (direction == GPIO_IN) {
 216                 v = __raw_readb(data_direction_register);
 217                 v &= ~(1 << (line & 7));
 218                 __raw_writeb(v, data_direction_register);
 219         }
 220         local_irq_restore(flags);
 221 }
 222 EXPORT_SYMBOL(gpio_line_config);
 223
 224 int gpio_line_get(int line)
 225 {
 226         unsigned int data_register;
 227
 228         data_register = EP93XX_GPIO_REG(data_register_offset[line >> 3]);
 229
 230         return !!(__raw_readb(data_register) & (1 << (line & 7)));
 231 }
 232 EXPORT_SYMBOL(gpio_line_get);
 233
 234 void gpio_line_set(int line, int value)
 235 {
 236         unsigned int data_register;
 237         unsigned long flags;
 238         unsigned char v;
 239
 240         data_register = EP93XX_GPIO_REG(data_register_offset[line >> 3]);
 241
 242         local_irq_save(flags);
 243         if (value == EP93XX_GPIO_HIGH) {
 244                 v = __raw_readb(data_register);
 245                 v |= 1 << (line & 7);
 246                 __raw_writeb(v, data_register);
 247         } else if (value == EP93XX_GPIO_LOW) {
 248                 v = __raw_readb(data_register);
 249                 v &= ~(1 << (line & 7));
 250                 __raw_writeb(v, data_register);
 251         }
 252         local_irq_restore(flags);
 253 }
 254 EXPORT_SYMBOL(gpio_line_set);
 255
 256
 257 /*************************************************************************
 258  * EP93xx IRQ handling
 259  *************************************************************************/
 260 static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
 261 {
 262         unsigned char status;
 263         int i;
 264
 265         status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
 266         for (i = 0; i < 8; i++) {
 267                 if (status & (1 << i)) {
 268                         desc = irq_desc + IRQ_EP93XX_GPIO(0) + i;
 269                         desc_handle_irq(IRQ_EP93XX_GPIO(0) + i, desc);
 270                 }
 271         }
 272
 273         status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
 274         for (i = 0; i < 8; i++) {
 275                 if (status & (1 << i)) {
 276                         desc = irq_desc + IRQ_EP93XX_GPIO(8) + i;
 277                         desc_handle_irq(IRQ_EP93XX_GPIO(8) + i, desc);
 278                 }
 279         }
 280 }
 281
 282 static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
 283 {
 284         int gpio_irq = IRQ_EP93XX_GPIO(16) + (((irq + 1) & 7) ^ 4);
 285
 286         desc_handle_irq(gpio_irq, irq_desc + gpio_irq);
 287 }
 288
 289 static void ep93xx_gpio_irq_mask_ack(unsigned int irq)
 290 {
 291         int line = irq - IRQ_EP93XX_GPIO(0);
 292         int port = line >> 3;
 293
 294         gpio_int_unmasked[port] &= ~(1 << (line & 7));
 295         update_gpio_int_params(port);
 296
 297         if (port == 0) {
 298                 __raw_writel(1 << (line & 7), EP93XX_GPIO_A_INT_ACK);
 299         } else if (port == 1) {
 300                 __raw_writel(1 << (line & 7), EP93XX_GPIO_B_INT_ACK);
 301         } else if (port == 2) {
 302                 __raw_writel(1 << (line & 7), EP93XX_GPIO_F_INT_ACK);
 303         }
 304 }
 305
 306 static void ep93xx_gpio_irq_mask(unsigned int irq)
 307 {
 308         int line = irq - IRQ_EP93XX_GPIO(0);
 309         int port = line >> 3;
 310
 311         gpio_int_unmasked[port] &= ~(1 << (line & 7));
 312         update_gpio_int_params(port);
 313 }
 314
 315 static void ep93xx_gpio_irq_unmask(unsigned int irq)
 316 {
 317         int line = irq - IRQ_EP93XX_GPIO(0);
 318         int port = line >> 3;
 319
 320         gpio_int_unmasked[port] |= 1 << (line & 7);
 321         update_gpio_int_params(port);
 322 }
 323
 324
 325 /*
 326  * gpio_int_type1 controls whether the interrupt is level (0) or
 327  * edge (1) triggered, while gpio_int_type2 controls whether it
 328  * triggers on low/falling (0) or high/rising (1).
 329  */
 330 static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type)
 331 {
 332         int port;
 333         int line;
 334
 335         line = irq - IRQ_EP93XX_GPIO(0);
 336         if (line >= 0 && line < 16) {
 337                 gpio_line_config(line, GPIO_IN);
 338         } else {
 339                 gpio_line_config(EP93XX_GPIO_LINE_F(line), GPIO_IN);
 340         }
 341
 342         port = line >> 3;
 343         line &= 7;
 344
 345         if (type & IRQT_RISING) {
 346                 gpio_int_enabled[port] |= 1 << line;
 347                 gpio_int_type1[port] |= 1 << line;
 348                 gpio_int_type2[port] |= 1 << line;
 349         } else if (type & IRQT_FALLING) {
 350                 gpio_int_enabled[port] |= 1 << line;
 351                 gpio_int_type1[port] |= 1 << line;
 352                 gpio_int_type2[port] &= ~(1 << line);
 353         } else if (type & IRQT_HIGH) {
 354                 gpio_int_enabled[port] |= 1 << line;
 355                 gpio_int_type1[port] &= ~(1 << line);
 356                 gpio_int_type2[port] |= 1 << line;
 357         } else if (type & IRQT_LOW) {
 358                 gpio_int_enabled[port] |= 1 << line;
 359                 gpio_int_type1[port] &= ~(1 << line);
 360                 gpio_int_type2[port] &= ~(1 << line);
 361         } else {
 362                 gpio_int_enabled[port] &= ~(1 << line);
 363         }
 364         update_gpio_int_params(port);
 365
 366         return 0;
 367 }
 368
 369 static struct irq_chip ep93xx_gpio_irq_chip = {
 370         .name           = "GPIO",
 371         .ack            = ep93xx_gpio_irq_mask_ack,
 372         .mask           = ep93xx_gpio_irq_mask,
 373         .unmask         = ep93xx_gpio_irq_unmask,
 374         .set_type       = ep93xx_gpio_irq_type,
 375 };
 376
 377
 378 void __init ep93xx_init_irq(void)
 379 {
 380         int irq;
 381
 382         vic_init((void *)EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK);
 383         vic_init((void *)EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK);
 384
 385         for (irq = IRQ_EP93XX_GPIO(0); irq <= IRQ_EP93XX_GPIO(23); irq++) {
 386                 set_irq_chip(irq, &ep93xx_gpio_irq_chip);
 387                 set_irq_handler(irq, handle_level_irq);
 388                 set_irq_flags(irq, IRQF_VALID);
 389         }
 390
 391         set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler);
 392         set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler);
 393         set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler);
 394         set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler);
 395         set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler);
 396         set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler);
 397         set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler);
 398         set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler);
 399         set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler);
 400 }
 401
 402
 403 /*************************************************************************
 404  * EP93xx peripheral handling
 405  *************************************************************************/
 406 #define EP93XX_UART_MCR_OFFSET          (0x0100)
 407
 408 static void ep93xx_uart_set_mctrl(struct amba_device *dev,
 409                                   void __iomem *base, unsigned int mctrl)
 410 {
 411         unsigned int mcr;
 412
 413         mcr = 0;
 414         if (!(mctrl & TIOCM_RTS))
 415                 mcr |= 2;
 416         if (!(mctrl & TIOCM_DTR))
 417                 mcr |= 1;
 418
 419         __raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET);
 420 }
 421
 422 static struct amba_pl010_data ep93xx_uart_data = {
 423         .set_mctrl      = ep93xx_uart_set_mctrl,
 424 };
 425
 426 static struct amba_device uart1_device = {
 427         .dev            = {
 428                 .bus_id         = "apb:uart1",
 429                 .platform_data  = &ep93xx_uart_data,
 430         },
 431         .res            = {
 432                 .start  = EP93XX_UART1_PHYS_BASE,
 433                 .end    = EP93XX_UART1_PHYS_BASE + 0x0fff,
 434                 .flags  = IORESOURCE_MEM,
 435         },
 436         .irq            = { IRQ_EP93XX_UART1, NO_IRQ },
 437         .periphid       = 0x00041010,
 438 };
 439
 440 static struct amba_device uart2_device = {
 441         .dev            = {
 442                 .bus_id         = "apb:uart2",
 443                 .platform_data  = &ep93xx_uart_data,
 444         },
 445         .res            = {
 446                 .start  = EP93XX_UART2_PHYS_BASE,
 447                 .end    = EP93XX_UART2_PHYS_BASE + 0x0fff,
 448                 .flags  = IORESOURCE_MEM,
 449         },
 450         .irq            = { IRQ_EP93XX_UART2, NO_IRQ },
 451         .periphid       = 0x00041010,
 452 };
 453
 454 static struct amba_device uart3_device = {
 455         .dev            = {
 456                 .bus_id         = "apb:uart3",
 457                 .platform_data  = &ep93xx_uart_data,
 458         },
 459         .res            = {
 460                 .start  = EP93XX_UART3_PHYS_BASE,
 461                 .end    = EP93XX_UART3_PHYS_BASE + 0x0fff,
 462                 .flags  = IORESOURCE_MEM,
 463         },
 464         .irq            = { IRQ_EP93XX_UART3, NO_IRQ },
 465         .periphid       = 0x00041010,
 466 };
 467
 468
 469 static struct platform_device ep93xx_rtc_device = {
 470        .name           = "ep93xx-rtc",
 471        .id             = -1,
 472        .num_resources  = 0,
 473 };
 474
 475
 476 static struct resource ep93xx_ohci_resources[] = {
 477         [0] = {
 478                 .start  = EP93XX_USB_PHYS_BASE,
 479                 .end    = EP93XX_USB_PHYS_BASE + 0x0fff,
 480                 .flags  = IORESOURCE_MEM,
 481         },
 482         [1] = {
 483                 .start  = IRQ_EP93XX_USB,
 484                 .end    = IRQ_EP93XX_USB,
 485                 .flags  = IORESOURCE_IRQ,
 486         },
 487 };
 488
 489 static struct platform_device ep93xx_ohci_device = {
 490         .name           = "ep93xx-ohci",
 491         .id             = -1,
 492         .dev            = {
 493                 .dma_mask               = (void *)0xffffffff,
 494                 .coherent_dma_mask      = 0xffffffff,
 495         },
 496         .num_resources  = ARRAY_SIZE(ep93xx_ohci_resources),
 497         .resource       = ep93xx_ohci_resources,
 498 };
 499
 500
 501 void __init ep93xx_init_devices(void)
 502 {
 503         unsigned int v;
 504
 505         /*
 506          * Disallow access to MaverickCrunch initially.
 507          */
 508         v = __raw_readl(EP93XX_SYSCON_DEVICE_CONFIG);
 509         v &= ~EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE;
 510         __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
 511         __raw_writel(v, EP93XX_SYSCON_DEVICE_CONFIG);
 512
 513         amba_device_register(&uart1_device, &iomem_resource);
 514         amba_device_register(&uart2_device, &iomem_resource);
 515         amba_device_register(&uart3_device, &iomem_resource);
 516
 517         platform_device_register(&ep93xx_rtc_device);
 518         platform_device_register(&ep93xx_ohci_device);
 519 }