arch/i386/kernel/nmi.c

   1 /*
   2  *  linux/arch/i386/nmi.c
   3  *
   4  *  NMI watchdog support on APIC systems
   5  *
   6  *  Started by Ingo Molnar <mingo@redhat.com>
   7  *
   8  *  Fixes:
   9  *  Mikael Pettersson   : AMD K7 support for local APIC NMI watchdog.
  10  *  Mikael Pettersson   : Power Management for local APIC NMI watchdog.
  11  *  Mikael Pettersson   : Pentium 4 support for local APIC NMI watchdog.
  12  *  Pavel Machek and
  13  *  Mikael Pettersson   : PM converted to driver model. Disable/enable API.
  14  */
  15
  16 #include <linux/config.h>
  17 #include <linux/delay.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/module.h>
  20 #include <linux/nmi.h>
  21 #include <linux/sysdev.h>
  22 #include <linux/sysctl.h>
  23 #include <linux/percpu.h>
  24
  25 #include <asm/smp.h>
  26 #include <asm/nmi.h>
  27 #include <asm/kdebug.h>
  28
  29 #include "mach_traps.h"
  30
  31 /* perfctr_nmi_owner tracks the ownership of the perfctr registers:
  32  * evtsel_nmi_owner tracks the ownership of the event selection
  33  * - different performance counters/ event selection may be reserved for
  34  *   different subsystems this reservation system just tries to coordinate
  35  *   things a little
  36  */
  37 static DEFINE_PER_CPU(unsigned long, perfctr_nmi_owner);
  38 static DEFINE_PER_CPU(unsigned long, evntsel_nmi_owner[3]);
  39
  40 /* this number is calculated from Intel's MSR_P4_CRU_ESCR5 register and it's
  41  * offset from MSR_P4_BSU_ESCR0.  It will be the max for all platforms (for now)
  42  */
  43 #define NMI_MAX_COUNTER_BITS 66
  44
  45 /* nmi_active:
  46  * >0: the lapic NMI watchdog is active, but can be disabled
  47  * <0: the lapic NMI watchdog has not been set up, and cannot
  48  *     be enabled
  49  *  0: the lapic NMI watchdog is disabled, but can be enabled
  50  */
  51 atomic_t nmi_active = ATOMIC_INIT(0);           /* oprofile uses this */
  52
  53 unsigned int nmi_watchdog = NMI_DEFAULT;
  54 static unsigned int nmi_hz = HZ;
  55
  56 struct nmi_watchdog_ctlblk {
  57         int enabled;
  58         u64 check_bit;
  59         unsigned int cccr_msr;
  60         unsigned int perfctr_msr;  /* the MSR to reset in NMI handler */
  61         unsigned int evntsel_msr;  /* the MSR to select the events to handle */
  62 };
  63 static DEFINE_PER_CPU(struct nmi_watchdog_ctlblk, nmi_watchdog_ctlblk);
  64
  65 /* local prototypes */
  66 static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu);
  67
  68 extern void show_registers(struct pt_regs *regs);
  69 extern int unknown_nmi_panic;
  70
  71 /* converts an msr to an appropriate reservation bit */
  72 static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr)
  73 {
  74         /* returns the bit offset of the performance counter register */
  75         switch (boot_cpu_data.x86_vendor) {
  76         case X86_VENDOR_AMD:
  77                 return (msr - MSR_K7_PERFCTR0);
  78         case X86_VENDOR_INTEL:
  79                 switch (boot_cpu_data.x86) {
  80                 case 6:
  81                         return (msr - MSR_P6_PERFCTR0);
  82                 case 15:
  83                         return (msr - MSR_P4_BPU_PERFCTR0);
  84                 }
  85         }
  86         return 0;
  87 }
  88
  89 /* converts an msr to an appropriate reservation bit */
  90 static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr)
  91 {
  92         /* returns the bit offset of the event selection register */
  93         switch (boot_cpu_data.x86_vendor) {
  94         case X86_VENDOR_AMD:
  95                 return (msr - MSR_K7_EVNTSEL0);
  96         case X86_VENDOR_INTEL:
  97                 switch (boot_cpu_data.x86) {
  98                 case 6:
  99                         return (msr - MSR_P6_EVNTSEL0);
 100                 case 15:
 101                         return (msr - MSR_P4_BSU_ESCR0);
 102                 }
 103         }
 104         return 0;
 105 }
 106
 107 /* checks for a bit availability (hack for oprofile) */
 108 int avail_to_resrv_perfctr_nmi_bit(unsigned int counter)
 109 {
 110         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 111
 112         return (!test_bit(counter, &__get_cpu_var(perfctr_nmi_owner)));
 113 }
 114
 115 /* checks the an msr for availability */
 116 int avail_to_resrv_perfctr_nmi(unsigned int msr)
 117 {
 118         unsigned int counter;
 119
 120         counter = nmi_perfctr_msr_to_bit(msr);
 121         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 122
 123         return (!test_bit(counter, &__get_cpu_var(perfctr_nmi_owner)));
 124 }
 125
 126 int reserve_perfctr_nmi(unsigned int msr)
 127 {
 128         unsigned int counter;
 129
 130         counter = nmi_perfctr_msr_to_bit(msr);
 131         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 132
 133         if (!test_and_set_bit(counter, &__get_cpu_var(perfctr_nmi_owner)))
 134                 return 1;
 135         return 0;
 136 }
 137
 138 void release_perfctr_nmi(unsigned int msr)
 139 {
 140         unsigned int counter;
 141
 142         counter = nmi_perfctr_msr_to_bit(msr);
 143         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 144
 145         clear_bit(counter, &__get_cpu_var(perfctr_nmi_owner));
 146 }
 147
 148 int reserve_evntsel_nmi(unsigned int msr)
 149 {
 150         unsigned int counter;
 151
 152         counter = nmi_evntsel_msr_to_bit(msr);
 153         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 154
 155         if (!test_and_set_bit(counter, &__get_cpu_var(evntsel_nmi_owner)[0]))
 156                 return 1;
 157         return 0;
 158 }
 159
 160 void release_evntsel_nmi(unsigned int msr)
 161 {
 162         unsigned int counter;
 163
 164         counter = nmi_evntsel_msr_to_bit(msr);
 165         BUG_ON(counter > NMI_MAX_COUNTER_BITS);
 166
 167         clear_bit(counter, &__get_cpu_var(evntsel_nmi_owner)[0]);
 168 }
 169
 170 static __cpuinit inline int nmi_known_cpu(void)
 171 {
 172         switch (boot_cpu_data.x86_vendor) {
 173         case X86_VENDOR_AMD:
 174                 return ((boot_cpu_data.x86 == 15) || (boot_cpu_data.x86 == 6));
 175         case X86_VENDOR_INTEL:
 176                 return ((boot_cpu_data.x86 == 15) || (boot_cpu_data.x86 == 6));
 177         }
 178         return 0;
 179 }
 180
 181 #ifdef CONFIG_SMP
 182 /* The performance counters used by NMI_LOCAL_APIC don't trigger when
 183  * the CPU is idle. To make sure the NMI watchdog really ticks on all
 184  * CPUs during the test make them busy.
 185  */
 186 static __init void nmi_cpu_busy(void *data)
 187 {
 188         volatile int *endflag = data;
 189         local_irq_enable_in_hardirq();
 190         /* Intentionally don't use cpu_relax here. This is
 191            to make sure that the performance counter really ticks,
 192            even if there is a simulator or similar that catches the
 193            pause instruction. On a real HT machine this is fine because
 194            all other CPUs are busy with "useless" delay loops and don't
 195            care if they get somewhat less cycles. */
 196         while (*endflag == 0)
 197                 barrier();
 198 }
 199 #endif
 200
 201 static int __init check_nmi_watchdog(void)
 202 {
 203         volatile int endflag = 0;
 204         unsigned int *prev_nmi_count;
 205         int cpu;
 206
 207         if ((nmi_watchdog == NMI_NONE) || (nmi_watchdog == NMI_DEFAULT))
 208                 return 0;
 209
 210         if (!atomic_read(&nmi_active))
 211                 return 0;
 212
 213         prev_nmi_count = kmalloc(NR_CPUS * sizeof(int), GFP_KERNEL);
 214         if (!prev_nmi_count)
 215                 return -1;
 216
 217         printk(KERN_INFO "Testing NMI watchdog ... ");
 218
 219         if (nmi_watchdog == NMI_LOCAL_APIC)
 220                 smp_call_function(nmi_cpu_busy, (void *)&endflag, 0, 0);
 221
 222         for_each_possible_cpu(cpu)
 223                 prev_nmi_count[cpu] = per_cpu(irq_stat, cpu).__nmi_count;
 224         local_irq_enable();
 225         mdelay((10*1000)/nmi_hz); // wait 10 ticks
 226
 227         for_each_possible_cpu(cpu) {
 228 #ifdef CONFIG_SMP
 229                 /* Check cpu_callin_map here because that is set
 230                    after the timer is started. */
 231                 if (!cpu_isset(cpu, cpu_callin_map))
 232                         continue;
 233 #endif
 234                 if (!per_cpu(nmi_watchdog_ctlblk, cpu).enabled)
 235                         continue;
 236                 if (nmi_count(cpu) - prev_nmi_count[cpu] <= 5) {
 237                         printk("CPU#%d: NMI appears to be stuck (%d->%d)!\n",
 238                                 cpu,
 239                                 prev_nmi_count[cpu],
 240                                 nmi_count(cpu));
 241                         per_cpu(nmi_watchdog_ctlblk, cpu).enabled = 0;
 242                         atomic_dec(&nmi_active);
 243                 }
 244         }
 245         if (!atomic_read(&nmi_active)) {
 246                 kfree(prev_nmi_count);
 247                 atomic_set(&nmi_active, -1);
 248                 return -1;
 249         }
 250         endflag = 1;
 251         printk("OK.\n");
 252
 253         /* now that we know it works we can reduce NMI frequency to
 254            something more reasonable; makes a difference in some configs */
 255         if (nmi_watchdog == NMI_LOCAL_APIC)
 256                 nmi_hz = 1;
 257
 258         kfree(prev_nmi_count);
 259         return 0;
 260 }
 261 /* This needs to happen later in boot so counters are working */
 262 late_initcall(check_nmi_watchdog);
 263
 264 static int __init setup_nmi_watchdog(char *str)
 265 {
 266         int nmi;
 267
 268         get_option(&str, &nmi);
 269
 270         if ((nmi >= NMI_INVALID) || (nmi < NMI_NONE))
 271                 return 0;
 272         /*
 273          * If any other x86 CPU has a local APIC, then
 274          * please test the NMI stuff there and send me the
 275          * missing bits. Right now Intel P6/P4 and AMD K7 only.
 276          */
 277         if ((nmi == NMI_LOCAL_APIC) && (nmi_known_cpu() == 0))
 278                 return 0;  /* no lapic support */
 279         nmi_watchdog = nmi;
 280         return 1;
 281 }
 282
 283 __setup("nmi_watchdog=", setup_nmi_watchdog);
 284
 285 static void disable_lapic_nmi_watchdog(void)
 286 {
 287         BUG_ON(nmi_watchdog != NMI_LOCAL_APIC);
 288
 289         if (atomic_read(&nmi_active) <= 0)
 290                 return;
 291
 292         on_each_cpu(stop_apic_nmi_watchdog, NULL, 0, 1);
 293
 294         BUG_ON(atomic_read(&nmi_active) != 0);
 295 }
 296
 297 static void enable_lapic_nmi_watchdog(void)
 298 {
 299         BUG_ON(nmi_watchdog != NMI_LOCAL_APIC);
 300
 301         /* are we already enabled */
 302         if (atomic_read(&nmi_active) != 0)
 303                 return;
 304
 305         /* are we lapic aware */
 306         if (nmi_known_cpu() <= 0)
 307                 return;
 308
 309         on_each_cpu(setup_apic_nmi_watchdog, NULL, 0, 1);
 310         touch_nmi_watchdog();
 311 }
 312
 313 void disable_timer_nmi_watchdog(void)
 314 {
 315         BUG_ON(nmi_watchdog != NMI_IO_APIC);
 316
 317         if (atomic_read(&nmi_active) <= 0)
 318                 return;
 319
 320         disable_irq(0);
 321         on_each_cpu(stop_apic_nmi_watchdog, NULL, 0, 1);
 322
 323         BUG_ON(atomic_read(&nmi_active) != 0);
 324 }
 325
 326 void enable_timer_nmi_watchdog(void)
 327 {
 328         BUG_ON(nmi_watchdog != NMI_IO_APIC);
 329
 330         if (atomic_read(&nmi_active) == 0) {
 331                 touch_nmi_watchdog();
 332                 on_each_cpu(setup_apic_nmi_watchdog, NULL, 0, 1);
 333                 enable_irq(0);
 334         }
 335 }
 336
 337 #ifdef CONFIG_PM
 338
 339 static int nmi_pm_active; /* nmi_active before suspend */
 340
 341 static int lapic_nmi_suspend(struct sys_device *dev, pm_message_t state)
 342 {
 343         /* only CPU0 goes here, other CPUs should be offline */
 344         nmi_pm_active = atomic_read(&nmi_active);
 345         stop_apic_nmi_watchdog(NULL);
 346         BUG_ON(atomic_read(&nmi_active) != 0);
 347         return 0;
 348 }
 349
 350 static int lapic_nmi_resume(struct sys_device *dev)
 351 {
 352         /* only CPU0 goes here, other CPUs should be offline */
 353         if (nmi_pm_active > 0) {
 354                 setup_apic_nmi_watchdog(NULL);
 355                 touch_nmi_watchdog();
 356         }
 357         return 0;
 358 }
 359
 360
 361 static struct sysdev_class nmi_sysclass = {
 362         set_kset_name("lapic_nmi"),
 363         .resume         = lapic_nmi_resume,
 364         .suspend        = lapic_nmi_suspend,
 365 };
 366
 367 static struct sys_device device_lapic_nmi = {
 368         .id     = 0,
 369         .cls    = &nmi_sysclass,
 370 };
 371
 372 static int __init init_lapic_nmi_sysfs(void)
 373 {
 374         int error;
 375
 376         /* should really be a BUG_ON but b/c this is an
 377          * init call, it just doesn't work.  -dcz
 378          */
 379         if (nmi_watchdog != NMI_LOCAL_APIC)
 380                 return 0;
 381
 382         if ( atomic_read(&nmi_active) < 0 )
 383                 return 0;
 384
 385         error = sysdev_class_register(&nmi_sysclass);
 386         if (!error)
 387                 error = sysdev_register(&device_lapic_nmi);
 388         return error;
 389 }
 390 /* must come after the local APIC's device_initcall() */
 391 late_initcall(init_lapic_nmi_sysfs);
 392
 393 #endif  /* CONFIG_PM */
 394
 395 /*
 396  * Activate the NMI watchdog via the local APIC.
 397  * Original code written by Keith Owens.
 398  */
 399
 400 static void write_watchdog_counter(unsigned int perfctr_msr, const char *descr)
 401 {
 402         u64 count = (u64)cpu_khz * 1000;
 403
 404         do_div(count, nmi_hz);
 405         if(descr)
 406                 Dprintk("setting %s to -0x%08Lx\n", descr, count);
 407         wrmsrl(perfctr_msr, 0 - count);
 408 }
 409
 410 /* Note that these events don't tick when the CPU idles. This means
 411    the frequency varies with CPU load. */
 412
 413 #define K7_EVNTSEL_ENABLE       (1 << 22)
 414 #define K7_EVNTSEL_INT          (1 << 20)
 415 #define K7_EVNTSEL_OS           (1 << 17)
 416 #define K7_EVNTSEL_USR          (1 << 16)
 417 #define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING    0x76
 418 #define K7_NMI_EVENT            K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
 419
 420 static int setup_k7_watchdog(void)
 421 {
 422         unsigned int perfctr_msr, evntsel_msr;
 423         unsigned int evntsel;
 424         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 425
 426         perfctr_msr = MSR_K7_PERFCTR0;
 427         evntsel_msr = MSR_K7_EVNTSEL0;
 428         if (!reserve_perfctr_nmi(perfctr_msr))
 429                 goto fail;
 430
 431         if (!reserve_evntsel_nmi(evntsel_msr))
 432                 goto fail1;
 433
 434         wrmsrl(perfctr_msr, 0UL);
 435
 436         evntsel = K7_EVNTSEL_INT
 437                 | K7_EVNTSEL_OS
 438                 | K7_EVNTSEL_USR
 439                 | K7_NMI_EVENT;
 440
 441         /* setup the timer */
 442         wrmsr(evntsel_msr, evntsel, 0);
 443         write_watchdog_counter(perfctr_msr, "K7_PERFCTR0");
 444         apic_write(APIC_LVTPC, APIC_DM_NMI);
 445         evntsel |= K7_EVNTSEL_ENABLE;
 446         wrmsr(evntsel_msr, evntsel, 0);
 447
 448         wd->perfctr_msr = perfctr_msr;
 449         wd->evntsel_msr = evntsel_msr;
 450         wd->cccr_msr = 0;  //unused
 451         wd->check_bit = 1ULL<<63;
 452         return 1;
 453 fail1:
 454         release_perfctr_nmi(perfctr_msr);
 455 fail:
 456         return 0;
 457 }
 458
 459 static void stop_k7_watchdog(void)
 460 {
 461         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 462
 463         wrmsr(wd->evntsel_msr, 0, 0);
 464
 465         release_evntsel_nmi(wd->evntsel_msr);
 466         release_perfctr_nmi(wd->perfctr_msr);
 467 }
 468
 469 #define P6_EVNTSEL0_ENABLE      (1 << 22)
 470 #define P6_EVNTSEL_INT          (1 << 20)
 471 #define P6_EVNTSEL_OS           (1 << 17)
 472 #define P6_EVNTSEL_USR          (1 << 16)
 473 #define P6_EVENT_CPU_CLOCKS_NOT_HALTED  0x79
 474 #define P6_NMI_EVENT            P6_EVENT_CPU_CLOCKS_NOT_HALTED
 475
 476 static int setup_p6_watchdog(void)
 477 {
 478         unsigned int perfctr_msr, evntsel_msr;
 479         unsigned int evntsel;
 480         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 481
 482         perfctr_msr = MSR_P6_PERFCTR0;
 483         evntsel_msr = MSR_P6_EVNTSEL0;
 484         if (!reserve_perfctr_nmi(perfctr_msr))
 485                 goto fail;
 486
 487         if (!reserve_evntsel_nmi(evntsel_msr))
 488                 goto fail1;
 489
 490         wrmsrl(perfctr_msr, 0UL);
 491
 492         evntsel = P6_EVNTSEL_INT
 493                 | P6_EVNTSEL_OS
 494                 | P6_EVNTSEL_USR
 495                 | P6_NMI_EVENT;
 496
 497         /* setup the timer */
 498         wrmsr(evntsel_msr, evntsel, 0);
 499         write_watchdog_counter(perfctr_msr, "P6_PERFCTR0");
 500         apic_write(APIC_LVTPC, APIC_DM_NMI);
 501         evntsel |= P6_EVNTSEL0_ENABLE;
 502         wrmsr(evntsel_msr, evntsel, 0);
 503
 504         wd->perfctr_msr = perfctr_msr;
 505         wd->evntsel_msr = evntsel_msr;
 506         wd->cccr_msr = 0;  //unused
 507         wd->check_bit = 1ULL<<39;
 508         return 1;
 509 fail1:
 510         release_perfctr_nmi(perfctr_msr);
 511 fail:
 512         return 0;
 513 }
 514
 515 static void stop_p6_watchdog(void)
 516 {
 517         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 518
 519         wrmsr(wd->evntsel_msr, 0, 0);
 520
 521         release_evntsel_nmi(wd->evntsel_msr);
 522         release_perfctr_nmi(wd->perfctr_msr);
 523 }
 524
 525 /* Note that these events don't tick when the CPU idles. This means
 526    the frequency varies with CPU load. */
 527
 528 #define MSR_P4_MISC_ENABLE_PERF_AVAIL   (1<<7)
 529 #define P4_ESCR_EVENT_SELECT(N) ((N)<<25)
 530 #define P4_ESCR_OS              (1<<3)
 531 #define P4_ESCR_USR             (1<<2)
 532 #define P4_CCCR_OVF_PMI0        (1<<26)
 533 #define P4_CCCR_OVF_PMI1        (1<<27)
 534 #define P4_CCCR_THRESHOLD(N)    ((N)<<20)
 535 #define P4_CCCR_COMPLEMENT      (1<<19)
 536 #define P4_CCCR_COMPARE         (1<<18)
 537 #define P4_CCCR_REQUIRED        (3<<16)
 538 #define P4_CCCR_ESCR_SELECT(N)  ((N)<<13)
 539 #define P4_CCCR_ENABLE          (1<<12)
 540 #define P4_CCCR_OVF             (1<<31)
 541 /* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
 542    CRU_ESCR0 (with any non-null event selector) through a complemented
 543    max threshold. [IA32-Vol3, Section 14.9.9] */
 544
 545 static int setup_p4_watchdog(void)
 546 {
 547         unsigned int perfctr_msr, evntsel_msr, cccr_msr;
 548         unsigned int evntsel, cccr_val;
 549         unsigned int misc_enable, dummy;
 550         unsigned int ht_num;
 551         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 552
 553         rdmsr(MSR_IA32_MISC_ENABLE, misc_enable, dummy);
 554         if (!(misc_enable & MSR_P4_MISC_ENABLE_PERF_AVAIL))
 555                 return 0;
 556
 557 #ifdef CONFIG_SMP
 558         /* detect which hyperthread we are on */
 559         if (smp_num_siblings == 2) {
 560                 unsigned int ebx, apicid;
 561
 562                 ebx = cpuid_ebx(1);
 563                 apicid = (ebx >> 24) & 0xff;
 564                 ht_num = apicid & 1;
 565         } else
 566 #endif
 567                 ht_num = 0;
 568
 569         /* performance counters are shared resources
 570          * assign each hyperthread its own set
 571          * (re-use the ESCR0 register, seems safe
 572          * and keeps the cccr_val the same)
 573          */
 574         if (!ht_num) {
 575                 /* logical cpu 0 */
 576                 perfctr_msr = MSR_P4_IQ_PERFCTR0;
 577                 evntsel_msr = MSR_P4_CRU_ESCR0;
 578                 cccr_msr = MSR_P4_IQ_CCCR0;
 579                 cccr_val = P4_CCCR_OVF_PMI0 | P4_CCCR_ESCR_SELECT(4);
 580         } else {
 581                 /* logical cpu 1 */
 582                 perfctr_msr = MSR_P4_IQ_PERFCTR1;
 583                 evntsel_msr = MSR_P4_CRU_ESCR0;
 584                 cccr_msr = MSR_P4_IQ_CCCR1;
 585                 cccr_val = P4_CCCR_OVF_PMI1 | P4_CCCR_ESCR_SELECT(4);
 586         }
 587
 588         if (!reserve_perfctr_nmi(perfctr_msr))
 589                 goto fail;
 590
 591         if (!reserve_evntsel_nmi(evntsel_msr))
 592                 goto fail1;
 593
 594         evntsel = P4_ESCR_EVENT_SELECT(0x3F)
 595                 | P4_ESCR_OS
 596                 | P4_ESCR_USR;
 597
 598         cccr_val |= P4_CCCR_THRESHOLD(15)
 599                  | P4_CCCR_COMPLEMENT
 600                  | P4_CCCR_COMPARE
 601                  | P4_CCCR_REQUIRED;
 602
 603         wrmsr(evntsel_msr, evntsel, 0);
 604         wrmsr(cccr_msr, cccr_val, 0);
 605         write_watchdog_counter(perfctr_msr, "P4_IQ_COUNTER0");
 606         apic_write(APIC_LVTPC, APIC_DM_NMI);
 607         cccr_val |= P4_CCCR_ENABLE;
 608         wrmsr(cccr_msr, cccr_val, 0);
 609         wd->perfctr_msr = perfctr_msr;
 610         wd->evntsel_msr = evntsel_msr;
 611         wd->cccr_msr = cccr_msr;
 612         wd->check_bit = 1ULL<<39;
 613         return 1;
 614 fail1:
 615         release_perfctr_nmi(perfctr_msr);
 616 fail:
 617         return 0;
 618 }
 619
 620 static void stop_p4_watchdog(void)
 621 {
 622         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 623
 624         wrmsr(wd->cccr_msr, 0, 0);
 625         wrmsr(wd->evntsel_msr, 0, 0);
 626
 627         release_evntsel_nmi(wd->evntsel_msr);
 628         release_perfctr_nmi(wd->perfctr_msr);
 629 }
 630
 631 void setup_apic_nmi_watchdog (void *unused)
 632 {
 633         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 634
 635         /* only support LOCAL and IO APICs for now */
 636         if ((nmi_watchdog != NMI_LOCAL_APIC) &&
 637             (nmi_watchdog != NMI_IO_APIC))
 638                 return;
 639
 640         if (wd->enabled == 1)
 641                 return;
 642
 643         /* cheap hack to support suspend/resume */
 644         /* if cpu0 is not active neither should the other cpus */
 645         if ((smp_processor_id() != 0) && (atomic_read(&nmi_active) <= 0))
 646                 return;
 647
 648         if (nmi_watchdog == NMI_LOCAL_APIC) {
 649                 switch (boot_cpu_data.x86_vendor) {
 650                 case X86_VENDOR_AMD:
 651                         if (boot_cpu_data.x86 != 6 && boot_cpu_data.x86 != 15)
 652                                 return;
 653                         if (!setup_k7_watchdog())
 654                                 return;
 655                         break;
 656                 case X86_VENDOR_INTEL:
 657                         switch (boot_cpu_data.x86) {
 658                         case 6:
 659                                 if (boot_cpu_data.x86_model > 0xd)
 660                                         return;
 661
 662                                 if (!setup_p6_watchdog())
 663                                         return;
 664                                 break;
 665                         case 15:
 666                                 if (boot_cpu_data.x86_model > 0x4)
 667                                         return;
 668
 669                                 if (!setup_p4_watchdog())
 670                                         return;
 671                                 break;
 672                         default:
 673                                 return;
 674                         }
 675                         break;
 676                 default:
 677                         return;
 678                 }
 679         }
 680         wd->enabled = 1;
 681         atomic_inc(&nmi_active);
 682 }
 683
 684 void stop_apic_nmi_watchdog(void *unused)
 685 {
 686         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 687
 688         /* only support LOCAL and IO APICs for now */
 689         if ((nmi_watchdog != NMI_LOCAL_APIC) &&
 690             (nmi_watchdog != NMI_IO_APIC))
 691                 return;
 692
 693         if (wd->enabled == 0)
 694                 return;
 695
 696         if (nmi_watchdog == NMI_LOCAL_APIC) {
 697                 switch (boot_cpu_data.x86_vendor) {
 698                 case X86_VENDOR_AMD:
 699                         stop_k7_watchdog();
 700                         break;
 701                 case X86_VENDOR_INTEL:
 702                         switch (boot_cpu_data.x86) {
 703                         case 6:
 704                                 if (boot_cpu_data.x86_model > 0xd)
 705                                         break;
 706                                 stop_p6_watchdog();
 707                                 break;
 708                         case 15:
 709                                 if (boot_cpu_data.x86_model > 0x4)
 710                                         break;
 711                                 stop_p4_watchdog();
 712                                 break;
 713                         }
 714                         break;
 715                 default:
 716                         return;
 717                 }
 718         }
 719         wd->enabled = 0;
 720         atomic_dec(&nmi_active);
 721 }
 722
 723 /*
 724  * the best way to detect whether a CPU has a 'hard lockup' problem
 725  * is to check it's local APIC timer IRQ counts. If they are not
 726  * changing then that CPU has some problem.
 727  *
 728  * as these watchdog NMI IRQs are generated on every CPU, we only
 729  * have to check the current processor.
 730  *
 731  * since NMIs don't listen to _any_ locks, we have to be extremely
 732  * careful not to rely on unsafe variables. The printk might lock
 733  * up though, so we have to break up any console locks first ...
 734  * [when there will be more tty-related locks, break them up
 735  *  here too!]
 736  */
 737
 738 static unsigned int
 739         last_irq_sums [NR_CPUS],
 740         alert_counter [NR_CPUS];
 741
 742 void touch_nmi_watchdog (void)
 743 {
 744         int i;
 745
 746         /*
 747          * Just reset the alert counters, (other CPUs might be
 748          * spinning on locks we hold):
 749          */
 750         for_each_possible_cpu(i)
 751                 alert_counter[i] = 0;
 752
 753         /*
 754          * Tickle the softlockup detector too:
 755          */
 756         touch_softlockup_watchdog();
 757 }
 758 EXPORT_SYMBOL(touch_nmi_watchdog);
 759
 760 extern void die_nmi(struct pt_regs *, const char *msg);
 761
 762 int nmi_watchdog_tick (struct pt_regs * regs, unsigned reason)
 763 {
 764
 765         /*
 766          * Since current_thread_info()-> is always on the stack, and we
 767          * always switch the stack NMI-atomically, it's safe to use
 768          * smp_processor_id().
 769          */
 770         unsigned int sum;
 771         int touched = 0;
 772         int cpu = smp_processor_id();
 773         struct nmi_watchdog_ctlblk *wd = &__get_cpu_var(nmi_watchdog_ctlblk);
 774         u64 dummy;
 775         int rc=0;
 776
 777         /* check for other users first */
 778         if (notify_die(DIE_NMI, "nmi", regs, reason, 2, SIGINT)
 779                         == NOTIFY_STOP) {
 780                 rc = 1;
 781                 touched = 1;
 782         }
 783
 784         sum = per_cpu(irq_stat, cpu).apic_timer_irqs;
 785
 786         /* if the apic timer isn't firing, this cpu isn't doing much */
 787         if (!touched && last_irq_sums[cpu] == sum) {
 788                 /*
 789                  * Ayiee, looks like this CPU is stuck ...
 790                  * wait a few IRQs (5 seconds) before doing the oops ...
 791                  */
 792                 alert_counter[cpu]++;
 793                 if (alert_counter[cpu] == 5*nmi_hz)
 794                         /*
 795                          * die_nmi will return ONLY if NOTIFY_STOP happens..
 796                          */
 797                         die_nmi(regs, "BUG: NMI Watchdog detected LOCKUP");
 798         } else {
 799                 last_irq_sums[cpu] = sum;
 800                 alert_counter[cpu] = 0;
 801         }
 802         /* see if the nmi watchdog went off */
 803         if (wd->enabled) {
 804                 if (nmi_watchdog == NMI_LOCAL_APIC) {
 805                         rdmsrl(wd->perfctr_msr, dummy);
 806                         if (dummy & wd->check_bit){
 807                                 /* this wasn't a watchdog timer interrupt */
 808                                 goto done;
 809                         }
 810
 811                         /* only Intel P4 uses the cccr msr */
 812                         if (wd->cccr_msr != 0) {
 813                                 /*
 814                                  * P4 quirks:
 815                                  * - An overflown perfctr will assert its interrupt
 816                                  *   until the OVF flag in its CCCR is cleared.
 817                                  * - LVTPC is masked on interrupt and must be
 818                                  *   unmasked by the LVTPC handler.
 819                                  */
 820                                 rdmsrl(wd->cccr_msr, dummy);
 821                                 dummy &= ~P4_CCCR_OVF;
 822                                 wrmsrl(wd->cccr_msr, dummy);
 823                                 apic_write(APIC_LVTPC, APIC_DM_NMI);
 824                         }
 825                         else if (wd->perfctr_msr == MSR_P6_PERFCTR0) {
 826                                 /* Only P6 based Pentium M need to re-unmask
 827                                  * the apic vector but it doesn't hurt
 828                                  * other P6 variant */
 829                                 apic_write(APIC_LVTPC, APIC_DM_NMI);
 830                         }
 831                         /* start the cycle over again */
 832                         write_watchdog_counter(wd->perfctr_msr, NULL);
 833                         rc = 1;
 834                 } else if (nmi_watchdog == NMI_IO_APIC) {
 835                         /* don't know how to accurately check for this.
 836                          * just assume it was a watchdog timer interrupt
 837                          * This matches the old behaviour.
 838                          */
 839                         rc = 1;
 840                 } else
 841                         printk(KERN_WARNING "Unknown enabled NMI hardware?!\n");
 842         }
 843 done:
 844         return rc;
 845 }
 846
 847 int do_nmi_callback(struct pt_regs * regs, int cpu)
 848 {
 849 #ifdef CONFIG_SYSCTL
 850         if (unknown_nmi_panic)
 851                 return unknown_nmi_panic_callback(regs, cpu);
 852 #endif
 853         return 0;
 854 }
 855
 856 #ifdef CONFIG_SYSCTL
 857
 858 static int unknown_nmi_panic_callback(struct pt_regs *regs, int cpu)
 859 {
 860         unsigned char reason = get_nmi_reason();
 861         char buf[64];
 862
 863         sprintf(buf, "NMI received for unknown reason %02x\n", reason);
 864         die_nmi(regs, buf);
 865         return 0;
 866 }
 867
 868 /*
 869  * proc handler for /proc/sys/kernel/nmi
 870  */
 871 int proc_nmi_enabled(struct ctl_table *table, int write, struct file *file,
 872                         void __user *buffer, size_t *length, loff_t *ppos)
 873 {
 874         int old_state;
 875
 876         nmi_watchdog_enabled = (atomic_read(&nmi_active) > 0) ? 1 : 0;
 877         old_state = nmi_watchdog_enabled;
 878         proc_dointvec(table, write, file, buffer, length, ppos);
 879         if (!!old_state == !!nmi_watchdog_enabled)
 880                 return 0;
 881
 882         if (atomic_read(&nmi_active) < 0) {
 883                 printk( KERN_WARNING "NMI watchdog is permanently disabled\n");
 884                 return -EIO;
 885         }
 886
 887         if (nmi_watchdog == NMI_DEFAULT) {
 888                 if (nmi_known_cpu() > 0)
 889                         nmi_watchdog = NMI_LOCAL_APIC;
 890                 else
 891                         nmi_watchdog = NMI_IO_APIC;
 892         }
 893
 894         if (nmi_watchdog == NMI_LOCAL_APIC) {
 895                 if (nmi_watchdog_enabled)
 896                         enable_lapic_nmi_watchdog();
 897                 else
 898                         disable_lapic_nmi_watchdog();
 899         } else {
 900                 printk( KERN_WARNING
 901                         "NMI watchdog doesn't know what hardware to touch\n");
 902                 return -EIO;
 903         }
 904         return 0;
 905 }
 906
 907 #endif
 908
 909 EXPORT_SYMBOL(nmi_active);
 910 EXPORT_SYMBOL(nmi_watchdog);
 911 EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi);
 912 EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi_bit);
 913 EXPORT_SYMBOL(reserve_perfctr_nmi);
 914 EXPORT_SYMBOL(release_perfctr_nmi);
 915 EXPORT_SYMBOL(reserve_evntsel_nmi);
 916 EXPORT_SYMBOL(release_evntsel_nmi);
 917 EXPORT_SYMBOL(disable_timer_nmi_watchdog);
 918 EXPORT_SYMBOL(enable_timer_nmi_watchdog);