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Merge branch 'batman-adv/next' of git://git.open-mesh.org/linux-merge
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / jme.h
blob1481a62a1f363c1cef2aca41a18e651407848c60
1 /*
2 * JMicron JMC2x0 series PCIe Ethernet Linux Device Driver
3 *
4 * Copyright 2008 JMicron Technology Corporation
5 * http://www.jmicron.com/
6 * Copyright (c) 2009 - 2010 Guo-Fu Tseng <cooldavid@cooldavid.org>
7 *
8 * Author: Guo-Fu Tseng <cooldavid@cooldavid.org>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 *
23 */
24
25 #ifndef __JME_H_INCLUDED__
26 #define __JME_H_INCLUDED__
27 #include <linux/interrupt.h>
28
29 #define DRV_NAME "jme"
30 #define DRV_VERSION "1.0.8"
31 #define PFX DRV_NAME ": "
32
33 #define PCI_DEVICE_ID_JMICRON_JMC250 0x0250
34 #define PCI_DEVICE_ID_JMICRON_JMC260 0x0260
35
36 /*
37 * Message related definitions
38 */
39 #define JME_DEF_MSG_ENABLE \
40 (NETIF_MSG_PROBE | \
41 NETIF_MSG_LINK | \
42 NETIF_MSG_RX_ERR | \
43 NETIF_MSG_TX_ERR | \
44 NETIF_MSG_HW)
45
46 #ifdef TX_DEBUG
47 #define tx_dbg(priv, fmt, args...) \
48 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args)
49 #else
50 #define tx_dbg(priv, fmt, args...) \
51 do { \
52 if (0) \
53 printk(KERN_DEBUG "%s: " fmt, (priv)->dev->name, ##args); \
54 } while (0)
55 #endif
56
57 /*
58 * Extra PCI Configuration space interface
59 */
60 #define PCI_DCSR_MRRS 0x59
61 #define PCI_DCSR_MRRS_MASK 0x70
62
63 enum pci_dcsr_mrrs_vals {
64 MRRS_128B = 0x00,
65 MRRS_256B = 0x10,
66 MRRS_512B = 0x20,
67 MRRS_1024B = 0x30,
68 MRRS_2048B = 0x40,
69 MRRS_4096B = 0x50,
70 };
71
72 #define PCI_SPI 0xB0
73
74 enum pci_spi_bits {
75 SPI_EN = 0x10,
76 SPI_MISO = 0x08,
77 SPI_MOSI = 0x04,
78 SPI_SCLK = 0x02,
79 SPI_CS = 0x01,
80 };
81
82 struct jme_spi_op {
83 void __user *uwbuf;
84 void __user *urbuf;
85 __u8 wn; /* Number of write actions */
86 __u8 rn; /* Number of read actions */
87 __u8 bitn; /* Number of bits per action */
88 __u8 spd; /* The maxim acceptable speed of controller, in MHz.*/
89 __u8 mode; /* CPOL, CPHA, and Duplex mode of SPI */
90
91 /* Internal use only */
92 u8 *kwbuf;
93 u8 *krbuf;
94 u8 sr;
95 u16 halfclk; /* Half of clock cycle calculated from spd, in ns */
96 };
97
98 enum jme_spi_op_bits {
99 SPI_MODE_CPHA = 0x01,
100 SPI_MODE_CPOL = 0x02,
101 SPI_MODE_DUP = 0x80,
102 };
103
104 #define HALF_US 500 /* 500 ns */
105 #define JMESPIIOCTL SIOCDEVPRIVATE
106
107 #define PCI_PRIV_PE1 0xE4
108
109 enum pci_priv_pe1_bit_masks {
110 PE1_ASPMSUPRT = 0x00000003, /*
111 * RW:
112 * Aspm_support[1:0]
113 * (R/W Port of 5C[11:10])
114 */
115 PE1_MULTIFUN = 0x00000004, /* RW: Multi_fun_bit */
116 PE1_RDYDMA = 0x00000008, /* RO: ~link.rdy_for_dma */
117 PE1_ASPMOPTL = 0x00000030, /* RW: link.rx10s_option[1:0] */
118 PE1_ASPMOPTH = 0x000000C0, /* RW: 10_req=[3]?HW:[2] */
119 PE1_GPREG0 = 0x0000FF00, /*
120 * SRW:
121 * Cfg_gp_reg0
122 * [7:6] phy_giga BG control
123 * [5] CREQ_N as CREQ_N1 (CPPE# as CREQ#)
124 * [4:0] Reserved
125 */
126 PE1_GPREG0_PBG = 0x0000C000, /* phy_giga BG control */
127 PE1_GPREG1 = 0x00FF0000, /* RW: Cfg_gp_reg1 */
128 PE1_REVID = 0xFF000000, /* RO: Rev ID */
129 };
130
131 enum pci_priv_pe1_values {
132 PE1_GPREG0_ENBG = 0x00000000, /* en BG */
133 PE1_GPREG0_PDD3COLD = 0x00004000, /* giga_PD + d3cold */
134 PE1_GPREG0_PDPCIESD = 0x00008000, /* giga_PD + pcie_shutdown */
135 PE1_GPREG0_PDPCIEIDDQ = 0x0000C000, /* giga_PD + pcie_iddq */
136 };
137
138 /*
139 * Dynamic(adaptive)/Static PCC values
140 */
141 enum dynamic_pcc_values {
142 PCC_OFF = 0,
143 PCC_P1 = 1,
144 PCC_P2 = 2,
145 PCC_P3 = 3,
146
147 PCC_OFF_TO = 0,
148 PCC_P1_TO = 1,
149 PCC_P2_TO = 64,
150 PCC_P3_TO = 128,
151
152 PCC_OFF_CNT = 0,
153 PCC_P1_CNT = 1,
154 PCC_P2_CNT = 16,
155 PCC_P3_CNT = 32,
156 };
157 struct dynpcc_info {
158 unsigned long last_bytes;
159 unsigned long last_pkts;
160 unsigned long intr_cnt;
161 unsigned char cur;
162 unsigned char attempt;
163 unsigned char cnt;
164 };
165 #define PCC_INTERVAL_US 100000
166 #define PCC_INTERVAL (HZ / (1000000 / PCC_INTERVAL_US))
167 #define PCC_P3_THRESHOLD (2 * 1024 * 1024)
168 #define PCC_P2_THRESHOLD 800
169 #define PCC_INTR_THRESHOLD 800
170 #define PCC_TX_TO 1000
171 #define PCC_TX_CNT 8
172
173 /*
174 * TX/RX Descriptors
175 *
176 * TX/RX Ring DESC Count Must be multiple of 16 and <= 1024
177 */
178 #define RING_DESC_ALIGN 16 /* Descriptor alignment */
179 #define TX_DESC_SIZE 16
180 #define TX_RING_NR 8
181 #define TX_RING_ALLOC_SIZE(s) ((s * TX_DESC_SIZE) + RING_DESC_ALIGN)
182
183 struct txdesc {
184 union {
185 __u8 all[16];
186 __le32 dw[4];
187 struct {
188 /* DW0 */
189 __le16 vlan;
190 __u8 rsv1;
191 __u8 flags;
192
193 /* DW1 */
194 __le16 datalen;
195 __le16 mss;
196
197 /* DW2 */
198 __le16 pktsize;
199 __le16 rsv2;
200
201 /* DW3 */
202 __le32 bufaddr;
203 } desc1;
204 struct {
205 /* DW0 */
206 __le16 rsv1;
207 __u8 rsv2;
208 __u8 flags;
209
210 /* DW1 */
211 __le16 datalen;
212 __le16 rsv3;
213
214 /* DW2 */
215 __le32 bufaddrh;
216
217 /* DW3 */
218 __le32 bufaddrl;
219 } desc2;
220 struct {
221 /* DW0 */
222 __u8 ehdrsz;
223 __u8 rsv1;
224 __u8 rsv2;
225 __u8 flags;
226
227 /* DW1 */
228 __le16 trycnt;
229 __le16 segcnt;
230
231 /* DW2 */
232 __le16 pktsz;
233 __le16 rsv3;
234
235 /* DW3 */
236 __le32 bufaddrl;
237 } descwb;
238 };
239 };
240
241 enum jme_txdesc_flags_bits {
242 TXFLAG_OWN = 0x80,
243 TXFLAG_INT = 0x40,
244 TXFLAG_64BIT = 0x20,
245 TXFLAG_TCPCS = 0x10,
246 TXFLAG_UDPCS = 0x08,
247 TXFLAG_IPCS = 0x04,
248 TXFLAG_LSEN = 0x02,
249 TXFLAG_TAGON = 0x01,
250 };
251
252 #define TXDESC_MSS_SHIFT 2
253 enum jme_txwbdesc_flags_bits {
254 TXWBFLAG_OWN = 0x80,
255 TXWBFLAG_INT = 0x40,
256 TXWBFLAG_TMOUT = 0x20,
257 TXWBFLAG_TRYOUT = 0x10,
258 TXWBFLAG_COL = 0x08,
259
260 TXWBFLAG_ALLERR = TXWBFLAG_TMOUT |
261 TXWBFLAG_TRYOUT |
262 TXWBFLAG_COL,
263 };
264
265 #define RX_DESC_SIZE 16
266 #define RX_RING_NR 4
267 #define RX_RING_ALLOC_SIZE(s) ((s * RX_DESC_SIZE) + RING_DESC_ALIGN)
268 #define RX_BUF_DMA_ALIGN 8
269 #define RX_PREPAD_SIZE 10
270 #define ETH_CRC_LEN 2
271 #define RX_VLANHDR_LEN 2
272 #define RX_EXTRA_LEN (RX_PREPAD_SIZE + \
273 ETH_HLEN + \
274 ETH_CRC_LEN + \
275 RX_VLANHDR_LEN + \
276 RX_BUF_DMA_ALIGN)
277
278 struct rxdesc {
279 union {
280 __u8 all[16];
281 __le32 dw[4];
282 struct {
283 /* DW0 */
284 __le16 rsv2;
285 __u8 rsv1;
286 __u8 flags;
287
288 /* DW1 */
289 __le16 datalen;
290 __le16 wbcpl;
291
292 /* DW2 */
293 __le32 bufaddrh;
294
295 /* DW3 */
296 __le32 bufaddrl;
297 } desc1;
298 struct {
299 /* DW0 */
300 __le16 vlan;
301 __le16 flags;
302
303 /* DW1 */
304 __le16 framesize;
305 __u8 errstat;
306 __u8 desccnt;
307
308 /* DW2 */
309 __le32 rsshash;
310
311 /* DW3 */
312 __u8 hashfun;
313 __u8 hashtype;
314 __le16 resrv;
315 } descwb;
316 };
317 };
318
319 enum jme_rxdesc_flags_bits {
320 RXFLAG_OWN = 0x80,
321 RXFLAG_INT = 0x40,
322 RXFLAG_64BIT = 0x20,
323 };
324
325 enum jme_rxwbdesc_flags_bits {
326 RXWBFLAG_OWN = 0x8000,
327 RXWBFLAG_INT = 0x4000,
328 RXWBFLAG_MF = 0x2000,
329 RXWBFLAG_64BIT = 0x2000,
330 RXWBFLAG_TCPON = 0x1000,
331 RXWBFLAG_UDPON = 0x0800,
332 RXWBFLAG_IPCS = 0x0400,
333 RXWBFLAG_TCPCS = 0x0200,
334 RXWBFLAG_UDPCS = 0x0100,
335 RXWBFLAG_TAGON = 0x0080,
336 RXWBFLAG_IPV4 = 0x0040,
337 RXWBFLAG_IPV6 = 0x0020,
338 RXWBFLAG_PAUSE = 0x0010,
339 RXWBFLAG_MAGIC = 0x0008,
340 RXWBFLAG_WAKEUP = 0x0004,
341 RXWBFLAG_DEST = 0x0003,
342 RXWBFLAG_DEST_UNI = 0x0001,
343 RXWBFLAG_DEST_MUL = 0x0002,
344 RXWBFLAG_DEST_BRO = 0x0003,
345 };
346
347 enum jme_rxwbdesc_desccnt_mask {
348 RXWBDCNT_WBCPL = 0x80,
349 RXWBDCNT_DCNT = 0x7F,
350 };
351
352 enum jme_rxwbdesc_errstat_bits {
353 RXWBERR_LIMIT = 0x80,
354 RXWBERR_MIIER = 0x40,
355 RXWBERR_NIBON = 0x20,
356 RXWBERR_COLON = 0x10,
357 RXWBERR_ABORT = 0x08,
358 RXWBERR_SHORT = 0x04,
359 RXWBERR_OVERUN = 0x02,
360 RXWBERR_CRCERR = 0x01,
361 RXWBERR_ALLERR = 0xFF,
362 };
363
364 /*
365 * Buffer information corresponding to ring descriptors.
366 */
367 struct jme_buffer_info {
368 struct sk_buff *skb;
369 dma_addr_t mapping;
370 int len;
371 int nr_desc;
372 unsigned long start_xmit;
373 };
374
375 /*
376 * The structure holding buffer information and ring descriptors all together.
377 */
378 struct jme_ring {
379 void *alloc; /* pointer to allocated memory */
380 void *desc; /* pointer to ring memory */
381 dma_addr_t dmaalloc; /* phys address of ring alloc */
382 dma_addr_t dma; /* phys address for ring dma */
383
384 /* Buffer information corresponding to each descriptor */
385 struct jme_buffer_info *bufinf;
386
387 int next_to_use;
388 atomic_t next_to_clean;
389 atomic_t nr_free;
390 };
391
392 #define NET_STAT(priv) (priv->dev->stats)
393 #define NETDEV_GET_STATS(netdev, fun_ptr)
394 #define DECLARE_NET_DEVICE_STATS
395
396 #define DECLARE_NAPI_STRUCT struct napi_struct napi;
397 #define NETIF_NAPI_SET(dev, napis, pollfn, q) \
398 netif_napi_add(dev, napis, pollfn, q);
399 #define JME_NAPI_HOLDER(holder) struct napi_struct *holder
400 #define JME_NAPI_WEIGHT(w) int w
401 #define JME_NAPI_WEIGHT_VAL(w) w
402 #define JME_NAPI_WEIGHT_SET(w, r)
403 #define JME_RX_COMPLETE(dev, napis) napi_complete(napis)
404 #define JME_NAPI_ENABLE(priv) napi_enable(&priv->napi);
405 #define JME_NAPI_DISABLE(priv) \
406 if (!napi_disable_pending(&priv->napi)) \
407 napi_disable(&priv->napi);
408 #define JME_RX_SCHEDULE_PREP(priv) \
409 napi_schedule_prep(&priv->napi)
410 #define JME_RX_SCHEDULE(priv) \
411 __napi_schedule(&priv->napi);
412
413 /*
414 * Jmac Adapter Private data
415 */
416 struct jme_adapter {
417 struct pci_dev *pdev;
418 struct net_device *dev;
419 void __iomem *regs;
420 struct mii_if_info mii_if;
421 struct jme_ring rxring[RX_RING_NR];
422 struct jme_ring txring[TX_RING_NR];
423 spinlock_t phy_lock;
424 spinlock_t macaddr_lock;
425 spinlock_t rxmcs_lock;
426 struct tasklet_struct rxempty_task;
427 struct tasklet_struct rxclean_task;
428 struct tasklet_struct txclean_task;
429 struct tasklet_struct linkch_task;
430 struct tasklet_struct pcc_task;
431 unsigned long flags;
432 u32 reg_txcs;
433 u32 reg_txpfc;
434 u32 reg_rxcs;
435 u32 reg_rxmcs;
436 u32 reg_ghc;
437 u32 reg_pmcs;
438 u32 reg_gpreg1;
439 u32 phylink;
440 u32 tx_ring_size;
441 u32 tx_ring_mask;
442 u32 tx_wake_threshold;
443 u32 rx_ring_size;
444 u32 rx_ring_mask;
445 u8 mrrs;
446 unsigned int fpgaver;
447 u8 chiprev;
448 u8 chip_main_rev;
449 u8 chip_sub_rev;
450 u8 pcirev;
451 u32 msg_enable;
452 struct ethtool_cmd old_ecmd;
453 unsigned int old_mtu;
454 struct vlan_group *vlgrp;
455 struct dynpcc_info dpi;
456 atomic_t intr_sem;
457 atomic_t link_changing;
458 atomic_t tx_cleaning;
459 atomic_t rx_cleaning;
460 atomic_t rx_empty;
461 int (*jme_rx)(struct sk_buff *skb);
462 int (*jme_vlan_rx)(struct sk_buff *skb,
463 struct vlan_group *grp,
464 unsigned short vlan_tag);
465 DECLARE_NAPI_STRUCT
466 DECLARE_NET_DEVICE_STATS
467 };
468
469 enum jme_flags_bits {
470 JME_FLAG_MSI = 1,
471 JME_FLAG_SSET = 2,
472 JME_FLAG_POLL = 5,
473 JME_FLAG_SHUTDOWN = 6,
474 };
475
476 #define TX_TIMEOUT (5 * HZ)
477 #define JME_REG_LEN 0x500
478 #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9216
479
480 static inline struct jme_adapter*
481 jme_napi_priv(struct napi_struct *napi)
482 {
483 struct jme_adapter *jme;
484 jme = container_of(napi, struct jme_adapter, napi);
485 return jme;
486 }
487
488 /*
489 * MMaped I/O Resters
490 */
491 enum jme_iomap_offsets {
492 JME_MAC = 0x0000,
493 JME_PHY = 0x0400,
494 JME_MISC = 0x0800,
495 JME_RSS = 0x0C00,
496 };
497
498 enum jme_iomap_lens {
499 JME_MAC_LEN = 0x80,
500 JME_PHY_LEN = 0x58,
501 JME_MISC_LEN = 0x98,
502 JME_RSS_LEN = 0xFF,
503 };
504
505 enum jme_iomap_regs {
506 JME_TXCS = JME_MAC | 0x00, /* Transmit Control and Status */
507 JME_TXDBA_LO = JME_MAC | 0x04, /* Transmit Queue Desc Base Addr */
508 JME_TXDBA_HI = JME_MAC | 0x08, /* Transmit Queue Desc Base Addr */
509 JME_TXQDC = JME_MAC | 0x0C, /* Transmit Queue Desc Count */
510 JME_TXNDA = JME_MAC | 0x10, /* Transmit Queue Next Desc Addr */
511 JME_TXMCS = JME_MAC | 0x14, /* Transmit MAC Control Status */
512 JME_TXPFC = JME_MAC | 0x18, /* Transmit Pause Frame Control */
513 JME_TXTRHD = JME_MAC | 0x1C, /* Transmit Timer/Retry@Half-Dup */
514
515 JME_RXCS = JME_MAC | 0x20, /* Receive Control and Status */
516 JME_RXDBA_LO = JME_MAC | 0x24, /* Receive Queue Desc Base Addr */
517 JME_RXDBA_HI = JME_MAC | 0x28, /* Receive Queue Desc Base Addr */
518 JME_RXQDC = JME_MAC | 0x2C, /* Receive Queue Desc Count */
519 JME_RXNDA = JME_MAC | 0x30, /* Receive Queue Next Desc Addr */
520 JME_RXMCS = JME_MAC | 0x34, /* Receive MAC Control Status */
521 JME_RXUMA_LO = JME_MAC | 0x38, /* Receive Unicast MAC Address */
522 JME_RXUMA_HI = JME_MAC | 0x3C, /* Receive Unicast MAC Address */
523 JME_RXMCHT_LO = JME_MAC | 0x40, /* Recv Multicast Addr HashTable */
524 JME_RXMCHT_HI = JME_MAC | 0x44, /* Recv Multicast Addr HashTable */
525 JME_WFODP = JME_MAC | 0x48, /* Wakeup Frame Output Data Port */
526 JME_WFOI = JME_MAC | 0x4C, /* Wakeup Frame Output Interface */
527
528 JME_SMI = JME_MAC | 0x50, /* Station Management Interface */
529 JME_GHC = JME_MAC | 0x54, /* Global Host Control */
530 JME_PMCS = JME_MAC | 0x60, /* Power Management Control/Stat */
531
532
533 JME_PHY_PWR = JME_PHY | 0x24, /* New PHY Power Ctrl Register */
534 JME_PHY_CS = JME_PHY | 0x28, /* PHY Ctrl and Status Register */
535 JME_PHY_LINK = JME_PHY | 0x30, /* PHY Link Status Register */
536 JME_SMBCSR = JME_PHY | 0x40, /* SMB Control and Status */
537 JME_SMBINTF = JME_PHY | 0x44, /* SMB Interface */
538
539
540 JME_TMCSR = JME_MISC | 0x00, /* Timer Control/Status Register */
541 JME_GPREG0 = JME_MISC | 0x08, /* General purpose REG-0 */
542 JME_GPREG1 = JME_MISC | 0x0C, /* General purpose REG-1 */
543 JME_IEVE = JME_MISC | 0x20, /* Interrupt Event Status */
544 JME_IREQ = JME_MISC | 0x24, /* Intr Req Status(For Debug) */
545 JME_IENS = JME_MISC | 0x28, /* Intr Enable - Setting Port */
546 JME_IENC = JME_MISC | 0x2C, /* Interrupt Enable - Clear Port */
547 JME_PCCRX0 = JME_MISC | 0x30, /* PCC Control for RX Queue 0 */
548 JME_PCCTX = JME_MISC | 0x40, /* PCC Control for TX Queues */
549 JME_CHIPMODE = JME_MISC | 0x44, /* Identify FPGA Version */
550 JME_SHBA_HI = JME_MISC | 0x48, /* Shadow Register Base HI */
551 JME_SHBA_LO = JME_MISC | 0x4C, /* Shadow Register Base LO */
552 JME_TIMER1 = JME_MISC | 0x70, /* Timer1 */
553 JME_TIMER2 = JME_MISC | 0x74, /* Timer2 */
554 JME_APMC = JME_MISC | 0x7C, /* Aggressive Power Mode Control */
555 JME_PCCSRX0 = JME_MISC | 0x80, /* PCC Status of RX0 */
556 };
557
558 /*
559 * TX Control/Status Bits
560 */
561 enum jme_txcs_bits {
562 TXCS_QUEUE7S = 0x00008000,
563 TXCS_QUEUE6S = 0x00004000,
564 TXCS_QUEUE5S = 0x00002000,
565 TXCS_QUEUE4S = 0x00001000,
566 TXCS_QUEUE3S = 0x00000800,
567 TXCS_QUEUE2S = 0x00000400,
568 TXCS_QUEUE1S = 0x00000200,
569 TXCS_QUEUE0S = 0x00000100,
570 TXCS_FIFOTH = 0x000000C0,
571 TXCS_DMASIZE = 0x00000030,
572 TXCS_BURST = 0x00000004,
573 TXCS_ENABLE = 0x00000001,
574 };
575
576 enum jme_txcs_value {
577 TXCS_FIFOTH_16QW = 0x000000C0,
578 TXCS_FIFOTH_12QW = 0x00000080,
579 TXCS_FIFOTH_8QW = 0x00000040,
580 TXCS_FIFOTH_4QW = 0x00000000,
581
582 TXCS_DMASIZE_64B = 0x00000000,
583 TXCS_DMASIZE_128B = 0x00000010,
584 TXCS_DMASIZE_256B = 0x00000020,
585 TXCS_DMASIZE_512B = 0x00000030,
586
587 TXCS_SELECT_QUEUE0 = 0x00000000,
588 TXCS_SELECT_QUEUE1 = 0x00010000,
589 TXCS_SELECT_QUEUE2 = 0x00020000,
590 TXCS_SELECT_QUEUE3 = 0x00030000,
591 TXCS_SELECT_QUEUE4 = 0x00040000,
592 TXCS_SELECT_QUEUE5 = 0x00050000,
593 TXCS_SELECT_QUEUE6 = 0x00060000,
594 TXCS_SELECT_QUEUE7 = 0x00070000,
595
596 TXCS_DEFAULT = TXCS_FIFOTH_4QW |
597 TXCS_BURST,
598 };
599
600 #define JME_TX_DISABLE_TIMEOUT 10 /* 10 msec */
601
602 /*
603 * TX MAC Control/Status Bits
604 */
605 enum jme_txmcs_bit_masks {
606 TXMCS_IFG2 = 0xC0000000,
607 TXMCS_IFG1 = 0x30000000,
608 TXMCS_TTHOLD = 0x00000300,
609 TXMCS_FBURST = 0x00000080,
610 TXMCS_CARRIEREXT = 0x00000040,
611 TXMCS_DEFER = 0x00000020,
612 TXMCS_BACKOFF = 0x00000010,
613 TXMCS_CARRIERSENSE = 0x00000008,
614 TXMCS_COLLISION = 0x00000004,
615 TXMCS_CRC = 0x00000002,
616 TXMCS_PADDING = 0x00000001,
617 };
618
619 enum jme_txmcs_values {
620 TXMCS_IFG2_6_4 = 0x00000000,
621 TXMCS_IFG2_8_5 = 0x40000000,
622 TXMCS_IFG2_10_6 = 0x80000000,
623 TXMCS_IFG2_12_7 = 0xC0000000,
624
625 TXMCS_IFG1_8_4 = 0x00000000,
626 TXMCS_IFG1_12_6 = 0x10000000,
627 TXMCS_IFG1_16_8 = 0x20000000,
628 TXMCS_IFG1_20_10 = 0x30000000,
629
630 TXMCS_TTHOLD_1_8 = 0x00000000,
631 TXMCS_TTHOLD_1_4 = 0x00000100,
632 TXMCS_TTHOLD_1_2 = 0x00000200,
633 TXMCS_TTHOLD_FULL = 0x00000300,
634
635 TXMCS_DEFAULT = TXMCS_IFG2_8_5 |
636 TXMCS_IFG1_16_8 |
637 TXMCS_TTHOLD_FULL |
638 TXMCS_DEFER |
639 TXMCS_CRC |
640 TXMCS_PADDING,
641 };
642
643 enum jme_txpfc_bits_masks {
644 TXPFC_VLAN_TAG = 0xFFFF0000,
645 TXPFC_VLAN_EN = 0x00008000,
646 TXPFC_PF_EN = 0x00000001,
647 };
648
649 enum jme_txtrhd_bits_masks {
650 TXTRHD_TXPEN = 0x80000000,
651 TXTRHD_TXP = 0x7FFFFF00,
652 TXTRHD_TXREN = 0x00000080,
653 TXTRHD_TXRL = 0x0000007F,
654 };
655
656 enum jme_txtrhd_shifts {
657 TXTRHD_TXP_SHIFT = 8,
658 TXTRHD_TXRL_SHIFT = 0,
659 };
660
661 enum jme_txtrhd_values {
662 TXTRHD_FULLDUPLEX = 0x00000000,
663 TXTRHD_HALFDUPLEX = TXTRHD_TXPEN |
664 ((0x2000 << TXTRHD_TXP_SHIFT) & TXTRHD_TXP) |
665 TXTRHD_TXREN |
666 ((8 << TXTRHD_TXRL_SHIFT) & TXTRHD_TXRL),
667 };
668
669 /*
670 * RX Control/Status Bits
671 */
672 enum jme_rxcs_bit_masks {
673 /* FIFO full threshold for transmitting Tx Pause Packet */
674 RXCS_FIFOTHTP = 0x30000000,
675 /* FIFO threshold for processing next packet */
676 RXCS_FIFOTHNP = 0x0C000000,
677 RXCS_DMAREQSZ = 0x03000000, /* DMA Request Size */
678 RXCS_QUEUESEL = 0x00030000, /* Queue selection */
679 RXCS_RETRYGAP = 0x0000F000, /* RX Desc full retry gap */
680 RXCS_RETRYCNT = 0x00000F00, /* RX Desc full retry counter */
681 RXCS_WAKEUP = 0x00000040, /* Enable receive wakeup packet */
682 RXCS_MAGIC = 0x00000020, /* Enable receive magic packet */
683 RXCS_SHORT = 0x00000010, /* Enable receive short packet */
684 RXCS_ABORT = 0x00000008, /* Enable receive errorr packet */
685 RXCS_QST = 0x00000004, /* Receive queue start */
686 RXCS_SUSPEND = 0x00000002,
687 RXCS_ENABLE = 0x00000001,
688 };
689
690 enum jme_rxcs_values {
691 RXCS_FIFOTHTP_16T = 0x00000000,
692 RXCS_FIFOTHTP_32T = 0x10000000,
693 RXCS_FIFOTHTP_64T = 0x20000000,
694 RXCS_FIFOTHTP_128T = 0x30000000,
695
696 RXCS_FIFOTHNP_16QW = 0x00000000,
697 RXCS_FIFOTHNP_32QW = 0x04000000,
698 RXCS_FIFOTHNP_64QW = 0x08000000,
699 RXCS_FIFOTHNP_128QW = 0x0C000000,
700
701 RXCS_DMAREQSZ_16B = 0x00000000,
702 RXCS_DMAREQSZ_32B = 0x01000000,
703 RXCS_DMAREQSZ_64B = 0x02000000,
704 RXCS_DMAREQSZ_128B = 0x03000000,
705
706 RXCS_QUEUESEL_Q0 = 0x00000000,
707 RXCS_QUEUESEL_Q1 = 0x00010000,
708 RXCS_QUEUESEL_Q2 = 0x00020000,
709 RXCS_QUEUESEL_Q3 = 0x00030000,
710
711 RXCS_RETRYGAP_256ns = 0x00000000,
712 RXCS_RETRYGAP_512ns = 0x00001000,
713 RXCS_RETRYGAP_1024ns = 0x00002000,
714 RXCS_RETRYGAP_2048ns = 0x00003000,
715 RXCS_RETRYGAP_4096ns = 0x00004000,
716 RXCS_RETRYGAP_8192ns = 0x00005000,
717 RXCS_RETRYGAP_16384ns = 0x00006000,
718 RXCS_RETRYGAP_32768ns = 0x00007000,
719
720 RXCS_RETRYCNT_0 = 0x00000000,
721 RXCS_RETRYCNT_4 = 0x00000100,
722 RXCS_RETRYCNT_8 = 0x00000200,
723 RXCS_RETRYCNT_12 = 0x00000300,
724 RXCS_RETRYCNT_16 = 0x00000400,
725 RXCS_RETRYCNT_20 = 0x00000500,
726 RXCS_RETRYCNT_24 = 0x00000600,
727 RXCS_RETRYCNT_28 = 0x00000700,
728 RXCS_RETRYCNT_32 = 0x00000800,
729 RXCS_RETRYCNT_36 = 0x00000900,
730 RXCS_RETRYCNT_40 = 0x00000A00,
731 RXCS_RETRYCNT_44 = 0x00000B00,
732 RXCS_RETRYCNT_48 = 0x00000C00,
733 RXCS_RETRYCNT_52 = 0x00000D00,
734 RXCS_RETRYCNT_56 = 0x00000E00,
735 RXCS_RETRYCNT_60 = 0x00000F00,
736
737 RXCS_DEFAULT = RXCS_FIFOTHTP_128T |
738 RXCS_FIFOTHNP_128QW |
739 RXCS_DMAREQSZ_128B |
740 RXCS_RETRYGAP_256ns |
741 RXCS_RETRYCNT_32,
742 };
743
744 #define JME_RX_DISABLE_TIMEOUT 10 /* 10 msec */
745
746 /*
747 * RX MAC Control/Status Bits
748 */
749 enum jme_rxmcs_bits {
750 RXMCS_ALLFRAME = 0x00000800,
751 RXMCS_BRDFRAME = 0x00000400,
752 RXMCS_MULFRAME = 0x00000200,
753 RXMCS_UNIFRAME = 0x00000100,
754 RXMCS_ALLMULFRAME = 0x00000080,
755 RXMCS_MULFILTERED = 0x00000040,
756 RXMCS_RXCOLLDEC = 0x00000020,
757 RXMCS_FLOWCTRL = 0x00000008,
758 RXMCS_VTAGRM = 0x00000004,
759 RXMCS_PREPAD = 0x00000002,
760 RXMCS_CHECKSUM = 0x00000001,
761
762 RXMCS_DEFAULT = RXMCS_VTAGRM |
763 RXMCS_PREPAD |
764 RXMCS_FLOWCTRL |
765 RXMCS_CHECKSUM,
766 };
767
768 /*
769 * Wakeup Frame setup interface registers
770 */
771 #define WAKEUP_FRAME_NR 8
772 #define WAKEUP_FRAME_MASK_DWNR 4
773
774 enum jme_wfoi_bit_masks {
775 WFOI_MASK_SEL = 0x00000070,
776 WFOI_CRC_SEL = 0x00000008,
777 WFOI_FRAME_SEL = 0x00000007,
778 };
779
780 enum jme_wfoi_shifts {
781 WFOI_MASK_SHIFT = 4,
782 };
783
784 /*
785 * SMI Related definitions
786 */
787 enum jme_smi_bit_mask {
788 SMI_DATA_MASK = 0xFFFF0000,
789 SMI_REG_ADDR_MASK = 0x0000F800,
790 SMI_PHY_ADDR_MASK = 0x000007C0,
791 SMI_OP_WRITE = 0x00000020,
792 /* Set to 1, after req done it'll be cleared to 0 */
793 SMI_OP_REQ = 0x00000010,
794 SMI_OP_MDIO = 0x00000008, /* Software assess In/Out */
795 SMI_OP_MDOE = 0x00000004, /* Software Output Enable */
796 SMI_OP_MDC = 0x00000002, /* Software CLK Control */
797 SMI_OP_MDEN = 0x00000001, /* Software access Enable */
798 };
799
800 enum jme_smi_bit_shift {
801 SMI_DATA_SHIFT = 16,
802 SMI_REG_ADDR_SHIFT = 11,
803 SMI_PHY_ADDR_SHIFT = 6,
804 };
805
806 static inline u32 smi_reg_addr(int x)
807 {
808 return (x << SMI_REG_ADDR_SHIFT) & SMI_REG_ADDR_MASK;
809 }
810
811 static inline u32 smi_phy_addr(int x)
812 {
813 return (x << SMI_PHY_ADDR_SHIFT) & SMI_PHY_ADDR_MASK;
814 }
815
816 #define JME_PHY_TIMEOUT 100 /* 100 msec */
817 #define JME_PHY_REG_NR 32
818
819 /*
820 * Global Host Control
821 */
822 enum jme_ghc_bit_mask {
823 GHC_SWRST = 0x40000000,
824 GHC_TO_CLK_SRC = 0x00C00000,
825 GHC_TXMAC_CLK_SRC = 0x00300000,
826 GHC_DPX = 0x00000040,
827 GHC_SPEED = 0x00000030,
828 GHC_LINK_POLL = 0x00000001,
829 };
830
831 enum jme_ghc_speed_val {
832 GHC_SPEED_10M = 0x00000010,
833 GHC_SPEED_100M = 0x00000020,
834 GHC_SPEED_1000M = 0x00000030,
835 };
836
837 enum jme_ghc_to_clk {
838 GHC_TO_CLK_OFF = 0x00000000,
839 GHC_TO_CLK_GPHY = 0x00400000,
840 GHC_TO_CLK_PCIE = 0x00800000,
841 GHC_TO_CLK_INVALID = 0x00C00000,
842 };
843
844 enum jme_ghc_txmac_clk {
845 GHC_TXMAC_CLK_OFF = 0x00000000,
846 GHC_TXMAC_CLK_GPHY = 0x00100000,
847 GHC_TXMAC_CLK_PCIE = 0x00200000,
848 GHC_TXMAC_CLK_INVALID = 0x00300000,
849 };
850
851 /*
852 * Power management control and status register
853 */
854 enum jme_pmcs_bit_masks {
855 PMCS_STMASK = 0xFFFF0000,
856 PMCS_WF7DET = 0x80000000,
857 PMCS_WF6DET = 0x40000000,
858 PMCS_WF5DET = 0x20000000,
859 PMCS_WF4DET = 0x10000000,
860 PMCS_WF3DET = 0x08000000,
861 PMCS_WF2DET = 0x04000000,
862 PMCS_WF1DET = 0x02000000,
863 PMCS_WF0DET = 0x01000000,
864 PMCS_LFDET = 0x00040000,
865 PMCS_LRDET = 0x00020000,
866 PMCS_MFDET = 0x00010000,
867 PMCS_ENMASK = 0x0000FFFF,
868 PMCS_WF7EN = 0x00008000,
869 PMCS_WF6EN = 0x00004000,
870 PMCS_WF5EN = 0x00002000,
871 PMCS_WF4EN = 0x00001000,
872 PMCS_WF3EN = 0x00000800,
873 PMCS_WF2EN = 0x00000400,
874 PMCS_WF1EN = 0x00000200,
875 PMCS_WF0EN = 0x00000100,
876 PMCS_LFEN = 0x00000004,
877 PMCS_LREN = 0x00000002,
878 PMCS_MFEN = 0x00000001,
879 };
880
881 /*
882 * New PHY Power Control Register
883 */
884 enum jme_phy_pwr_bit_masks {
885 PHY_PWR_DWN1SEL = 0x01000000, /* Phy_giga.p_PWR_DOWN1_SEL */
886 PHY_PWR_DWN1SW = 0x02000000, /* Phy_giga.p_PWR_DOWN1_SW */
887 PHY_PWR_DWN2 = 0x04000000, /* Phy_giga.p_PWR_DOWN2 */
888 PHY_PWR_CLKSEL = 0x08000000, /*
889 * XTL_OUT Clock select
890 * (an internal free-running clock)
891 * 0: xtl_out = phy_giga.A_XTL25_O
892 * 1: xtl_out = phy_giga.PD_OSC
893 */
894 };
895
896 /*
897 * Giga PHY Status Registers
898 */
899 enum jme_phy_link_bit_mask {
900 PHY_LINK_SPEED_MASK = 0x0000C000,
901 PHY_LINK_DUPLEX = 0x00002000,
902 PHY_LINK_SPEEDDPU_RESOLVED = 0x00000800,
903 PHY_LINK_UP = 0x00000400,
904 PHY_LINK_AUTONEG_COMPLETE = 0x00000200,
905 PHY_LINK_MDI_STAT = 0x00000040,
906 };
907
908 enum jme_phy_link_speed_val {
909 PHY_LINK_SPEED_10M = 0x00000000,
910 PHY_LINK_SPEED_100M = 0x00004000,
911 PHY_LINK_SPEED_1000M = 0x00008000,
912 };
913
914 #define JME_SPDRSV_TIMEOUT 500 /* 500 us */
915
916 /*
917 * SMB Control and Status
918 */
919 enum jme_smbcsr_bit_mask {
920 SMBCSR_CNACK = 0x00020000,
921 SMBCSR_RELOAD = 0x00010000,
922 SMBCSR_EEPROMD = 0x00000020,
923 SMBCSR_INITDONE = 0x00000010,
924 SMBCSR_BUSY = 0x0000000F,
925 };
926
927 enum jme_smbintf_bit_mask {
928 SMBINTF_HWDATR = 0xFF000000,
929 SMBINTF_HWDATW = 0x00FF0000,
930 SMBINTF_HWADDR = 0x0000FF00,
931 SMBINTF_HWRWN = 0x00000020,
932 SMBINTF_HWCMD = 0x00000010,
933 SMBINTF_FASTM = 0x00000008,
934 SMBINTF_GPIOSCL = 0x00000004,
935 SMBINTF_GPIOSDA = 0x00000002,
936 SMBINTF_GPIOEN = 0x00000001,
937 };
938
939 enum jme_smbintf_vals {
940 SMBINTF_HWRWN_READ = 0x00000020,
941 SMBINTF_HWRWN_WRITE = 0x00000000,
942 };
943
944 enum jme_smbintf_shifts {
945 SMBINTF_HWDATR_SHIFT = 24,
946 SMBINTF_HWDATW_SHIFT = 16,
947 SMBINTF_HWADDR_SHIFT = 8,
948 };
949
950 #define JME_EEPROM_RELOAD_TIMEOUT 2000 /* 2000 msec */
951 #define JME_SMB_BUSY_TIMEOUT 20 /* 20 msec */
952 #define JME_SMB_LEN 256
953 #define JME_EEPROM_MAGIC 0x250
954
955 /*
956 * Timer Control/Status Register
957 */
958 enum jme_tmcsr_bit_masks {
959 TMCSR_SWIT = 0x80000000,
960 TMCSR_EN = 0x01000000,
961 TMCSR_CNT = 0x00FFFFFF,
962 };
963
964 /*
965 * General Purpose REG-0
966 */
967 enum jme_gpreg0_masks {
968 GPREG0_DISSH = 0xFF000000,
969 GPREG0_PCIRLMT = 0x00300000,
970 GPREG0_PCCNOMUTCLR = 0x00040000,
971 GPREG0_LNKINTPOLL = 0x00001000,
972 GPREG0_PCCTMR = 0x00000300,
973 GPREG0_PHYADDR = 0x0000001F,
974 };
975
976 enum jme_gpreg0_vals {
977 GPREG0_DISSH_DW7 = 0x80000000,
978 GPREG0_DISSH_DW6 = 0x40000000,
979 GPREG0_DISSH_DW5 = 0x20000000,
980 GPREG0_DISSH_DW4 = 0x10000000,
981 GPREG0_DISSH_DW3 = 0x08000000,
982 GPREG0_DISSH_DW2 = 0x04000000,
983 GPREG0_DISSH_DW1 = 0x02000000,
984 GPREG0_DISSH_DW0 = 0x01000000,
985 GPREG0_DISSH_ALL = 0xFF000000,
986
987 GPREG0_PCIRLMT_8 = 0x00000000,
988 GPREG0_PCIRLMT_6 = 0x00100000,
989 GPREG0_PCIRLMT_5 = 0x00200000,
990 GPREG0_PCIRLMT_4 = 0x00300000,
991
992 GPREG0_PCCTMR_16ns = 0x00000000,
993 GPREG0_PCCTMR_256ns = 0x00000100,
994 GPREG0_PCCTMR_1us = 0x00000200,
995 GPREG0_PCCTMR_1ms = 0x00000300,
996
997 GPREG0_PHYADDR_1 = 0x00000001,
998
999 GPREG0_DEFAULT = GPREG0_PCIRLMT_4 |
1000 GPREG0_PCCTMR_1us |
1001 GPREG0_PHYADDR_1,
1002 };
1003
1004 /*
1005 * General Purpose REG-1
1006 */
1007 enum jme_gpreg1_bit_masks {
1008 GPREG1_RXCLKOFF = 0x04000000,
1009 GPREG1_PCREQN = 0x00020000,
1010 GPREG1_HALFMODEPATCH = 0x00000040, /* For Chip revision 0x11 only */
1011 GPREG1_RSSPATCH = 0x00000020, /* For Chip revision 0x11 only */
1012 GPREG1_INTRDELAYUNIT = 0x00000018,
1013 GPREG1_INTRDELAYENABLE = 0x00000007,
1014 };
1015
1016 enum jme_gpreg1_vals {
1017 GPREG1_INTDLYUNIT_16NS = 0x00000000,
1018 GPREG1_INTDLYUNIT_256NS = 0x00000008,
1019 GPREG1_INTDLYUNIT_1US = 0x00000010,
1020 GPREG1_INTDLYUNIT_16US = 0x00000018,
1021
1022 GPREG1_INTDLYEN_1U = 0x00000001,
1023 GPREG1_INTDLYEN_2U = 0x00000002,
1024 GPREG1_INTDLYEN_3U = 0x00000003,
1025 GPREG1_INTDLYEN_4U = 0x00000004,
1026 GPREG1_INTDLYEN_5U = 0x00000005,
1027 GPREG1_INTDLYEN_6U = 0x00000006,
1028 GPREG1_INTDLYEN_7U = 0x00000007,
1029
1030 GPREG1_DEFAULT = GPREG1_PCREQN,
1031 };
1032
1033 /*
1034 * Interrupt Status Bits
1035 */
1036 enum jme_interrupt_bits {
1037 INTR_SWINTR = 0x80000000,
1038 INTR_TMINTR = 0x40000000,
1039 INTR_LINKCH = 0x20000000,
1040 INTR_PAUSERCV = 0x10000000,
1041 INTR_MAGICRCV = 0x08000000,
1042 INTR_WAKERCV = 0x04000000,
1043 INTR_PCCRX0TO = 0x02000000,
1044 INTR_PCCRX1TO = 0x01000000,
1045 INTR_PCCRX2TO = 0x00800000,
1046 INTR_PCCRX3TO = 0x00400000,
1047 INTR_PCCTXTO = 0x00200000,
1048 INTR_PCCRX0 = 0x00100000,
1049 INTR_PCCRX1 = 0x00080000,
1050 INTR_PCCRX2 = 0x00040000,
1051 INTR_PCCRX3 = 0x00020000,
1052 INTR_PCCTX = 0x00010000,
1053 INTR_RX3EMP = 0x00008000,
1054 INTR_RX2EMP = 0x00004000,
1055 INTR_RX1EMP = 0x00002000,
1056 INTR_RX0EMP = 0x00001000,
1057 INTR_RX3 = 0x00000800,
1058 INTR_RX2 = 0x00000400,
1059 INTR_RX1 = 0x00000200,
1060 INTR_RX0 = 0x00000100,
1061 INTR_TX7 = 0x00000080,
1062 INTR_TX6 = 0x00000040,
1063 INTR_TX5 = 0x00000020,
1064 INTR_TX4 = 0x00000010,
1065 INTR_TX3 = 0x00000008,
1066 INTR_TX2 = 0x00000004,
1067 INTR_TX1 = 0x00000002,
1068 INTR_TX0 = 0x00000001,
1069 };
1070
1071 static const u32 INTR_ENABLE = INTR_SWINTR |
1072 INTR_TMINTR |
1073 INTR_LINKCH |
1074 INTR_PCCRX0TO |
1075 INTR_PCCRX0 |
1076 INTR_PCCTXTO |
1077 INTR_PCCTX |
1078 INTR_RX0EMP;
1079
1080 /*
1081 * PCC Control Registers
1082 */
1083 enum jme_pccrx_masks {
1084 PCCRXTO_MASK = 0xFFFF0000,
1085 PCCRX_MASK = 0x0000FF00,
1086 };
1087
1088 enum jme_pcctx_masks {
1089 PCCTXTO_MASK = 0xFFFF0000,
1090 PCCTX_MASK = 0x0000FF00,
1091 PCCTX_QS_MASK = 0x000000FF,
1092 };
1093
1094 enum jme_pccrx_shifts {
1095 PCCRXTO_SHIFT = 16,
1096 PCCRX_SHIFT = 8,
1097 };
1098
1099 enum jme_pcctx_shifts {
1100 PCCTXTO_SHIFT = 16,
1101 PCCTX_SHIFT = 8,
1102 };
1103
1104 enum jme_pcctx_bits {
1105 PCCTXQ0_EN = 0x00000001,
1106 PCCTXQ1_EN = 0x00000002,
1107 PCCTXQ2_EN = 0x00000004,
1108 PCCTXQ3_EN = 0x00000008,
1109 PCCTXQ4_EN = 0x00000010,
1110 PCCTXQ5_EN = 0x00000020,
1111 PCCTXQ6_EN = 0x00000040,
1112 PCCTXQ7_EN = 0x00000080,
1113 };
1114
1115 /*
1116 * Chip Mode Register
1117 */
1118 enum jme_chipmode_bit_masks {
1119 CM_FPGAVER_MASK = 0xFFFF0000,
1120 CM_CHIPREV_MASK = 0x0000FF00,
1121 CM_CHIPMODE_MASK = 0x0000000F,
1122 };
1123
1124 enum jme_chipmode_shifts {
1125 CM_FPGAVER_SHIFT = 16,
1126 CM_CHIPREV_SHIFT = 8,
1127 };
1128
1129 /*
1130 * Aggressive Power Mode Control
1131 */
1132 enum jme_apmc_bits {
1133 JME_APMC_PCIE_SD_EN = 0x40000000,
1134 JME_APMC_PSEUDO_HP_EN = 0x20000000,
1135 JME_APMC_EPIEN = 0x04000000,
1136 JME_APMC_EPIEN_CTRL = 0x03000000,
1137 };
1138
1139 enum jme_apmc_values {
1140 JME_APMC_EPIEN_CTRL_EN = 0x02000000,
1141 JME_APMC_EPIEN_CTRL_DIS = 0x01000000,
1142 };
1143
1144 #define APMC_PHP_SHUTDOWN_DELAY (10 * 1000 * 1000)
1145
1146 #ifdef REG_DEBUG
1147 static char *MAC_REG_NAME[] = {
1148 "JME_TXCS", "JME_TXDBA_LO", "JME_TXDBA_HI", "JME_TXQDC",
1149 "JME_TXNDA", "JME_TXMCS", "JME_TXPFC", "JME_TXTRHD",
1150 "JME_RXCS", "JME_RXDBA_LO", "JME_RXDBA_HI", "JME_RXQDC",
1151 "JME_RXNDA", "JME_RXMCS", "JME_RXUMA_LO", "JME_RXUMA_HI",
1152 "JME_RXMCHT_LO", "JME_RXMCHT_HI", "JME_WFODP", "JME_WFOI",
1153 "JME_SMI", "JME_GHC", "UNKNOWN", "UNKNOWN",
1154 "JME_PMCS"};
1155
1156 static char *PE_REG_NAME[] = {
1157 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1158 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1159 "UNKNOWN", "UNKNOWN", "JME_PHY_CS", "UNKNOWN",
1160 "JME_PHY_LINK", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1161 "JME_SMBCSR", "JME_SMBINTF"};
1162
1163 static char *MISC_REG_NAME[] = {
1164 "JME_TMCSR", "JME_GPIO", "JME_GPREG0", "JME_GPREG1",
1165 "JME_IEVE", "JME_IREQ", "JME_IENS", "JME_IENC",
1166 "JME_PCCRX0", "JME_PCCRX1", "JME_PCCRX2", "JME_PCCRX3",
1167 "JME_PCCTX0", "JME_CHIPMODE", "JME_SHBA_HI", "JME_SHBA_LO",
1168 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1169 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1170 "UNKNOWN", "UNKNOWN", "UNKNOWN", "UNKNOWN",
1171 "JME_TIMER1", "JME_TIMER2", "UNKNOWN", "JME_APMC",
1172 "JME_PCCSRX0"};
1173
1174 static inline void reg_dbg(const struct jme_adapter *jme,
1175 const char *msg, u32 val, u32 reg)
1176 {
1177 const char *regname;
1178 switch (reg & 0xF00) {
1179 case 0x000:
1180 regname = MAC_REG_NAME[(reg & 0xFF) >> 2];
1181 break;
1182 case 0x400:
1183 regname = PE_REG_NAME[(reg & 0xFF) >> 2];
1184 break;
1185 case 0x800:
1186 regname = MISC_REG_NAME[(reg & 0xFF) >> 2];
1187 break;
1188 default:
1189 regname = PE_REG_NAME[0];
1190 }
1191 printk(KERN_DEBUG "%s: %-20s %08x@%s\n", jme->dev->name,
1192 msg, val, regname);
1193 }
1194 #else
1195 static inline void reg_dbg(const struct jme_adapter *jme,
1196 const char *msg, u32 val, u32 reg) {}
1197 #endif
1198
1199 /*
1200 * Read/Write MMaped I/O Registers
1201 */
1202 static inline u32 jread32(struct jme_adapter *jme, u32 reg)
1203 {
1204 return readl(jme->regs + reg);
1205 }
1206
1207 static inline void jwrite32(struct jme_adapter *jme, u32 reg, u32 val)
1208 {
1209 reg_dbg(jme, "REG WRITE", val, reg);
1210 writel(val, jme->regs + reg);
1211 reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1212 }
1213
1214 static inline void jwrite32f(struct jme_adapter *jme, u32 reg, u32 val)
1215 {
1216 /*
1217 * Read after write should cause flush
1218 */
1219 reg_dbg(jme, "REG WRITE FLUSH", val, reg);
1220 writel(val, jme->regs + reg);
1221 readl(jme->regs + reg);
1222 reg_dbg(jme, "VAL AFTER WRITE", readl(jme->regs + reg), reg);
1223 }
1224
1225 /*
1226 * PHY Regs
1227 */
1228 enum jme_phy_reg17_bit_masks {
1229 PREG17_SPEED = 0xC000,
1230 PREG17_DUPLEX = 0x2000,
1231 PREG17_SPDRSV = 0x0800,
1232 PREG17_LNKUP = 0x0400,
1233 PREG17_MDI = 0x0040,
1234 };
1235
1236 enum jme_phy_reg17_vals {
1237 PREG17_SPEED_10M = 0x0000,
1238 PREG17_SPEED_100M = 0x4000,
1239 PREG17_SPEED_1000M = 0x8000,
1240 };
1241
1242 #define BMSR_ANCOMP 0x0020
1243
1244 /*
1245 * Workaround
1246 */
1247 static inline int is_buggy250(unsigned short device, u8 chiprev)
1248 {
1249 return device == PCI_DEVICE_ID_JMICRON_JMC250 && chiprev == 0x11;
1250 }
1251
1252 static inline int new_phy_power_ctrl(u8 chip_main_rev)
1253 {
1254 return chip_main_rev >= 5;
1255 }
1256
1257 /*
1258 * Function prototypes
1259 */
1260 static int jme_set_settings(struct net_device *netdev,
1261 struct ethtool_cmd *ecmd);
1262 static void jme_set_unicastaddr(struct net_device *netdev);
1263 static void jme_set_multi(struct net_device *netdev);
1264
1265 #endif
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree