2 * debugfs ops for the L1 cache
4 * Copyright (C) 2006 Paul Mundt
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
10 #include <linux/init.h>
11 #include <linux/module.h>
12 #include <linux/debugfs.h>
13 #include <linux/seq_file.h>
14 #include <asm/processor.h>
15 #include <asm/uaccess.h>
16 #include <asm/cache.h>
25 static int cache_seq_show(struct seq_file
*file
, void *iter
)
27 unsigned int cache_type
= (unsigned int)file
->private;
28 struct cache_info
*cache
;
29 unsigned int waysize
, way
, cache_size
;
30 unsigned long ccr
, base
;
31 static unsigned long addrstart
= 0;
34 * Go uncached immediately so we don't skew the results any
35 * more than we already are..
39 ccr
= __raw_readl(CCR
);
40 if ((ccr
& CCR_CACHE_ENABLE
) == 0) {
43 seq_printf(file
, "disabled\n");
47 if (cache_type
== CACHE_TYPE_DCACHE
) {
48 base
= CACHE_OC_ADDRESS_ARRAY
;
49 cache
= ¤t_cpu_data
.dcache
;
51 base
= CACHE_IC_ADDRESS_ARRAY
;
52 cache
= ¤t_cpu_data
.icache
;
56 * Due to the amount of data written out (depending on the cache size),
57 * we may be iterated over multiple times. In this case, keep track of
58 * the entry position in addrstart, and rewind it when we've hit the
61 * Likewise, the same code is used for multiple caches, so care must
62 * be taken for bouncing addrstart back and forth so the appropriate
65 cache_size
= cache
->ways
* cache
->sets
* cache
->linesz
;
66 if (((addrstart
& 0xff000000) != base
) ||
67 (addrstart
& 0x00ffffff) > cache_size
)
70 waysize
= cache
->sets
;
73 * If the OC is already in RAM mode, we only have
74 * half of the entries to consider..
76 if ((ccr
& CCR_CACHE_ORA
) && cache_type
== CACHE_TYPE_DCACHE
)
79 waysize
<<= cache
->entry_shift
;
81 for (way
= 0; way
< cache
->ways
; way
++) {
85 seq_printf(file
, "-----------------------------------------\n");
86 seq_printf(file
, "Way %d\n", way
);
87 seq_printf(file
, "-----------------------------------------\n");
89 for (addr
= addrstart
, line
= 0;
90 addr
< addrstart
+ waysize
;
91 addr
+= cache
->linesz
, line
++) {
92 unsigned long data
= __raw_readl(addr
);
94 /* Check the V bit, ignore invalid cachelines */
98 /* U: Dirty, cache tag is 10 bits up */
99 seq_printf(file
, "%3d: %c 0x%lx\n",
100 line
, data
& 2 ? 'U' : ' ',
104 addrstart
+= cache
->way_incr
;
112 static int cache_debugfs_open(struct inode
*inode
, struct file
*file
)
114 return single_open(file
, cache_seq_show
, inode
->i_private
);
117 static const struct file_operations cache_debugfs_fops
= {
118 .owner
= THIS_MODULE
,
119 .open
= cache_debugfs_open
,
122 .release
= single_release
,
125 static int __init
cache_debugfs_init(void)
127 struct dentry
*dcache_dentry
, *icache_dentry
;
129 dcache_dentry
= debugfs_create_file("dcache", S_IRUSR
, sh_debugfs_root
,
130 (unsigned int *)CACHE_TYPE_DCACHE
,
131 &cache_debugfs_fops
);
134 if (IS_ERR(dcache_dentry
))
135 return PTR_ERR(dcache_dentry
);
137 icache_dentry
= debugfs_create_file("icache", S_IRUSR
, sh_debugfs_root
,
138 (unsigned int *)CACHE_TYPE_ICACHE
,
139 &cache_debugfs_fops
);
140 if (!icache_dentry
) {
141 debugfs_remove(dcache_dentry
);
144 if (IS_ERR(icache_dentry
)) {
145 debugfs_remove(dcache_dentry
);
146 return PTR_ERR(icache_dentry
);
151 module_init(cache_debugfs_init
);
153 MODULE_LICENSE("GPL v2");