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iwlwifi: add SM PS support for 6x50 series
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / iwlwifi / iwl-agn.c
blobb5fe8f87aa7efb0cf145de2fe32a1013ab8d216f
1 /******************************************************************************
2 *
3 * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
4 *
5 * Portions of this file are derived from the ipw3945 project, as well
6 * as portions of the ieee80211 subsystem header files.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of version 2 of the GNU General Public License as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 * more details.
16 *
17 * You should have received a copy of the GNU General Public License along with
18 * this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
20 *
21 * The full GNU General Public License is included in this distribution in the
22 * file called LICENSE.
23 *
24 * Contact Information:
25 * Intel Linux Wireless <ilw@linux.intel.com>
26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *
28 *****************************************************************************/
29
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/init.h>
33 #include <linux/pci.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/delay.h>
36 #include <linux/skbuff.h>
37 #include <linux/netdevice.h>
38 #include <linux/wireless.h>
39 #include <linux/firmware.h>
40 #include <linux/etherdevice.h>
41 #include <linux/if_arp.h>
42
43 #include <net/mac80211.h>
44
45 #include <asm/div64.h>
46
47 #define DRV_NAME "iwlagn"
48
49 #include "iwl-eeprom.h"
50 #include "iwl-dev.h"
51 #include "iwl-core.h"
52 #include "iwl-io.h"
53 #include "iwl-helpers.h"
54 #include "iwl-sta.h"
55 #include "iwl-calib.h"
56
57
58 /******************************************************************************
59 *
60 * module boiler plate
61 *
62 ******************************************************************************/
63
64 /*
65 * module name, copyright, version, etc.
66 */
67 #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
68
69 #ifdef CONFIG_IWLWIFI_DEBUG
70 #define VD "d"
71 #else
72 #define VD
73 #endif
74
75 #ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT
76 #define VS "s"
77 #else
78 #define VS
79 #endif
80
81 #define DRV_VERSION IWLWIFI_VERSION VD VS
82
83
84 MODULE_DESCRIPTION(DRV_DESCRIPTION);
85 MODULE_VERSION(DRV_VERSION);
86 MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
87 MODULE_LICENSE("GPL");
88 MODULE_ALIAS("iwl4965");
89
90 /*************** STATION TABLE MANAGEMENT ****
91 * mac80211 should be examined to determine if sta_info is duplicating
92 * the functionality provided here
93 */
94
95 /**************************************************************/
96
97 /**
98 * iwl_commit_rxon - commit staging_rxon to hardware
99 *
100 * The RXON command in staging_rxon is committed to the hardware and
101 * the active_rxon structure is updated with the new data. This
102 * function correctly transitions out of the RXON_ASSOC_MSK state if
103 * a HW tune is required based on the RXON structure changes.
104 */
105 int iwl_commit_rxon(struct iwl_priv *priv)
106 {
107 /* cast away the const for active_rxon in this function */
108 struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
109 int ret;
110 bool new_assoc =
111 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
112
113 if (!iwl_is_alive(priv))
114 return -EBUSY;
115
116 /* always get timestamp with Rx frame */
117 priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
118
119 ret = iwl_check_rxon_cmd(priv);
120 if (ret) {
121 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
122 return -EINVAL;
123 }
124
125 /* If we don't need to send a full RXON, we can use
126 * iwl_rxon_assoc_cmd which is used to reconfigure filter
127 * and other flags for the current radio configuration. */
128 if (!iwl_full_rxon_required(priv)) {
129 ret = iwl_send_rxon_assoc(priv);
130 if (ret) {
131 IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
132 return ret;
133 }
134
135 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
136 return 0;
137 }
138
139 /* station table will be cleared */
140 priv->assoc_station_added = 0;
141
142 /* If we are currently associated and the new config requires
143 * an RXON_ASSOC and the new config wants the associated mask enabled,
144 * we must clear the associated from the active configuration
145 * before we apply the new config */
146 if (iwl_is_associated(priv) && new_assoc) {
147 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
148 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
149
150 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
151 sizeof(struct iwl_rxon_cmd),
152 &priv->active_rxon);
153
154 /* If the mask clearing failed then we set
155 * active_rxon back to what it was previously */
156 if (ret) {
157 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
158 IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
159 return ret;
160 }
161 }
162
163 IWL_DEBUG_INFO(priv, "Sending RXON\n"
164 "* with%s RXON_FILTER_ASSOC_MSK\n"
165 "* channel = %d\n"
166 "* bssid = %pM\n",
167 (new_assoc ? "" : "out"),
168 le16_to_cpu(priv->staging_rxon.channel),
169 priv->staging_rxon.bssid_addr);
170
171 iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
172
173 /* Apply the new configuration
174 * RXON unassoc clears the station table in uCode, send it before
175 * we add the bcast station. If assoc bit is set, we will send RXON
176 * after having added the bcast and bssid station.
177 */
178 if (!new_assoc) {
179 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
180 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
181 if (ret) {
182 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
183 return ret;
184 }
185 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
186 }
187
188 iwl_clear_stations_table(priv);
189
190 priv->start_calib = 0;
191
192 /* Add the broadcast address so we can send broadcast frames */
193 iwl_add_bcast_station(priv);
194
195 /* If we have set the ASSOC_MSK and we are in BSS mode then
196 * add the IWL_AP_ID to the station rate table */
197 if (new_assoc) {
198 if (priv->iw_mode == NL80211_IFTYPE_STATION) {
199 ret = iwl_rxon_add_station(priv,
200 priv->active_rxon.bssid_addr, 1);
201 if (ret == IWL_INVALID_STATION) {
202 IWL_ERR(priv,
203 "Error adding AP address for TX.\n");
204 return -EIO;
205 }
206 priv->assoc_station_added = 1;
207 if (priv->default_wep_key &&
208 iwl_send_static_wepkey_cmd(priv, 0))
209 IWL_ERR(priv,
210 "Could not send WEP static key.\n");
211 }
212
213 /*
214 * allow CTS-to-self if possible for new association.
215 * this is relevant only for 5000 series and up,
216 * but will not damage 4965
217 */
218 priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
219
220 /* Apply the new configuration
221 * RXON assoc doesn't clear the station table in uCode,
222 */
223 ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
224 sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
225 if (ret) {
226 IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
227 return ret;
228 }
229 memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
230 }
231
232 iwl_init_sensitivity(priv);
233
234 /* If we issue a new RXON command which required a tune then we must
235 * send a new TXPOWER command or we won't be able to Tx any frames */
236 ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
237 if (ret) {
238 IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
239 return ret;
240 }
241
242 return 0;
243 }
244
245 void iwl_update_chain_flags(struct iwl_priv *priv)
246 {
247
248 if (priv->cfg->ops->hcmd->set_rxon_chain)
249 priv->cfg->ops->hcmd->set_rxon_chain(priv);
250 iwlcore_commit_rxon(priv);
251 }
252
253 static void iwl_clear_free_frames(struct iwl_priv *priv)
254 {
255 struct list_head *element;
256
257 IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
258 priv->frames_count);
259
260 while (!list_empty(&priv->free_frames)) {
261 element = priv->free_frames.next;
262 list_del(element);
263 kfree(list_entry(element, struct iwl_frame, list));
264 priv->frames_count--;
265 }
266
267 if (priv->frames_count) {
268 IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
269 priv->frames_count);
270 priv->frames_count = 0;
271 }
272 }
273
274 static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
275 {
276 struct iwl_frame *frame;
277 struct list_head *element;
278 if (list_empty(&priv->free_frames)) {
279 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
280 if (!frame) {
281 IWL_ERR(priv, "Could not allocate frame!\n");
282 return NULL;
283 }
284
285 priv->frames_count++;
286 return frame;
287 }
288
289 element = priv->free_frames.next;
290 list_del(element);
291 return list_entry(element, struct iwl_frame, list);
292 }
293
294 static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
295 {
296 memset(frame, 0, sizeof(*frame));
297 list_add(&frame->list, &priv->free_frames);
298 }
299
300 static unsigned int iwl_fill_beacon_frame(struct iwl_priv *priv,
301 struct ieee80211_hdr *hdr,
302 int left)
303 {
304 if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
305 ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
306 (priv->iw_mode != NL80211_IFTYPE_AP)))
307 return 0;
308
309 if (priv->ibss_beacon->len > left)
310 return 0;
311
312 memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
313
314 return priv->ibss_beacon->len;
315 }
316
317 static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
318 struct iwl_frame *frame, u8 rate)
319 {
320 struct iwl_tx_beacon_cmd *tx_beacon_cmd;
321 unsigned int frame_size;
322
323 tx_beacon_cmd = &frame->u.beacon;
324 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
325
326 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
327 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
328
329 frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
330 sizeof(frame->u) - sizeof(*tx_beacon_cmd));
331
332 BUG_ON(frame_size > MAX_MPDU_SIZE);
333 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
334
335 if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
336 tx_beacon_cmd->tx.rate_n_flags =
337 iwl_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
338 else
339 tx_beacon_cmd->tx.rate_n_flags =
340 iwl_hw_set_rate_n_flags(rate, 0);
341
342 tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
343 TX_CMD_FLG_TSF_MSK |
344 TX_CMD_FLG_STA_RATE_MSK;
345
346 return sizeof(*tx_beacon_cmd) + frame_size;
347 }
348 static int iwl_send_beacon_cmd(struct iwl_priv *priv)
349 {
350 struct iwl_frame *frame;
351 unsigned int frame_size;
352 int rc;
353 u8 rate;
354
355 frame = iwl_get_free_frame(priv);
356
357 if (!frame) {
358 IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
359 "command.\n");
360 return -ENOMEM;
361 }
362
363 rate = iwl_rate_get_lowest_plcp(priv);
364
365 frame_size = iwl_hw_get_beacon_cmd(priv, frame, rate);
366
367 rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
368 &frame->u.cmd[0]);
369
370 iwl_free_frame(priv, frame);
371
372 return rc;
373 }
374
375 static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
376 {
377 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
378
379 dma_addr_t addr = get_unaligned_le32(&tb->lo);
380 if (sizeof(dma_addr_t) > sizeof(u32))
381 addr |=
382 ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
383
384 return addr;
385 }
386
387 static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
388 {
389 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
390
391 return le16_to_cpu(tb->hi_n_len) >> 4;
392 }
393
394 static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
395 dma_addr_t addr, u16 len)
396 {
397 struct iwl_tfd_tb *tb = &tfd->tbs[idx];
398 u16 hi_n_len = len << 4;
399
400 put_unaligned_le32(addr, &tb->lo);
401 if (sizeof(dma_addr_t) > sizeof(u32))
402 hi_n_len |= ((addr >> 16) >> 16) & 0xF;
403
404 tb->hi_n_len = cpu_to_le16(hi_n_len);
405
406 tfd->num_tbs = idx + 1;
407 }
408
409 static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
410 {
411 return tfd->num_tbs & 0x1f;
412 }
413
414 /**
415 * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
416 * @priv - driver private data
417 * @txq - tx queue
418 *
419 * Does NOT advance any TFD circular buffer read/write indexes
420 * Does NOT free the TFD itself (which is within circular buffer)
421 */
422 void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
423 {
424 struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
425 struct iwl_tfd *tfd;
426 struct pci_dev *dev = priv->pci_dev;
427 int index = txq->q.read_ptr;
428 int i;
429 int num_tbs;
430
431 tfd = &tfd_tmp[index];
432
433 /* Sanity check on number of chunks */
434 num_tbs = iwl_tfd_get_num_tbs(tfd);
435
436 if (num_tbs >= IWL_NUM_OF_TBS) {
437 IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
438 /* @todo issue fatal error, it is quite serious situation */
439 return;
440 }
441
442 /* Unmap tx_cmd */
443 if (num_tbs)
444 pci_unmap_single(dev,
445 pci_unmap_addr(&txq->meta[index], mapping),
446 pci_unmap_len(&txq->meta[index], len),
447 PCI_DMA_BIDIRECTIONAL);
448
449 /* Unmap chunks, if any. */
450 for (i = 1; i < num_tbs; i++) {
451 pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
452 iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
453
454 if (txq->txb) {
455 dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
456 txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
457 }
458 }
459 }
460
461 int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
462 struct iwl_tx_queue *txq,
463 dma_addr_t addr, u16 len,
464 u8 reset, u8 pad)
465 {
466 struct iwl_queue *q;
467 struct iwl_tfd *tfd, *tfd_tmp;
468 u32 num_tbs;
469
470 q = &txq->q;
471 tfd_tmp = (struct iwl_tfd *)txq->tfds;
472 tfd = &tfd_tmp[q->write_ptr];
473
474 if (reset)
475 memset(tfd, 0, sizeof(*tfd));
476
477 num_tbs = iwl_tfd_get_num_tbs(tfd);
478
479 /* Each TFD can point to a maximum 20 Tx buffers */
480 if (num_tbs >= IWL_NUM_OF_TBS) {
481 IWL_ERR(priv, "Error can not send more than %d chunks\n",
482 IWL_NUM_OF_TBS);
483 return -EINVAL;
484 }
485
486 BUG_ON(addr & ~DMA_BIT_MASK(36));
487 if (unlikely(addr & ~IWL_TX_DMA_MASK))
488 IWL_ERR(priv, "Unaligned address = %llx\n",
489 (unsigned long long)addr);
490
491 iwl_tfd_set_tb(tfd, num_tbs, addr, len);
492
493 return 0;
494 }
495
496 /*
497 * Tell nic where to find circular buffer of Tx Frame Descriptors for
498 * given Tx queue, and enable the DMA channel used for that queue.
499 *
500 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
501 * channels supported in hardware.
502 */
503 int iwl_hw_tx_queue_init(struct iwl_priv *priv,
504 struct iwl_tx_queue *txq)
505 {
506 int txq_id = txq->q.id;
507
508 /* Circular buffer (TFD queue in DRAM) physical base address */
509 iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
510 txq->q.dma_addr >> 8);
511
512 return 0;
513 }
514
515 /******************************************************************************
516 *
517 * Generic RX handler implementations
518 *
519 ******************************************************************************/
520 static void iwl_rx_reply_alive(struct iwl_priv *priv,
521 struct iwl_rx_mem_buffer *rxb)
522 {
523 struct iwl_rx_packet *pkt = rxb_addr(rxb);
524 struct iwl_alive_resp *palive;
525 struct delayed_work *pwork;
526
527 palive = &pkt->u.alive_frame;
528
529 IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
530 "0x%01X 0x%01X\n",
531 palive->is_valid, palive->ver_type,
532 palive->ver_subtype);
533
534 if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
535 IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
536 memcpy(&priv->card_alive_init,
537 &pkt->u.alive_frame,
538 sizeof(struct iwl_init_alive_resp));
539 pwork = &priv->init_alive_start;
540 } else {
541 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
542 memcpy(&priv->card_alive, &pkt->u.alive_frame,
543 sizeof(struct iwl_alive_resp));
544 pwork = &priv->alive_start;
545 }
546
547 /* We delay the ALIVE response by 5ms to
548 * give the HW RF Kill time to activate... */
549 if (palive->is_valid == UCODE_VALID_OK)
550 queue_delayed_work(priv->workqueue, pwork,
551 msecs_to_jiffies(5));
552 else
553 IWL_WARN(priv, "uCode did not respond OK.\n");
554 }
555
556 static void iwl_bg_beacon_update(struct work_struct *work)
557 {
558 struct iwl_priv *priv =
559 container_of(work, struct iwl_priv, beacon_update);
560 struct sk_buff *beacon;
561
562 /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
563 beacon = ieee80211_beacon_get(priv->hw, priv->vif);
564
565 if (!beacon) {
566 IWL_ERR(priv, "update beacon failed\n");
567 return;
568 }
569
570 mutex_lock(&priv->mutex);
571 /* new beacon skb is allocated every time; dispose previous.*/
572 if (priv->ibss_beacon)
573 dev_kfree_skb(priv->ibss_beacon);
574
575 priv->ibss_beacon = beacon;
576 mutex_unlock(&priv->mutex);
577
578 iwl_send_beacon_cmd(priv);
579 }
580
581 /**
582 * iwl_bg_statistics_periodic - Timer callback to queue statistics
583 *
584 * This callback is provided in order to send a statistics request.
585 *
586 * This timer function is continually reset to execute within
587 * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
588 * was received. We need to ensure we receive the statistics in order
589 * to update the temperature used for calibrating the TXPOWER.
590 */
591 static void iwl_bg_statistics_periodic(unsigned long data)
592 {
593 struct iwl_priv *priv = (struct iwl_priv *)data;
594
595 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
596 return;
597
598 /* dont send host command if rf-kill is on */
599 if (!iwl_is_ready_rf(priv))
600 return;
601
602 iwl_send_statistics_request(priv, CMD_ASYNC);
603 }
604
605 static void iwl_rx_beacon_notif(struct iwl_priv *priv,
606 struct iwl_rx_mem_buffer *rxb)
607 {
608 #ifdef CONFIG_IWLWIFI_DEBUG
609 struct iwl_rx_packet *pkt = rxb_addr(rxb);
610 struct iwl4965_beacon_notif *beacon =
611 (struct iwl4965_beacon_notif *)pkt->u.raw;
612 u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
613
614 IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
615 "tsf %d %d rate %d\n",
616 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
617 beacon->beacon_notify_hdr.failure_frame,
618 le32_to_cpu(beacon->ibss_mgr_status),
619 le32_to_cpu(beacon->high_tsf),
620 le32_to_cpu(beacon->low_tsf), rate);
621 #endif
622
623 if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
624 (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
625 queue_work(priv->workqueue, &priv->beacon_update);
626 }
627
628 /* Handle notification from uCode that card's power state is changing
629 * due to software, hardware, or critical temperature RFKILL */
630 static void iwl_rx_card_state_notif(struct iwl_priv *priv,
631 struct iwl_rx_mem_buffer *rxb)
632 {
633 struct iwl_rx_packet *pkt = rxb_addr(rxb);
634 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
635 unsigned long status = priv->status;
636
637 IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n",
638 (flags & HW_CARD_DISABLED) ? "Kill" : "On",
639 (flags & SW_CARD_DISABLED) ? "Kill" : "On");
640
641 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
642 RF_CARD_DISABLED)) {
643
644 iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
645 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
646
647 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
648 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
649
650 if (!(flags & RXON_CARD_DISABLED)) {
651 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
652 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
653 iwl_write_direct32(priv, HBUS_TARG_MBX_C,
654 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
655 }
656 if (flags & RF_CARD_DISABLED)
657 iwl_tt_enter_ct_kill(priv);
658 }
659 if (!(flags & RF_CARD_DISABLED))
660 iwl_tt_exit_ct_kill(priv);
661
662 if (flags & HW_CARD_DISABLED)
663 set_bit(STATUS_RF_KILL_HW, &priv->status);
664 else
665 clear_bit(STATUS_RF_KILL_HW, &priv->status);
666
667
668 if (!(flags & RXON_CARD_DISABLED))
669 iwl_scan_cancel(priv);
670
671 if ((test_bit(STATUS_RF_KILL_HW, &status) !=
672 test_bit(STATUS_RF_KILL_HW, &priv->status)))
673 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
674 test_bit(STATUS_RF_KILL_HW, &priv->status));
675 else
676 wake_up_interruptible(&priv->wait_command_queue);
677 }
678
679 int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
680 {
681 if (src == IWL_PWR_SRC_VAUX) {
682 if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
683 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
684 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
685 ~APMG_PS_CTRL_MSK_PWR_SRC);
686 } else {
687 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
688 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
689 ~APMG_PS_CTRL_MSK_PWR_SRC);
690 }
691
692 return 0;
693 }
694
695 /**
696 * iwl_setup_rx_handlers - Initialize Rx handler callbacks
697 *
698 * Setup the RX handlers for each of the reply types sent from the uCode
699 * to the host.
700 *
701 * This function chains into the hardware specific files for them to setup
702 * any hardware specific handlers as well.
703 */
704 static void iwl_setup_rx_handlers(struct iwl_priv *priv)
705 {
706 priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
707 priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
708 priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
709 priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
710 priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
711 iwl_rx_pm_debug_statistics_notif;
712 priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
713
714 /*
715 * The same handler is used for both the REPLY to a discrete
716 * statistics request from the host as well as for the periodic
717 * statistics notifications (after received beacons) from the uCode.
718 */
719 priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_rx_statistics;
720 priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
721
722 iwl_setup_spectrum_handlers(priv);
723 iwl_setup_rx_scan_handlers(priv);
724
725 /* status change handler */
726 priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
727
728 priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
729 iwl_rx_missed_beacon_notif;
730 /* Rx handlers */
731 priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
732 priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
733 /* block ack */
734 priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
735 /* Set up hardware specific Rx handlers */
736 priv->cfg->ops->lib->rx_handler_setup(priv);
737 }
738
739 /**
740 * iwl_rx_handle - Main entry function for receiving responses from uCode
741 *
742 * Uses the priv->rx_handlers callback function array to invoke
743 * the appropriate handlers, including command responses,
744 * frame-received notifications, and other notifications.
745 */
746 void iwl_rx_handle(struct iwl_priv *priv)
747 {
748 struct iwl_rx_mem_buffer *rxb;
749 struct iwl_rx_packet *pkt;
750 struct iwl_rx_queue *rxq = &priv->rxq;
751 u32 r, i;
752 int reclaim;
753 unsigned long flags;
754 u8 fill_rx = 0;
755 u32 count = 8;
756 int total_empty;
757
758 /* uCode's read index (stored in shared DRAM) indicates the last Rx
759 * buffer that the driver may process (last buffer filled by ucode). */
760 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
761 i = rxq->read;
762
763 /* Rx interrupt, but nothing sent from uCode */
764 if (i == r)
765 IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
766
767 /* calculate total frames need to be restock after handling RX */
768 total_empty = r - rxq->write_actual;
769 if (total_empty < 0)
770 total_empty += RX_QUEUE_SIZE;
771
772 if (total_empty > (RX_QUEUE_SIZE / 2))
773 fill_rx = 1;
774
775 while (i != r) {
776 rxb = rxq->queue[i];
777
778 /* If an RXB doesn't have a Rx queue slot associated with it,
779 * then a bug has been introduced in the queue refilling
780 * routines -- catch it here */
781 BUG_ON(rxb == NULL);
782
783 rxq->queue[i] = NULL;
784
785 pci_unmap_page(priv->pci_dev, rxb->page_dma,
786 PAGE_SIZE << priv->hw_params.rx_page_order,
787 PCI_DMA_FROMDEVICE);
788 pkt = rxb_addr(rxb);
789
790 trace_iwlwifi_dev_rx(priv, pkt,
791 le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
792
793 /* Reclaim a command buffer only if this packet is a response
794 * to a (driver-originated) command.
795 * If the packet (e.g. Rx frame) originated from uCode,
796 * there is no command buffer to reclaim.
797 * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
798 * but apparently a few don't get set; catch them here. */
799 reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
800 (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
801 (pkt->hdr.cmd != REPLY_RX) &&
802 (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
803 (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
804 (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
805 (pkt->hdr.cmd != REPLY_TX);
806
807 /* Based on type of command response or notification,
808 * handle those that need handling via function in
809 * rx_handlers table. See iwl_setup_rx_handlers() */
810 if (priv->rx_handlers[pkt->hdr.cmd]) {
811 IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
812 i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
813 priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
814 priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
815 } else {
816 /* No handling needed */
817 IWL_DEBUG_RX(priv,
818 "r %d i %d No handler needed for %s, 0x%02x\n",
819 r, i, get_cmd_string(pkt->hdr.cmd),
820 pkt->hdr.cmd);
821 }
822
823 /*
824 * XXX: After here, we should always check rxb->page
825 * against NULL before touching it or its virtual
826 * memory (pkt). Because some rx_handler might have
827 * already taken or freed the pages.
828 */
829
830 if (reclaim) {
831 /* Invoke any callbacks, transfer the buffer to caller,
832 * and fire off the (possibly) blocking iwl_send_cmd()
833 * as we reclaim the driver command queue */
834 if (rxb->page)
835 iwl_tx_cmd_complete(priv, rxb);
836 else
837 IWL_WARN(priv, "Claim null rxb?\n");
838 }
839
840 /* Reuse the page if possible. For notification packets and
841 * SKBs that fail to Rx correctly, add them back into the
842 * rx_free list for reuse later. */
843 spin_lock_irqsave(&rxq->lock, flags);
844 if (rxb->page != NULL) {
845 rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
846 0, PAGE_SIZE << priv->hw_params.rx_page_order,
847 PCI_DMA_FROMDEVICE);
848 list_add_tail(&rxb->list, &rxq->rx_free);
849 rxq->free_count++;
850 } else
851 list_add_tail(&rxb->list, &rxq->rx_used);
852
853 spin_unlock_irqrestore(&rxq->lock, flags);
854
855 i = (i + 1) & RX_QUEUE_MASK;
856 /* If there are a lot of unused frames,
857 * restock the Rx queue so ucode wont assert. */
858 if (fill_rx) {
859 count++;
860 if (count >= 8) {
861 rxq->read = i;
862 iwl_rx_replenish_now(priv);
863 count = 0;
864 }
865 }
866 }
867
868 /* Backtrack one entry */
869 rxq->read = i;
870 if (fill_rx)
871 iwl_rx_replenish_now(priv);
872 else
873 iwl_rx_queue_restock(priv);
874 }
875
876 /* call this function to flush any scheduled tasklet */
877 static inline void iwl_synchronize_irq(struct iwl_priv *priv)
878 {
879 /* wait to make sure we flush pending tasklet*/
880 synchronize_irq(priv->pci_dev->irq);
881 tasklet_kill(&priv->irq_tasklet);
882 }
883
884 static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
885 {
886 u32 inta, handled = 0;
887 u32 inta_fh;
888 unsigned long flags;
889 u32 i;
890 #ifdef CONFIG_IWLWIFI_DEBUG
891 u32 inta_mask;
892 #endif
893
894 spin_lock_irqsave(&priv->lock, flags);
895
896 /* Ack/clear/reset pending uCode interrupts.
897 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
898 * and will clear only when CSR_FH_INT_STATUS gets cleared. */
899 inta = iwl_read32(priv, CSR_INT);
900 iwl_write32(priv, CSR_INT, inta);
901
902 /* Ack/clear/reset pending flow-handler (DMA) interrupts.
903 * Any new interrupts that happen after this, either while we're
904 * in this tasklet, or later, will show up in next ISR/tasklet. */
905 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
906 iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
907
908 #ifdef CONFIG_IWLWIFI_DEBUG
909 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
910 /* just for debug */
911 inta_mask = iwl_read32(priv, CSR_INT_MASK);
912 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
913 inta, inta_mask, inta_fh);
914 }
915 #endif
916
917 spin_unlock_irqrestore(&priv->lock, flags);
918
919 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
920 * atomic, make sure that inta covers all the interrupts that
921 * we've discovered, even if FH interrupt came in just after
922 * reading CSR_INT. */
923 if (inta_fh & CSR49_FH_INT_RX_MASK)
924 inta |= CSR_INT_BIT_FH_RX;
925 if (inta_fh & CSR49_FH_INT_TX_MASK)
926 inta |= CSR_INT_BIT_FH_TX;
927
928 /* Now service all interrupt bits discovered above. */
929 if (inta & CSR_INT_BIT_HW_ERR) {
930 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
931
932 /* Tell the device to stop sending interrupts */
933 iwl_disable_interrupts(priv);
934
935 priv->isr_stats.hw++;
936 iwl_irq_handle_error(priv);
937
938 handled |= CSR_INT_BIT_HW_ERR;
939
940 return;
941 }
942
943 #ifdef CONFIG_IWLWIFI_DEBUG
944 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
945 /* NIC fires this, but we don't use it, redundant with WAKEUP */
946 if (inta & CSR_INT_BIT_SCD) {
947 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
948 "the frame/frames.\n");
949 priv->isr_stats.sch++;
950 }
951
952 /* Alive notification via Rx interrupt will do the real work */
953 if (inta & CSR_INT_BIT_ALIVE) {
954 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
955 priv->isr_stats.alive++;
956 }
957 }
958 #endif
959 /* Safely ignore these bits for debug checks below */
960 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
961
962 /* HW RF KILL switch toggled */
963 if (inta & CSR_INT_BIT_RF_KILL) {
964 int hw_rf_kill = 0;
965 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
966 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
967 hw_rf_kill = 1;
968
969 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
970 hw_rf_kill ? "disable radio" : "enable radio");
971
972 priv->isr_stats.rfkill++;
973
974 /* driver only loads ucode once setting the interface up.
975 * the driver allows loading the ucode even if the radio
976 * is killed. Hence update the killswitch state here. The
977 * rfkill handler will care about restarting if needed.
978 */
979 if (!test_bit(STATUS_ALIVE, &priv->status)) {
980 if (hw_rf_kill)
981 set_bit(STATUS_RF_KILL_HW, &priv->status);
982 else
983 clear_bit(STATUS_RF_KILL_HW, &priv->status);
984 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
985 }
986
987 handled |= CSR_INT_BIT_RF_KILL;
988 }
989
990 /* Chip got too hot and stopped itself */
991 if (inta & CSR_INT_BIT_CT_KILL) {
992 IWL_ERR(priv, "Microcode CT kill error detected.\n");
993 priv->isr_stats.ctkill++;
994 handled |= CSR_INT_BIT_CT_KILL;
995 }
996
997 /* Error detected by uCode */
998 if (inta & CSR_INT_BIT_SW_ERR) {
999 IWL_ERR(priv, "Microcode SW error detected. "
1000 " Restarting 0x%X.\n", inta);
1001 priv->isr_stats.sw++;
1002 priv->isr_stats.sw_err = inta;
1003 iwl_irq_handle_error(priv);
1004 handled |= CSR_INT_BIT_SW_ERR;
1005 }
1006
1007 /*
1008 * uCode wakes up after power-down sleep.
1009 * Tell device about any new tx or host commands enqueued,
1010 * and about any Rx buffers made available while asleep.
1011 */
1012 if (inta & CSR_INT_BIT_WAKEUP) {
1013 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1014 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1015 for (i = 0; i < priv->hw_params.max_txq_num; i++)
1016 iwl_txq_update_write_ptr(priv, &priv->txq[i]);
1017 priv->isr_stats.wakeup++;
1018 handled |= CSR_INT_BIT_WAKEUP;
1019 }
1020
1021 /* All uCode command responses, including Tx command responses,
1022 * Rx "responses" (frame-received notification), and other
1023 * notifications from uCode come through here*/
1024 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1025 iwl_rx_handle(priv);
1026 priv->isr_stats.rx++;
1027 iwl_leds_background(priv);
1028 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1029 }
1030
1031 /* This "Tx" DMA channel is used only for loading uCode */
1032 if (inta & CSR_INT_BIT_FH_TX) {
1033 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1034 priv->isr_stats.tx++;
1035 handled |= CSR_INT_BIT_FH_TX;
1036 /* Wake up uCode load routine, now that load is complete */
1037 priv->ucode_write_complete = 1;
1038 wake_up_interruptible(&priv->wait_command_queue);
1039 }
1040
1041 if (inta & ~handled) {
1042 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1043 priv->isr_stats.unhandled++;
1044 }
1045
1046 if (inta & ~(priv->inta_mask)) {
1047 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1048 inta & ~priv->inta_mask);
1049 IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
1050 }
1051
1052 /* Re-enable all interrupts */
1053 /* only Re-enable if diabled by irq */
1054 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1055 iwl_enable_interrupts(priv);
1056
1057 #ifdef CONFIG_IWLWIFI_DEBUG
1058 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1059 inta = iwl_read32(priv, CSR_INT);
1060 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1061 inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
1062 IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
1063 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
1064 }
1065 #endif
1066 }
1067
1068 /* tasklet for iwlagn interrupt */
1069 static void iwl_irq_tasklet(struct iwl_priv *priv)
1070 {
1071 u32 inta = 0;
1072 u32 handled = 0;
1073 unsigned long flags;
1074 #ifdef CONFIG_IWLWIFI_DEBUG
1075 u32 inta_mask;
1076 #endif
1077
1078 spin_lock_irqsave(&priv->lock, flags);
1079
1080 /* Ack/clear/reset pending uCode interrupts.
1081 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
1082 */
1083 iwl_write32(priv, CSR_INT, priv->inta);
1084
1085 inta = priv->inta;
1086
1087 #ifdef CONFIG_IWLWIFI_DEBUG
1088 if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
1089 /* just for debug */
1090 inta_mask = iwl_read32(priv, CSR_INT_MASK);
1091 IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
1092 inta, inta_mask);
1093 }
1094 #endif
1095
1096 spin_unlock_irqrestore(&priv->lock, flags);
1097
1098 /* saved interrupt in inta variable now we can reset priv->inta */
1099 priv->inta = 0;
1100
1101 /* Now service all interrupt bits discovered above. */
1102 if (inta & CSR_INT_BIT_HW_ERR) {
1103 IWL_ERR(priv, "Hardware error detected. Restarting.\n");
1104
1105 /* Tell the device to stop sending interrupts */
1106 iwl_disable_interrupts(priv);
1107
1108 priv->isr_stats.hw++;
1109 iwl_irq_handle_error(priv);
1110
1111 handled |= CSR_INT_BIT_HW_ERR;
1112
1113 return;
1114 }
1115
1116 #ifdef CONFIG_IWLWIFI_DEBUG
1117 if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
1118 /* NIC fires this, but we don't use it, redundant with WAKEUP */
1119 if (inta & CSR_INT_BIT_SCD) {
1120 IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
1121 "the frame/frames.\n");
1122 priv->isr_stats.sch++;
1123 }
1124
1125 /* Alive notification via Rx interrupt will do the real work */
1126 if (inta & CSR_INT_BIT_ALIVE) {
1127 IWL_DEBUG_ISR(priv, "Alive interrupt\n");
1128 priv->isr_stats.alive++;
1129 }
1130 }
1131 #endif
1132 /* Safely ignore these bits for debug checks below */
1133 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
1134
1135 /* HW RF KILL switch toggled */
1136 if (inta & CSR_INT_BIT_RF_KILL) {
1137 int hw_rf_kill = 0;
1138 if (!(iwl_read32(priv, CSR_GP_CNTRL) &
1139 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
1140 hw_rf_kill = 1;
1141
1142 IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
1143 hw_rf_kill ? "disable radio" : "enable radio");
1144
1145 priv->isr_stats.rfkill++;
1146
1147 /* driver only loads ucode once setting the interface up.
1148 * the driver allows loading the ucode even if the radio
1149 * is killed. Hence update the killswitch state here. The
1150 * rfkill handler will care about restarting if needed.
1151 */
1152 if (!test_bit(STATUS_ALIVE, &priv->status)) {
1153 if (hw_rf_kill)
1154 set_bit(STATUS_RF_KILL_HW, &priv->status);
1155 else
1156 clear_bit(STATUS_RF_KILL_HW, &priv->status);
1157 wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
1158 }
1159
1160 handled |= CSR_INT_BIT_RF_KILL;
1161 }
1162
1163 /* Chip got too hot and stopped itself */
1164 if (inta & CSR_INT_BIT_CT_KILL) {
1165 IWL_ERR(priv, "Microcode CT kill error detected.\n");
1166 priv->isr_stats.ctkill++;
1167 handled |= CSR_INT_BIT_CT_KILL;
1168 }
1169
1170 /* Error detected by uCode */
1171 if (inta & CSR_INT_BIT_SW_ERR) {
1172 IWL_ERR(priv, "Microcode SW error detected. "
1173 " Restarting 0x%X.\n", inta);
1174 priv->isr_stats.sw++;
1175 priv->isr_stats.sw_err = inta;
1176 iwl_irq_handle_error(priv);
1177 handled |= CSR_INT_BIT_SW_ERR;
1178 }
1179
1180 /* uCode wakes up after power-down sleep */
1181 if (inta & CSR_INT_BIT_WAKEUP) {
1182 IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
1183 iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
1184 iwl_txq_update_write_ptr(priv, &priv->txq[0]);
1185 iwl_txq_update_write_ptr(priv, &priv->txq[1]);
1186 iwl_txq_update_write_ptr(priv, &priv->txq[2]);
1187 iwl_txq_update_write_ptr(priv, &priv->txq[3]);
1188 iwl_txq_update_write_ptr(priv, &priv->txq[4]);
1189 iwl_txq_update_write_ptr(priv, &priv->txq[5]);
1190
1191 priv->isr_stats.wakeup++;
1192
1193 handled |= CSR_INT_BIT_WAKEUP;
1194 }
1195
1196 /* All uCode command responses, including Tx command responses,
1197 * Rx "responses" (frame-received notification), and other
1198 * notifications from uCode come through here*/
1199 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
1200 CSR_INT_BIT_RX_PERIODIC)) {
1201 IWL_DEBUG_ISR(priv, "Rx interrupt\n");
1202 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
1203 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
1204 iwl_write32(priv, CSR_FH_INT_STATUS,
1205 CSR49_FH_INT_RX_MASK);
1206 }
1207 if (inta & CSR_INT_BIT_RX_PERIODIC) {
1208 handled |= CSR_INT_BIT_RX_PERIODIC;
1209 iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
1210 }
1211 /* Sending RX interrupt require many steps to be done in the
1212 * the device:
1213 * 1- write interrupt to current index in ICT table.
1214 * 2- dma RX frame.
1215 * 3- update RX shared data to indicate last write index.
1216 * 4- send interrupt.
1217 * This could lead to RX race, driver could receive RX interrupt
1218 * but the shared data changes does not reflect this.
1219 * this could lead to RX race, RX periodic will solve this race
1220 */
1221 iwl_write32(priv, CSR_INT_PERIODIC_REG,
1222 CSR_INT_PERIODIC_DIS);
1223 iwl_rx_handle(priv);
1224 /* Only set RX periodic if real RX is received. */
1225 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
1226 iwl_write32(priv, CSR_INT_PERIODIC_REG,
1227 CSR_INT_PERIODIC_ENA);
1228
1229 priv->isr_stats.rx++;
1230 iwl_leds_background(priv);
1231 }
1232
1233 /* This "Tx" DMA channel is used only for loading uCode */
1234 if (inta & CSR_INT_BIT_FH_TX) {
1235 iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
1236 IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
1237 priv->isr_stats.tx++;
1238 handled |= CSR_INT_BIT_FH_TX;
1239 /* Wake up uCode load routine, now that load is complete */
1240 priv->ucode_write_complete = 1;
1241 wake_up_interruptible(&priv->wait_command_queue);
1242 }
1243
1244 if (inta & ~handled) {
1245 IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
1246 priv->isr_stats.unhandled++;
1247 }
1248
1249 if (inta & ~(priv->inta_mask)) {
1250 IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
1251 inta & ~priv->inta_mask);
1252 }
1253
1254 /* Re-enable all interrupts */
1255 /* only Re-enable if diabled by irq */
1256 if (test_bit(STATUS_INT_ENABLED, &priv->status))
1257 iwl_enable_interrupts(priv);
1258 }
1259
1260
1261 /******************************************************************************
1262 *
1263 * uCode download functions
1264 *
1265 ******************************************************************************/
1266
1267 static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
1268 {
1269 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
1270 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
1271 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1272 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
1273 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1274 iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
1275 }
1276
1277 static void iwl_nic_start(struct iwl_priv *priv)
1278 {
1279 /* Remove all resets to allow NIC to operate */
1280 iwl_write32(priv, CSR_RESET, 0);
1281 }
1282
1283
1284 /**
1285 * iwl_read_ucode - Read uCode images from disk file.
1286 *
1287 * Copy into buffers for card to fetch via bus-mastering
1288 */
1289 static int iwl_read_ucode(struct iwl_priv *priv)
1290 {
1291 struct iwl_ucode_header *ucode;
1292 int ret = -EINVAL, index;
1293 const struct firmware *ucode_raw;
1294 const char *name_pre = priv->cfg->fw_name_pre;
1295 const unsigned int api_max = priv->cfg->ucode_api_max;
1296 const unsigned int api_min = priv->cfg->ucode_api_min;
1297 char buf[25];
1298 u8 *src;
1299 size_t len;
1300 u32 api_ver, build;
1301 u32 inst_size, data_size, init_size, init_data_size, boot_size;
1302 u16 eeprom_ver;
1303
1304 /* Ask kernel firmware_class module to get the boot firmware off disk.
1305 * request_firmware() is synchronous, file is in memory on return. */
1306 for (index = api_max; index >= api_min; index--) {
1307 sprintf(buf, "%s%d%s", name_pre, index, ".ucode");
1308 ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
1309 if (ret < 0) {
1310 IWL_ERR(priv, "%s firmware file req failed: %d\n",
1311 buf, ret);
1312 if (ret == -ENOENT)
1313 continue;
1314 else
1315 goto error;
1316 } else {
1317 if (index < api_max)
1318 IWL_ERR(priv, "Loaded firmware %s, "
1319 "which is deprecated. "
1320 "Please use API v%u instead.\n",
1321 buf, api_max);
1322
1323 IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n",
1324 buf, ucode_raw->size);
1325 break;
1326 }
1327 }
1328
1329 if (ret < 0)
1330 goto error;
1331
1332 /* Make sure that we got at least the v1 header! */
1333 if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
1334 IWL_ERR(priv, "File size way too small!\n");
1335 ret = -EINVAL;
1336 goto err_release;
1337 }
1338
1339 /* Data from ucode file: header followed by uCode images */
1340 ucode = (struct iwl_ucode_header *)ucode_raw->data;
1341
1342 priv->ucode_ver = le32_to_cpu(ucode->ver);
1343 api_ver = IWL_UCODE_API(priv->ucode_ver);
1344 build = priv->cfg->ops->ucode->get_build(ucode, api_ver);
1345 inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
1346 data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
1347 init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
1348 init_data_size =
1349 priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
1350 boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
1351 src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
1352
1353 /* api_ver should match the api version forming part of the
1354 * firmware filename ... but we don't check for that and only rely
1355 * on the API version read from firmware header from here on forward */
1356
1357 if (api_ver < api_min || api_ver > api_max) {
1358 IWL_ERR(priv, "Driver unable to support your firmware API. "
1359 "Driver supports v%u, firmware is v%u.\n",
1360 api_max, api_ver);
1361 priv->ucode_ver = 0;
1362 ret = -EINVAL;
1363 goto err_release;
1364 }
1365 if (api_ver != api_max)
1366 IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
1367 "got v%u. New firmware can be obtained "
1368 "from http://www.intellinuxwireless.org.\n",
1369 api_max, api_ver);
1370
1371 IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
1372 IWL_UCODE_MAJOR(priv->ucode_ver),
1373 IWL_UCODE_MINOR(priv->ucode_ver),
1374 IWL_UCODE_API(priv->ucode_ver),
1375 IWL_UCODE_SERIAL(priv->ucode_ver));
1376
1377 snprintf(priv->hw->wiphy->fw_version,
1378 sizeof(priv->hw->wiphy->fw_version),
1379 "%u.%u.%u.%u",
1380 IWL_UCODE_MAJOR(priv->ucode_ver),
1381 IWL_UCODE_MINOR(priv->ucode_ver),
1382 IWL_UCODE_API(priv->ucode_ver),
1383 IWL_UCODE_SERIAL(priv->ucode_ver));
1384
1385 if (build)
1386 IWL_DEBUG_INFO(priv, "Build %u\n", build);
1387
1388 eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
1389 IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n",
1390 (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
1391 ? "OTP" : "EEPROM", eeprom_ver);
1392
1393 IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
1394 priv->ucode_ver);
1395 IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
1396 inst_size);
1397 IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
1398 data_size);
1399 IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
1400 init_size);
1401 IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
1402 init_data_size);
1403 IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
1404 boot_size);
1405
1406 /* Verify size of file vs. image size info in file's header */
1407 if (ucode_raw->size !=
1408 priv->cfg->ops->ucode->get_header_size(api_ver) +
1409 inst_size + data_size + init_size +
1410 init_data_size + boot_size) {
1411
1412 IWL_DEBUG_INFO(priv,
1413 "uCode file size %d does not match expected size\n",
1414 (int)ucode_raw->size);
1415 ret = -EINVAL;
1416 goto err_release;
1417 }
1418
1419 /* Verify that uCode images will fit in card's SRAM */
1420 if (inst_size > priv->hw_params.max_inst_size) {
1421 IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
1422 inst_size);
1423 ret = -EINVAL;
1424 goto err_release;
1425 }
1426
1427 if (data_size > priv->hw_params.max_data_size) {
1428 IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
1429 data_size);
1430 ret = -EINVAL;
1431 goto err_release;
1432 }
1433 if (init_size > priv->hw_params.max_inst_size) {
1434 IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
1435 init_size);
1436 ret = -EINVAL;
1437 goto err_release;
1438 }
1439 if (init_data_size > priv->hw_params.max_data_size) {
1440 IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
1441 init_data_size);
1442 ret = -EINVAL;
1443 goto err_release;
1444 }
1445 if (boot_size > priv->hw_params.max_bsm_size) {
1446 IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
1447 boot_size);
1448 ret = -EINVAL;
1449 goto err_release;
1450 }
1451
1452 /* Allocate ucode buffers for card's bus-master loading ... */
1453
1454 /* Runtime instructions and 2 copies of data:
1455 * 1) unmodified from disk
1456 * 2) backup cache for save/restore during power-downs */
1457 priv->ucode_code.len = inst_size;
1458 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
1459
1460 priv->ucode_data.len = data_size;
1461 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
1462
1463 priv->ucode_data_backup.len = data_size;
1464 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
1465
1466 if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
1467 !priv->ucode_data_backup.v_addr)
1468 goto err_pci_alloc;
1469
1470 /* Initialization instructions and data */
1471 if (init_size && init_data_size) {
1472 priv->ucode_init.len = init_size;
1473 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
1474
1475 priv->ucode_init_data.len = init_data_size;
1476 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
1477
1478 if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
1479 goto err_pci_alloc;
1480 }
1481
1482 /* Bootstrap (instructions only, no data) */
1483 if (boot_size) {
1484 priv->ucode_boot.len = boot_size;
1485 iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
1486
1487 if (!priv->ucode_boot.v_addr)
1488 goto err_pci_alloc;
1489 }
1490
1491 /* Copy images into buffers for card's bus-master reads ... */
1492
1493 /* Runtime instructions (first block of data in file) */
1494 len = inst_size;
1495 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
1496 memcpy(priv->ucode_code.v_addr, src, len);
1497 src += len;
1498
1499 IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
1500 priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
1501
1502 /* Runtime data (2nd block)
1503 * NOTE: Copy into backup buffer will be done in iwl_up() */
1504 len = data_size;
1505 IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
1506 memcpy(priv->ucode_data.v_addr, src, len);
1507 memcpy(priv->ucode_data_backup.v_addr, src, len);
1508 src += len;
1509
1510 /* Initialization instructions (3rd block) */
1511 if (init_size) {
1512 len = init_size;
1513 IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
1514 len);
1515 memcpy(priv->ucode_init.v_addr, src, len);
1516 src += len;
1517 }
1518
1519 /* Initialization data (4th block) */
1520 if (init_data_size) {
1521 len = init_data_size;
1522 IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
1523 len);
1524 memcpy(priv->ucode_init_data.v_addr, src, len);
1525 src += len;
1526 }
1527
1528 /* Bootstrap instructions (5th block) */
1529 len = boot_size;
1530 IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
1531 memcpy(priv->ucode_boot.v_addr, src, len);
1532
1533 /* We have our copies now, allow OS release its copies */
1534 release_firmware(ucode_raw);
1535 return 0;
1536
1537 err_pci_alloc:
1538 IWL_ERR(priv, "failed to allocate pci memory\n");
1539 ret = -ENOMEM;
1540 iwl_dealloc_ucode_pci(priv);
1541
1542 err_release:
1543 release_firmware(ucode_raw);
1544
1545 error:
1546 return ret;
1547 }
1548
1549 #ifdef CONFIG_IWLWIFI_DEBUG
1550 static const char *desc_lookup_text[] = {
1551 "OK",
1552 "FAIL",
1553 "BAD_PARAM",
1554 "BAD_CHECKSUM",
1555 "NMI_INTERRUPT_WDG",
1556 "SYSASSERT",
1557 "FATAL_ERROR",
1558 "BAD_COMMAND",
1559 "HW_ERROR_TUNE_LOCK",
1560 "HW_ERROR_TEMPERATURE",
1561 "ILLEGAL_CHAN_FREQ",
1562 "VCC_NOT_STABLE",
1563 "FH_ERROR",
1564 "NMI_INTERRUPT_HOST",
1565 "NMI_INTERRUPT_ACTION_PT",
1566 "NMI_INTERRUPT_UNKNOWN",
1567 "UCODE_VERSION_MISMATCH",
1568 "HW_ERROR_ABS_LOCK",
1569 "HW_ERROR_CAL_LOCK_FAIL",
1570 "NMI_INTERRUPT_INST_ACTION_PT",
1571 "NMI_INTERRUPT_DATA_ACTION_PT",
1572 "NMI_TRM_HW_ER",
1573 "NMI_INTERRUPT_TRM",
1574 "NMI_INTERRUPT_BREAK_POINT"
1575 "DEBUG_0",
1576 "DEBUG_1",
1577 "DEBUG_2",
1578 "DEBUG_3",
1579 "UNKNOWN"
1580 };
1581
1582 static const char *desc_lookup(int i)
1583 {
1584 int max = ARRAY_SIZE(desc_lookup_text) - 1;
1585
1586 if (i < 0 || i > max)
1587 i = max;
1588
1589 return desc_lookup_text[i];
1590 }
1591
1592 #define ERROR_START_OFFSET (1 * sizeof(u32))
1593 #define ERROR_ELEM_SIZE (7 * sizeof(u32))
1594
1595 void iwl_dump_nic_error_log(struct iwl_priv *priv)
1596 {
1597 u32 data2, line;
1598 u32 desc, time, count, base, data1;
1599 u32 blink1, blink2, ilink1, ilink2;
1600
1601 if (priv->ucode_type == UCODE_INIT)
1602 base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
1603 else
1604 base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
1605
1606 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1607 IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
1608 return;
1609 }
1610
1611 count = iwl_read_targ_mem(priv, base);
1612
1613 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
1614 IWL_ERR(priv, "Start IWL Error Log Dump:\n");
1615 IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
1616 priv->status, count);
1617 }
1618
1619 desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
1620 blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
1621 blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
1622 ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
1623 ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
1624 data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
1625 data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
1626 line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
1627 time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
1628
1629 trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
1630 blink1, blink2, ilink1, ilink2);
1631
1632 IWL_ERR(priv, "Desc Time "
1633 "data1 data2 line\n");
1634 IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
1635 desc_lookup(desc), desc, time, data1, data2, line);
1636 IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
1637 IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
1638 ilink1, ilink2);
1639
1640 }
1641
1642 #define EVENT_START_OFFSET (4 * sizeof(u32))
1643
1644 /**
1645 * iwl_print_event_log - Dump error event log to syslog
1646 *
1647 */
1648 static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
1649 u32 num_events, u32 mode)
1650 {
1651 u32 i;
1652 u32 base; /* SRAM byte address of event log header */
1653 u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
1654 u32 ptr; /* SRAM byte address of log data */
1655 u32 ev, time, data; /* event log data */
1656
1657 if (num_events == 0)
1658 return;
1659 if (priv->ucode_type == UCODE_INIT)
1660 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1661 else
1662 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1663
1664 if (mode == 0)
1665 event_size = 2 * sizeof(u32);
1666 else
1667 event_size = 3 * sizeof(u32);
1668
1669 ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
1670
1671 /* "time" is actually "data" for mode 0 (no timestamp).
1672 * place event id # at far right for easier visual parsing. */
1673 for (i = 0; i < num_events; i++) {
1674 ev = iwl_read_targ_mem(priv, ptr);
1675 ptr += sizeof(u32);
1676 time = iwl_read_targ_mem(priv, ptr);
1677 ptr += sizeof(u32);
1678 if (mode == 0) {
1679 /* data, ev */
1680 trace_iwlwifi_dev_ucode_event(priv, 0, time, ev);
1681 IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", time, ev);
1682 } else {
1683 data = iwl_read_targ_mem(priv, ptr);
1684 ptr += sizeof(u32);
1685 IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
1686 time, data, ev);
1687 trace_iwlwifi_dev_ucode_event(priv, time, data, ev);
1688 }
1689 }
1690 }
1691
1692 void iwl_dump_nic_event_log(struct iwl_priv *priv)
1693 {
1694 u32 base; /* SRAM byte address of event log header */
1695 u32 capacity; /* event log capacity in # entries */
1696 u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
1697 u32 num_wraps; /* # times uCode wrapped to top of log */
1698 u32 next_entry; /* index of next entry to be written by uCode */
1699 u32 size; /* # entries that we'll print */
1700
1701 if (priv->ucode_type == UCODE_INIT)
1702 base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
1703 else
1704 base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
1705
1706 if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
1707 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
1708 return;
1709 }
1710
1711 /* event log header */
1712 capacity = iwl_read_targ_mem(priv, base);
1713 mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
1714 num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
1715 next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
1716
1717 size = num_wraps ? capacity : next_entry;
1718
1719 /* bail out if nothing in log */
1720 if (size == 0) {
1721 IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
1722 return;
1723 }
1724
1725 IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
1726 size, num_wraps);
1727
1728 /* if uCode has wrapped back to top of log, start at the oldest entry,
1729 * i.e the next one that uCode would fill. */
1730 if (num_wraps)
1731 iwl_print_event_log(priv, next_entry,
1732 capacity - next_entry, mode);
1733 /* (then/else) start at top of log */
1734 iwl_print_event_log(priv, 0, next_entry, mode);
1735
1736 }
1737 #endif
1738
1739 /**
1740 * iwl_alive_start - called after REPLY_ALIVE notification received
1741 * from protocol/runtime uCode (initialization uCode's
1742 * Alive gets handled by iwl_init_alive_start()).
1743 */
1744 static void iwl_alive_start(struct iwl_priv *priv)
1745 {
1746 int ret = 0;
1747
1748 IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
1749
1750 if (priv->card_alive.is_valid != UCODE_VALID_OK) {
1751 /* We had an error bringing up the hardware, so take it
1752 * all the way back down so we can try again */
1753 IWL_DEBUG_INFO(priv, "Alive failed.\n");
1754 goto restart;
1755 }
1756
1757 /* Initialize uCode has loaded Runtime uCode ... verify inst image.
1758 * This is a paranoid check, because we would not have gotten the
1759 * "runtime" alive if code weren't properly loaded. */
1760 if (iwl_verify_ucode(priv)) {
1761 /* Runtime instruction load was bad;
1762 * take it all the way back down so we can try again */
1763 IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
1764 goto restart;
1765 }
1766
1767 iwl_clear_stations_table(priv);
1768 ret = priv->cfg->ops->lib->alive_notify(priv);
1769 if (ret) {
1770 IWL_WARN(priv,
1771 "Could not complete ALIVE transition [ntf]: %d\n", ret);
1772 goto restart;
1773 }
1774
1775 /* After the ALIVE response, we can send host commands to the uCode */
1776 set_bit(STATUS_ALIVE, &priv->status);
1777
1778 if (iwl_is_rfkill(priv))
1779 return;
1780
1781 ieee80211_wake_queues(priv->hw);
1782
1783 priv->active_rate = priv->rates_mask;
1784 priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
1785
1786 /* Configure Tx antenna selection based on H/W config */
1787 if (priv->cfg->ops->hcmd->set_tx_ant)
1788 priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
1789
1790 if (iwl_is_associated(priv)) {
1791 struct iwl_rxon_cmd *active_rxon =
1792 (struct iwl_rxon_cmd *)&priv->active_rxon;
1793 /* apply any changes in staging */
1794 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
1795 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
1796 } else {
1797 /* Initialize our rx_config data */
1798 iwl_connection_init_rx_config(priv, priv->iw_mode);
1799
1800 if (priv->cfg->ops->hcmd->set_rxon_chain)
1801 priv->cfg->ops->hcmd->set_rxon_chain(priv);
1802
1803 memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
1804 }
1805
1806 /* Configure Bluetooth device coexistence support */
1807 iwl_send_bt_config(priv);
1808
1809 iwl_reset_run_time_calib(priv);
1810
1811 /* Configure the adapter for unassociated operation */
1812 iwlcore_commit_rxon(priv);
1813
1814 /* At this point, the NIC is initialized and operational */
1815 iwl_rf_kill_ct_config(priv);
1816
1817 iwl_leds_init(priv);
1818
1819 IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
1820 set_bit(STATUS_READY, &priv->status);
1821 wake_up_interruptible(&priv->wait_command_queue);
1822
1823 iwl_power_update_mode(priv, true);
1824
1825 /* reassociate for ADHOC mode */
1826 if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
1827 struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
1828 priv->vif);
1829 if (beacon)
1830 iwl_mac_beacon_update(priv->hw, beacon);
1831 }
1832
1833
1834 if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
1835 iwl_set_mode(priv, priv->iw_mode);
1836
1837 return;
1838
1839 restart:
1840 queue_work(priv->workqueue, &priv->restart);
1841 }
1842
1843 static void iwl_cancel_deferred_work(struct iwl_priv *priv);
1844
1845 static void __iwl_down(struct iwl_priv *priv)
1846 {
1847 unsigned long flags;
1848 int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
1849
1850 IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
1851
1852 if (!exit_pending)
1853 set_bit(STATUS_EXIT_PENDING, &priv->status);
1854
1855 iwl_clear_stations_table(priv);
1856
1857 /* Unblock any waiting calls */
1858 wake_up_interruptible_all(&priv->wait_command_queue);
1859
1860 /* Wipe out the EXIT_PENDING status bit if we are not actually
1861 * exiting the module */
1862 if (!exit_pending)
1863 clear_bit(STATUS_EXIT_PENDING, &priv->status);
1864
1865 /* stop and reset the on-board processor */
1866 iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
1867
1868 /* tell the device to stop sending interrupts */
1869 spin_lock_irqsave(&priv->lock, flags);
1870 iwl_disable_interrupts(priv);
1871 spin_unlock_irqrestore(&priv->lock, flags);
1872 iwl_synchronize_irq(priv);
1873
1874 if (priv->mac80211_registered)
1875 ieee80211_stop_queues(priv->hw);
1876
1877 /* If we have not previously called iwl_init() then
1878 * clear all bits but the RF Kill bit and return */
1879 if (!iwl_is_init(priv)) {
1880 priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
1881 STATUS_RF_KILL_HW |
1882 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
1883 STATUS_GEO_CONFIGURED |
1884 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
1885 STATUS_EXIT_PENDING;
1886 goto exit;
1887 }
1888
1889 /* ...otherwise clear out all the status bits but the RF Kill
1890 * bit and continue taking the NIC down. */
1891 priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
1892 STATUS_RF_KILL_HW |
1893 test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
1894 STATUS_GEO_CONFIGURED |
1895 test_bit(STATUS_FW_ERROR, &priv->status) <<
1896 STATUS_FW_ERROR |
1897 test_bit(STATUS_EXIT_PENDING, &priv->status) <<
1898 STATUS_EXIT_PENDING;
1899
1900 /* device going down, Stop using ICT table */
1901 iwl_disable_ict(priv);
1902 spin_lock_irqsave(&priv->lock, flags);
1903 iwl_clear_bit(priv, CSR_GP_CNTRL,
1904 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
1905 spin_unlock_irqrestore(&priv->lock, flags);
1906
1907 iwl_txq_ctx_stop(priv);
1908 iwl_rxq_stop(priv);
1909
1910 iwl_write_prph(priv, APMG_CLK_DIS_REG,
1911 APMG_CLK_VAL_DMA_CLK_RQT);
1912
1913 udelay(5);
1914
1915 /* Stop the device, and put it in low power state */
1916 priv->cfg->ops->lib->apm_ops.stop(priv);
1917
1918 exit:
1919 memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
1920
1921 if (priv->ibss_beacon)
1922 dev_kfree_skb(priv->ibss_beacon);
1923 priv->ibss_beacon = NULL;
1924
1925 /* clear out any free frames */
1926 iwl_clear_free_frames(priv);
1927 }
1928
1929 static void iwl_down(struct iwl_priv *priv)
1930 {
1931 mutex_lock(&priv->mutex);
1932 __iwl_down(priv);
1933 mutex_unlock(&priv->mutex);
1934
1935 iwl_cancel_deferred_work(priv);
1936 }
1937
1938 #define HW_READY_TIMEOUT (50)
1939
1940 static int iwl_set_hw_ready(struct iwl_priv *priv)
1941 {
1942 int ret = 0;
1943
1944 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1945 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
1946
1947 /* See if we got it */
1948 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
1949 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
1950 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
1951 HW_READY_TIMEOUT);
1952 if (ret != -ETIMEDOUT)
1953 priv->hw_ready = true;
1954 else
1955 priv->hw_ready = false;
1956
1957 IWL_DEBUG_INFO(priv, "hardware %s\n",
1958 (priv->hw_ready == 1) ? "ready" : "not ready");
1959 return ret;
1960 }
1961
1962 static int iwl_prepare_card_hw(struct iwl_priv *priv)
1963 {
1964 int ret = 0;
1965
1966 IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n");
1967
1968 ret = iwl_set_hw_ready(priv);
1969 if (priv->hw_ready)
1970 return ret;
1971
1972 /* If HW is not ready, prepare the conditions to check again */
1973 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
1974 CSR_HW_IF_CONFIG_REG_PREPARE);
1975
1976 ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
1977 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
1978 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
1979
1980 /* HW should be ready by now, check again. */
1981 if (ret != -ETIMEDOUT)
1982 iwl_set_hw_ready(priv);
1983
1984 return ret;
1985 }
1986
1987 #define MAX_HW_RESTARTS 5
1988
1989 static int __iwl_up(struct iwl_priv *priv)
1990 {
1991 int i;
1992 int ret;
1993
1994 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
1995 IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
1996 return -EIO;
1997 }
1998
1999 if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
2000 IWL_ERR(priv, "ucode not available for device bringup\n");
2001 return -EIO;
2002 }
2003
2004 iwl_prepare_card_hw(priv);
2005
2006 if (!priv->hw_ready) {
2007 IWL_WARN(priv, "Exit HW not ready\n");
2008 return -EIO;
2009 }
2010
2011 /* If platform's RF_KILL switch is NOT set to KILL */
2012 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
2013 clear_bit(STATUS_RF_KILL_HW, &priv->status);
2014 else
2015 set_bit(STATUS_RF_KILL_HW, &priv->status);
2016
2017 if (iwl_is_rfkill(priv)) {
2018 wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
2019
2020 iwl_enable_interrupts(priv);
2021 IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
2022 return 0;
2023 }
2024
2025 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2026
2027 ret = iwl_hw_nic_init(priv);
2028 if (ret) {
2029 IWL_ERR(priv, "Unable to init nic\n");
2030 return ret;
2031 }
2032
2033 /* make sure rfkill handshake bits are cleared */
2034 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2035 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
2036 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
2037
2038 /* clear (again), then enable host interrupts */
2039 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2040 iwl_enable_interrupts(priv);
2041
2042 /* really make sure rfkill handshake bits are cleared */
2043 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2044 iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
2045
2046 /* Copy original ucode data image from disk into backup cache.
2047 * This will be used to initialize the on-board processor's
2048 * data SRAM for a clean start when the runtime program first loads. */
2049 memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
2050 priv->ucode_data.len);
2051
2052 for (i = 0; i < MAX_HW_RESTARTS; i++) {
2053
2054 iwl_clear_stations_table(priv);
2055
2056 /* load bootstrap state machine,
2057 * load bootstrap program into processor's memory,
2058 * prepare to load the "initialize" uCode */
2059 ret = priv->cfg->ops->lib->load_ucode(priv);
2060
2061 if (ret) {
2062 IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
2063 ret);
2064 continue;
2065 }
2066
2067 /* start card; "initialize" will load runtime ucode */
2068 iwl_nic_start(priv);
2069
2070 IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
2071
2072 return 0;
2073 }
2074
2075 set_bit(STATUS_EXIT_PENDING, &priv->status);
2076 __iwl_down(priv);
2077 clear_bit(STATUS_EXIT_PENDING, &priv->status);
2078
2079 /* tried to restart and config the device for as long as our
2080 * patience could withstand */
2081 IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
2082 return -EIO;
2083 }
2084
2085
2086 /*****************************************************************************
2087 *
2088 * Workqueue callbacks
2089 *
2090 *****************************************************************************/
2091
2092 static void iwl_bg_init_alive_start(struct work_struct *data)
2093 {
2094 struct iwl_priv *priv =
2095 container_of(data, struct iwl_priv, init_alive_start.work);
2096
2097 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2098 return;
2099
2100 mutex_lock(&priv->mutex);
2101 priv->cfg->ops->lib->init_alive_start(priv);
2102 mutex_unlock(&priv->mutex);
2103 }
2104
2105 static void iwl_bg_alive_start(struct work_struct *data)
2106 {
2107 struct iwl_priv *priv =
2108 container_of(data, struct iwl_priv, alive_start.work);
2109
2110 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2111 return;
2112
2113 /* enable dram interrupt */
2114 iwl_reset_ict(priv);
2115
2116 mutex_lock(&priv->mutex);
2117 iwl_alive_start(priv);
2118 mutex_unlock(&priv->mutex);
2119 }
2120
2121 static void iwl_bg_run_time_calib_work(struct work_struct *work)
2122 {
2123 struct iwl_priv *priv = container_of(work, struct iwl_priv,
2124 run_time_calib_work);
2125
2126 mutex_lock(&priv->mutex);
2127
2128 if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
2129 test_bit(STATUS_SCANNING, &priv->status)) {
2130 mutex_unlock(&priv->mutex);
2131 return;
2132 }
2133
2134 if (priv->start_calib) {
2135 iwl_chain_noise_calibration(priv, &priv->statistics);
2136
2137 iwl_sensitivity_calibration(priv, &priv->statistics);
2138 }
2139
2140 mutex_unlock(&priv->mutex);
2141 return;
2142 }
2143
2144 static void iwl_bg_up(struct work_struct *data)
2145 {
2146 struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
2147
2148 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2149 return;
2150
2151 mutex_lock(&priv->mutex);
2152 __iwl_up(priv);
2153 mutex_unlock(&priv->mutex);
2154 }
2155
2156 static void iwl_bg_restart(struct work_struct *data)
2157 {
2158 struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
2159
2160 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2161 return;
2162
2163 if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
2164 mutex_lock(&priv->mutex);
2165 priv->vif = NULL;
2166 priv->is_open = 0;
2167 mutex_unlock(&priv->mutex);
2168 iwl_down(priv);
2169 ieee80211_restart_hw(priv->hw);
2170 } else {
2171 iwl_down(priv);
2172 queue_work(priv->workqueue, &priv->up);
2173 }
2174 }
2175
2176 static void iwl_bg_rx_replenish(struct work_struct *data)
2177 {
2178 struct iwl_priv *priv =
2179 container_of(data, struct iwl_priv, rx_replenish);
2180
2181 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2182 return;
2183
2184 mutex_lock(&priv->mutex);
2185 iwl_rx_replenish(priv);
2186 mutex_unlock(&priv->mutex);
2187 }
2188
2189 #define IWL_DELAY_NEXT_SCAN (HZ*2)
2190
2191 void iwl_post_associate(struct iwl_priv *priv)
2192 {
2193 struct ieee80211_conf *conf = NULL;
2194 int ret = 0;
2195 unsigned long flags;
2196
2197 if (priv->iw_mode == NL80211_IFTYPE_AP) {
2198 IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
2199 return;
2200 }
2201
2202 IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
2203 priv->assoc_id, priv->active_rxon.bssid_addr);
2204
2205
2206 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2207 return;
2208
2209
2210 if (!priv->vif || !priv->is_open)
2211 return;
2212
2213 iwl_scan_cancel_timeout(priv, 200);
2214
2215 conf = ieee80211_get_hw_conf(priv->hw);
2216
2217 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2218 iwlcore_commit_rxon(priv);
2219
2220 iwl_setup_rxon_timing(priv);
2221 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
2222 sizeof(priv->rxon_timing), &priv->rxon_timing);
2223 if (ret)
2224 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
2225 "Attempting to continue.\n");
2226
2227 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
2228
2229 iwl_set_rxon_ht(priv, &priv->current_ht_config);
2230
2231 if (priv->cfg->ops->hcmd->set_rxon_chain)
2232 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2233
2234 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2235
2236 IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
2237 priv->assoc_id, priv->beacon_int);
2238
2239 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2240 priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
2241 else
2242 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
2243
2244 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2245 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
2246 priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
2247 else
2248 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2249
2250 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
2251 priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
2252
2253 }
2254
2255 iwlcore_commit_rxon(priv);
2256
2257 switch (priv->iw_mode) {
2258 case NL80211_IFTYPE_STATION:
2259 break;
2260
2261 case NL80211_IFTYPE_ADHOC:
2262
2263 /* assume default assoc id */
2264 priv->assoc_id = 1;
2265
2266 iwl_rxon_add_station(priv, priv->bssid, 0);
2267 iwl_send_beacon_cmd(priv);
2268
2269 break;
2270
2271 default:
2272 IWL_ERR(priv, "%s Should not be called in %d mode\n",
2273 __func__, priv->iw_mode);
2274 break;
2275 }
2276
2277 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
2278 priv->assoc_station_added = 1;
2279
2280 spin_lock_irqsave(&priv->lock, flags);
2281 iwl_activate_qos(priv, 0);
2282 spin_unlock_irqrestore(&priv->lock, flags);
2283
2284 /* the chain noise calibration will enabled PM upon completion
2285 * If chain noise has already been run, then we need to enable
2286 * power management here */
2287 if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
2288 iwl_power_update_mode(priv, false);
2289
2290 /* Enable Rx differential gain and sensitivity calibrations */
2291 iwl_chain_noise_reset(priv);
2292 priv->start_calib = 1;
2293
2294 }
2295
2296 /*****************************************************************************
2297 *
2298 * mac80211 entry point functions
2299 *
2300 *****************************************************************************/
2301
2302 #define UCODE_READY_TIMEOUT (4 * HZ)
2303
2304 /*
2305 * Not a mac80211 entry point function, but it fits in with all the
2306 * other mac80211 functions grouped here.
2307 */
2308 static int iwl_setup_mac(struct iwl_priv *priv)
2309 {
2310 int ret;
2311 struct ieee80211_hw *hw = priv->hw;
2312 hw->rate_control_algorithm = "iwl-agn-rs";
2313
2314 /* Tell mac80211 our characteristics */
2315 hw->flags = IEEE80211_HW_SIGNAL_DBM |
2316 IEEE80211_HW_NOISE_DBM |
2317 IEEE80211_HW_AMPDU_AGGREGATION |
2318 IEEE80211_HW_SPECTRUM_MGMT;
2319
2320 if (!priv->cfg->broken_powersave)
2321 hw->flags |= IEEE80211_HW_SUPPORTS_PS |
2322 IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
2323
2324 hw->sta_data_size = sizeof(struct iwl_station_priv);
2325 hw->wiphy->interface_modes =
2326 BIT(NL80211_IFTYPE_STATION) |
2327 BIT(NL80211_IFTYPE_ADHOC);
2328
2329 hw->wiphy->custom_regulatory = true;
2330
2331 /* Firmware does not support this */
2332 hw->wiphy->disable_beacon_hints = true;
2333
2334 /*
2335 * For now, disable PS by default because it affects
2336 * RX performance significantly.
2337 */
2338 hw->wiphy->ps_default = false;
2339
2340 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
2341 /* we create the 802.11 header and a zero-length SSID element */
2342 hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
2343
2344 /* Default value; 4 EDCA QOS priorities */
2345 hw->queues = 4;
2346
2347 hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
2348
2349 if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
2350 priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
2351 &priv->bands[IEEE80211_BAND_2GHZ];
2352 if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
2353 priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
2354 &priv->bands[IEEE80211_BAND_5GHZ];
2355
2356 ret = ieee80211_register_hw(priv->hw);
2357 if (ret) {
2358 IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
2359 return ret;
2360 }
2361 priv->mac80211_registered = 1;
2362
2363 return 0;
2364 }
2365
2366
2367 static int iwl_mac_start(struct ieee80211_hw *hw)
2368 {
2369 struct iwl_priv *priv = hw->priv;
2370 int ret;
2371
2372 IWL_DEBUG_MAC80211(priv, "enter\n");
2373
2374 /* we should be verifying the device is ready to be opened */
2375 mutex_lock(&priv->mutex);
2376
2377 /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
2378 * ucode filename and max sizes are card-specific. */
2379
2380 if (!priv->ucode_code.len) {
2381 ret = iwl_read_ucode(priv);
2382 if (ret) {
2383 IWL_ERR(priv, "Could not read microcode: %d\n", ret);
2384 mutex_unlock(&priv->mutex);
2385 return ret;
2386 }
2387 }
2388
2389 ret = __iwl_up(priv);
2390
2391 mutex_unlock(&priv->mutex);
2392
2393 if (ret)
2394 return ret;
2395
2396 if (iwl_is_rfkill(priv))
2397 goto out;
2398
2399 IWL_DEBUG_INFO(priv, "Start UP work done.\n");
2400
2401 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
2402 * mac80211 will not be run successfully. */
2403 ret = wait_event_interruptible_timeout(priv->wait_command_queue,
2404 test_bit(STATUS_READY, &priv->status),
2405 UCODE_READY_TIMEOUT);
2406 if (!ret) {
2407 if (!test_bit(STATUS_READY, &priv->status)) {
2408 IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
2409 jiffies_to_msecs(UCODE_READY_TIMEOUT));
2410 return -ETIMEDOUT;
2411 }
2412 }
2413
2414 iwl_led_start(priv);
2415
2416 out:
2417 priv->is_open = 1;
2418 IWL_DEBUG_MAC80211(priv, "leave\n");
2419 return 0;
2420 }
2421
2422 static void iwl_mac_stop(struct ieee80211_hw *hw)
2423 {
2424 struct iwl_priv *priv = hw->priv;
2425
2426 IWL_DEBUG_MAC80211(priv, "enter\n");
2427
2428 if (!priv->is_open)
2429 return;
2430
2431 priv->is_open = 0;
2432
2433 if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
2434 /* stop mac, cancel any scan request and clear
2435 * RXON_FILTER_ASSOC_MSK BIT
2436 */
2437 mutex_lock(&priv->mutex);
2438 iwl_scan_cancel_timeout(priv, 100);
2439 mutex_unlock(&priv->mutex);
2440 }
2441
2442 iwl_down(priv);
2443
2444 flush_workqueue(priv->workqueue);
2445
2446 /* enable interrupts again in order to receive rfkill changes */
2447 iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
2448 iwl_enable_interrupts(priv);
2449
2450 IWL_DEBUG_MAC80211(priv, "leave\n");
2451 }
2452
2453 static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
2454 {
2455 struct iwl_priv *priv = hw->priv;
2456
2457 IWL_DEBUG_MACDUMP(priv, "enter\n");
2458
2459 IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
2460 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
2461
2462 if (iwl_tx_skb(priv, skb))
2463 dev_kfree_skb_any(skb);
2464
2465 IWL_DEBUG_MACDUMP(priv, "leave\n");
2466 return NETDEV_TX_OK;
2467 }
2468
2469 void iwl_config_ap(struct iwl_priv *priv)
2470 {
2471 int ret = 0;
2472 unsigned long flags;
2473
2474 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2475 return;
2476
2477 /* The following should be done only at AP bring up */
2478 if (!iwl_is_associated(priv)) {
2479
2480 /* RXON - unassoc (to set timing command) */
2481 priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
2482 iwlcore_commit_rxon(priv);
2483
2484 /* RXON Timing */
2485 iwl_setup_rxon_timing(priv);
2486 ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
2487 sizeof(priv->rxon_timing), &priv->rxon_timing);
2488 if (ret)
2489 IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
2490 "Attempting to continue.\n");
2491
2492 if (priv->cfg->ops->hcmd->set_rxon_chain)
2493 priv->cfg->ops->hcmd->set_rxon_chain(priv);
2494
2495 /* FIXME: what should be the assoc_id for AP? */
2496 priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
2497 if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
2498 priv->staging_rxon.flags |=
2499 RXON_FLG_SHORT_PREAMBLE_MSK;
2500 else
2501 priv->staging_rxon.flags &=
2502 ~RXON_FLG_SHORT_PREAMBLE_MSK;
2503
2504 if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
2505 if (priv->assoc_capability &
2506 WLAN_CAPABILITY_SHORT_SLOT_TIME)
2507 priv->staging_rxon.flags |=
2508 RXON_FLG_SHORT_SLOT_MSK;
2509 else
2510 priv->staging_rxon.flags &=
2511 ~RXON_FLG_SHORT_SLOT_MSK;
2512
2513 if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
2514 priv->staging_rxon.flags &=
2515 ~RXON_FLG_SHORT_SLOT_MSK;
2516 }
2517 /* restore RXON assoc */
2518 priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
2519 iwlcore_commit_rxon(priv);
2520 spin_lock_irqsave(&priv->lock, flags);
2521 iwl_activate_qos(priv, 1);
2522 spin_unlock_irqrestore(&priv->lock, flags);
2523 iwl_add_bcast_station(priv);
2524 }
2525 iwl_send_beacon_cmd(priv);
2526
2527 /* FIXME - we need to add code here to detect a totally new
2528 * configuration, reset the AP, unassoc, rxon timing, assoc,
2529 * clear sta table, add BCAST sta... */
2530 }
2531
2532 static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
2533 struct ieee80211_key_conf *keyconf, const u8 *addr,
2534 u32 iv32, u16 *phase1key)
2535 {
2536
2537 struct iwl_priv *priv = hw->priv;
2538 IWL_DEBUG_MAC80211(priv, "enter\n");
2539
2540 iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key);
2541
2542 IWL_DEBUG_MAC80211(priv, "leave\n");
2543 }
2544
2545 static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
2546 struct ieee80211_vif *vif,
2547 struct ieee80211_sta *sta,
2548 struct ieee80211_key_conf *key)
2549 {
2550 struct iwl_priv *priv = hw->priv;
2551 const u8 *addr;
2552 int ret;
2553 u8 sta_id;
2554 bool is_default_wep_key = false;
2555
2556 IWL_DEBUG_MAC80211(priv, "enter\n");
2557
2558 if (priv->cfg->mod_params->sw_crypto) {
2559 IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
2560 return -EOPNOTSUPP;
2561 }
2562 addr = sta ? sta->addr : iwl_bcast_addr;
2563 sta_id = iwl_find_station(priv, addr);
2564 if (sta_id == IWL_INVALID_STATION) {
2565 IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
2566 addr);
2567 return -EINVAL;
2568
2569 }
2570
2571 mutex_lock(&priv->mutex);
2572 iwl_scan_cancel_timeout(priv, 100);
2573 mutex_unlock(&priv->mutex);
2574
2575 /* If we are getting WEP group key and we didn't receive any key mapping
2576 * so far, we are in legacy wep mode (group key only), otherwise we are
2577 * in 1X mode.
2578 * In legacy wep mode, we use another host command to the uCode */
2579 if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
2580 priv->iw_mode != NL80211_IFTYPE_AP) {
2581 if (cmd == SET_KEY)
2582 is_default_wep_key = !priv->key_mapping_key;
2583 else
2584 is_default_wep_key =
2585 (key->hw_key_idx == HW_KEY_DEFAULT);
2586 }
2587
2588 switch (cmd) {
2589 case SET_KEY:
2590 if (is_default_wep_key)
2591 ret = iwl_set_default_wep_key(priv, key);
2592 else
2593 ret = iwl_set_dynamic_key(priv, key, sta_id);
2594
2595 IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
2596 break;
2597 case DISABLE_KEY:
2598 if (is_default_wep_key)
2599 ret = iwl_remove_default_wep_key(priv, key);
2600 else
2601 ret = iwl_remove_dynamic_key(priv, key, sta_id);
2602
2603 IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
2604 break;
2605 default:
2606 ret = -EINVAL;
2607 }
2608
2609 IWL_DEBUG_MAC80211(priv, "leave\n");
2610
2611 return ret;
2612 }
2613
2614 static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
2615 enum ieee80211_ampdu_mlme_action action,
2616 struct ieee80211_sta *sta, u16 tid, u16 *ssn)
2617 {
2618 struct iwl_priv *priv = hw->priv;
2619 int ret;
2620
2621 IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
2622 sta->addr, tid);
2623
2624 if (!(priv->cfg->sku & IWL_SKU_N))
2625 return -EACCES;
2626
2627 switch (action) {
2628 case IEEE80211_AMPDU_RX_START:
2629 IWL_DEBUG_HT(priv, "start Rx\n");
2630 return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
2631 case IEEE80211_AMPDU_RX_STOP:
2632 IWL_DEBUG_HT(priv, "stop Rx\n");
2633 ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
2634 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2635 return 0;
2636 else
2637 return ret;
2638 case IEEE80211_AMPDU_TX_START:
2639 IWL_DEBUG_HT(priv, "start Tx\n");
2640 return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
2641 case IEEE80211_AMPDU_TX_STOP:
2642 IWL_DEBUG_HT(priv, "stop Tx\n");
2643 ret = iwl_tx_agg_stop(priv, sta->addr, tid);
2644 if (test_bit(STATUS_EXIT_PENDING, &priv->status))
2645 return 0;
2646 else
2647 return ret;
2648 default:
2649 IWL_DEBUG_HT(priv, "unknown\n");
2650 return -EINVAL;
2651 break;
2652 }
2653 return 0;
2654 }
2655
2656 static int iwl_mac_get_stats(struct ieee80211_hw *hw,
2657 struct ieee80211_low_level_stats *stats)
2658 {
2659 struct iwl_priv *priv = hw->priv;
2660
2661 priv = hw->priv;
2662 IWL_DEBUG_MAC80211(priv, "enter\n");
2663 IWL_DEBUG_MAC80211(priv, "leave\n");
2664
2665 return 0;
2666 }
2667
2668 /*****************************************************************************
2669 *
2670 * sysfs attributes
2671 *
2672 *****************************************************************************/
2673
2674 #ifdef CONFIG_IWLWIFI_DEBUG
2675
2676 /*
2677 * The following adds a new attribute to the sysfs representation
2678 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
2679 * used for controlling the debug level.
2680 *
2681 * See the level definitions in iwl for details.
2682 *
2683 * The debug_level being managed using sysfs below is a per device debug
2684 * level that is used instead of the global debug level if it (the per
2685 * device debug level) is set.
2686 */
2687 static ssize_t show_debug_level(struct device *d,
2688 struct device_attribute *attr, char *buf)
2689 {
2690 struct iwl_priv *priv = dev_get_drvdata(d);
2691 return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
2692 }
2693 static ssize_t store_debug_level(struct device *d,
2694 struct device_attribute *attr,
2695 const char *buf, size_t count)
2696 {
2697 struct iwl_priv *priv = dev_get_drvdata(d);
2698 unsigned long val;
2699 int ret;
2700
2701 ret = strict_strtoul(buf, 0, &val);
2702 if (ret)
2703 IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
2704 else {
2705 priv->debug_level = val;
2706 if (iwl_alloc_traffic_mem(priv))
2707 IWL_ERR(priv,
2708 "Not enough memory to generate traffic log\n");
2709 }
2710 return strnlen(buf, count);
2711 }
2712
2713 static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
2714 show_debug_level, store_debug_level);
2715
2716
2717 #endif /* CONFIG_IWLWIFI_DEBUG */
2718
2719
2720 static ssize_t show_temperature(struct device *d,
2721 struct device_attribute *attr, char *buf)
2722 {
2723 struct iwl_priv *priv = dev_get_drvdata(d);
2724
2725 if (!iwl_is_alive(priv))
2726 return -EAGAIN;
2727
2728 return sprintf(buf, "%d\n", priv->temperature);
2729 }
2730
2731 static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
2732
2733 static ssize_t show_tx_power(struct device *d,
2734 struct device_attribute *attr, char *buf)
2735 {
2736 struct iwl_priv *priv = dev_get_drvdata(d);
2737
2738 if (!iwl_is_ready_rf(priv))
2739 return sprintf(buf, "off\n");
2740 else
2741 return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
2742 }
2743
2744 static ssize_t store_tx_power(struct device *d,
2745 struct device_attribute *attr,
2746 const char *buf, size_t count)
2747 {
2748 struct iwl_priv *priv = dev_get_drvdata(d);
2749 unsigned long val;
2750 int ret;
2751
2752 ret = strict_strtoul(buf, 10, &val);
2753 if (ret)
2754 IWL_INFO(priv, "%s is not in decimal form.\n", buf);
2755 else {
2756 ret = iwl_set_tx_power(priv, val, false);
2757 if (ret)
2758 IWL_ERR(priv, "failed setting tx power (0x%d).\n",
2759 ret);
2760 else
2761 ret = count;
2762 }
2763 return ret;
2764 }
2765
2766 static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
2767
2768 static ssize_t show_flags(struct device *d,
2769 struct device_attribute *attr, char *buf)
2770 {
2771 struct iwl_priv *priv = dev_get_drvdata(d);
2772
2773 return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
2774 }
2775
2776 static ssize_t store_flags(struct device *d,
2777 struct device_attribute *attr,
2778 const char *buf, size_t count)
2779 {
2780 struct iwl_priv *priv = dev_get_drvdata(d);
2781 unsigned long val;
2782 u32 flags;
2783 int ret = strict_strtoul(buf, 0, &val);
2784 if (ret)
2785 return ret;
2786 flags = (u32)val;
2787
2788 mutex_lock(&priv->mutex);
2789 if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
2790 /* Cancel any currently running scans... */
2791 if (iwl_scan_cancel_timeout(priv, 100))
2792 IWL_WARN(priv, "Could not cancel scan.\n");
2793 else {
2794 IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags);
2795 priv->staging_rxon.flags = cpu_to_le32(flags);
2796 iwlcore_commit_rxon(priv);
2797 }
2798 }
2799 mutex_unlock(&priv->mutex);
2800
2801 return count;
2802 }
2803
2804 static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
2805
2806 static ssize_t show_filter_flags(struct device *d,
2807 struct device_attribute *attr, char *buf)
2808 {
2809 struct iwl_priv *priv = dev_get_drvdata(d);
2810
2811 return sprintf(buf, "0x%04X\n",
2812 le32_to_cpu(priv->active_rxon.filter_flags));
2813 }
2814
2815 static ssize_t store_filter_flags(struct device *d,
2816 struct device_attribute *attr,
2817 const char *buf, size_t count)
2818 {
2819 struct iwl_priv *priv = dev_get_drvdata(d);
2820 unsigned long val;
2821 u32 filter_flags;
2822 int ret = strict_strtoul(buf, 0, &val);
2823 if (ret)
2824 return ret;
2825 filter_flags = (u32)val;
2826
2827 mutex_lock(&priv->mutex);
2828 if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
2829 /* Cancel any currently running scans... */
2830 if (iwl_scan_cancel_timeout(priv, 100))
2831 IWL_WARN(priv, "Could not cancel scan.\n");
2832 else {
2833 IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
2834 "0x%04X\n", filter_flags);
2835 priv->staging_rxon.filter_flags =
2836 cpu_to_le32(filter_flags);
2837 iwlcore_commit_rxon(priv);
2838 }
2839 }
2840 mutex_unlock(&priv->mutex);
2841
2842 return count;
2843 }
2844
2845 static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
2846 store_filter_flags);
2847
2848
2849 static ssize_t show_statistics(struct device *d,
2850 struct device_attribute *attr, char *buf)
2851 {
2852 struct iwl_priv *priv = dev_get_drvdata(d);
2853 u32 size = sizeof(struct iwl_notif_statistics);
2854 u32 len = 0, ofs = 0;
2855 u8 *data = (u8 *)&priv->statistics;
2856 int rc = 0;
2857
2858 if (!iwl_is_alive(priv))
2859 return -EAGAIN;
2860
2861 mutex_lock(&priv->mutex);
2862 rc = iwl_send_statistics_request(priv, 0);
2863 mutex_unlock(&priv->mutex);
2864
2865 if (rc) {
2866 len = sprintf(buf,
2867 "Error sending statistics request: 0x%08X\n", rc);
2868 return len;
2869 }
2870
2871 while (size && (PAGE_SIZE - len)) {
2872 hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
2873 PAGE_SIZE - len, 1);
2874 len = strlen(buf);
2875 if (PAGE_SIZE - len)
2876 buf[len++] = '\n';
2877
2878 ofs += 16;
2879 size -= min(size, 16U);
2880 }
2881
2882 return len;
2883 }
2884
2885 static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
2886
2887 static ssize_t show_rts_ht_protection(struct device *d,
2888 struct device_attribute *attr, char *buf)
2889 {
2890 struct iwl_priv *priv = dev_get_drvdata(d);
2891
2892 return sprintf(buf, "%s\n",
2893 priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self");
2894 }
2895
2896 static ssize_t store_rts_ht_protection(struct device *d,
2897 struct device_attribute *attr,
2898 const char *buf, size_t count)
2899 {
2900 struct iwl_priv *priv = dev_get_drvdata(d);
2901 unsigned long val;
2902 int ret;
2903
2904 ret = strict_strtoul(buf, 10, &val);
2905 if (ret)
2906 IWL_INFO(priv, "Input is not in decimal form.\n");
2907 else {
2908 if (!iwl_is_associated(priv))
2909 priv->cfg->use_rts_for_ht = val ? true : false;
2910 else
2911 IWL_ERR(priv, "Sta associated with AP - "
2912 "Change protection mechanism is not allowed\n");
2913 ret = count;
2914 }
2915 return ret;
2916 }
2917
2918 static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO,
2919 show_rts_ht_protection, store_rts_ht_protection);
2920
2921
2922 /*****************************************************************************
2923 *
2924 * driver setup and teardown
2925 *
2926 *****************************************************************************/
2927
2928 static void iwl_setup_deferred_work(struct iwl_priv *priv)
2929 {
2930 priv->workqueue = create_singlethread_workqueue(DRV_NAME);
2931
2932 init_waitqueue_head(&priv->wait_command_queue);
2933
2934 INIT_WORK(&priv->up, iwl_bg_up);
2935 INIT_WORK(&priv->restart, iwl_bg_restart);
2936 INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
2937 INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
2938 INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
2939 INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
2940 INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
2941
2942 iwl_setup_scan_deferred_work(priv);
2943
2944 if (priv->cfg->ops->lib->setup_deferred_work)
2945 priv->cfg->ops->lib->setup_deferred_work(priv);
2946
2947 init_timer(&priv->statistics_periodic);
2948 priv->statistics_periodic.data = (unsigned long)priv;
2949 priv->statistics_periodic.function = iwl_bg_statistics_periodic;
2950
2951 if (!priv->cfg->use_isr_legacy)
2952 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
2953 iwl_irq_tasklet, (unsigned long)priv);
2954 else
2955 tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
2956 iwl_irq_tasklet_legacy, (unsigned long)priv);
2957 }
2958
2959 static void iwl_cancel_deferred_work(struct iwl_priv *priv)
2960 {
2961 if (priv->cfg->ops->lib->cancel_deferred_work)
2962 priv->cfg->ops->lib->cancel_deferred_work(priv);
2963
2964 cancel_delayed_work_sync(&priv->init_alive_start);
2965 cancel_delayed_work(&priv->scan_check);
2966 cancel_delayed_work(&priv->alive_start);
2967 cancel_work_sync(&priv->beacon_update);
2968 del_timer_sync(&priv->statistics_periodic);
2969 }
2970
2971 static void iwl_init_hw_rates(struct iwl_priv *priv,
2972 struct ieee80211_rate *rates)
2973 {
2974 int i;
2975
2976 for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
2977 rates[i].bitrate = iwl_rates[i].ieee * 5;
2978 rates[i].hw_value = i; /* Rate scaling will work on indexes */
2979 rates[i].hw_value_short = i;
2980 rates[i].flags = 0;
2981 if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
2982 /*
2983 * If CCK != 1M then set short preamble rate flag.
2984 */
2985 rates[i].flags |=
2986 (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
2987 0 : IEEE80211_RATE_SHORT_PREAMBLE;
2988 }
2989 }
2990 }
2991
2992 static int iwl_init_drv(struct iwl_priv *priv)
2993 {
2994 int ret;
2995
2996 priv->ibss_beacon = NULL;
2997
2998 spin_lock_init(&priv->lock);
2999 spin_lock_init(&priv->sta_lock);
3000 spin_lock_init(&priv->hcmd_lock);
3001
3002 INIT_LIST_HEAD(&priv->free_frames);
3003
3004 mutex_init(&priv->mutex);
3005
3006 /* Clear the driver's (not device's) station table */
3007 iwl_clear_stations_table(priv);
3008
3009 priv->ieee_channels = NULL;
3010 priv->ieee_rates = NULL;
3011 priv->band = IEEE80211_BAND_2GHZ;
3012
3013 priv->iw_mode = NL80211_IFTYPE_STATION;
3014 if (priv->cfg->support_sm_ps)
3015 priv->current_ht_config.sm_ps = WLAN_HT_CAP_SM_PS_DYNAMIC;
3016 else
3017 priv->current_ht_config.sm_ps = WLAN_HT_CAP_SM_PS_DISABLED;
3018
3019 /* Choose which receivers/antennas to use */
3020 if (priv->cfg->ops->hcmd->set_rxon_chain)
3021 priv->cfg->ops->hcmd->set_rxon_chain(priv);
3022
3023 iwl_init_scan_params(priv);
3024
3025 iwl_reset_qos(priv);
3026
3027 priv->qos_data.qos_active = 0;
3028 priv->qos_data.qos_cap.val = 0;
3029
3030 priv->rates_mask = IWL_RATES_MASK;
3031 /* Set the tx_power_user_lmt to the lowest power level
3032 * this value will get overwritten by channel max power avg
3033 * from eeprom */
3034 priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MIN;
3035
3036 ret = iwl_init_channel_map(priv);
3037 if (ret) {
3038 IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
3039 goto err;
3040 }
3041
3042 ret = iwlcore_init_geos(priv);
3043 if (ret) {
3044 IWL_ERR(priv, "initializing geos failed: %d\n", ret);
3045 goto err_free_channel_map;
3046 }
3047 iwl_init_hw_rates(priv, priv->ieee_rates);
3048
3049 return 0;
3050
3051 err_free_channel_map:
3052 iwl_free_channel_map(priv);
3053 err:
3054 return ret;
3055 }
3056
3057 static void iwl_uninit_drv(struct iwl_priv *priv)
3058 {
3059 iwl_calib_free_results(priv);
3060 iwlcore_free_geos(priv);
3061 iwl_free_channel_map(priv);
3062 kfree(priv->scan);
3063 }
3064
3065 static struct attribute *iwl_sysfs_entries[] = {
3066 &dev_attr_flags.attr,
3067 &dev_attr_filter_flags.attr,
3068 &dev_attr_statistics.attr,
3069 &dev_attr_temperature.attr,
3070 &dev_attr_tx_power.attr,
3071 &dev_attr_rts_ht_protection.attr,
3072 #ifdef CONFIG_IWLWIFI_DEBUG
3073 &dev_attr_debug_level.attr,
3074 #endif
3075 NULL
3076 };
3077
3078 static struct attribute_group iwl_attribute_group = {
3079 .name = NULL, /* put in device directory */
3080 .attrs = iwl_sysfs_entries,
3081 };
3082
3083 static struct ieee80211_ops iwl_hw_ops = {
3084 .tx = iwl_mac_tx,
3085 .start = iwl_mac_start,
3086 .stop = iwl_mac_stop,
3087 .add_interface = iwl_mac_add_interface,
3088 .remove_interface = iwl_mac_remove_interface,
3089 .config = iwl_mac_config,
3090 .configure_filter = iwl_configure_filter,
3091 .set_key = iwl_mac_set_key,
3092 .update_tkip_key = iwl_mac_update_tkip_key,
3093 .get_stats = iwl_mac_get_stats,
3094 .get_tx_stats = iwl_mac_get_tx_stats,
3095 .conf_tx = iwl_mac_conf_tx,
3096 .reset_tsf = iwl_mac_reset_tsf,
3097 .bss_info_changed = iwl_bss_info_changed,
3098 .ampdu_action = iwl_mac_ampdu_action,
3099 .hw_scan = iwl_mac_hw_scan
3100 };
3101
3102 static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3103 {
3104 int err = 0;
3105 struct iwl_priv *priv;
3106 struct ieee80211_hw *hw;
3107 struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
3108 unsigned long flags;
3109 u16 pci_cmd;
3110
3111 /************************
3112 * 1. Allocating HW data
3113 ************************/
3114
3115 /* Disabling hardware scan means that mac80211 will perform scans
3116 * "the hard way", rather than using device's scan. */
3117 if (cfg->mod_params->disable_hw_scan) {
3118 if (iwl_debug_level & IWL_DL_INFO)
3119 dev_printk(KERN_DEBUG, &(pdev->dev),
3120 "Disabling hw_scan\n");
3121 iwl_hw_ops.hw_scan = NULL;
3122 }
3123
3124 hw = iwl_alloc_all(cfg, &iwl_hw_ops);
3125 if (!hw) {
3126 err = -ENOMEM;
3127 goto out;
3128 }
3129 priv = hw->priv;
3130 /* At this point both hw and priv are allocated. */
3131
3132 SET_IEEE80211_DEV(hw, &pdev->dev);
3133
3134 IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
3135 priv->cfg = cfg;
3136 priv->pci_dev = pdev;
3137 priv->inta_mask = CSR_INI_SET_MASK;
3138
3139 #ifdef CONFIG_IWLWIFI_DEBUG
3140 atomic_set(&priv->restrict_refcnt, 0);
3141 #endif
3142 if (iwl_alloc_traffic_mem(priv))
3143 IWL_ERR(priv, "Not enough memory to generate traffic log\n");
3144
3145 /**************************
3146 * 2. Initializing PCI bus
3147 **************************/
3148 if (pci_enable_device(pdev)) {
3149 err = -ENODEV;
3150 goto out_ieee80211_free_hw;
3151 }
3152
3153 pci_set_master(pdev);
3154
3155 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
3156 if (!err)
3157 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
3158 if (err) {
3159 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3160 if (!err)
3161 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3162 /* both attempts failed: */
3163 if (err) {
3164 IWL_WARN(priv, "No suitable DMA available.\n");
3165 goto out_pci_disable_device;
3166 }
3167 }
3168
3169 err = pci_request_regions(pdev, DRV_NAME);
3170 if (err)
3171 goto out_pci_disable_device;
3172
3173 pci_set_drvdata(pdev, priv);
3174
3175
3176 /***********************
3177 * 3. Read REV register
3178 ***********************/
3179 priv->hw_base = pci_iomap(pdev, 0, 0);
3180 if (!priv->hw_base) {
3181 err = -ENODEV;
3182 goto out_pci_release_regions;
3183 }
3184
3185 IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
3186 (unsigned long long) pci_resource_len(pdev, 0));
3187 IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
3188
3189 /* this spin lock will be used in apm_ops.init and EEPROM access
3190 * we should init now
3191 */
3192 spin_lock_init(&priv->reg_lock);
3193 iwl_hw_detect(priv);
3194 IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
3195 priv->cfg->name, priv->hw_rev);
3196
3197 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3198 * PCI Tx retries from interfering with C3 CPU state */
3199 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
3200
3201 iwl_prepare_card_hw(priv);
3202 if (!priv->hw_ready) {
3203 IWL_WARN(priv, "Failed, HW not ready\n");
3204 goto out_iounmap;
3205 }
3206
3207 /*****************
3208 * 4. Read EEPROM
3209 *****************/
3210 /* Read the EEPROM */
3211 err = iwl_eeprom_init(priv);
3212 if (err) {
3213 IWL_ERR(priv, "Unable to init EEPROM\n");
3214 goto out_iounmap;
3215 }
3216 err = iwl_eeprom_check_version(priv);
3217 if (err)
3218 goto out_free_eeprom;
3219
3220 /* extract MAC Address */
3221 iwl_eeprom_get_mac(priv, priv->mac_addr);
3222 IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
3223 SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
3224
3225 /************************
3226 * 5. Setup HW constants
3227 ************************/
3228 if (iwl_set_hw_params(priv)) {
3229 IWL_ERR(priv, "failed to set hw parameters\n");
3230 goto out_free_eeprom;
3231 }
3232
3233 /*******************
3234 * 6. Setup priv
3235 *******************/
3236
3237 err = iwl_init_drv(priv);
3238 if (err)
3239 goto out_free_eeprom;
3240 /* At this point both hw and priv are initialized. */
3241
3242 /********************
3243 * 7. Setup services
3244 ********************/
3245 spin_lock_irqsave(&priv->lock, flags);
3246 iwl_disable_interrupts(priv);
3247 spin_unlock_irqrestore(&priv->lock, flags);
3248
3249 pci_enable_msi(priv->pci_dev);
3250
3251 iwl_alloc_isr_ict(priv);
3252 err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
3253 IRQF_SHARED, DRV_NAME, priv);
3254 if (err) {
3255 IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
3256 goto out_disable_msi;
3257 }
3258 err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
3259 if (err) {
3260 IWL_ERR(priv, "failed to create sysfs device attributes\n");
3261 goto out_free_irq;
3262 }
3263
3264 iwl_setup_deferred_work(priv);
3265 iwl_setup_rx_handlers(priv);
3266
3267 /**********************************
3268 * 8. Setup and register mac80211
3269 **********************************/
3270
3271 /* enable interrupts if needed: hw bug w/a */
3272 pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
3273 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
3274 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
3275 pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
3276 }
3277
3278 iwl_enable_interrupts(priv);
3279
3280 err = iwl_setup_mac(priv);
3281 if (err)
3282 goto out_remove_sysfs;
3283
3284 err = iwl_dbgfs_register(priv, DRV_NAME);
3285 if (err)
3286 IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
3287
3288 /* If platform's RF_KILL switch is NOT set to KILL */
3289 if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
3290 clear_bit(STATUS_RF_KILL_HW, &priv->status);
3291 else
3292 set_bit(STATUS_RF_KILL_HW, &priv->status);
3293
3294 wiphy_rfkill_set_hw_state(priv->hw->wiphy,
3295 test_bit(STATUS_RF_KILL_HW, &priv->status));
3296
3297 iwl_power_initialize(priv);
3298 iwl_tt_initialize(priv);
3299 return 0;
3300
3301 out_remove_sysfs:
3302 destroy_workqueue(priv->workqueue);
3303 priv->workqueue = NULL;
3304 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
3305 out_free_irq:
3306 free_irq(priv->pci_dev->irq, priv);
3307 iwl_free_isr_ict(priv);
3308 out_disable_msi:
3309 pci_disable_msi(priv->pci_dev);
3310 iwl_uninit_drv(priv);
3311 out_free_eeprom:
3312 iwl_eeprom_free(priv);
3313 out_iounmap:
3314 pci_iounmap(pdev, priv->hw_base);
3315 out_pci_release_regions:
3316 pci_set_drvdata(pdev, NULL);
3317 pci_release_regions(pdev);
3318 out_pci_disable_device:
3319 pci_disable_device(pdev);
3320 out_ieee80211_free_hw:
3321 iwl_free_traffic_mem(priv);
3322 ieee80211_free_hw(priv->hw);
3323 out:
3324 return err;
3325 }
3326
3327 static void __devexit iwl_pci_remove(struct pci_dev *pdev)
3328 {
3329 struct iwl_priv *priv = pci_get_drvdata(pdev);
3330 unsigned long flags;
3331
3332 if (!priv)
3333 return;
3334
3335 IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
3336
3337 iwl_dbgfs_unregister(priv);
3338 sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
3339
3340 /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
3341 * to be called and iwl_down since we are removing the device
3342 * we need to set STATUS_EXIT_PENDING bit.
3343 */
3344 set_bit(STATUS_EXIT_PENDING, &priv->status);
3345 if (priv->mac80211_registered) {
3346 ieee80211_unregister_hw(priv->hw);
3347 priv->mac80211_registered = 0;
3348 } else {
3349 iwl_down(priv);
3350 }
3351
3352 /*
3353 * Make sure device is reset to low power before unloading driver.
3354 * This may be redundant with iwl_down(), but there are paths to
3355 * run iwl_down() without calling apm_ops.stop(), and there are
3356 * paths to avoid running iwl_down() at all before leaving driver.
3357 * This (inexpensive) call *makes sure* device is reset.
3358 */
3359 priv->cfg->ops->lib->apm_ops.stop(priv);
3360
3361 iwl_tt_exit(priv);
3362
3363 /* make sure we flush any pending irq or
3364 * tasklet for the driver
3365 */
3366 spin_lock_irqsave(&priv->lock, flags);
3367 iwl_disable_interrupts(priv);
3368 spin_unlock_irqrestore(&priv->lock, flags);
3369
3370 iwl_synchronize_irq(priv);
3371
3372 iwl_dealloc_ucode_pci(priv);
3373
3374 if (priv->rxq.bd)
3375 iwl_rx_queue_free(priv, &priv->rxq);
3376 iwl_hw_txq_ctx_free(priv);
3377
3378 iwl_clear_stations_table(priv);
3379 iwl_eeprom_free(priv);
3380
3381
3382 /*netif_stop_queue(dev); */
3383 flush_workqueue(priv->workqueue);
3384
3385 /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
3386 * priv->workqueue... so we can't take down the workqueue
3387 * until now... */
3388 destroy_workqueue(priv->workqueue);
3389 priv->workqueue = NULL;
3390 iwl_free_traffic_mem(priv);
3391
3392 free_irq(priv->pci_dev->irq, priv);
3393 pci_disable_msi(priv->pci_dev);
3394 pci_iounmap(pdev, priv->hw_base);
3395 pci_release_regions(pdev);
3396 pci_disable_device(pdev);
3397 pci_set_drvdata(pdev, NULL);
3398
3399 iwl_uninit_drv(priv);
3400
3401 iwl_free_isr_ict(priv);
3402
3403 if (priv->ibss_beacon)
3404 dev_kfree_skb(priv->ibss_beacon);
3405
3406 ieee80211_free_hw(priv->hw);
3407 }
3408
3409
3410 /*****************************************************************************
3411 *
3412 * driver and module entry point
3413 *
3414 *****************************************************************************/
3415
3416 /* Hardware specific file defines the PCI IDs table for that hardware module */
3417 static struct pci_device_id iwl_hw_card_ids[] = {
3418 #ifdef CONFIG_IWL4965
3419 {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
3420 {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
3421 #endif /* CONFIG_IWL4965 */
3422 #ifdef CONFIG_IWL5000
3423 {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bg_cfg)},
3424 {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bg_cfg)},
3425 {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)},
3426 {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)},
3427 {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)},
3428 {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)},
3429 {IWL_PCI_DEVICE(0x4232, PCI_ANY_ID, iwl5100_agn_cfg)},
3430 {IWL_PCI_DEVICE(0x4235, PCI_ANY_ID, iwl5300_agn_cfg)},
3431 {IWL_PCI_DEVICE(0x4236, PCI_ANY_ID, iwl5300_agn_cfg)},
3432 {IWL_PCI_DEVICE(0x4237, PCI_ANY_ID, iwl5100_agn_cfg)},
3433 /* 5350 WiFi/WiMax */
3434 {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)},
3435 {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)},
3436 {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)},
3437 /* 5150 Wifi/WiMax */
3438 {IWL_PCI_DEVICE(0x423C, PCI_ANY_ID, iwl5150_agn_cfg)},
3439 {IWL_PCI_DEVICE(0x423D, PCI_ANY_ID, iwl5150_agn_cfg)},
3440
3441 /* 6x00 Series */
3442 {IWL_PCI_DEVICE(0x008D, 0x1301, iwl6000h_2agn_cfg)},
3443 {IWL_PCI_DEVICE(0x008D, 0x1321, iwl6000h_2agn_cfg)},
3444 {IWL_PCI_DEVICE(0x008D, 0x1326, iwl6000h_2abg_cfg)},
3445 {IWL_PCI_DEVICE(0x008D, 0x1306, iwl6000h_2abg_cfg)},
3446 {IWL_PCI_DEVICE(0x008D, 0x1307, iwl6000h_2bg_cfg)},
3447 {IWL_PCI_DEVICE(0x008E, 0x1311, iwl6000h_2agn_cfg)},
3448 {IWL_PCI_DEVICE(0x008E, 0x1316, iwl6000h_2abg_cfg)},
3449
3450 {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
3451 {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
3452 {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
3453 {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
3454 {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
3455 {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
3456 {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
3457 {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
3458 {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
3459 {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
3460
3461 /* 6x50 WiFi/WiMax Series */
3462 {IWL_PCI_DEVICE(0x0086, 0x1101, iwl6050_3agn_cfg)},
3463 {IWL_PCI_DEVICE(0x0086, 0x1121, iwl6050_3agn_cfg)},
3464 {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
3465 {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
3466 {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
3467 {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
3468 {IWL_PCI_DEVICE(0x0088, 0x1111, iwl6050_3agn_cfg)},
3469 {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
3470 {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
3471
3472 /* 1000 Series WiFi */
3473 {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
3474 {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
3475 {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
3476 {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
3477 {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
3478 {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
3479 {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
3480 {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
3481 {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
3482 {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
3483 {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
3484 {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
3485 #endif /* CONFIG_IWL5000 */
3486
3487 {0}
3488 };
3489 MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
3490
3491 static struct pci_driver iwl_driver = {
3492 .name = DRV_NAME,
3493 .id_table = iwl_hw_card_ids,
3494 .probe = iwl_pci_probe,
3495 .remove = __devexit_p(iwl_pci_remove),
3496 #ifdef CONFIG_PM
3497 .suspend = iwl_pci_suspend,
3498 .resume = iwl_pci_resume,
3499 #endif
3500 };
3501
3502 static int __init iwl_init(void)
3503 {
3504
3505 int ret;
3506 printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
3507 printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
3508
3509 ret = iwlagn_rate_control_register();
3510 if (ret) {
3511 printk(KERN_ERR DRV_NAME
3512 "Unable to register rate control algorithm: %d\n", ret);
3513 return ret;
3514 }
3515
3516 ret = pci_register_driver(&iwl_driver);
3517 if (ret) {
3518 printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
3519 goto error_register;
3520 }
3521
3522 return ret;
3523
3524 error_register:
3525 iwlagn_rate_control_unregister();
3526 return ret;
3527 }
3528
3529 static void __exit iwl_exit(void)
3530 {
3531 pci_unregister_driver(&iwl_driver);
3532 iwlagn_rate_control_unregister();
3533 }
3534
3535 module_exit(iwl_exit);
3536 module_init(iwl_init);
3537
3538 #ifdef CONFIG_IWLWIFI_DEBUG
3539 module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
3540 MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
3541 module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
3542 MODULE_PARM_DESC(debug, "debug output mask");
3543 #endif
3544
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree