2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <joerg.roedel@amd.com>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/bitmap.h>
22 #include <linux/slab.h>
23 #include <linux/debugfs.h>
24 #include <linux/scatterlist.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/iommu-helper.h>
27 #include <linux/iommu.h>
28 #include <asm/proto.h>
29 #include <asm/iommu.h>
31 #include <asm/amd_iommu_proto.h>
32 #include <asm/amd_iommu_types.h>
33 #include <asm/amd_iommu.h>
35 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
37 #define EXIT_LOOP_COUNT 10000000
39 static DEFINE_RWLOCK(amd_iommu_devtable_lock
);
41 /* A list of preallocated protection domains */
42 static LIST_HEAD(iommu_pd_list
);
43 static DEFINE_SPINLOCK(iommu_pd_list_lock
);
46 * Domain for untranslated devices - only allocated
47 * if iommu=pt passed on kernel cmd line.
49 static struct protection_domain
*pt_domain
;
51 static struct iommu_ops amd_iommu_ops
;
54 * general struct to manage commands send to an IOMMU
60 static void reset_iommu_command_buffer(struct amd_iommu
*iommu
);
61 static void update_domain(struct protection_domain
*domain
);
63 /****************************************************************************
67 ****************************************************************************/
69 static inline u16
get_device_id(struct device
*dev
)
71 struct pci_dev
*pdev
= to_pci_dev(dev
);
73 return calc_devid(pdev
->bus
->number
, pdev
->devfn
);
76 static struct iommu_dev_data
*get_dev_data(struct device
*dev
)
78 return dev
->archdata
.iommu
;
82 * In this function the list of preallocated protection domains is traversed to
83 * find the domain for a specific device
85 static struct dma_ops_domain
*find_protection_domain(u16 devid
)
87 struct dma_ops_domain
*entry
, *ret
= NULL
;
89 u16 alias
= amd_iommu_alias_table
[devid
];
91 if (list_empty(&iommu_pd_list
))
94 spin_lock_irqsave(&iommu_pd_list_lock
, flags
);
96 list_for_each_entry(entry
, &iommu_pd_list
, list
) {
97 if (entry
->target_dev
== devid
||
98 entry
->target_dev
== alias
) {
104 spin_unlock_irqrestore(&iommu_pd_list_lock
, flags
);
110 * This function checks if the driver got a valid device from the caller to
111 * avoid dereferencing invalid pointers.
113 static bool check_device(struct device
*dev
)
117 if (!dev
|| !dev
->dma_mask
)
120 /* No device or no PCI device */
121 if (dev
->bus
!= &pci_bus_type
)
124 devid
= get_device_id(dev
);
126 /* Out of our scope? */
127 if (devid
> amd_iommu_last_bdf
)
130 if (amd_iommu_rlookup_table
[devid
] == NULL
)
136 static int iommu_init_device(struct device
*dev
)
138 struct iommu_dev_data
*dev_data
;
139 struct pci_dev
*pdev
;
142 if (dev
->archdata
.iommu
)
145 dev_data
= kzalloc(sizeof(*dev_data
), GFP_KERNEL
);
151 devid
= get_device_id(dev
);
152 alias
= amd_iommu_alias_table
[devid
];
153 pdev
= pci_get_bus_and_slot(PCI_BUS(alias
), alias
& 0xff);
155 dev_data
->alias
= &pdev
->dev
;
157 atomic_set(&dev_data
->bind
, 0);
159 dev
->archdata
.iommu
= dev_data
;
165 static void iommu_uninit_device(struct device
*dev
)
167 kfree(dev
->archdata
.iommu
);
170 void __init
amd_iommu_uninit_devices(void)
172 struct pci_dev
*pdev
= NULL
;
174 for_each_pci_dev(pdev
) {
176 if (!check_device(&pdev
->dev
))
179 iommu_uninit_device(&pdev
->dev
);
183 int __init
amd_iommu_init_devices(void)
185 struct pci_dev
*pdev
= NULL
;
188 for_each_pci_dev(pdev
) {
190 if (!check_device(&pdev
->dev
))
193 ret
= iommu_init_device(&pdev
->dev
);
202 amd_iommu_uninit_devices();
206 #ifdef CONFIG_AMD_IOMMU_STATS
209 * Initialization code for statistics collection
212 DECLARE_STATS_COUNTER(compl_wait
);
213 DECLARE_STATS_COUNTER(cnt_map_single
);
214 DECLARE_STATS_COUNTER(cnt_unmap_single
);
215 DECLARE_STATS_COUNTER(cnt_map_sg
);
216 DECLARE_STATS_COUNTER(cnt_unmap_sg
);
217 DECLARE_STATS_COUNTER(cnt_alloc_coherent
);
218 DECLARE_STATS_COUNTER(cnt_free_coherent
);
219 DECLARE_STATS_COUNTER(cross_page
);
220 DECLARE_STATS_COUNTER(domain_flush_single
);
221 DECLARE_STATS_COUNTER(domain_flush_all
);
222 DECLARE_STATS_COUNTER(alloced_io_mem
);
223 DECLARE_STATS_COUNTER(total_map_requests
);
225 static struct dentry
*stats_dir
;
226 static struct dentry
*de_fflush
;
228 static void amd_iommu_stats_add(struct __iommu_counter
*cnt
)
230 if (stats_dir
== NULL
)
233 cnt
->dent
= debugfs_create_u64(cnt
->name
, 0444, stats_dir
,
237 static void amd_iommu_stats_init(void)
239 stats_dir
= debugfs_create_dir("amd-iommu", NULL
);
240 if (stats_dir
== NULL
)
243 de_fflush
= debugfs_create_bool("fullflush", 0444, stats_dir
,
244 (u32
*)&amd_iommu_unmap_flush
);
246 amd_iommu_stats_add(&compl_wait
);
247 amd_iommu_stats_add(&cnt_map_single
);
248 amd_iommu_stats_add(&cnt_unmap_single
);
249 amd_iommu_stats_add(&cnt_map_sg
);
250 amd_iommu_stats_add(&cnt_unmap_sg
);
251 amd_iommu_stats_add(&cnt_alloc_coherent
);
252 amd_iommu_stats_add(&cnt_free_coherent
);
253 amd_iommu_stats_add(&cross_page
);
254 amd_iommu_stats_add(&domain_flush_single
);
255 amd_iommu_stats_add(&domain_flush_all
);
256 amd_iommu_stats_add(&alloced_io_mem
);
257 amd_iommu_stats_add(&total_map_requests
);
262 /****************************************************************************
264 * Interrupt handling functions
266 ****************************************************************************/
268 static void dump_dte_entry(u16 devid
)
272 for (i
= 0; i
< 8; ++i
)
273 pr_err("AMD-Vi: DTE[%d]: %08x\n", i
,
274 amd_iommu_dev_table
[devid
].data
[i
]);
277 static void dump_command(unsigned long phys_addr
)
279 struct iommu_cmd
*cmd
= phys_to_virt(phys_addr
);
282 for (i
= 0; i
< 4; ++i
)
283 pr_err("AMD-Vi: CMD[%d]: %08x\n", i
, cmd
->data
[i
]);
286 static void iommu_print_event(struct amd_iommu
*iommu
, void *__evt
)
289 int type
= (event
[1] >> EVENT_TYPE_SHIFT
) & EVENT_TYPE_MASK
;
290 int devid
= (event
[0] >> EVENT_DEVID_SHIFT
) & EVENT_DEVID_MASK
;
291 int domid
= (event
[1] >> EVENT_DOMID_SHIFT
) & EVENT_DOMID_MASK
;
292 int flags
= (event
[1] >> EVENT_FLAGS_SHIFT
) & EVENT_FLAGS_MASK
;
293 u64 address
= (u64
)(((u64
)event
[3]) << 32) | event
[2];
295 printk(KERN_ERR
"AMD-Vi: Event logged [");
298 case EVENT_TYPE_ILL_DEV
:
299 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
300 "address=0x%016llx flags=0x%04x]\n",
301 PCI_BUS(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
303 dump_dte_entry(devid
);
305 case EVENT_TYPE_IO_FAULT
:
306 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
307 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
308 PCI_BUS(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
309 domid
, address
, flags
);
311 case EVENT_TYPE_DEV_TAB_ERR
:
312 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
313 "address=0x%016llx flags=0x%04x]\n",
314 PCI_BUS(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
317 case EVENT_TYPE_PAGE_TAB_ERR
:
318 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
319 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
320 PCI_BUS(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
321 domid
, address
, flags
);
323 case EVENT_TYPE_ILL_CMD
:
324 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address
);
325 iommu
->reset_in_progress
= true;
326 reset_iommu_command_buffer(iommu
);
327 dump_command(address
);
329 case EVENT_TYPE_CMD_HARD_ERR
:
330 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
331 "flags=0x%04x]\n", address
, flags
);
333 case EVENT_TYPE_IOTLB_INV_TO
:
334 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
335 "address=0x%016llx]\n",
336 PCI_BUS(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
339 case EVENT_TYPE_INV_DEV_REQ
:
340 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
341 "address=0x%016llx flags=0x%04x]\n",
342 PCI_BUS(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
346 printk(KERN_ERR
"UNKNOWN type=0x%02x]\n", type
);
350 static void iommu_poll_events(struct amd_iommu
*iommu
)
355 spin_lock_irqsave(&iommu
->lock
, flags
);
357 head
= readl(iommu
->mmio_base
+ MMIO_EVT_HEAD_OFFSET
);
358 tail
= readl(iommu
->mmio_base
+ MMIO_EVT_TAIL_OFFSET
);
360 while (head
!= tail
) {
361 iommu_print_event(iommu
, iommu
->evt_buf
+ head
);
362 head
= (head
+ EVENT_ENTRY_SIZE
) % iommu
->evt_buf_size
;
365 writel(head
, iommu
->mmio_base
+ MMIO_EVT_HEAD_OFFSET
);
367 spin_unlock_irqrestore(&iommu
->lock
, flags
);
370 irqreturn_t
amd_iommu_int_handler(int irq
, void *data
)
372 struct amd_iommu
*iommu
;
374 for_each_iommu(iommu
)
375 iommu_poll_events(iommu
);
380 /****************************************************************************
382 * IOMMU command queuing functions
384 ****************************************************************************/
387 * Writes the command to the IOMMUs command buffer and informs the
388 * hardware about the new command. Must be called with iommu->lock held.
390 static int __iommu_queue_command(struct amd_iommu
*iommu
, struct iommu_cmd
*cmd
)
395 WARN_ON(iommu
->cmd_buf_size
& CMD_BUFFER_UNINITIALIZED
);
396 tail
= readl(iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
397 target
= iommu
->cmd_buf
+ tail
;
398 memcpy_toio(target
, cmd
, sizeof(*cmd
));
399 tail
= (tail
+ sizeof(*cmd
)) % iommu
->cmd_buf_size
;
400 head
= readl(iommu
->mmio_base
+ MMIO_CMD_HEAD_OFFSET
);
403 writel(tail
, iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
409 * General queuing function for commands. Takes iommu->lock and calls
410 * __iommu_queue_command().
412 static int iommu_queue_command(struct amd_iommu
*iommu
, struct iommu_cmd
*cmd
)
417 spin_lock_irqsave(&iommu
->lock
, flags
);
418 ret
= __iommu_queue_command(iommu
, cmd
);
420 iommu
->need_sync
= true;
421 spin_unlock_irqrestore(&iommu
->lock
, flags
);
427 * This function waits until an IOMMU has completed a completion
430 static void __iommu_wait_for_completion(struct amd_iommu
*iommu
)
436 INC_STATS_COUNTER(compl_wait
);
438 while (!ready
&& (i
< EXIT_LOOP_COUNT
)) {
440 /* wait for the bit to become one */
441 status
= readl(iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
442 ready
= status
& MMIO_STATUS_COM_WAIT_INT_MASK
;
445 /* set bit back to zero */
446 status
&= ~MMIO_STATUS_COM_WAIT_INT_MASK
;
447 writel(status
, iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
449 if (unlikely(i
== EXIT_LOOP_COUNT
))
450 iommu
->reset_in_progress
= true;
454 * This function queues a completion wait command into the command
457 static int __iommu_completion_wait(struct amd_iommu
*iommu
)
459 struct iommu_cmd cmd
;
461 memset(&cmd
, 0, sizeof(cmd
));
462 cmd
.data
[0] = CMD_COMPL_WAIT_INT_MASK
;
463 CMD_SET_TYPE(&cmd
, CMD_COMPL_WAIT
);
465 return __iommu_queue_command(iommu
, &cmd
);
469 * This function is called whenever we need to ensure that the IOMMU has
470 * completed execution of all commands we sent. It sends a
471 * COMPLETION_WAIT command and waits for it to finish. The IOMMU informs
472 * us about that by writing a value to a physical address we pass with
475 static int iommu_completion_wait(struct amd_iommu
*iommu
)
480 spin_lock_irqsave(&iommu
->lock
, flags
);
482 if (!iommu
->need_sync
)
485 ret
= __iommu_completion_wait(iommu
);
487 iommu
->need_sync
= false;
492 __iommu_wait_for_completion(iommu
);
495 spin_unlock_irqrestore(&iommu
->lock
, flags
);
497 if (iommu
->reset_in_progress
)
498 reset_iommu_command_buffer(iommu
);
503 static void iommu_flush_complete(struct protection_domain
*domain
)
507 for (i
= 0; i
< amd_iommus_present
; ++i
) {
508 if (!domain
->dev_iommu
[i
])
512 * Devices of this domain are behind this IOMMU
513 * We need to wait for completion of all commands.
515 iommu_completion_wait(amd_iommus
[i
]);
520 * Command send function for invalidating a device table entry
522 static int iommu_flush_device(struct device
*dev
)
524 struct amd_iommu
*iommu
;
525 struct iommu_cmd cmd
;
528 devid
= get_device_id(dev
);
529 iommu
= amd_iommu_rlookup_table
[devid
];
532 memset(&cmd
, 0, sizeof(cmd
));
533 CMD_SET_TYPE(&cmd
, CMD_INV_DEV_ENTRY
);
536 return iommu_queue_command(iommu
, &cmd
);
539 static void __iommu_build_inv_iommu_pages(struct iommu_cmd
*cmd
, u64 address
,
540 u16 domid
, int pde
, int s
)
542 memset(cmd
, 0, sizeof(*cmd
));
543 address
&= PAGE_MASK
;
544 CMD_SET_TYPE(cmd
, CMD_INV_IOMMU_PAGES
);
545 cmd
->data
[1] |= domid
;
546 cmd
->data
[2] = lower_32_bits(address
);
547 cmd
->data
[3] = upper_32_bits(address
);
548 if (s
) /* size bit - we flush more than one 4kb page */
549 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
550 if (pde
) /* PDE bit - we wan't flush everything not only the PTEs */
551 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK
;
555 * Generic command send function for invalidaing TLB entries
557 static int iommu_queue_inv_iommu_pages(struct amd_iommu
*iommu
,
558 u64 address
, u16 domid
, int pde
, int s
)
560 struct iommu_cmd cmd
;
563 __iommu_build_inv_iommu_pages(&cmd
, address
, domid
, pde
, s
);
565 ret
= iommu_queue_command(iommu
, &cmd
);
571 * TLB invalidation function which is called from the mapping functions.
572 * It invalidates a single PTE if the range to flush is within a single
573 * page. Otherwise it flushes the whole TLB of the IOMMU.
575 static void __iommu_flush_pages(struct protection_domain
*domain
,
576 u64 address
, size_t size
, int pde
)
579 unsigned long pages
= iommu_num_pages(address
, size
, PAGE_SIZE
);
581 address
&= PAGE_MASK
;
585 * If we have to flush more than one page, flush all
586 * TLB entries for this domain
588 address
= CMD_INV_IOMMU_ALL_PAGES_ADDRESS
;
593 for (i
= 0; i
< amd_iommus_present
; ++i
) {
594 if (!domain
->dev_iommu
[i
])
598 * Devices of this domain are behind this IOMMU
599 * We need a TLB flush
601 iommu_queue_inv_iommu_pages(amd_iommus
[i
], address
,
608 static void iommu_flush_pages(struct protection_domain
*domain
,
609 u64 address
, size_t size
)
611 __iommu_flush_pages(domain
, address
, size
, 0);
614 /* Flush the whole IO/TLB for a given protection domain */
615 static void iommu_flush_tlb(struct protection_domain
*domain
)
617 __iommu_flush_pages(domain
, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
, 0);
620 /* Flush the whole IO/TLB for a given protection domain - including PDE */
621 static void iommu_flush_tlb_pde(struct protection_domain
*domain
)
623 __iommu_flush_pages(domain
, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
, 1);
628 * This function flushes the DTEs for all devices in domain
630 static void iommu_flush_domain_devices(struct protection_domain
*domain
)
632 struct iommu_dev_data
*dev_data
;
635 spin_lock_irqsave(&domain
->lock
, flags
);
637 list_for_each_entry(dev_data
, &domain
->dev_list
, list
)
638 iommu_flush_device(dev_data
->dev
);
640 spin_unlock_irqrestore(&domain
->lock
, flags
);
643 static void iommu_flush_all_domain_devices(void)
645 struct protection_domain
*domain
;
648 spin_lock_irqsave(&amd_iommu_pd_lock
, flags
);
650 list_for_each_entry(domain
, &amd_iommu_pd_list
, list
) {
651 iommu_flush_domain_devices(domain
);
652 iommu_flush_complete(domain
);
655 spin_unlock_irqrestore(&amd_iommu_pd_lock
, flags
);
658 void amd_iommu_flush_all_devices(void)
660 iommu_flush_all_domain_devices();
664 * This function uses heavy locking and may disable irqs for some time. But
665 * this is no issue because it is only called during resume.
667 void amd_iommu_flush_all_domains(void)
669 struct protection_domain
*domain
;
672 spin_lock_irqsave(&amd_iommu_pd_lock
, flags
);
674 list_for_each_entry(domain
, &amd_iommu_pd_list
, list
) {
675 spin_lock(&domain
->lock
);
676 iommu_flush_tlb_pde(domain
);
677 iommu_flush_complete(domain
);
678 spin_unlock(&domain
->lock
);
681 spin_unlock_irqrestore(&amd_iommu_pd_lock
, flags
);
684 static void reset_iommu_command_buffer(struct amd_iommu
*iommu
)
686 pr_err("AMD-Vi: Resetting IOMMU command buffer\n");
688 if (iommu
->reset_in_progress
)
689 panic("AMD-Vi: ILLEGAL_COMMAND_ERROR while resetting command buffer\n");
691 amd_iommu_reset_cmd_buffer(iommu
);
692 amd_iommu_flush_all_devices();
693 amd_iommu_flush_all_domains();
695 iommu
->reset_in_progress
= false;
698 /****************************************************************************
700 * The functions below are used the create the page table mappings for
701 * unity mapped regions.
703 ****************************************************************************/
706 * This function is used to add another level to an IO page table. Adding
707 * another level increases the size of the address space by 9 bits to a size up
710 static bool increase_address_space(struct protection_domain
*domain
,
715 if (domain
->mode
== PAGE_MODE_6_LEVEL
)
716 /* address space already 64 bit large */
719 pte
= (void *)get_zeroed_page(gfp
);
723 *pte
= PM_LEVEL_PDE(domain
->mode
,
724 virt_to_phys(domain
->pt_root
));
725 domain
->pt_root
= pte
;
727 domain
->updated
= true;
732 static u64
*alloc_pte(struct protection_domain
*domain
,
733 unsigned long address
,
734 unsigned long page_size
,
741 BUG_ON(!is_power_of_2(page_size
));
743 while (address
> PM_LEVEL_SIZE(domain
->mode
))
744 increase_address_space(domain
, gfp
);
746 level
= domain
->mode
- 1;
747 pte
= &domain
->pt_root
[PM_LEVEL_INDEX(level
, address
)];
748 address
= PAGE_SIZE_ALIGN(address
, page_size
);
749 end_lvl
= PAGE_SIZE_LEVEL(page_size
);
751 while (level
> end_lvl
) {
752 if (!IOMMU_PTE_PRESENT(*pte
)) {
753 page
= (u64
*)get_zeroed_page(gfp
);
756 *pte
= PM_LEVEL_PDE(level
, virt_to_phys(page
));
759 /* No level skipping support yet */
760 if (PM_PTE_LEVEL(*pte
) != level
)
765 pte
= IOMMU_PTE_PAGE(*pte
);
767 if (pte_page
&& level
== end_lvl
)
770 pte
= &pte
[PM_LEVEL_INDEX(level
, address
)];
777 * This function checks if there is a PTE for a given dma address. If
778 * there is one, it returns the pointer to it.
780 static u64
*fetch_pte(struct protection_domain
*domain
, unsigned long address
)
785 if (address
> PM_LEVEL_SIZE(domain
->mode
))
788 level
= domain
->mode
- 1;
789 pte
= &domain
->pt_root
[PM_LEVEL_INDEX(level
, address
)];
794 if (!IOMMU_PTE_PRESENT(*pte
))
798 if (PM_PTE_LEVEL(*pte
) == 0x07) {
799 unsigned long pte_mask
, __pte
;
802 * If we have a series of large PTEs, make
803 * sure to return a pointer to the first one.
805 pte_mask
= PTE_PAGE_SIZE(*pte
);
806 pte_mask
= ~((PAGE_SIZE_PTE_COUNT(pte_mask
) << 3) - 1);
807 __pte
= ((unsigned long)pte
) & pte_mask
;
812 /* No level skipping support yet */
813 if (PM_PTE_LEVEL(*pte
) != level
)
818 /* Walk to the next level */
819 pte
= IOMMU_PTE_PAGE(*pte
);
820 pte
= &pte
[PM_LEVEL_INDEX(level
, address
)];
827 * Generic mapping functions. It maps a physical address into a DMA
828 * address space. It allocates the page table pages if necessary.
829 * In the future it can be extended to a generic mapping function
830 * supporting all features of AMD IOMMU page tables like level skipping
831 * and full 64 bit address spaces.
833 static int iommu_map_page(struct protection_domain
*dom
,
834 unsigned long bus_addr
,
835 unsigned long phys_addr
,
837 unsigned long page_size
)
842 if (!(prot
& IOMMU_PROT_MASK
))
845 bus_addr
= PAGE_ALIGN(bus_addr
);
846 phys_addr
= PAGE_ALIGN(phys_addr
);
847 count
= PAGE_SIZE_PTE_COUNT(page_size
);
848 pte
= alloc_pte(dom
, bus_addr
, page_size
, NULL
, GFP_KERNEL
);
850 for (i
= 0; i
< count
; ++i
)
851 if (IOMMU_PTE_PRESENT(pte
[i
]))
854 if (page_size
> PAGE_SIZE
) {
855 __pte
= PAGE_SIZE_PTE(phys_addr
, page_size
);
856 __pte
|= PM_LEVEL_ENC(7) | IOMMU_PTE_P
| IOMMU_PTE_FC
;
858 __pte
= phys_addr
| IOMMU_PTE_P
| IOMMU_PTE_FC
;
860 if (prot
& IOMMU_PROT_IR
)
861 __pte
|= IOMMU_PTE_IR
;
862 if (prot
& IOMMU_PROT_IW
)
863 __pte
|= IOMMU_PTE_IW
;
865 for (i
= 0; i
< count
; ++i
)
873 static unsigned long iommu_unmap_page(struct protection_domain
*dom
,
874 unsigned long bus_addr
,
875 unsigned long page_size
)
877 unsigned long long unmap_size
, unmapped
;
880 BUG_ON(!is_power_of_2(page_size
));
884 while (unmapped
< page_size
) {
886 pte
= fetch_pte(dom
, bus_addr
);
890 * No PTE for this address
891 * move forward in 4kb steps
893 unmap_size
= PAGE_SIZE
;
894 } else if (PM_PTE_LEVEL(*pte
) == 0) {
895 /* 4kb PTE found for this address */
896 unmap_size
= PAGE_SIZE
;
901 /* Large PTE found which maps this address */
902 unmap_size
= PTE_PAGE_SIZE(*pte
);
903 count
= PAGE_SIZE_PTE_COUNT(unmap_size
);
904 for (i
= 0; i
< count
; i
++)
908 bus_addr
= (bus_addr
& ~(unmap_size
- 1)) + unmap_size
;
909 unmapped
+= unmap_size
;
912 BUG_ON(!is_power_of_2(unmapped
));
918 * This function checks if a specific unity mapping entry is needed for
919 * this specific IOMMU.
921 static int iommu_for_unity_map(struct amd_iommu
*iommu
,
922 struct unity_map_entry
*entry
)
926 for (i
= entry
->devid_start
; i
<= entry
->devid_end
; ++i
) {
927 bdf
= amd_iommu_alias_table
[i
];
928 if (amd_iommu_rlookup_table
[bdf
] == iommu
)
936 * This function actually applies the mapping to the page table of the
939 static int dma_ops_unity_map(struct dma_ops_domain
*dma_dom
,
940 struct unity_map_entry
*e
)
945 for (addr
= e
->address_start
; addr
< e
->address_end
;
947 ret
= iommu_map_page(&dma_dom
->domain
, addr
, addr
, e
->prot
,
952 * if unity mapping is in aperture range mark the page
953 * as allocated in the aperture
955 if (addr
< dma_dom
->aperture_size
)
956 __set_bit(addr
>> PAGE_SHIFT
,
957 dma_dom
->aperture
[0]->bitmap
);
964 * Init the unity mappings for a specific IOMMU in the system
966 * Basically iterates over all unity mapping entries and applies them to
967 * the default domain DMA of that IOMMU if necessary.
969 static int iommu_init_unity_mappings(struct amd_iommu
*iommu
)
971 struct unity_map_entry
*entry
;
974 list_for_each_entry(entry
, &amd_iommu_unity_map
, list
) {
975 if (!iommu_for_unity_map(iommu
, entry
))
977 ret
= dma_ops_unity_map(iommu
->default_dom
, entry
);
986 * Inits the unity mappings required for a specific device
988 static int init_unity_mappings_for_device(struct dma_ops_domain
*dma_dom
,
991 struct unity_map_entry
*e
;
994 list_for_each_entry(e
, &amd_iommu_unity_map
, list
) {
995 if (!(devid
>= e
->devid_start
&& devid
<= e
->devid_end
))
997 ret
= dma_ops_unity_map(dma_dom
, e
);
1005 /****************************************************************************
1007 * The next functions belong to the address allocator for the dma_ops
1008 * interface functions. They work like the allocators in the other IOMMU
1009 * drivers. Its basically a bitmap which marks the allocated pages in
1010 * the aperture. Maybe it could be enhanced in the future to a more
1011 * efficient allocator.
1013 ****************************************************************************/
1016 * The address allocator core functions.
1018 * called with domain->lock held
1022 * Used to reserve address ranges in the aperture (e.g. for exclusion
1025 static void dma_ops_reserve_addresses(struct dma_ops_domain
*dom
,
1026 unsigned long start_page
,
1029 unsigned int i
, last_page
= dom
->aperture_size
>> PAGE_SHIFT
;
1031 if (start_page
+ pages
> last_page
)
1032 pages
= last_page
- start_page
;
1034 for (i
= start_page
; i
< start_page
+ pages
; ++i
) {
1035 int index
= i
/ APERTURE_RANGE_PAGES
;
1036 int page
= i
% APERTURE_RANGE_PAGES
;
1037 __set_bit(page
, dom
->aperture
[index
]->bitmap
);
1042 * This function is used to add a new aperture range to an existing
1043 * aperture in case of dma_ops domain allocation or address allocation
1046 static int alloc_new_range(struct dma_ops_domain
*dma_dom
,
1047 bool populate
, gfp_t gfp
)
1049 int index
= dma_dom
->aperture_size
>> APERTURE_RANGE_SHIFT
;
1050 struct amd_iommu
*iommu
;
1053 #ifdef CONFIG_IOMMU_STRESS
1057 if (index
>= APERTURE_MAX_RANGES
)
1060 dma_dom
->aperture
[index
] = kzalloc(sizeof(struct aperture_range
), gfp
);
1061 if (!dma_dom
->aperture
[index
])
1064 dma_dom
->aperture
[index
]->bitmap
= (void *)get_zeroed_page(gfp
);
1065 if (!dma_dom
->aperture
[index
]->bitmap
)
1068 dma_dom
->aperture
[index
]->offset
= dma_dom
->aperture_size
;
1071 unsigned long address
= dma_dom
->aperture_size
;
1072 int i
, num_ptes
= APERTURE_RANGE_PAGES
/ 512;
1073 u64
*pte
, *pte_page
;
1075 for (i
= 0; i
< num_ptes
; ++i
) {
1076 pte
= alloc_pte(&dma_dom
->domain
, address
, PAGE_SIZE
,
1081 dma_dom
->aperture
[index
]->pte_pages
[i
] = pte_page
;
1083 address
+= APERTURE_RANGE_SIZE
/ 64;
1087 dma_dom
->aperture_size
+= APERTURE_RANGE_SIZE
;
1089 /* Intialize the exclusion range if necessary */
1090 for_each_iommu(iommu
) {
1091 if (iommu
->exclusion_start
&&
1092 iommu
->exclusion_start
>= dma_dom
->aperture
[index
]->offset
1093 && iommu
->exclusion_start
< dma_dom
->aperture_size
) {
1094 unsigned long startpage
;
1095 int pages
= iommu_num_pages(iommu
->exclusion_start
,
1096 iommu
->exclusion_length
,
1098 startpage
= iommu
->exclusion_start
>> PAGE_SHIFT
;
1099 dma_ops_reserve_addresses(dma_dom
, startpage
, pages
);
1104 * Check for areas already mapped as present in the new aperture
1105 * range and mark those pages as reserved in the allocator. Such
1106 * mappings may already exist as a result of requested unity
1107 * mappings for devices.
1109 for (i
= dma_dom
->aperture
[index
]->offset
;
1110 i
< dma_dom
->aperture_size
;
1112 u64
*pte
= fetch_pte(&dma_dom
->domain
, i
);
1113 if (!pte
|| !IOMMU_PTE_PRESENT(*pte
))
1116 dma_ops_reserve_addresses(dma_dom
, i
<< PAGE_SHIFT
, 1);
1119 update_domain(&dma_dom
->domain
);
1124 update_domain(&dma_dom
->domain
);
1126 free_page((unsigned long)dma_dom
->aperture
[index
]->bitmap
);
1128 kfree(dma_dom
->aperture
[index
]);
1129 dma_dom
->aperture
[index
] = NULL
;
1134 static unsigned long dma_ops_area_alloc(struct device
*dev
,
1135 struct dma_ops_domain
*dom
,
1137 unsigned long align_mask
,
1139 unsigned long start
)
1141 unsigned long next_bit
= dom
->next_address
% APERTURE_RANGE_SIZE
;
1142 int max_index
= dom
->aperture_size
>> APERTURE_RANGE_SHIFT
;
1143 int i
= start
>> APERTURE_RANGE_SHIFT
;
1144 unsigned long boundary_size
;
1145 unsigned long address
= -1;
1146 unsigned long limit
;
1148 next_bit
>>= PAGE_SHIFT
;
1150 boundary_size
= ALIGN(dma_get_seg_boundary(dev
) + 1,
1151 PAGE_SIZE
) >> PAGE_SHIFT
;
1153 for (;i
< max_index
; ++i
) {
1154 unsigned long offset
= dom
->aperture
[i
]->offset
>> PAGE_SHIFT
;
1156 if (dom
->aperture
[i
]->offset
>= dma_mask
)
1159 limit
= iommu_device_max_index(APERTURE_RANGE_PAGES
, offset
,
1160 dma_mask
>> PAGE_SHIFT
);
1162 address
= iommu_area_alloc(dom
->aperture
[i
]->bitmap
,
1163 limit
, next_bit
, pages
, 0,
1164 boundary_size
, align_mask
);
1165 if (address
!= -1) {
1166 address
= dom
->aperture
[i
]->offset
+
1167 (address
<< PAGE_SHIFT
);
1168 dom
->next_address
= address
+ (pages
<< PAGE_SHIFT
);
1178 static unsigned long dma_ops_alloc_addresses(struct device
*dev
,
1179 struct dma_ops_domain
*dom
,
1181 unsigned long align_mask
,
1184 unsigned long address
;
1186 #ifdef CONFIG_IOMMU_STRESS
1187 dom
->next_address
= 0;
1188 dom
->need_flush
= true;
1191 address
= dma_ops_area_alloc(dev
, dom
, pages
, align_mask
,
1192 dma_mask
, dom
->next_address
);
1194 if (address
== -1) {
1195 dom
->next_address
= 0;
1196 address
= dma_ops_area_alloc(dev
, dom
, pages
, align_mask
,
1198 dom
->need_flush
= true;
1201 if (unlikely(address
== -1))
1202 address
= DMA_ERROR_CODE
;
1204 WARN_ON((address
+ (PAGE_SIZE
*pages
)) > dom
->aperture_size
);
1210 * The address free function.
1212 * called with domain->lock held
1214 static void dma_ops_free_addresses(struct dma_ops_domain
*dom
,
1215 unsigned long address
,
1218 unsigned i
= address
>> APERTURE_RANGE_SHIFT
;
1219 struct aperture_range
*range
= dom
->aperture
[i
];
1221 BUG_ON(i
>= APERTURE_MAX_RANGES
|| range
== NULL
);
1223 #ifdef CONFIG_IOMMU_STRESS
1228 if (address
>= dom
->next_address
)
1229 dom
->need_flush
= true;
1231 address
= (address
% APERTURE_RANGE_SIZE
) >> PAGE_SHIFT
;
1233 bitmap_clear(range
->bitmap
, address
, pages
);
1237 /****************************************************************************
1239 * The next functions belong to the domain allocation. A domain is
1240 * allocated for every IOMMU as the default domain. If device isolation
1241 * is enabled, every device get its own domain. The most important thing
1242 * about domains is the page table mapping the DMA address space they
1245 ****************************************************************************/
1248 * This function adds a protection domain to the global protection domain list
1250 static void add_domain_to_list(struct protection_domain
*domain
)
1252 unsigned long flags
;
1254 spin_lock_irqsave(&amd_iommu_pd_lock
, flags
);
1255 list_add(&domain
->list
, &amd_iommu_pd_list
);
1256 spin_unlock_irqrestore(&amd_iommu_pd_lock
, flags
);
1260 * This function removes a protection domain to the global
1261 * protection domain list
1263 static void del_domain_from_list(struct protection_domain
*domain
)
1265 unsigned long flags
;
1267 spin_lock_irqsave(&amd_iommu_pd_lock
, flags
);
1268 list_del(&domain
->list
);
1269 spin_unlock_irqrestore(&amd_iommu_pd_lock
, flags
);
1272 static u16
domain_id_alloc(void)
1274 unsigned long flags
;
1277 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1278 id
= find_first_zero_bit(amd_iommu_pd_alloc_bitmap
, MAX_DOMAIN_ID
);
1280 if (id
> 0 && id
< MAX_DOMAIN_ID
)
1281 __set_bit(id
, amd_iommu_pd_alloc_bitmap
);
1284 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1289 static void domain_id_free(int id
)
1291 unsigned long flags
;
1293 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1294 if (id
> 0 && id
< MAX_DOMAIN_ID
)
1295 __clear_bit(id
, amd_iommu_pd_alloc_bitmap
);
1296 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1299 static void free_pagetable(struct protection_domain
*domain
)
1304 p1
= domain
->pt_root
;
1309 for (i
= 0; i
< 512; ++i
) {
1310 if (!IOMMU_PTE_PRESENT(p1
[i
]))
1313 p2
= IOMMU_PTE_PAGE(p1
[i
]);
1314 for (j
= 0; j
< 512; ++j
) {
1315 if (!IOMMU_PTE_PRESENT(p2
[j
]))
1317 p3
= IOMMU_PTE_PAGE(p2
[j
]);
1318 free_page((unsigned long)p3
);
1321 free_page((unsigned long)p2
);
1324 free_page((unsigned long)p1
);
1326 domain
->pt_root
= NULL
;
1330 * Free a domain, only used if something went wrong in the
1331 * allocation path and we need to free an already allocated page table
1333 static void dma_ops_domain_free(struct dma_ops_domain
*dom
)
1340 del_domain_from_list(&dom
->domain
);
1342 free_pagetable(&dom
->domain
);
1344 for (i
= 0; i
< APERTURE_MAX_RANGES
; ++i
) {
1345 if (!dom
->aperture
[i
])
1347 free_page((unsigned long)dom
->aperture
[i
]->bitmap
);
1348 kfree(dom
->aperture
[i
]);
1355 * Allocates a new protection domain usable for the dma_ops functions.
1356 * It also intializes the page table and the address allocator data
1357 * structures required for the dma_ops interface
1359 static struct dma_ops_domain
*dma_ops_domain_alloc(void)
1361 struct dma_ops_domain
*dma_dom
;
1363 dma_dom
= kzalloc(sizeof(struct dma_ops_domain
), GFP_KERNEL
);
1367 spin_lock_init(&dma_dom
->domain
.lock
);
1369 dma_dom
->domain
.id
= domain_id_alloc();
1370 if (dma_dom
->domain
.id
== 0)
1372 INIT_LIST_HEAD(&dma_dom
->domain
.dev_list
);
1373 dma_dom
->domain
.mode
= PAGE_MODE_2_LEVEL
;
1374 dma_dom
->domain
.pt_root
= (void *)get_zeroed_page(GFP_KERNEL
);
1375 dma_dom
->domain
.flags
= PD_DMA_OPS_MASK
;
1376 dma_dom
->domain
.priv
= dma_dom
;
1377 if (!dma_dom
->domain
.pt_root
)
1380 dma_dom
->need_flush
= false;
1381 dma_dom
->target_dev
= 0xffff;
1383 add_domain_to_list(&dma_dom
->domain
);
1385 if (alloc_new_range(dma_dom
, true, GFP_KERNEL
))
1389 * mark the first page as allocated so we never return 0 as
1390 * a valid dma-address. So we can use 0 as error value
1392 dma_dom
->aperture
[0]->bitmap
[0] = 1;
1393 dma_dom
->next_address
= 0;
1399 dma_ops_domain_free(dma_dom
);
1405 * little helper function to check whether a given protection domain is a
1408 static bool dma_ops_domain(struct protection_domain
*domain
)
1410 return domain
->flags
& PD_DMA_OPS_MASK
;
1413 static void set_dte_entry(u16 devid
, struct protection_domain
*domain
)
1415 u64 pte_root
= virt_to_phys(domain
->pt_root
);
1417 pte_root
|= (domain
->mode
& DEV_ENTRY_MODE_MASK
)
1418 << DEV_ENTRY_MODE_SHIFT
;
1419 pte_root
|= IOMMU_PTE_IR
| IOMMU_PTE_IW
| IOMMU_PTE_P
| IOMMU_PTE_TV
;
1421 amd_iommu_dev_table
[devid
].data
[2] = domain
->id
;
1422 amd_iommu_dev_table
[devid
].data
[1] = upper_32_bits(pte_root
);
1423 amd_iommu_dev_table
[devid
].data
[0] = lower_32_bits(pte_root
);
1426 static void clear_dte_entry(u16 devid
)
1428 /* remove entry from the device table seen by the hardware */
1429 amd_iommu_dev_table
[devid
].data
[0] = IOMMU_PTE_P
| IOMMU_PTE_TV
;
1430 amd_iommu_dev_table
[devid
].data
[1] = 0;
1431 amd_iommu_dev_table
[devid
].data
[2] = 0;
1433 amd_iommu_apply_erratum_63(devid
);
1436 static void do_attach(struct device
*dev
, struct protection_domain
*domain
)
1438 struct iommu_dev_data
*dev_data
;
1439 struct amd_iommu
*iommu
;
1442 devid
= get_device_id(dev
);
1443 iommu
= amd_iommu_rlookup_table
[devid
];
1444 dev_data
= get_dev_data(dev
);
1446 /* Update data structures */
1447 dev_data
->domain
= domain
;
1448 list_add(&dev_data
->list
, &domain
->dev_list
);
1449 set_dte_entry(devid
, domain
);
1451 /* Do reference counting */
1452 domain
->dev_iommu
[iommu
->index
] += 1;
1453 domain
->dev_cnt
+= 1;
1455 /* Flush the DTE entry */
1456 iommu_flush_device(dev
);
1459 static void do_detach(struct device
*dev
)
1461 struct iommu_dev_data
*dev_data
;
1462 struct amd_iommu
*iommu
;
1465 devid
= get_device_id(dev
);
1466 iommu
= amd_iommu_rlookup_table
[devid
];
1467 dev_data
= get_dev_data(dev
);
1469 /* decrease reference counters */
1470 dev_data
->domain
->dev_iommu
[iommu
->index
] -= 1;
1471 dev_data
->domain
->dev_cnt
-= 1;
1473 /* Update data structures */
1474 dev_data
->domain
= NULL
;
1475 list_del(&dev_data
->list
);
1476 clear_dte_entry(devid
);
1478 /* Flush the DTE entry */
1479 iommu_flush_device(dev
);
1483 * If a device is not yet associated with a domain, this function does
1484 * assigns it visible for the hardware
1486 static int __attach_device(struct device
*dev
,
1487 struct protection_domain
*domain
)
1489 struct iommu_dev_data
*dev_data
, *alias_data
;
1492 dev_data
= get_dev_data(dev
);
1493 alias_data
= get_dev_data(dev_data
->alias
);
1499 spin_lock(&domain
->lock
);
1501 /* Some sanity checks */
1503 if (alias_data
->domain
!= NULL
&&
1504 alias_data
->domain
!= domain
)
1507 if (dev_data
->domain
!= NULL
&&
1508 dev_data
->domain
!= domain
)
1511 /* Do real assignment */
1512 if (dev_data
->alias
!= dev
) {
1513 alias_data
= get_dev_data(dev_data
->alias
);
1514 if (alias_data
->domain
== NULL
)
1515 do_attach(dev_data
->alias
, domain
);
1517 atomic_inc(&alias_data
->bind
);
1520 if (dev_data
->domain
== NULL
)
1521 do_attach(dev
, domain
);
1523 atomic_inc(&dev_data
->bind
);
1530 spin_unlock(&domain
->lock
);
1536 * If a device is not yet associated with a domain, this function does
1537 * assigns it visible for the hardware
1539 static int attach_device(struct device
*dev
,
1540 struct protection_domain
*domain
)
1542 unsigned long flags
;
1545 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1546 ret
= __attach_device(dev
, domain
);
1547 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1550 * We might boot into a crash-kernel here. The crashed kernel
1551 * left the caches in the IOMMU dirty. So we have to flush
1552 * here to evict all dirty stuff.
1554 iommu_flush_tlb_pde(domain
);
1560 * Removes a device from a protection domain (unlocked)
1562 static void __detach_device(struct device
*dev
)
1564 struct iommu_dev_data
*dev_data
= get_dev_data(dev
);
1565 struct iommu_dev_data
*alias_data
;
1566 struct protection_domain
*domain
;
1567 unsigned long flags
;
1569 BUG_ON(!dev_data
->domain
);
1571 domain
= dev_data
->domain
;
1573 spin_lock_irqsave(&domain
->lock
, flags
);
1575 if (dev_data
->alias
!= dev
) {
1576 alias_data
= get_dev_data(dev_data
->alias
);
1577 if (atomic_dec_and_test(&alias_data
->bind
))
1578 do_detach(dev_data
->alias
);
1581 if (atomic_dec_and_test(&dev_data
->bind
))
1584 spin_unlock_irqrestore(&domain
->lock
, flags
);
1587 * If we run in passthrough mode the device must be assigned to the
1588 * passthrough domain if it is detached from any other domain.
1589 * Make sure we can deassign from the pt_domain itself.
1591 if (iommu_pass_through
&&
1592 (dev_data
->domain
== NULL
&& domain
!= pt_domain
))
1593 __attach_device(dev
, pt_domain
);
1597 * Removes a device from a protection domain (with devtable_lock held)
1599 static void detach_device(struct device
*dev
)
1601 unsigned long flags
;
1603 /* lock device table */
1604 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1605 __detach_device(dev
);
1606 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1610 * Find out the protection domain structure for a given PCI device. This
1611 * will give us the pointer to the page table root for example.
1613 static struct protection_domain
*domain_for_device(struct device
*dev
)
1615 struct protection_domain
*dom
;
1616 struct iommu_dev_data
*dev_data
, *alias_data
;
1617 unsigned long flags
;
1620 devid
= get_device_id(dev
);
1621 alias
= amd_iommu_alias_table
[devid
];
1622 dev_data
= get_dev_data(dev
);
1623 alias_data
= get_dev_data(dev_data
->alias
);
1627 read_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1628 dom
= dev_data
->domain
;
1630 alias_data
->domain
!= NULL
) {
1631 __attach_device(dev
, alias_data
->domain
);
1632 dom
= alias_data
->domain
;
1635 read_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1640 static int device_change_notifier(struct notifier_block
*nb
,
1641 unsigned long action
, void *data
)
1643 struct device
*dev
= data
;
1645 struct protection_domain
*domain
;
1646 struct dma_ops_domain
*dma_domain
;
1647 struct amd_iommu
*iommu
;
1648 unsigned long flags
;
1650 if (!check_device(dev
))
1653 devid
= get_device_id(dev
);
1654 iommu
= amd_iommu_rlookup_table
[devid
];
1657 case BUS_NOTIFY_UNBOUND_DRIVER
:
1659 domain
= domain_for_device(dev
);
1663 if (iommu_pass_through
)
1667 case BUS_NOTIFY_ADD_DEVICE
:
1669 iommu_init_device(dev
);
1671 domain
= domain_for_device(dev
);
1673 /* allocate a protection domain if a device is added */
1674 dma_domain
= find_protection_domain(devid
);
1677 dma_domain
= dma_ops_domain_alloc();
1680 dma_domain
->target_dev
= devid
;
1682 spin_lock_irqsave(&iommu_pd_list_lock
, flags
);
1683 list_add_tail(&dma_domain
->list
, &iommu_pd_list
);
1684 spin_unlock_irqrestore(&iommu_pd_list_lock
, flags
);
1687 case BUS_NOTIFY_DEL_DEVICE
:
1689 iommu_uninit_device(dev
);
1695 iommu_flush_device(dev
);
1696 iommu_completion_wait(iommu
);
1702 static struct notifier_block device_nb
= {
1703 .notifier_call
= device_change_notifier
,
1706 void amd_iommu_init_notifier(void)
1708 bus_register_notifier(&pci_bus_type
, &device_nb
);
1711 /*****************************************************************************
1713 * The next functions belong to the dma_ops mapping/unmapping code.
1715 *****************************************************************************/
1718 * In the dma_ops path we only have the struct device. This function
1719 * finds the corresponding IOMMU, the protection domain and the
1720 * requestor id for a given device.
1721 * If the device is not yet associated with a domain this is also done
1724 static struct protection_domain
*get_domain(struct device
*dev
)
1726 struct protection_domain
*domain
;
1727 struct dma_ops_domain
*dma_dom
;
1728 u16 devid
= get_device_id(dev
);
1730 if (!check_device(dev
))
1731 return ERR_PTR(-EINVAL
);
1733 domain
= domain_for_device(dev
);
1734 if (domain
!= NULL
&& !dma_ops_domain(domain
))
1735 return ERR_PTR(-EBUSY
);
1740 /* Device not bount yet - bind it */
1741 dma_dom
= find_protection_domain(devid
);
1743 dma_dom
= amd_iommu_rlookup_table
[devid
]->default_dom
;
1744 attach_device(dev
, &dma_dom
->domain
);
1745 DUMP_printk("Using protection domain %d for device %s\n",
1746 dma_dom
->domain
.id
, dev_name(dev
));
1748 return &dma_dom
->domain
;
1751 static void update_device_table(struct protection_domain
*domain
)
1753 struct iommu_dev_data
*dev_data
;
1755 list_for_each_entry(dev_data
, &domain
->dev_list
, list
) {
1756 u16 devid
= get_device_id(dev_data
->dev
);
1757 set_dte_entry(devid
, domain
);
1761 static void update_domain(struct protection_domain
*domain
)
1763 if (!domain
->updated
)
1766 update_device_table(domain
);
1767 iommu_flush_domain_devices(domain
);
1768 iommu_flush_tlb_pde(domain
);
1770 domain
->updated
= false;
1774 * This function fetches the PTE for a given address in the aperture
1776 static u64
* dma_ops_get_pte(struct dma_ops_domain
*dom
,
1777 unsigned long address
)
1779 struct aperture_range
*aperture
;
1780 u64
*pte
, *pte_page
;
1782 aperture
= dom
->aperture
[APERTURE_RANGE_INDEX(address
)];
1786 pte
= aperture
->pte_pages
[APERTURE_PAGE_INDEX(address
)];
1788 pte
= alloc_pte(&dom
->domain
, address
, PAGE_SIZE
, &pte_page
,
1790 aperture
->pte_pages
[APERTURE_PAGE_INDEX(address
)] = pte_page
;
1792 pte
+= PM_LEVEL_INDEX(0, address
);
1794 update_domain(&dom
->domain
);
1800 * This is the generic map function. It maps one 4kb page at paddr to
1801 * the given address in the DMA address space for the domain.
1803 static dma_addr_t
dma_ops_domain_map(struct dma_ops_domain
*dom
,
1804 unsigned long address
,
1810 WARN_ON(address
> dom
->aperture_size
);
1814 pte
= dma_ops_get_pte(dom
, address
);
1816 return DMA_ERROR_CODE
;
1818 __pte
= paddr
| IOMMU_PTE_P
| IOMMU_PTE_FC
;
1820 if (direction
== DMA_TO_DEVICE
)
1821 __pte
|= IOMMU_PTE_IR
;
1822 else if (direction
== DMA_FROM_DEVICE
)
1823 __pte
|= IOMMU_PTE_IW
;
1824 else if (direction
== DMA_BIDIRECTIONAL
)
1825 __pte
|= IOMMU_PTE_IR
| IOMMU_PTE_IW
;
1831 return (dma_addr_t
)address
;
1835 * The generic unmapping function for on page in the DMA address space.
1837 static void dma_ops_domain_unmap(struct dma_ops_domain
*dom
,
1838 unsigned long address
)
1840 struct aperture_range
*aperture
;
1843 if (address
>= dom
->aperture_size
)
1846 aperture
= dom
->aperture
[APERTURE_RANGE_INDEX(address
)];
1850 pte
= aperture
->pte_pages
[APERTURE_PAGE_INDEX(address
)];
1854 pte
+= PM_LEVEL_INDEX(0, address
);
1862 * This function contains common code for mapping of a physically
1863 * contiguous memory region into DMA address space. It is used by all
1864 * mapping functions provided with this IOMMU driver.
1865 * Must be called with the domain lock held.
1867 static dma_addr_t
__map_single(struct device
*dev
,
1868 struct dma_ops_domain
*dma_dom
,
1875 dma_addr_t offset
= paddr
& ~PAGE_MASK
;
1876 dma_addr_t address
, start
, ret
;
1878 unsigned long align_mask
= 0;
1881 pages
= iommu_num_pages(paddr
, size
, PAGE_SIZE
);
1884 INC_STATS_COUNTER(total_map_requests
);
1887 INC_STATS_COUNTER(cross_page
);
1890 align_mask
= (1UL << get_order(size
)) - 1;
1893 address
= dma_ops_alloc_addresses(dev
, dma_dom
, pages
, align_mask
,
1895 if (unlikely(address
== DMA_ERROR_CODE
)) {
1897 * setting next_address here will let the address
1898 * allocator only scan the new allocated range in the
1899 * first run. This is a small optimization.
1901 dma_dom
->next_address
= dma_dom
->aperture_size
;
1903 if (alloc_new_range(dma_dom
, false, GFP_ATOMIC
))
1907 * aperture was successfully enlarged by 128 MB, try
1914 for (i
= 0; i
< pages
; ++i
) {
1915 ret
= dma_ops_domain_map(dma_dom
, start
, paddr
, dir
);
1916 if (ret
== DMA_ERROR_CODE
)
1924 ADD_STATS_COUNTER(alloced_io_mem
, size
);
1926 if (unlikely(dma_dom
->need_flush
&& !amd_iommu_unmap_flush
)) {
1927 iommu_flush_tlb(&dma_dom
->domain
);
1928 dma_dom
->need_flush
= false;
1929 } else if (unlikely(amd_iommu_np_cache
))
1930 iommu_flush_pages(&dma_dom
->domain
, address
, size
);
1937 for (--i
; i
>= 0; --i
) {
1939 dma_ops_domain_unmap(dma_dom
, start
);
1942 dma_ops_free_addresses(dma_dom
, address
, pages
);
1944 return DMA_ERROR_CODE
;
1948 * Does the reverse of the __map_single function. Must be called with
1949 * the domain lock held too
1951 static void __unmap_single(struct dma_ops_domain
*dma_dom
,
1952 dma_addr_t dma_addr
,
1956 dma_addr_t flush_addr
;
1957 dma_addr_t i
, start
;
1960 if ((dma_addr
== DMA_ERROR_CODE
) ||
1961 (dma_addr
+ size
> dma_dom
->aperture_size
))
1964 flush_addr
= dma_addr
;
1965 pages
= iommu_num_pages(dma_addr
, size
, PAGE_SIZE
);
1966 dma_addr
&= PAGE_MASK
;
1969 for (i
= 0; i
< pages
; ++i
) {
1970 dma_ops_domain_unmap(dma_dom
, start
);
1974 SUB_STATS_COUNTER(alloced_io_mem
, size
);
1976 dma_ops_free_addresses(dma_dom
, dma_addr
, pages
);
1978 if (amd_iommu_unmap_flush
|| dma_dom
->need_flush
) {
1979 iommu_flush_pages(&dma_dom
->domain
, flush_addr
, size
);
1980 dma_dom
->need_flush
= false;
1985 * The exported map_single function for dma_ops.
1987 static dma_addr_t
map_page(struct device
*dev
, struct page
*page
,
1988 unsigned long offset
, size_t size
,
1989 enum dma_data_direction dir
,
1990 struct dma_attrs
*attrs
)
1992 unsigned long flags
;
1993 struct protection_domain
*domain
;
1996 phys_addr_t paddr
= page_to_phys(page
) + offset
;
1998 INC_STATS_COUNTER(cnt_map_single
);
2000 domain
= get_domain(dev
);
2001 if (PTR_ERR(domain
) == -EINVAL
)
2002 return (dma_addr_t
)paddr
;
2003 else if (IS_ERR(domain
))
2004 return DMA_ERROR_CODE
;
2006 dma_mask
= *dev
->dma_mask
;
2008 spin_lock_irqsave(&domain
->lock
, flags
);
2010 addr
= __map_single(dev
, domain
->priv
, paddr
, size
, dir
, false,
2012 if (addr
== DMA_ERROR_CODE
)
2015 iommu_flush_complete(domain
);
2018 spin_unlock_irqrestore(&domain
->lock
, flags
);
2024 * The exported unmap_single function for dma_ops.
2026 static void unmap_page(struct device
*dev
, dma_addr_t dma_addr
, size_t size
,
2027 enum dma_data_direction dir
, struct dma_attrs
*attrs
)
2029 unsigned long flags
;
2030 struct protection_domain
*domain
;
2032 INC_STATS_COUNTER(cnt_unmap_single
);
2034 domain
= get_domain(dev
);
2038 spin_lock_irqsave(&domain
->lock
, flags
);
2040 __unmap_single(domain
->priv
, dma_addr
, size
, dir
);
2042 iommu_flush_complete(domain
);
2044 spin_unlock_irqrestore(&domain
->lock
, flags
);
2048 * This is a special map_sg function which is used if we should map a
2049 * device which is not handled by an AMD IOMMU in the system.
2051 static int map_sg_no_iommu(struct device
*dev
, struct scatterlist
*sglist
,
2052 int nelems
, int dir
)
2054 struct scatterlist
*s
;
2057 for_each_sg(sglist
, s
, nelems
, i
) {
2058 s
->dma_address
= (dma_addr_t
)sg_phys(s
);
2059 s
->dma_length
= s
->length
;
2066 * The exported map_sg function for dma_ops (handles scatter-gather
2069 static int map_sg(struct device
*dev
, struct scatterlist
*sglist
,
2070 int nelems
, enum dma_data_direction dir
,
2071 struct dma_attrs
*attrs
)
2073 unsigned long flags
;
2074 struct protection_domain
*domain
;
2076 struct scatterlist
*s
;
2078 int mapped_elems
= 0;
2081 INC_STATS_COUNTER(cnt_map_sg
);
2083 domain
= get_domain(dev
);
2084 if (PTR_ERR(domain
) == -EINVAL
)
2085 return map_sg_no_iommu(dev
, sglist
, nelems
, dir
);
2086 else if (IS_ERR(domain
))
2089 dma_mask
= *dev
->dma_mask
;
2091 spin_lock_irqsave(&domain
->lock
, flags
);
2093 for_each_sg(sglist
, s
, nelems
, i
) {
2096 s
->dma_address
= __map_single(dev
, domain
->priv
,
2097 paddr
, s
->length
, dir
, false,
2100 if (s
->dma_address
) {
2101 s
->dma_length
= s
->length
;
2107 iommu_flush_complete(domain
);
2110 spin_unlock_irqrestore(&domain
->lock
, flags
);
2112 return mapped_elems
;
2114 for_each_sg(sglist
, s
, mapped_elems
, i
) {
2116 __unmap_single(domain
->priv
, s
->dma_address
,
2117 s
->dma_length
, dir
);
2118 s
->dma_address
= s
->dma_length
= 0;
2127 * The exported map_sg function for dma_ops (handles scatter-gather
2130 static void unmap_sg(struct device
*dev
, struct scatterlist
*sglist
,
2131 int nelems
, enum dma_data_direction dir
,
2132 struct dma_attrs
*attrs
)
2134 unsigned long flags
;
2135 struct protection_domain
*domain
;
2136 struct scatterlist
*s
;
2139 INC_STATS_COUNTER(cnt_unmap_sg
);
2141 domain
= get_domain(dev
);
2145 spin_lock_irqsave(&domain
->lock
, flags
);
2147 for_each_sg(sglist
, s
, nelems
, i
) {
2148 __unmap_single(domain
->priv
, s
->dma_address
,
2149 s
->dma_length
, dir
);
2150 s
->dma_address
= s
->dma_length
= 0;
2153 iommu_flush_complete(domain
);
2155 spin_unlock_irqrestore(&domain
->lock
, flags
);
2159 * The exported alloc_coherent function for dma_ops.
2161 static void *alloc_coherent(struct device
*dev
, size_t size
,
2162 dma_addr_t
*dma_addr
, gfp_t flag
)
2164 unsigned long flags
;
2166 struct protection_domain
*domain
;
2168 u64 dma_mask
= dev
->coherent_dma_mask
;
2170 INC_STATS_COUNTER(cnt_alloc_coherent
);
2172 domain
= get_domain(dev
);
2173 if (PTR_ERR(domain
) == -EINVAL
) {
2174 virt_addr
= (void *)__get_free_pages(flag
, get_order(size
));
2175 *dma_addr
= __pa(virt_addr
);
2177 } else if (IS_ERR(domain
))
2180 dma_mask
= dev
->coherent_dma_mask
;
2181 flag
&= ~(__GFP_DMA
| __GFP_HIGHMEM
| __GFP_DMA32
);
2184 virt_addr
= (void *)__get_free_pages(flag
, get_order(size
));
2188 paddr
= virt_to_phys(virt_addr
);
2191 dma_mask
= *dev
->dma_mask
;
2193 spin_lock_irqsave(&domain
->lock
, flags
);
2195 *dma_addr
= __map_single(dev
, domain
->priv
, paddr
,
2196 size
, DMA_BIDIRECTIONAL
, true, dma_mask
);
2198 if (*dma_addr
== DMA_ERROR_CODE
) {
2199 spin_unlock_irqrestore(&domain
->lock
, flags
);
2203 iommu_flush_complete(domain
);
2205 spin_unlock_irqrestore(&domain
->lock
, flags
);
2211 free_pages((unsigned long)virt_addr
, get_order(size
));
2217 * The exported free_coherent function for dma_ops.
2219 static void free_coherent(struct device
*dev
, size_t size
,
2220 void *virt_addr
, dma_addr_t dma_addr
)
2222 unsigned long flags
;
2223 struct protection_domain
*domain
;
2225 INC_STATS_COUNTER(cnt_free_coherent
);
2227 domain
= get_domain(dev
);
2231 spin_lock_irqsave(&domain
->lock
, flags
);
2233 __unmap_single(domain
->priv
, dma_addr
, size
, DMA_BIDIRECTIONAL
);
2235 iommu_flush_complete(domain
);
2237 spin_unlock_irqrestore(&domain
->lock
, flags
);
2240 free_pages((unsigned long)virt_addr
, get_order(size
));
2244 * This function is called by the DMA layer to find out if we can handle a
2245 * particular device. It is part of the dma_ops.
2247 static int amd_iommu_dma_supported(struct device
*dev
, u64 mask
)
2249 return check_device(dev
);
2253 * The function for pre-allocating protection domains.
2255 * If the driver core informs the DMA layer if a driver grabs a device
2256 * we don't need to preallocate the protection domains anymore.
2257 * For now we have to.
2259 static void prealloc_protection_domains(void)
2261 struct pci_dev
*dev
= NULL
;
2262 struct dma_ops_domain
*dma_dom
;
2265 for_each_pci_dev(dev
) {
2267 /* Do we handle this device? */
2268 if (!check_device(&dev
->dev
))
2271 /* Is there already any domain for it? */
2272 if (domain_for_device(&dev
->dev
))
2275 devid
= get_device_id(&dev
->dev
);
2277 dma_dom
= dma_ops_domain_alloc();
2280 init_unity_mappings_for_device(dma_dom
, devid
);
2281 dma_dom
->target_dev
= devid
;
2283 attach_device(&dev
->dev
, &dma_dom
->domain
);
2285 list_add_tail(&dma_dom
->list
, &iommu_pd_list
);
2289 static struct dma_map_ops amd_iommu_dma_ops
= {
2290 .alloc_coherent
= alloc_coherent
,
2291 .free_coherent
= free_coherent
,
2292 .map_page
= map_page
,
2293 .unmap_page
= unmap_page
,
2295 .unmap_sg
= unmap_sg
,
2296 .dma_supported
= amd_iommu_dma_supported
,
2300 * The function which clues the AMD IOMMU driver into dma_ops.
2303 void __init
amd_iommu_init_api(void)
2305 register_iommu(&amd_iommu_ops
);
2308 int __init
amd_iommu_init_dma_ops(void)
2310 struct amd_iommu
*iommu
;
2314 * first allocate a default protection domain for every IOMMU we
2315 * found in the system. Devices not assigned to any other
2316 * protection domain will be assigned to the default one.
2318 for_each_iommu(iommu
) {
2319 iommu
->default_dom
= dma_ops_domain_alloc();
2320 if (iommu
->default_dom
== NULL
)
2322 iommu
->default_dom
->domain
.flags
|= PD_DEFAULT_MASK
;
2323 ret
= iommu_init_unity_mappings(iommu
);
2329 * Pre-allocate the protection domains for each device.
2331 prealloc_protection_domains();
2336 /* Make the driver finally visible to the drivers */
2337 dma_ops
= &amd_iommu_dma_ops
;
2339 amd_iommu_stats_init();
2345 for_each_iommu(iommu
) {
2346 if (iommu
->default_dom
)
2347 dma_ops_domain_free(iommu
->default_dom
);
2353 /*****************************************************************************
2355 * The following functions belong to the exported interface of AMD IOMMU
2357 * This interface allows access to lower level functions of the IOMMU
2358 * like protection domain handling and assignement of devices to domains
2359 * which is not possible with the dma_ops interface.
2361 *****************************************************************************/
2363 static void cleanup_domain(struct protection_domain
*domain
)
2365 struct iommu_dev_data
*dev_data
, *next
;
2366 unsigned long flags
;
2368 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
2370 list_for_each_entry_safe(dev_data
, next
, &domain
->dev_list
, list
) {
2371 struct device
*dev
= dev_data
->dev
;
2373 __detach_device(dev
);
2374 atomic_set(&dev_data
->bind
, 0);
2377 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
2380 static void protection_domain_free(struct protection_domain
*domain
)
2385 del_domain_from_list(domain
);
2388 domain_id_free(domain
->id
);
2393 static struct protection_domain
*protection_domain_alloc(void)
2395 struct protection_domain
*domain
;
2397 domain
= kzalloc(sizeof(*domain
), GFP_KERNEL
);
2401 spin_lock_init(&domain
->lock
);
2402 mutex_init(&domain
->api_lock
);
2403 domain
->id
= domain_id_alloc();
2406 INIT_LIST_HEAD(&domain
->dev_list
);
2408 add_domain_to_list(domain
);
2418 static int amd_iommu_domain_init(struct iommu_domain
*dom
)
2420 struct protection_domain
*domain
;
2422 domain
= protection_domain_alloc();
2426 domain
->mode
= PAGE_MODE_3_LEVEL
;
2427 domain
->pt_root
= (void *)get_zeroed_page(GFP_KERNEL
);
2428 if (!domain
->pt_root
)
2436 protection_domain_free(domain
);
2441 static void amd_iommu_domain_destroy(struct iommu_domain
*dom
)
2443 struct protection_domain
*domain
= dom
->priv
;
2448 if (domain
->dev_cnt
> 0)
2449 cleanup_domain(domain
);
2451 BUG_ON(domain
->dev_cnt
!= 0);
2453 free_pagetable(domain
);
2455 protection_domain_free(domain
);
2460 static void amd_iommu_detach_device(struct iommu_domain
*dom
,
2463 struct iommu_dev_data
*dev_data
= dev
->archdata
.iommu
;
2464 struct amd_iommu
*iommu
;
2467 if (!check_device(dev
))
2470 devid
= get_device_id(dev
);
2472 if (dev_data
->domain
!= NULL
)
2475 iommu
= amd_iommu_rlookup_table
[devid
];
2479 iommu_flush_device(dev
);
2480 iommu_completion_wait(iommu
);
2483 static int amd_iommu_attach_device(struct iommu_domain
*dom
,
2486 struct protection_domain
*domain
= dom
->priv
;
2487 struct iommu_dev_data
*dev_data
;
2488 struct amd_iommu
*iommu
;
2492 if (!check_device(dev
))
2495 dev_data
= dev
->archdata
.iommu
;
2497 devid
= get_device_id(dev
);
2499 iommu
= amd_iommu_rlookup_table
[devid
];
2503 if (dev_data
->domain
)
2506 ret
= attach_device(dev
, domain
);
2508 iommu_completion_wait(iommu
);
2513 static int amd_iommu_map(struct iommu_domain
*dom
, unsigned long iova
,
2514 phys_addr_t paddr
, int gfp_order
, int iommu_prot
)
2516 unsigned long page_size
= 0x1000UL
<< gfp_order
;
2517 struct protection_domain
*domain
= dom
->priv
;
2521 if (iommu_prot
& IOMMU_READ
)
2522 prot
|= IOMMU_PROT_IR
;
2523 if (iommu_prot
& IOMMU_WRITE
)
2524 prot
|= IOMMU_PROT_IW
;
2526 mutex_lock(&domain
->api_lock
);
2527 ret
= iommu_map_page(domain
, iova
, paddr
, prot
, page_size
);
2528 mutex_unlock(&domain
->api_lock
);
2533 static int amd_iommu_unmap(struct iommu_domain
*dom
, unsigned long iova
,
2536 struct protection_domain
*domain
= dom
->priv
;
2537 unsigned long page_size
, unmap_size
;
2539 page_size
= 0x1000UL
<< gfp_order
;
2541 mutex_lock(&domain
->api_lock
);
2542 unmap_size
= iommu_unmap_page(domain
, iova
, page_size
);
2543 mutex_unlock(&domain
->api_lock
);
2545 iommu_flush_tlb_pde(domain
);
2547 return get_order(unmap_size
);
2550 static phys_addr_t
amd_iommu_iova_to_phys(struct iommu_domain
*dom
,
2553 struct protection_domain
*domain
= dom
->priv
;
2554 unsigned long offset_mask
;
2558 pte
= fetch_pte(domain
, iova
);
2560 if (!pte
|| !IOMMU_PTE_PRESENT(*pte
))
2563 if (PM_PTE_LEVEL(*pte
) == 0)
2564 offset_mask
= PAGE_SIZE
- 1;
2566 offset_mask
= PTE_PAGE_SIZE(*pte
) - 1;
2568 __pte
= *pte
& PM_ADDR_MASK
;
2569 paddr
= (__pte
& ~offset_mask
) | (iova
& offset_mask
);
2574 static int amd_iommu_domain_has_cap(struct iommu_domain
*domain
,
2578 case IOMMU_CAP_CACHE_COHERENCY
:
2585 static struct iommu_ops amd_iommu_ops
= {
2586 .domain_init
= amd_iommu_domain_init
,
2587 .domain_destroy
= amd_iommu_domain_destroy
,
2588 .attach_dev
= amd_iommu_attach_device
,
2589 .detach_dev
= amd_iommu_detach_device
,
2590 .map
= amd_iommu_map
,
2591 .unmap
= amd_iommu_unmap
,
2592 .iova_to_phys
= amd_iommu_iova_to_phys
,
2593 .domain_has_cap
= amd_iommu_domain_has_cap
,
2596 /*****************************************************************************
2598 * The next functions do a basic initialization of IOMMU for pass through
2601 * In passthrough mode the IOMMU is initialized and enabled but not used for
2602 * DMA-API translation.
2604 *****************************************************************************/
2606 int __init
amd_iommu_init_passthrough(void)
2608 struct amd_iommu
*iommu
;
2609 struct pci_dev
*dev
= NULL
;
2612 /* allocate passthrough domain */
2613 pt_domain
= protection_domain_alloc();
2617 pt_domain
->mode
|= PAGE_MODE_NONE
;
2619 for_each_pci_dev(dev
) {
2620 if (!check_device(&dev
->dev
))
2623 devid
= get_device_id(&dev
->dev
);
2625 iommu
= amd_iommu_rlookup_table
[devid
];
2629 attach_device(&dev
->dev
, pt_domain
);
2632 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");