mm: stack based kmap_atomic()
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / i915 / i915_gem.c
blobeb6c473c6d1b40f9d55f6cb77f6c72f43ece9b5b
1 /*
2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
28 #include "drmP.h"
29 #include "drm.h"
30 #include "i915_drm.h"
31 #include "i915_drv.h"
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/slab.h>
35 #include <linux/swap.h>
36 #include <linux/pci.h>
37 #include <linux/intel-gtt.h>
39 static uint32_t i915_gem_get_gtt_alignment(struct drm_gem_object *obj);
40 static int i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj);
41 static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj);
42 static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj);
43 static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj,
44 int write);
45 static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
46 uint64_t offset,
47 uint64_t size);
48 static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj);
49 static int i915_gem_object_wait_rendering(struct drm_gem_object *obj);
50 static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj,
51 unsigned alignment);
52 static void i915_gem_clear_fence_reg(struct drm_gem_object *obj);
53 static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
54 struct drm_i915_gem_pwrite *args,
55 struct drm_file *file_priv);
56 static void i915_gem_free_object_tail(struct drm_gem_object *obj);
58 static LIST_HEAD(shrink_list);
59 static DEFINE_SPINLOCK(shrink_list_lock);
61 static inline bool
62 i915_gem_object_is_inactive(struct drm_i915_gem_object *obj_priv)
64 return obj_priv->gtt_space &&
65 !obj_priv->active &&
66 obj_priv->pin_count == 0;
69 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
70 unsigned long end)
72 drm_i915_private_t *dev_priv = dev->dev_private;
74 if (start >= end ||
75 (start & (PAGE_SIZE - 1)) != 0 ||
76 (end & (PAGE_SIZE - 1)) != 0) {
77 return -EINVAL;
80 drm_mm_init(&dev_priv->mm.gtt_space, start,
81 end - start);
83 dev->gtt_total = (uint32_t) (end - start);
85 return 0;
88 int
89 i915_gem_init_ioctl(struct drm_device *dev, void *data,
90 struct drm_file *file_priv)
92 struct drm_i915_gem_init *args = data;
93 int ret;
95 mutex_lock(&dev->struct_mutex);
96 ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end);
97 mutex_unlock(&dev->struct_mutex);
99 return ret;
103 i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
104 struct drm_file *file_priv)
106 struct drm_i915_gem_get_aperture *args = data;
108 if (!(dev->driver->driver_features & DRIVER_GEM))
109 return -ENODEV;
111 args->aper_size = dev->gtt_total;
112 args->aper_available_size = (args->aper_size -
113 atomic_read(&dev->pin_memory));
115 return 0;
120 * Creates a new mm object and returns a handle to it.
123 i915_gem_create_ioctl(struct drm_device *dev, void *data,
124 struct drm_file *file_priv)
126 struct drm_i915_gem_create *args = data;
127 struct drm_gem_object *obj;
128 int ret;
129 u32 handle;
131 args->size = roundup(args->size, PAGE_SIZE);
133 /* Allocate the new object */
134 obj = i915_gem_alloc_object(dev, args->size);
135 if (obj == NULL)
136 return -ENOMEM;
138 ret = drm_gem_handle_create(file_priv, obj, &handle);
139 /* drop reference from allocate - handle holds it now */
140 drm_gem_object_unreference_unlocked(obj);
141 if (ret) {
142 return ret;
145 args->handle = handle;
146 return 0;
149 static inline int
150 fast_shmem_read(struct page **pages,
151 loff_t page_base, int page_offset,
152 char __user *data,
153 int length)
155 char __iomem *vaddr;
156 int unwritten;
158 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT]);
159 if (vaddr == NULL)
160 return -ENOMEM;
161 unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length);
162 kunmap_atomic(vaddr);
164 if (unwritten)
165 return -EFAULT;
167 return 0;
170 static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj)
172 drm_i915_private_t *dev_priv = obj->dev->dev_private;
173 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
175 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
176 obj_priv->tiling_mode != I915_TILING_NONE;
179 static inline void
180 slow_shmem_copy(struct page *dst_page,
181 int dst_offset,
182 struct page *src_page,
183 int src_offset,
184 int length)
186 char *dst_vaddr, *src_vaddr;
188 dst_vaddr = kmap(dst_page);
189 src_vaddr = kmap(src_page);
191 memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length);
193 kunmap(src_page);
194 kunmap(dst_page);
197 static inline void
198 slow_shmem_bit17_copy(struct page *gpu_page,
199 int gpu_offset,
200 struct page *cpu_page,
201 int cpu_offset,
202 int length,
203 int is_read)
205 char *gpu_vaddr, *cpu_vaddr;
207 /* Use the unswizzled path if this page isn't affected. */
208 if ((page_to_phys(gpu_page) & (1 << 17)) == 0) {
209 if (is_read)
210 return slow_shmem_copy(cpu_page, cpu_offset,
211 gpu_page, gpu_offset, length);
212 else
213 return slow_shmem_copy(gpu_page, gpu_offset,
214 cpu_page, cpu_offset, length);
217 gpu_vaddr = kmap(gpu_page);
218 cpu_vaddr = kmap(cpu_page);
220 /* Copy the data, XORing A6 with A17 (1). The user already knows he's
221 * XORing with the other bits (A9 for Y, A9 and A10 for X)
223 while (length > 0) {
224 int cacheline_end = ALIGN(gpu_offset + 1, 64);
225 int this_length = min(cacheline_end - gpu_offset, length);
226 int swizzled_gpu_offset = gpu_offset ^ 64;
228 if (is_read) {
229 memcpy(cpu_vaddr + cpu_offset,
230 gpu_vaddr + swizzled_gpu_offset,
231 this_length);
232 } else {
233 memcpy(gpu_vaddr + swizzled_gpu_offset,
234 cpu_vaddr + cpu_offset,
235 this_length);
237 cpu_offset += this_length;
238 gpu_offset += this_length;
239 length -= this_length;
242 kunmap(cpu_page);
243 kunmap(gpu_page);
247 * This is the fast shmem pread path, which attempts to copy_from_user directly
248 * from the backing pages of the object to the user's address space. On a
249 * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow().
251 static int
252 i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj,
253 struct drm_i915_gem_pread *args,
254 struct drm_file *file_priv)
256 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
257 ssize_t remain;
258 loff_t offset, page_base;
259 char __user *user_data;
260 int page_offset, page_length;
261 int ret;
263 user_data = (char __user *) (uintptr_t) args->data_ptr;
264 remain = args->size;
266 mutex_lock(&dev->struct_mutex);
268 ret = i915_gem_object_get_pages(obj, 0);
269 if (ret != 0)
270 goto fail_unlock;
272 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
273 args->size);
274 if (ret != 0)
275 goto fail_put_pages;
277 obj_priv = to_intel_bo(obj);
278 offset = args->offset;
280 while (remain > 0) {
281 /* Operation in this page
283 * page_base = page offset within aperture
284 * page_offset = offset within page
285 * page_length = bytes to copy for this page
287 page_base = (offset & ~(PAGE_SIZE-1));
288 page_offset = offset & (PAGE_SIZE-1);
289 page_length = remain;
290 if ((page_offset + remain) > PAGE_SIZE)
291 page_length = PAGE_SIZE - page_offset;
293 ret = fast_shmem_read(obj_priv->pages,
294 page_base, page_offset,
295 user_data, page_length);
296 if (ret)
297 goto fail_put_pages;
299 remain -= page_length;
300 user_data += page_length;
301 offset += page_length;
304 fail_put_pages:
305 i915_gem_object_put_pages(obj);
306 fail_unlock:
307 mutex_unlock(&dev->struct_mutex);
309 return ret;
312 static int
313 i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj)
315 int ret;
317 ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN);
319 /* If we've insufficient memory to map in the pages, attempt
320 * to make some space by throwing out some old buffers.
322 if (ret == -ENOMEM) {
323 struct drm_device *dev = obj->dev;
325 ret = i915_gem_evict_something(dev, obj->size,
326 i915_gem_get_gtt_alignment(obj));
327 if (ret)
328 return ret;
330 ret = i915_gem_object_get_pages(obj, 0);
333 return ret;
337 * This is the fallback shmem pread path, which allocates temporary storage
338 * in kernel space to copy_to_user into outside of the struct_mutex, so we
339 * can copy out of the object's backing pages while holding the struct mutex
340 * and not take page faults.
342 static int
343 i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj,
344 struct drm_i915_gem_pread *args,
345 struct drm_file *file_priv)
347 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
348 struct mm_struct *mm = current->mm;
349 struct page **user_pages;
350 ssize_t remain;
351 loff_t offset, pinned_pages, i;
352 loff_t first_data_page, last_data_page, num_pages;
353 int shmem_page_index, shmem_page_offset;
354 int data_page_index, data_page_offset;
355 int page_length;
356 int ret;
357 uint64_t data_ptr = args->data_ptr;
358 int do_bit17_swizzling;
360 remain = args->size;
362 /* Pin the user pages containing the data. We can't fault while
363 * holding the struct mutex, yet we want to hold it while
364 * dereferencing the user data.
366 first_data_page = data_ptr / PAGE_SIZE;
367 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
368 num_pages = last_data_page - first_data_page + 1;
370 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
371 if (user_pages == NULL)
372 return -ENOMEM;
374 down_read(&mm->mmap_sem);
375 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
376 num_pages, 1, 0, user_pages, NULL);
377 up_read(&mm->mmap_sem);
378 if (pinned_pages < num_pages) {
379 ret = -EFAULT;
380 goto fail_put_user_pages;
383 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
385 mutex_lock(&dev->struct_mutex);
387 ret = i915_gem_object_get_pages_or_evict(obj);
388 if (ret)
389 goto fail_unlock;
391 ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset,
392 args->size);
393 if (ret != 0)
394 goto fail_put_pages;
396 obj_priv = to_intel_bo(obj);
397 offset = args->offset;
399 while (remain > 0) {
400 /* Operation in this page
402 * shmem_page_index = page number within shmem file
403 * shmem_page_offset = offset within page in shmem file
404 * data_page_index = page number in get_user_pages return
405 * data_page_offset = offset with data_page_index page.
406 * page_length = bytes to copy for this page
408 shmem_page_index = offset / PAGE_SIZE;
409 shmem_page_offset = offset & ~PAGE_MASK;
410 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
411 data_page_offset = data_ptr & ~PAGE_MASK;
413 page_length = remain;
414 if ((shmem_page_offset + page_length) > PAGE_SIZE)
415 page_length = PAGE_SIZE - shmem_page_offset;
416 if ((data_page_offset + page_length) > PAGE_SIZE)
417 page_length = PAGE_SIZE - data_page_offset;
419 if (do_bit17_swizzling) {
420 slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
421 shmem_page_offset,
422 user_pages[data_page_index],
423 data_page_offset,
424 page_length,
426 } else {
427 slow_shmem_copy(user_pages[data_page_index],
428 data_page_offset,
429 obj_priv->pages[shmem_page_index],
430 shmem_page_offset,
431 page_length);
434 remain -= page_length;
435 data_ptr += page_length;
436 offset += page_length;
439 fail_put_pages:
440 i915_gem_object_put_pages(obj);
441 fail_unlock:
442 mutex_unlock(&dev->struct_mutex);
443 fail_put_user_pages:
444 for (i = 0; i < pinned_pages; i++) {
445 SetPageDirty(user_pages[i]);
446 page_cache_release(user_pages[i]);
448 drm_free_large(user_pages);
450 return ret;
454 * Reads data from the object referenced by handle.
456 * On error, the contents of *data are undefined.
459 i915_gem_pread_ioctl(struct drm_device *dev, void *data,
460 struct drm_file *file_priv)
462 struct drm_i915_gem_pread *args = data;
463 struct drm_gem_object *obj;
464 struct drm_i915_gem_object *obj_priv;
465 int ret;
467 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
468 if (obj == NULL)
469 return -ENOENT;
470 obj_priv = to_intel_bo(obj);
472 /* Bounds check source. */
473 if (args->offset > obj->size || args->size > obj->size - args->offset) {
474 ret = -EINVAL;
475 goto err;
478 if (!access_ok(VERIFY_WRITE,
479 (char __user *)(uintptr_t)args->data_ptr,
480 args->size)) {
481 ret = -EFAULT;
482 goto err;
485 if (i915_gem_object_needs_bit17_swizzle(obj)) {
486 ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv);
487 } else {
488 ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv);
489 if (ret != 0)
490 ret = i915_gem_shmem_pread_slow(dev, obj, args,
491 file_priv);
494 err:
495 drm_gem_object_unreference_unlocked(obj);
496 return ret;
499 /* This is the fast write path which cannot handle
500 * page faults in the source data
503 static inline int
504 fast_user_write(struct io_mapping *mapping,
505 loff_t page_base, int page_offset,
506 char __user *user_data,
507 int length)
509 char *vaddr_atomic;
510 unsigned long unwritten;
512 vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base);
513 unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset,
514 user_data, length);
515 io_mapping_unmap_atomic(vaddr_atomic);
516 if (unwritten)
517 return -EFAULT;
518 return 0;
521 /* Here's the write path which can sleep for
522 * page faults
525 static inline void
526 slow_kernel_write(struct io_mapping *mapping,
527 loff_t gtt_base, int gtt_offset,
528 struct page *user_page, int user_offset,
529 int length)
531 char __iomem *dst_vaddr;
532 char *src_vaddr;
534 dst_vaddr = io_mapping_map_wc(mapping, gtt_base);
535 src_vaddr = kmap(user_page);
537 memcpy_toio(dst_vaddr + gtt_offset,
538 src_vaddr + user_offset,
539 length);
541 kunmap(user_page);
542 io_mapping_unmap(dst_vaddr);
545 static inline int
546 fast_shmem_write(struct page **pages,
547 loff_t page_base, int page_offset,
548 char __user *data,
549 int length)
551 char __iomem *vaddr;
552 unsigned long unwritten;
554 vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT]);
555 if (vaddr == NULL)
556 return -ENOMEM;
557 unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length);
558 kunmap_atomic(vaddr);
560 if (unwritten)
561 return -EFAULT;
562 return 0;
566 * This is the fast pwrite path, where we copy the data directly from the
567 * user into the GTT, uncached.
569 static int
570 i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
571 struct drm_i915_gem_pwrite *args,
572 struct drm_file *file_priv)
574 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
575 drm_i915_private_t *dev_priv = dev->dev_private;
576 ssize_t remain;
577 loff_t offset, page_base;
578 char __user *user_data;
579 int page_offset, page_length;
580 int ret;
582 user_data = (char __user *) (uintptr_t) args->data_ptr;
583 remain = args->size;
586 mutex_lock(&dev->struct_mutex);
587 ret = i915_gem_object_pin(obj, 0);
588 if (ret) {
589 mutex_unlock(&dev->struct_mutex);
590 return ret;
592 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
593 if (ret)
594 goto fail;
596 obj_priv = to_intel_bo(obj);
597 offset = obj_priv->gtt_offset + args->offset;
599 while (remain > 0) {
600 /* Operation in this page
602 * page_base = page offset within aperture
603 * page_offset = offset within page
604 * page_length = bytes to copy for this page
606 page_base = (offset & ~(PAGE_SIZE-1));
607 page_offset = offset & (PAGE_SIZE-1);
608 page_length = remain;
609 if ((page_offset + remain) > PAGE_SIZE)
610 page_length = PAGE_SIZE - page_offset;
612 ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base,
613 page_offset, user_data, page_length);
615 /* If we get a fault while copying data, then (presumably) our
616 * source page isn't available. Return the error and we'll
617 * retry in the slow path.
619 if (ret)
620 goto fail;
622 remain -= page_length;
623 user_data += page_length;
624 offset += page_length;
627 fail:
628 i915_gem_object_unpin(obj);
629 mutex_unlock(&dev->struct_mutex);
631 return ret;
635 * This is the fallback GTT pwrite path, which uses get_user_pages to pin
636 * the memory and maps it using kmap_atomic for copying.
638 * This code resulted in x11perf -rgb10text consuming about 10% more CPU
639 * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit).
641 static int
642 i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
643 struct drm_i915_gem_pwrite *args,
644 struct drm_file *file_priv)
646 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
647 drm_i915_private_t *dev_priv = dev->dev_private;
648 ssize_t remain;
649 loff_t gtt_page_base, offset;
650 loff_t first_data_page, last_data_page, num_pages;
651 loff_t pinned_pages, i;
652 struct page **user_pages;
653 struct mm_struct *mm = current->mm;
654 int gtt_page_offset, data_page_offset, data_page_index, page_length;
655 int ret;
656 uint64_t data_ptr = args->data_ptr;
658 remain = args->size;
660 /* Pin the user pages containing the data. We can't fault while
661 * holding the struct mutex, and all of the pwrite implementations
662 * want to hold it while dereferencing the user data.
664 first_data_page = data_ptr / PAGE_SIZE;
665 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
666 num_pages = last_data_page - first_data_page + 1;
668 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
669 if (user_pages == NULL)
670 return -ENOMEM;
672 down_read(&mm->mmap_sem);
673 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
674 num_pages, 0, 0, user_pages, NULL);
675 up_read(&mm->mmap_sem);
676 if (pinned_pages < num_pages) {
677 ret = -EFAULT;
678 goto out_unpin_pages;
681 mutex_lock(&dev->struct_mutex);
682 ret = i915_gem_object_pin(obj, 0);
683 if (ret)
684 goto out_unlock;
686 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
687 if (ret)
688 goto out_unpin_object;
690 obj_priv = to_intel_bo(obj);
691 offset = obj_priv->gtt_offset + args->offset;
693 while (remain > 0) {
694 /* Operation in this page
696 * gtt_page_base = page offset within aperture
697 * gtt_page_offset = offset within page in aperture
698 * data_page_index = page number in get_user_pages return
699 * data_page_offset = offset with data_page_index page.
700 * page_length = bytes to copy for this page
702 gtt_page_base = offset & PAGE_MASK;
703 gtt_page_offset = offset & ~PAGE_MASK;
704 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
705 data_page_offset = data_ptr & ~PAGE_MASK;
707 page_length = remain;
708 if ((gtt_page_offset + page_length) > PAGE_SIZE)
709 page_length = PAGE_SIZE - gtt_page_offset;
710 if ((data_page_offset + page_length) > PAGE_SIZE)
711 page_length = PAGE_SIZE - data_page_offset;
713 slow_kernel_write(dev_priv->mm.gtt_mapping,
714 gtt_page_base, gtt_page_offset,
715 user_pages[data_page_index],
716 data_page_offset,
717 page_length);
719 remain -= page_length;
720 offset += page_length;
721 data_ptr += page_length;
724 out_unpin_object:
725 i915_gem_object_unpin(obj);
726 out_unlock:
727 mutex_unlock(&dev->struct_mutex);
728 out_unpin_pages:
729 for (i = 0; i < pinned_pages; i++)
730 page_cache_release(user_pages[i]);
731 drm_free_large(user_pages);
733 return ret;
737 * This is the fast shmem pwrite path, which attempts to directly
738 * copy_from_user into the kmapped pages backing the object.
740 static int
741 i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj,
742 struct drm_i915_gem_pwrite *args,
743 struct drm_file *file_priv)
745 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
746 ssize_t remain;
747 loff_t offset, page_base;
748 char __user *user_data;
749 int page_offset, page_length;
750 int ret;
752 user_data = (char __user *) (uintptr_t) args->data_ptr;
753 remain = args->size;
755 mutex_lock(&dev->struct_mutex);
757 ret = i915_gem_object_get_pages(obj, 0);
758 if (ret != 0)
759 goto fail_unlock;
761 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
762 if (ret != 0)
763 goto fail_put_pages;
765 obj_priv = to_intel_bo(obj);
766 offset = args->offset;
767 obj_priv->dirty = 1;
769 while (remain > 0) {
770 /* Operation in this page
772 * page_base = page offset within aperture
773 * page_offset = offset within page
774 * page_length = bytes to copy for this page
776 page_base = (offset & ~(PAGE_SIZE-1));
777 page_offset = offset & (PAGE_SIZE-1);
778 page_length = remain;
779 if ((page_offset + remain) > PAGE_SIZE)
780 page_length = PAGE_SIZE - page_offset;
782 ret = fast_shmem_write(obj_priv->pages,
783 page_base, page_offset,
784 user_data, page_length);
785 if (ret)
786 goto fail_put_pages;
788 remain -= page_length;
789 user_data += page_length;
790 offset += page_length;
793 fail_put_pages:
794 i915_gem_object_put_pages(obj);
795 fail_unlock:
796 mutex_unlock(&dev->struct_mutex);
798 return ret;
802 * This is the fallback shmem pwrite path, which uses get_user_pages to pin
803 * the memory and maps it using kmap_atomic for copying.
805 * This avoids taking mmap_sem for faulting on the user's address while the
806 * struct_mutex is held.
808 static int
809 i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj,
810 struct drm_i915_gem_pwrite *args,
811 struct drm_file *file_priv)
813 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
814 struct mm_struct *mm = current->mm;
815 struct page **user_pages;
816 ssize_t remain;
817 loff_t offset, pinned_pages, i;
818 loff_t first_data_page, last_data_page, num_pages;
819 int shmem_page_index, shmem_page_offset;
820 int data_page_index, data_page_offset;
821 int page_length;
822 int ret;
823 uint64_t data_ptr = args->data_ptr;
824 int do_bit17_swizzling;
826 remain = args->size;
828 /* Pin the user pages containing the data. We can't fault while
829 * holding the struct mutex, and all of the pwrite implementations
830 * want to hold it while dereferencing the user data.
832 first_data_page = data_ptr / PAGE_SIZE;
833 last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE;
834 num_pages = last_data_page - first_data_page + 1;
836 user_pages = drm_calloc_large(num_pages, sizeof(struct page *));
837 if (user_pages == NULL)
838 return -ENOMEM;
840 down_read(&mm->mmap_sem);
841 pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr,
842 num_pages, 0, 0, user_pages, NULL);
843 up_read(&mm->mmap_sem);
844 if (pinned_pages < num_pages) {
845 ret = -EFAULT;
846 goto fail_put_user_pages;
849 do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj);
851 mutex_lock(&dev->struct_mutex);
853 ret = i915_gem_object_get_pages_or_evict(obj);
854 if (ret)
855 goto fail_unlock;
857 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
858 if (ret != 0)
859 goto fail_put_pages;
861 obj_priv = to_intel_bo(obj);
862 offset = args->offset;
863 obj_priv->dirty = 1;
865 while (remain > 0) {
866 /* Operation in this page
868 * shmem_page_index = page number within shmem file
869 * shmem_page_offset = offset within page in shmem file
870 * data_page_index = page number in get_user_pages return
871 * data_page_offset = offset with data_page_index page.
872 * page_length = bytes to copy for this page
874 shmem_page_index = offset / PAGE_SIZE;
875 shmem_page_offset = offset & ~PAGE_MASK;
876 data_page_index = data_ptr / PAGE_SIZE - first_data_page;
877 data_page_offset = data_ptr & ~PAGE_MASK;
879 page_length = remain;
880 if ((shmem_page_offset + page_length) > PAGE_SIZE)
881 page_length = PAGE_SIZE - shmem_page_offset;
882 if ((data_page_offset + page_length) > PAGE_SIZE)
883 page_length = PAGE_SIZE - data_page_offset;
885 if (do_bit17_swizzling) {
886 slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index],
887 shmem_page_offset,
888 user_pages[data_page_index],
889 data_page_offset,
890 page_length,
892 } else {
893 slow_shmem_copy(obj_priv->pages[shmem_page_index],
894 shmem_page_offset,
895 user_pages[data_page_index],
896 data_page_offset,
897 page_length);
900 remain -= page_length;
901 data_ptr += page_length;
902 offset += page_length;
905 fail_put_pages:
906 i915_gem_object_put_pages(obj);
907 fail_unlock:
908 mutex_unlock(&dev->struct_mutex);
909 fail_put_user_pages:
910 for (i = 0; i < pinned_pages; i++)
911 page_cache_release(user_pages[i]);
912 drm_free_large(user_pages);
914 return ret;
918 * Writes data to the object referenced by handle.
920 * On error, the contents of the buffer that were to be modified are undefined.
923 i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
924 struct drm_file *file_priv)
926 struct drm_i915_gem_pwrite *args = data;
927 struct drm_gem_object *obj;
928 struct drm_i915_gem_object *obj_priv;
929 int ret = 0;
931 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
932 if (obj == NULL)
933 return -ENOENT;
934 obj_priv = to_intel_bo(obj);
936 /* Bounds check destination. */
937 if (args->offset > obj->size || args->size > obj->size - args->offset) {
938 ret = -EINVAL;
939 goto err;
942 if (!access_ok(VERIFY_READ,
943 (char __user *)(uintptr_t)args->data_ptr,
944 args->size)) {
945 ret = -EFAULT;
946 goto err;
949 /* We can only do the GTT pwrite on untiled buffers, as otherwise
950 * it would end up going through the fenced access, and we'll get
951 * different detiling behavior between reading and writing.
952 * pread/pwrite currently are reading and writing from the CPU
953 * perspective, requiring manual detiling by the client.
955 if (obj_priv->phys_obj)
956 ret = i915_gem_phys_pwrite(dev, obj, args, file_priv);
957 else if (obj_priv->tiling_mode == I915_TILING_NONE &&
958 dev->gtt_total != 0 &&
959 obj->write_domain != I915_GEM_DOMAIN_CPU) {
960 ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv);
961 if (ret == -EFAULT) {
962 ret = i915_gem_gtt_pwrite_slow(dev, obj, args,
963 file_priv);
965 } else if (i915_gem_object_needs_bit17_swizzle(obj)) {
966 ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv);
967 } else {
968 ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv);
969 if (ret == -EFAULT) {
970 ret = i915_gem_shmem_pwrite_slow(dev, obj, args,
971 file_priv);
975 #if WATCH_PWRITE
976 if (ret)
977 DRM_INFO("pwrite failed %d\n", ret);
978 #endif
980 err:
981 drm_gem_object_unreference_unlocked(obj);
982 return ret;
986 * Called when user space prepares to use an object with the CPU, either
987 * through the mmap ioctl's mapping or a GTT mapping.
990 i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
991 struct drm_file *file_priv)
993 struct drm_i915_private *dev_priv = dev->dev_private;
994 struct drm_i915_gem_set_domain *args = data;
995 struct drm_gem_object *obj;
996 struct drm_i915_gem_object *obj_priv;
997 uint32_t read_domains = args->read_domains;
998 uint32_t write_domain = args->write_domain;
999 int ret;
1001 if (!(dev->driver->driver_features & DRIVER_GEM))
1002 return -ENODEV;
1004 /* Only handle setting domains to types used by the CPU. */
1005 if (write_domain & I915_GEM_GPU_DOMAINS)
1006 return -EINVAL;
1008 if (read_domains & I915_GEM_GPU_DOMAINS)
1009 return -EINVAL;
1011 /* Having something in the write domain implies it's in the read
1012 * domain, and only that read domain. Enforce that in the request.
1014 if (write_domain != 0 && read_domains != write_domain)
1015 return -EINVAL;
1017 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1018 if (obj == NULL)
1019 return -ENOENT;
1020 obj_priv = to_intel_bo(obj);
1022 mutex_lock(&dev->struct_mutex);
1024 intel_mark_busy(dev, obj);
1026 #if WATCH_BUF
1027 DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n",
1028 obj, obj->size, read_domains, write_domain);
1029 #endif
1030 if (read_domains & I915_GEM_DOMAIN_GTT) {
1031 ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0);
1033 /* Update the LRU on the fence for the CPU access that's
1034 * about to occur.
1036 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1037 struct drm_i915_fence_reg *reg =
1038 &dev_priv->fence_regs[obj_priv->fence_reg];
1039 list_move_tail(&reg->lru_list,
1040 &dev_priv->mm.fence_list);
1043 /* Silently promote "you're not bound, there was nothing to do"
1044 * to success, since the client was just asking us to
1045 * make sure everything was done.
1047 if (ret == -EINVAL)
1048 ret = 0;
1049 } else {
1050 ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0);
1054 /* Maintain LRU order of "inactive" objects */
1055 if (ret == 0 && i915_gem_object_is_inactive(obj_priv))
1056 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1058 drm_gem_object_unreference(obj);
1059 mutex_unlock(&dev->struct_mutex);
1060 return ret;
1064 * Called when user space has done writes to this buffer
1067 i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1068 struct drm_file *file_priv)
1070 struct drm_i915_gem_sw_finish *args = data;
1071 struct drm_gem_object *obj;
1072 struct drm_i915_gem_object *obj_priv;
1073 int ret = 0;
1075 if (!(dev->driver->driver_features & DRIVER_GEM))
1076 return -ENODEV;
1078 mutex_lock(&dev->struct_mutex);
1079 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1080 if (obj == NULL) {
1081 mutex_unlock(&dev->struct_mutex);
1082 return -ENOENT;
1085 #if WATCH_BUF
1086 DRM_INFO("%s: sw_finish %d (%p %zd)\n",
1087 __func__, args->handle, obj, obj->size);
1088 #endif
1089 obj_priv = to_intel_bo(obj);
1091 /* Pinned buffers may be scanout, so flush the cache */
1092 if (obj_priv->pin_count)
1093 i915_gem_object_flush_cpu_write_domain(obj);
1095 drm_gem_object_unreference(obj);
1096 mutex_unlock(&dev->struct_mutex);
1097 return ret;
1101 * Maps the contents of an object, returning the address it is mapped
1102 * into.
1104 * While the mapping holds a reference on the contents of the object, it doesn't
1105 * imply a ref on the object itself.
1108 i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1109 struct drm_file *file_priv)
1111 struct drm_i915_gem_mmap *args = data;
1112 struct drm_gem_object *obj;
1113 loff_t offset;
1114 unsigned long addr;
1116 if (!(dev->driver->driver_features & DRIVER_GEM))
1117 return -ENODEV;
1119 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1120 if (obj == NULL)
1121 return -ENOENT;
1123 offset = args->offset;
1125 down_write(&current->mm->mmap_sem);
1126 addr = do_mmap(obj->filp, 0, args->size,
1127 PROT_READ | PROT_WRITE, MAP_SHARED,
1128 args->offset);
1129 up_write(&current->mm->mmap_sem);
1130 drm_gem_object_unreference_unlocked(obj);
1131 if (IS_ERR((void *)addr))
1132 return addr;
1134 args->addr_ptr = (uint64_t) addr;
1136 return 0;
1140 * i915_gem_fault - fault a page into the GTT
1141 * vma: VMA in question
1142 * vmf: fault info
1144 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1145 * from userspace. The fault handler takes care of binding the object to
1146 * the GTT (if needed), allocating and programming a fence register (again,
1147 * only if needed based on whether the old reg is still valid or the object
1148 * is tiled) and inserting a new PTE into the faulting process.
1150 * Note that the faulting process may involve evicting existing objects
1151 * from the GTT and/or fence registers to make room. So performance may
1152 * suffer if the GTT working set is large or there are few fence registers
1153 * left.
1155 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
1157 struct drm_gem_object *obj = vma->vm_private_data;
1158 struct drm_device *dev = obj->dev;
1159 drm_i915_private_t *dev_priv = dev->dev_private;
1160 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1161 pgoff_t page_offset;
1162 unsigned long pfn;
1163 int ret = 0;
1164 bool write = !!(vmf->flags & FAULT_FLAG_WRITE);
1166 /* We don't use vmf->pgoff since that has the fake offset */
1167 page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >>
1168 PAGE_SHIFT;
1170 /* Now bind it into the GTT if needed */
1171 mutex_lock(&dev->struct_mutex);
1172 if (!obj_priv->gtt_space) {
1173 ret = i915_gem_object_bind_to_gtt(obj, 0);
1174 if (ret)
1175 goto unlock;
1177 ret = i915_gem_object_set_to_gtt_domain(obj, write);
1178 if (ret)
1179 goto unlock;
1182 /* Need a new fence register? */
1183 if (obj_priv->tiling_mode != I915_TILING_NONE) {
1184 ret = i915_gem_object_get_fence_reg(obj);
1185 if (ret)
1186 goto unlock;
1189 if (i915_gem_object_is_inactive(obj_priv))
1190 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1192 pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) +
1193 page_offset;
1195 /* Finally, remap it using the new GTT offset */
1196 ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
1197 unlock:
1198 mutex_unlock(&dev->struct_mutex);
1200 switch (ret) {
1201 case 0:
1202 case -ERESTARTSYS:
1203 return VM_FAULT_NOPAGE;
1204 case -ENOMEM:
1205 case -EAGAIN:
1206 return VM_FAULT_OOM;
1207 default:
1208 return VM_FAULT_SIGBUS;
1213 * i915_gem_create_mmap_offset - create a fake mmap offset for an object
1214 * @obj: obj in question
1216 * GEM memory mapping works by handing back to userspace a fake mmap offset
1217 * it can use in a subsequent mmap(2) call. The DRM core code then looks
1218 * up the object based on the offset and sets up the various memory mapping
1219 * structures.
1221 * This routine allocates and attaches a fake offset for @obj.
1223 static int
1224 i915_gem_create_mmap_offset(struct drm_gem_object *obj)
1226 struct drm_device *dev = obj->dev;
1227 struct drm_gem_mm *mm = dev->mm_private;
1228 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1229 struct drm_map_list *list;
1230 struct drm_local_map *map;
1231 int ret = 0;
1233 /* Set the object up for mmap'ing */
1234 list = &obj->map_list;
1235 list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
1236 if (!list->map)
1237 return -ENOMEM;
1239 map = list->map;
1240 map->type = _DRM_GEM;
1241 map->size = obj->size;
1242 map->handle = obj;
1244 /* Get a DRM GEM mmap offset allocated... */
1245 list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
1246 obj->size / PAGE_SIZE, 0, 0);
1247 if (!list->file_offset_node) {
1248 DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
1249 ret = -ENOMEM;
1250 goto out_free_list;
1253 list->file_offset_node = drm_mm_get_block(list->file_offset_node,
1254 obj->size / PAGE_SIZE, 0);
1255 if (!list->file_offset_node) {
1256 ret = -ENOMEM;
1257 goto out_free_list;
1260 list->hash.key = list->file_offset_node->start;
1261 if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) {
1262 DRM_ERROR("failed to add to map hash\n");
1263 ret = -ENOMEM;
1264 goto out_free_mm;
1267 /* By now we should be all set, any drm_mmap request on the offset
1268 * below will get to our mmap & fault handler */
1269 obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT;
1271 return 0;
1273 out_free_mm:
1274 drm_mm_put_block(list->file_offset_node);
1275 out_free_list:
1276 kfree(list->map);
1278 return ret;
1282 * i915_gem_release_mmap - remove physical page mappings
1283 * @obj: obj in question
1285 * Preserve the reservation of the mmapping with the DRM core code, but
1286 * relinquish ownership of the pages back to the system.
1288 * It is vital that we remove the page mapping if we have mapped a tiled
1289 * object through the GTT and then lose the fence register due to
1290 * resource pressure. Similarly if the object has been moved out of the
1291 * aperture, than pages mapped into userspace must be revoked. Removing the
1292 * mapping will then trigger a page fault on the next user access, allowing
1293 * fixup by i915_gem_fault().
1295 void
1296 i915_gem_release_mmap(struct drm_gem_object *obj)
1298 struct drm_device *dev = obj->dev;
1299 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1301 if (dev->dev_mapping)
1302 unmap_mapping_range(dev->dev_mapping,
1303 obj_priv->mmap_offset, obj->size, 1);
1306 static void
1307 i915_gem_free_mmap_offset(struct drm_gem_object *obj)
1309 struct drm_device *dev = obj->dev;
1310 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1311 struct drm_gem_mm *mm = dev->mm_private;
1312 struct drm_map_list *list;
1314 list = &obj->map_list;
1315 drm_ht_remove_item(&mm->offset_hash, &list->hash);
1317 if (list->file_offset_node) {
1318 drm_mm_put_block(list->file_offset_node);
1319 list->file_offset_node = NULL;
1322 if (list->map) {
1323 kfree(list->map);
1324 list->map = NULL;
1327 obj_priv->mmap_offset = 0;
1331 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1332 * @obj: object to check
1334 * Return the required GTT alignment for an object, taking into account
1335 * potential fence register mapping if needed.
1337 static uint32_t
1338 i915_gem_get_gtt_alignment(struct drm_gem_object *obj)
1340 struct drm_device *dev = obj->dev;
1341 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1342 int start, i;
1345 * Minimum alignment is 4k (GTT page size), but might be greater
1346 * if a fence register is needed for the object.
1348 if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE)
1349 return 4096;
1352 * Previous chips need to be aligned to the size of the smallest
1353 * fence register that can contain the object.
1355 if (IS_I9XX(dev))
1356 start = 1024*1024;
1357 else
1358 start = 512*1024;
1360 for (i = start; i < obj->size; i <<= 1)
1363 return i;
1367 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1368 * @dev: DRM device
1369 * @data: GTT mapping ioctl data
1370 * @file_priv: GEM object info
1372 * Simply returns the fake offset to userspace so it can mmap it.
1373 * The mmap call will end up in drm_gem_mmap(), which will set things
1374 * up so we can get faults in the handler above.
1376 * The fault handler will take care of binding the object into the GTT
1377 * (since it may have been evicted to make room for something), allocating
1378 * a fence register, and mapping the appropriate aperture address into
1379 * userspace.
1382 i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1383 struct drm_file *file_priv)
1385 struct drm_i915_gem_mmap_gtt *args = data;
1386 struct drm_gem_object *obj;
1387 struct drm_i915_gem_object *obj_priv;
1388 int ret;
1390 if (!(dev->driver->driver_features & DRIVER_GEM))
1391 return -ENODEV;
1393 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
1394 if (obj == NULL)
1395 return -ENOENT;
1397 mutex_lock(&dev->struct_mutex);
1399 obj_priv = to_intel_bo(obj);
1401 if (obj_priv->madv != I915_MADV_WILLNEED) {
1402 DRM_ERROR("Attempting to mmap a purgeable buffer\n");
1403 drm_gem_object_unreference(obj);
1404 mutex_unlock(&dev->struct_mutex);
1405 return -EINVAL;
1409 if (!obj_priv->mmap_offset) {
1410 ret = i915_gem_create_mmap_offset(obj);
1411 if (ret) {
1412 drm_gem_object_unreference(obj);
1413 mutex_unlock(&dev->struct_mutex);
1414 return ret;
1418 args->offset = obj_priv->mmap_offset;
1421 * Pull it into the GTT so that we have a page list (makes the
1422 * initial fault faster and any subsequent flushing possible).
1424 if (!obj_priv->agp_mem) {
1425 ret = i915_gem_object_bind_to_gtt(obj, 0);
1426 if (ret) {
1427 drm_gem_object_unreference(obj);
1428 mutex_unlock(&dev->struct_mutex);
1429 return ret;
1433 drm_gem_object_unreference(obj);
1434 mutex_unlock(&dev->struct_mutex);
1436 return 0;
1439 void
1440 i915_gem_object_put_pages(struct drm_gem_object *obj)
1442 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1443 int page_count = obj->size / PAGE_SIZE;
1444 int i;
1446 BUG_ON(obj_priv->pages_refcount == 0);
1447 BUG_ON(obj_priv->madv == __I915_MADV_PURGED);
1449 if (--obj_priv->pages_refcount != 0)
1450 return;
1452 if (obj_priv->tiling_mode != I915_TILING_NONE)
1453 i915_gem_object_save_bit_17_swizzle(obj);
1455 if (obj_priv->madv == I915_MADV_DONTNEED)
1456 obj_priv->dirty = 0;
1458 for (i = 0; i < page_count; i++) {
1459 if (obj_priv->dirty)
1460 set_page_dirty(obj_priv->pages[i]);
1462 if (obj_priv->madv == I915_MADV_WILLNEED)
1463 mark_page_accessed(obj_priv->pages[i]);
1465 page_cache_release(obj_priv->pages[i]);
1467 obj_priv->dirty = 0;
1469 drm_free_large(obj_priv->pages);
1470 obj_priv->pages = NULL;
1473 static void
1474 i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno,
1475 struct intel_ring_buffer *ring)
1477 struct drm_device *dev = obj->dev;
1478 drm_i915_private_t *dev_priv = dev->dev_private;
1479 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1480 BUG_ON(ring == NULL);
1481 obj_priv->ring = ring;
1483 /* Add a reference if we're newly entering the active list. */
1484 if (!obj_priv->active) {
1485 drm_gem_object_reference(obj);
1486 obj_priv->active = 1;
1488 /* Move from whatever list we were on to the tail of execution. */
1489 spin_lock(&dev_priv->mm.active_list_lock);
1490 list_move_tail(&obj_priv->list, &ring->active_list);
1491 spin_unlock(&dev_priv->mm.active_list_lock);
1492 obj_priv->last_rendering_seqno = seqno;
1495 static void
1496 i915_gem_object_move_to_flushing(struct drm_gem_object *obj)
1498 struct drm_device *dev = obj->dev;
1499 drm_i915_private_t *dev_priv = dev->dev_private;
1500 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1502 BUG_ON(!obj_priv->active);
1503 list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list);
1504 obj_priv->last_rendering_seqno = 0;
1507 /* Immediately discard the backing storage */
1508 static void
1509 i915_gem_object_truncate(struct drm_gem_object *obj)
1511 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1512 struct inode *inode;
1514 /* Our goal here is to return as much of the memory as
1515 * is possible back to the system as we are called from OOM.
1516 * To do this we must instruct the shmfs to drop all of its
1517 * backing pages, *now*. Here we mirror the actions taken
1518 * when by shmem_delete_inode() to release the backing store.
1520 inode = obj->filp->f_path.dentry->d_inode;
1521 truncate_inode_pages(inode->i_mapping, 0);
1522 if (inode->i_op->truncate_range)
1523 inode->i_op->truncate_range(inode, 0, (loff_t)-1);
1525 obj_priv->madv = __I915_MADV_PURGED;
1528 static inline int
1529 i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv)
1531 return obj_priv->madv == I915_MADV_DONTNEED;
1534 static void
1535 i915_gem_object_move_to_inactive(struct drm_gem_object *obj)
1537 struct drm_device *dev = obj->dev;
1538 drm_i915_private_t *dev_priv = dev->dev_private;
1539 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1541 i915_verify_inactive(dev, __FILE__, __LINE__);
1542 if (obj_priv->pin_count != 0)
1543 list_del_init(&obj_priv->list);
1544 else
1545 list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
1547 BUG_ON(!list_empty(&obj_priv->gpu_write_list));
1549 obj_priv->last_rendering_seqno = 0;
1550 obj_priv->ring = NULL;
1551 if (obj_priv->active) {
1552 obj_priv->active = 0;
1553 drm_gem_object_unreference(obj);
1555 i915_verify_inactive(dev, __FILE__, __LINE__);
1558 static void
1559 i915_gem_process_flushing_list(struct drm_device *dev,
1560 uint32_t flush_domains, uint32_t seqno,
1561 struct intel_ring_buffer *ring)
1563 drm_i915_private_t *dev_priv = dev->dev_private;
1564 struct drm_i915_gem_object *obj_priv, *next;
1566 list_for_each_entry_safe(obj_priv, next,
1567 &dev_priv->mm.gpu_write_list,
1568 gpu_write_list) {
1569 struct drm_gem_object *obj = &obj_priv->base;
1571 if ((obj->write_domain & flush_domains) ==
1572 obj->write_domain &&
1573 obj_priv->ring->ring_flag == ring->ring_flag) {
1574 uint32_t old_write_domain = obj->write_domain;
1576 obj->write_domain = 0;
1577 list_del_init(&obj_priv->gpu_write_list);
1578 i915_gem_object_move_to_active(obj, seqno, ring);
1580 /* update the fence lru list */
1581 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
1582 struct drm_i915_fence_reg *reg =
1583 &dev_priv->fence_regs[obj_priv->fence_reg];
1584 list_move_tail(&reg->lru_list,
1585 &dev_priv->mm.fence_list);
1588 trace_i915_gem_object_change_domain(obj,
1589 obj->read_domains,
1590 old_write_domain);
1595 uint32_t
1596 i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
1597 uint32_t flush_domains, struct intel_ring_buffer *ring)
1599 drm_i915_private_t *dev_priv = dev->dev_private;
1600 struct drm_i915_file_private *i915_file_priv = NULL;
1601 struct drm_i915_gem_request *request;
1602 uint32_t seqno;
1603 int was_empty;
1605 if (file_priv != NULL)
1606 i915_file_priv = file_priv->driver_priv;
1608 request = kzalloc(sizeof(*request), GFP_KERNEL);
1609 if (request == NULL)
1610 return 0;
1612 seqno = ring->add_request(dev, ring, file_priv, flush_domains);
1614 request->seqno = seqno;
1615 request->ring = ring;
1616 request->emitted_jiffies = jiffies;
1617 was_empty = list_empty(&ring->request_list);
1618 list_add_tail(&request->list, &ring->request_list);
1620 if (i915_file_priv) {
1621 list_add_tail(&request->client_list,
1622 &i915_file_priv->mm.request_list);
1623 } else {
1624 INIT_LIST_HEAD(&request->client_list);
1627 /* Associate any objects on the flushing list matching the write
1628 * domain we're flushing with our flush.
1630 if (flush_domains != 0)
1631 i915_gem_process_flushing_list(dev, flush_domains, seqno, ring);
1633 if (!dev_priv->mm.suspended) {
1634 mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD);
1635 if (was_empty)
1636 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1638 return seqno;
1642 * Command execution barrier
1644 * Ensures that all commands in the ring are finished
1645 * before signalling the CPU
1647 static uint32_t
1648 i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring)
1650 uint32_t flush_domains = 0;
1652 /* The sampler always gets flushed on i965 (sigh) */
1653 if (IS_I965G(dev))
1654 flush_domains |= I915_GEM_DOMAIN_SAMPLER;
1656 ring->flush(dev, ring,
1657 I915_GEM_DOMAIN_COMMAND, flush_domains);
1658 return flush_domains;
1662 * Moves buffers associated only with the given active seqno from the active
1663 * to inactive list, potentially freeing them.
1665 static void
1666 i915_gem_retire_request(struct drm_device *dev,
1667 struct drm_i915_gem_request *request)
1669 drm_i915_private_t *dev_priv = dev->dev_private;
1671 trace_i915_gem_request_retire(dev, request->seqno);
1673 /* Move any buffers on the active list that are no longer referenced
1674 * by the ringbuffer to the flushing/inactive lists as appropriate.
1676 spin_lock(&dev_priv->mm.active_list_lock);
1677 while (!list_empty(&request->ring->active_list)) {
1678 struct drm_gem_object *obj;
1679 struct drm_i915_gem_object *obj_priv;
1681 obj_priv = list_first_entry(&request->ring->active_list,
1682 struct drm_i915_gem_object,
1683 list);
1684 obj = &obj_priv->base;
1686 /* If the seqno being retired doesn't match the oldest in the
1687 * list, then the oldest in the list must still be newer than
1688 * this seqno.
1690 if (obj_priv->last_rendering_seqno != request->seqno)
1691 goto out;
1693 #if WATCH_LRU
1694 DRM_INFO("%s: retire %d moves to inactive list %p\n",
1695 __func__, request->seqno, obj);
1696 #endif
1698 if (obj->write_domain != 0)
1699 i915_gem_object_move_to_flushing(obj);
1700 else {
1701 /* Take a reference on the object so it won't be
1702 * freed while the spinlock is held. The list
1703 * protection for this spinlock is safe when breaking
1704 * the lock like this since the next thing we do
1705 * is just get the head of the list again.
1707 drm_gem_object_reference(obj);
1708 i915_gem_object_move_to_inactive(obj);
1709 spin_unlock(&dev_priv->mm.active_list_lock);
1710 drm_gem_object_unreference(obj);
1711 spin_lock(&dev_priv->mm.active_list_lock);
1714 out:
1715 spin_unlock(&dev_priv->mm.active_list_lock);
1719 * Returns true if seq1 is later than seq2.
1721 bool
1722 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1724 return (int32_t)(seq1 - seq2) >= 0;
1727 uint32_t
1728 i915_get_gem_seqno(struct drm_device *dev,
1729 struct intel_ring_buffer *ring)
1731 return ring->get_gem_seqno(dev, ring);
1735 * This function clears the request list as sequence numbers are passed.
1737 static void
1738 i915_gem_retire_requests_ring(struct drm_device *dev,
1739 struct intel_ring_buffer *ring)
1741 drm_i915_private_t *dev_priv = dev->dev_private;
1742 uint32_t seqno;
1744 if (!ring->status_page.page_addr
1745 || list_empty(&ring->request_list))
1746 return;
1748 seqno = i915_get_gem_seqno(dev, ring);
1750 while (!list_empty(&ring->request_list)) {
1751 struct drm_i915_gem_request *request;
1752 uint32_t retiring_seqno;
1754 request = list_first_entry(&ring->request_list,
1755 struct drm_i915_gem_request,
1756 list);
1757 retiring_seqno = request->seqno;
1759 if (i915_seqno_passed(seqno, retiring_seqno) ||
1760 atomic_read(&dev_priv->mm.wedged)) {
1761 i915_gem_retire_request(dev, request);
1763 list_del(&request->list);
1764 list_del(&request->client_list);
1765 kfree(request);
1766 } else
1767 break;
1770 if (unlikely (dev_priv->trace_irq_seqno &&
1771 i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) {
1773 ring->user_irq_put(dev, ring);
1774 dev_priv->trace_irq_seqno = 0;
1778 void
1779 i915_gem_retire_requests(struct drm_device *dev)
1781 drm_i915_private_t *dev_priv = dev->dev_private;
1783 if (!list_empty(&dev_priv->mm.deferred_free_list)) {
1784 struct drm_i915_gem_object *obj_priv, *tmp;
1786 /* We must be careful that during unbind() we do not
1787 * accidentally infinitely recurse into retire requests.
1788 * Currently:
1789 * retire -> free -> unbind -> wait -> retire_ring
1791 list_for_each_entry_safe(obj_priv, tmp,
1792 &dev_priv->mm.deferred_free_list,
1793 list)
1794 i915_gem_free_object_tail(&obj_priv->base);
1797 i915_gem_retire_requests_ring(dev, &dev_priv->render_ring);
1798 if (HAS_BSD(dev))
1799 i915_gem_retire_requests_ring(dev, &dev_priv->bsd_ring);
1802 void
1803 i915_gem_retire_work_handler(struct work_struct *work)
1805 drm_i915_private_t *dev_priv;
1806 struct drm_device *dev;
1808 dev_priv = container_of(work, drm_i915_private_t,
1809 mm.retire_work.work);
1810 dev = dev_priv->dev;
1812 mutex_lock(&dev->struct_mutex);
1813 i915_gem_retire_requests(dev);
1815 if (!dev_priv->mm.suspended &&
1816 (!list_empty(&dev_priv->render_ring.request_list) ||
1817 (HAS_BSD(dev) &&
1818 !list_empty(&dev_priv->bsd_ring.request_list))))
1819 queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ);
1820 mutex_unlock(&dev->struct_mutex);
1824 i915_do_wait_request(struct drm_device *dev, uint32_t seqno,
1825 int interruptible, struct intel_ring_buffer *ring)
1827 drm_i915_private_t *dev_priv = dev->dev_private;
1828 u32 ier;
1829 int ret = 0;
1831 BUG_ON(seqno == 0);
1833 if (atomic_read(&dev_priv->mm.wedged))
1834 return -EIO;
1836 if (!i915_seqno_passed(ring->get_gem_seqno(dev, ring), seqno)) {
1837 if (HAS_PCH_SPLIT(dev))
1838 ier = I915_READ(DEIER) | I915_READ(GTIER);
1839 else
1840 ier = I915_READ(IER);
1841 if (!ier) {
1842 DRM_ERROR("something (likely vbetool) disabled "
1843 "interrupts, re-enabling\n");
1844 i915_driver_irq_preinstall(dev);
1845 i915_driver_irq_postinstall(dev);
1848 trace_i915_gem_request_wait_begin(dev, seqno);
1850 ring->waiting_gem_seqno = seqno;
1851 ring->user_irq_get(dev, ring);
1852 if (interruptible)
1853 ret = wait_event_interruptible(ring->irq_queue,
1854 i915_seqno_passed(
1855 ring->get_gem_seqno(dev, ring), seqno)
1856 || atomic_read(&dev_priv->mm.wedged));
1857 else
1858 wait_event(ring->irq_queue,
1859 i915_seqno_passed(
1860 ring->get_gem_seqno(dev, ring), seqno)
1861 || atomic_read(&dev_priv->mm.wedged));
1863 ring->user_irq_put(dev, ring);
1864 ring->waiting_gem_seqno = 0;
1866 trace_i915_gem_request_wait_end(dev, seqno);
1868 if (atomic_read(&dev_priv->mm.wedged))
1869 ret = -EIO;
1871 if (ret && ret != -ERESTARTSYS)
1872 DRM_ERROR("%s returns %d (awaiting %d at %d)\n",
1873 __func__, ret, seqno, ring->get_gem_seqno(dev, ring));
1875 /* Directly dispatch request retiring. While we have the work queue
1876 * to handle this, the waiter on a request often wants an associated
1877 * buffer to have made it to the inactive list, and we would need
1878 * a separate wait queue to handle that.
1880 if (ret == 0)
1881 i915_gem_retire_requests_ring(dev, ring);
1883 return ret;
1887 * Waits for a sequence number to be signaled, and cleans up the
1888 * request and object lists appropriately for that event.
1890 static int
1891 i915_wait_request(struct drm_device *dev, uint32_t seqno,
1892 struct intel_ring_buffer *ring)
1894 return i915_do_wait_request(dev, seqno, 1, ring);
1897 static void
1898 i915_gem_flush(struct drm_device *dev,
1899 uint32_t invalidate_domains,
1900 uint32_t flush_domains)
1902 drm_i915_private_t *dev_priv = dev->dev_private;
1903 if (flush_domains & I915_GEM_DOMAIN_CPU)
1904 drm_agp_chipset_flush(dev);
1905 dev_priv->render_ring.flush(dev, &dev_priv->render_ring,
1906 invalidate_domains,
1907 flush_domains);
1909 if (HAS_BSD(dev))
1910 dev_priv->bsd_ring.flush(dev, &dev_priv->bsd_ring,
1911 invalidate_domains,
1912 flush_domains);
1916 * Ensures that all rendering to the object has completed and the object is
1917 * safe to unbind from the GTT or access from the CPU.
1919 static int
1920 i915_gem_object_wait_rendering(struct drm_gem_object *obj)
1922 struct drm_device *dev = obj->dev;
1923 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1924 int ret;
1926 /* This function only exists to support waiting for existing rendering,
1927 * not for emitting required flushes.
1929 BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0);
1931 /* If there is rendering queued on the buffer being evicted, wait for
1932 * it.
1934 if (obj_priv->active) {
1935 #if WATCH_BUF
1936 DRM_INFO("%s: object %p wait for seqno %08x\n",
1937 __func__, obj, obj_priv->last_rendering_seqno);
1938 #endif
1939 ret = i915_wait_request(dev,
1940 obj_priv->last_rendering_seqno, obj_priv->ring);
1941 if (ret != 0)
1942 return ret;
1945 return 0;
1949 * Unbinds an object from the GTT aperture.
1952 i915_gem_object_unbind(struct drm_gem_object *obj)
1954 struct drm_device *dev = obj->dev;
1955 drm_i915_private_t *dev_priv = dev->dev_private;
1956 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1957 int ret = 0;
1959 #if WATCH_BUF
1960 DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj);
1961 DRM_INFO("gtt_space %p\n", obj_priv->gtt_space);
1962 #endif
1963 if (obj_priv->gtt_space == NULL)
1964 return 0;
1966 if (obj_priv->pin_count != 0) {
1967 DRM_ERROR("Attempting to unbind pinned buffer\n");
1968 return -EINVAL;
1971 /* blow away mappings if mapped through GTT */
1972 i915_gem_release_mmap(obj);
1974 /* Move the object to the CPU domain to ensure that
1975 * any possible CPU writes while it's not in the GTT
1976 * are flushed when we go to remap it. This will
1977 * also ensure that all pending GPU writes are finished
1978 * before we unbind.
1980 ret = i915_gem_object_set_to_cpu_domain(obj, 1);
1981 if (ret == -ERESTARTSYS)
1982 return ret;
1983 /* Continue on if we fail due to EIO, the GPU is hung so we
1984 * should be safe and we need to cleanup or else we might
1985 * cause memory corruption through use-after-free.
1988 /* release the fence reg _after_ flushing */
1989 if (obj_priv->fence_reg != I915_FENCE_REG_NONE)
1990 i915_gem_clear_fence_reg(obj);
1992 if (obj_priv->agp_mem != NULL) {
1993 drm_unbind_agp(obj_priv->agp_mem);
1994 drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE);
1995 obj_priv->agp_mem = NULL;
1998 i915_gem_object_put_pages(obj);
1999 BUG_ON(obj_priv->pages_refcount);
2001 if (obj_priv->gtt_space) {
2002 atomic_dec(&dev->gtt_count);
2003 atomic_sub(obj->size, &dev->gtt_memory);
2005 drm_mm_put_block(obj_priv->gtt_space);
2006 obj_priv->gtt_space = NULL;
2009 /* Remove ourselves from the LRU list if present. */
2010 spin_lock(&dev_priv->mm.active_list_lock);
2011 if (!list_empty(&obj_priv->list))
2012 list_del_init(&obj_priv->list);
2013 spin_unlock(&dev_priv->mm.active_list_lock);
2015 if (i915_gem_object_is_purgeable(obj_priv))
2016 i915_gem_object_truncate(obj);
2018 trace_i915_gem_object_unbind(obj);
2020 return ret;
2024 i915_gpu_idle(struct drm_device *dev)
2026 drm_i915_private_t *dev_priv = dev->dev_private;
2027 bool lists_empty;
2028 uint32_t seqno1, seqno2;
2029 int ret;
2031 spin_lock(&dev_priv->mm.active_list_lock);
2032 lists_empty = (list_empty(&dev_priv->mm.flushing_list) &&
2033 list_empty(&dev_priv->render_ring.active_list) &&
2034 (!HAS_BSD(dev) ||
2035 list_empty(&dev_priv->bsd_ring.active_list)));
2036 spin_unlock(&dev_priv->mm.active_list_lock);
2038 if (lists_empty)
2039 return 0;
2041 /* Flush everything onto the inactive list. */
2042 i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
2043 seqno1 = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS,
2044 &dev_priv->render_ring);
2045 if (seqno1 == 0)
2046 return -ENOMEM;
2047 ret = i915_wait_request(dev, seqno1, &dev_priv->render_ring);
2049 if (HAS_BSD(dev)) {
2050 seqno2 = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS,
2051 &dev_priv->bsd_ring);
2052 if (seqno2 == 0)
2053 return -ENOMEM;
2055 ret = i915_wait_request(dev, seqno2, &dev_priv->bsd_ring);
2056 if (ret)
2057 return ret;
2061 return ret;
2065 i915_gem_object_get_pages(struct drm_gem_object *obj,
2066 gfp_t gfpmask)
2068 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2069 int page_count, i;
2070 struct address_space *mapping;
2071 struct inode *inode;
2072 struct page *page;
2074 BUG_ON(obj_priv->pages_refcount
2075 == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT);
2077 if (obj_priv->pages_refcount++ != 0)
2078 return 0;
2080 /* Get the list of pages out of our struct file. They'll be pinned
2081 * at this point until we release them.
2083 page_count = obj->size / PAGE_SIZE;
2084 BUG_ON(obj_priv->pages != NULL);
2085 obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *));
2086 if (obj_priv->pages == NULL) {
2087 obj_priv->pages_refcount--;
2088 return -ENOMEM;
2091 inode = obj->filp->f_path.dentry->d_inode;
2092 mapping = inode->i_mapping;
2093 for (i = 0; i < page_count; i++) {
2094 page = read_cache_page_gfp(mapping, i,
2095 GFP_HIGHUSER |
2096 __GFP_COLD |
2097 __GFP_RECLAIMABLE |
2098 gfpmask);
2099 if (IS_ERR(page))
2100 goto err_pages;
2102 obj_priv->pages[i] = page;
2105 if (obj_priv->tiling_mode != I915_TILING_NONE)
2106 i915_gem_object_do_bit_17_swizzle(obj);
2108 return 0;
2110 err_pages:
2111 while (i--)
2112 page_cache_release(obj_priv->pages[i]);
2114 drm_free_large(obj_priv->pages);
2115 obj_priv->pages = NULL;
2116 obj_priv->pages_refcount--;
2117 return PTR_ERR(page);
2120 static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg)
2122 struct drm_gem_object *obj = reg->obj;
2123 struct drm_device *dev = obj->dev;
2124 drm_i915_private_t *dev_priv = dev->dev_private;
2125 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2126 int regnum = obj_priv->fence_reg;
2127 uint64_t val;
2129 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2130 0xfffff000) << 32;
2131 val |= obj_priv->gtt_offset & 0xfffff000;
2132 val |= (uint64_t)((obj_priv->stride / 128) - 1) <<
2133 SANDYBRIDGE_FENCE_PITCH_SHIFT;
2135 if (obj_priv->tiling_mode == I915_TILING_Y)
2136 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2137 val |= I965_FENCE_REG_VALID;
2139 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val);
2142 static void i965_write_fence_reg(struct drm_i915_fence_reg *reg)
2144 struct drm_gem_object *obj = reg->obj;
2145 struct drm_device *dev = obj->dev;
2146 drm_i915_private_t *dev_priv = dev->dev_private;
2147 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2148 int regnum = obj_priv->fence_reg;
2149 uint64_t val;
2151 val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) &
2152 0xfffff000) << 32;
2153 val |= obj_priv->gtt_offset & 0xfffff000;
2154 val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT;
2155 if (obj_priv->tiling_mode == I915_TILING_Y)
2156 val |= 1 << I965_FENCE_TILING_Y_SHIFT;
2157 val |= I965_FENCE_REG_VALID;
2159 I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val);
2162 static void i915_write_fence_reg(struct drm_i915_fence_reg *reg)
2164 struct drm_gem_object *obj = reg->obj;
2165 struct drm_device *dev = obj->dev;
2166 drm_i915_private_t *dev_priv = dev->dev_private;
2167 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2168 int regnum = obj_priv->fence_reg;
2169 int tile_width;
2170 uint32_t fence_reg, val;
2171 uint32_t pitch_val;
2173 if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) ||
2174 (obj_priv->gtt_offset & (obj->size - 1))) {
2175 WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n",
2176 __func__, obj_priv->gtt_offset, obj->size);
2177 return;
2180 if (obj_priv->tiling_mode == I915_TILING_Y &&
2181 HAS_128_BYTE_Y_TILING(dev))
2182 tile_width = 128;
2183 else
2184 tile_width = 512;
2186 /* Note: pitch better be a power of two tile widths */
2187 pitch_val = obj_priv->stride / tile_width;
2188 pitch_val = ffs(pitch_val) - 1;
2190 if (obj_priv->tiling_mode == I915_TILING_Y &&
2191 HAS_128_BYTE_Y_TILING(dev))
2192 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2193 else
2194 WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL);
2196 val = obj_priv->gtt_offset;
2197 if (obj_priv->tiling_mode == I915_TILING_Y)
2198 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2199 val |= I915_FENCE_SIZE_BITS(obj->size);
2200 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2201 val |= I830_FENCE_REG_VALID;
2203 if (regnum < 8)
2204 fence_reg = FENCE_REG_830_0 + (regnum * 4);
2205 else
2206 fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4);
2207 I915_WRITE(fence_reg, val);
2210 static void i830_write_fence_reg(struct drm_i915_fence_reg *reg)
2212 struct drm_gem_object *obj = reg->obj;
2213 struct drm_device *dev = obj->dev;
2214 drm_i915_private_t *dev_priv = dev->dev_private;
2215 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2216 int regnum = obj_priv->fence_reg;
2217 uint32_t val;
2218 uint32_t pitch_val;
2219 uint32_t fence_size_bits;
2221 if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) ||
2222 (obj_priv->gtt_offset & (obj->size - 1))) {
2223 WARN(1, "%s: object 0x%08x not 512K or size aligned\n",
2224 __func__, obj_priv->gtt_offset);
2225 return;
2228 pitch_val = obj_priv->stride / 128;
2229 pitch_val = ffs(pitch_val) - 1;
2230 WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL);
2232 val = obj_priv->gtt_offset;
2233 if (obj_priv->tiling_mode == I915_TILING_Y)
2234 val |= 1 << I830_FENCE_TILING_Y_SHIFT;
2235 fence_size_bits = I830_FENCE_SIZE_BITS(obj->size);
2236 WARN_ON(fence_size_bits & ~0x00000f00);
2237 val |= fence_size_bits;
2238 val |= pitch_val << I830_FENCE_PITCH_SHIFT;
2239 val |= I830_FENCE_REG_VALID;
2241 I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val);
2244 static int i915_find_fence_reg(struct drm_device *dev)
2246 struct drm_i915_fence_reg *reg = NULL;
2247 struct drm_i915_gem_object *obj_priv = NULL;
2248 struct drm_i915_private *dev_priv = dev->dev_private;
2249 struct drm_gem_object *obj = NULL;
2250 int i, avail, ret;
2252 /* First try to find a free reg */
2253 avail = 0;
2254 for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) {
2255 reg = &dev_priv->fence_regs[i];
2256 if (!reg->obj)
2257 return i;
2259 obj_priv = to_intel_bo(reg->obj);
2260 if (!obj_priv->pin_count)
2261 avail++;
2264 if (avail == 0)
2265 return -ENOSPC;
2267 /* None available, try to steal one or wait for a user to finish */
2268 i = I915_FENCE_REG_NONE;
2269 list_for_each_entry(reg, &dev_priv->mm.fence_list,
2270 lru_list) {
2271 obj = reg->obj;
2272 obj_priv = to_intel_bo(obj);
2274 if (obj_priv->pin_count)
2275 continue;
2277 /* found one! */
2278 i = obj_priv->fence_reg;
2279 break;
2282 BUG_ON(i == I915_FENCE_REG_NONE);
2284 /* We only have a reference on obj from the active list. put_fence_reg
2285 * might drop that one, causing a use-after-free in it. So hold a
2286 * private reference to obj like the other callers of put_fence_reg
2287 * (set_tiling ioctl) do. */
2288 drm_gem_object_reference(obj);
2289 ret = i915_gem_object_put_fence_reg(obj);
2290 drm_gem_object_unreference(obj);
2291 if (ret != 0)
2292 return ret;
2294 return i;
2298 * i915_gem_object_get_fence_reg - set up a fence reg for an object
2299 * @obj: object to map through a fence reg
2301 * When mapping objects through the GTT, userspace wants to be able to write
2302 * to them without having to worry about swizzling if the object is tiled.
2304 * This function walks the fence regs looking for a free one for @obj,
2305 * stealing one if it can't find any.
2307 * It then sets up the reg based on the object's properties: address, pitch
2308 * and tiling format.
2311 i915_gem_object_get_fence_reg(struct drm_gem_object *obj)
2313 struct drm_device *dev = obj->dev;
2314 struct drm_i915_private *dev_priv = dev->dev_private;
2315 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2316 struct drm_i915_fence_reg *reg = NULL;
2317 int ret;
2319 /* Just update our place in the LRU if our fence is getting used. */
2320 if (obj_priv->fence_reg != I915_FENCE_REG_NONE) {
2321 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2322 list_move_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2323 return 0;
2326 switch (obj_priv->tiling_mode) {
2327 case I915_TILING_NONE:
2328 WARN(1, "allocating a fence for non-tiled object?\n");
2329 break;
2330 case I915_TILING_X:
2331 if (!obj_priv->stride)
2332 return -EINVAL;
2333 WARN((obj_priv->stride & (512 - 1)),
2334 "object 0x%08x is X tiled but has non-512B pitch\n",
2335 obj_priv->gtt_offset);
2336 break;
2337 case I915_TILING_Y:
2338 if (!obj_priv->stride)
2339 return -EINVAL;
2340 WARN((obj_priv->stride & (128 - 1)),
2341 "object 0x%08x is Y tiled but has non-128B pitch\n",
2342 obj_priv->gtt_offset);
2343 break;
2346 ret = i915_find_fence_reg(dev);
2347 if (ret < 0)
2348 return ret;
2350 obj_priv->fence_reg = ret;
2351 reg = &dev_priv->fence_regs[obj_priv->fence_reg];
2352 list_add_tail(&reg->lru_list, &dev_priv->mm.fence_list);
2354 reg->obj = obj;
2356 switch (INTEL_INFO(dev)->gen) {
2357 case 6:
2358 sandybridge_write_fence_reg(reg);
2359 break;
2360 case 5:
2361 case 4:
2362 i965_write_fence_reg(reg);
2363 break;
2364 case 3:
2365 i915_write_fence_reg(reg);
2366 break;
2367 case 2:
2368 i830_write_fence_reg(reg);
2369 break;
2372 trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg,
2373 obj_priv->tiling_mode);
2375 return 0;
2379 * i915_gem_clear_fence_reg - clear out fence register info
2380 * @obj: object to clear
2382 * Zeroes out the fence register itself and clears out the associated
2383 * data structures in dev_priv and obj_priv.
2385 static void
2386 i915_gem_clear_fence_reg(struct drm_gem_object *obj)
2388 struct drm_device *dev = obj->dev;
2389 drm_i915_private_t *dev_priv = dev->dev_private;
2390 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2391 struct drm_i915_fence_reg *reg =
2392 &dev_priv->fence_regs[obj_priv->fence_reg];
2393 uint32_t fence_reg;
2395 switch (INTEL_INFO(dev)->gen) {
2396 case 6:
2397 I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 +
2398 (obj_priv->fence_reg * 8), 0);
2399 break;
2400 case 5:
2401 case 4:
2402 I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0);
2403 break;
2404 case 3:
2405 if (obj_priv->fence_reg >= 8)
2406 fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - 8) * 4;
2407 else
2408 case 2:
2409 fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4;
2411 I915_WRITE(fence_reg, 0);
2412 break;
2415 reg->obj = NULL;
2416 obj_priv->fence_reg = I915_FENCE_REG_NONE;
2417 list_del_init(&reg->lru_list);
2421 * i915_gem_object_put_fence_reg - waits on outstanding fenced access
2422 * to the buffer to finish, and then resets the fence register.
2423 * @obj: tiled object holding a fence register.
2425 * Zeroes out the fence register itself and clears out the associated
2426 * data structures in dev_priv and obj_priv.
2429 i915_gem_object_put_fence_reg(struct drm_gem_object *obj)
2431 struct drm_device *dev = obj->dev;
2432 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2434 if (obj_priv->fence_reg == I915_FENCE_REG_NONE)
2435 return 0;
2437 /* If we've changed tiling, GTT-mappings of the object
2438 * need to re-fault to ensure that the correct fence register
2439 * setup is in place.
2441 i915_gem_release_mmap(obj);
2443 /* On the i915, GPU access to tiled buffers is via a fence,
2444 * therefore we must wait for any outstanding access to complete
2445 * before clearing the fence.
2447 if (!IS_I965G(dev)) {
2448 int ret;
2450 ret = i915_gem_object_flush_gpu_write_domain(obj);
2451 if (ret != 0)
2452 return ret;
2454 ret = i915_gem_object_wait_rendering(obj);
2455 if (ret != 0)
2456 return ret;
2459 i915_gem_object_flush_gtt_write_domain(obj);
2460 i915_gem_clear_fence_reg (obj);
2462 return 0;
2466 * Finds free space in the GTT aperture and binds the object there.
2468 static int
2469 i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment)
2471 struct drm_device *dev = obj->dev;
2472 drm_i915_private_t *dev_priv = dev->dev_private;
2473 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2474 struct drm_mm_node *free_space;
2475 gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN;
2476 int ret;
2478 if (obj_priv->madv != I915_MADV_WILLNEED) {
2479 DRM_ERROR("Attempting to bind a purgeable object\n");
2480 return -EINVAL;
2483 if (alignment == 0)
2484 alignment = i915_gem_get_gtt_alignment(obj);
2485 if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) {
2486 DRM_ERROR("Invalid object alignment requested %u\n", alignment);
2487 return -EINVAL;
2490 /* If the object is bigger than the entire aperture, reject it early
2491 * before evicting everything in a vain attempt to find space.
2493 if (obj->size > dev->gtt_total) {
2494 DRM_ERROR("Attempting to bind an object larger than the aperture\n");
2495 return -E2BIG;
2498 search_free:
2499 free_space = drm_mm_search_free(&dev_priv->mm.gtt_space,
2500 obj->size, alignment, 0);
2501 if (free_space != NULL) {
2502 obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size,
2503 alignment);
2504 if (obj_priv->gtt_space != NULL)
2505 obj_priv->gtt_offset = obj_priv->gtt_space->start;
2507 if (obj_priv->gtt_space == NULL) {
2508 /* If the gtt is empty and we're still having trouble
2509 * fitting our object in, we're out of memory.
2511 #if WATCH_LRU
2512 DRM_INFO("%s: GTT full, evicting something\n", __func__);
2513 #endif
2514 ret = i915_gem_evict_something(dev, obj->size, alignment);
2515 if (ret)
2516 return ret;
2518 goto search_free;
2521 #if WATCH_BUF
2522 DRM_INFO("Binding object of size %zd at 0x%08x\n",
2523 obj->size, obj_priv->gtt_offset);
2524 #endif
2525 ret = i915_gem_object_get_pages(obj, gfpmask);
2526 if (ret) {
2527 drm_mm_put_block(obj_priv->gtt_space);
2528 obj_priv->gtt_space = NULL;
2530 if (ret == -ENOMEM) {
2531 /* first try to clear up some space from the GTT */
2532 ret = i915_gem_evict_something(dev, obj->size,
2533 alignment);
2534 if (ret) {
2535 /* now try to shrink everyone else */
2536 if (gfpmask) {
2537 gfpmask = 0;
2538 goto search_free;
2541 return ret;
2544 goto search_free;
2547 return ret;
2550 /* Create an AGP memory structure pointing at our pages, and bind it
2551 * into the GTT.
2553 obj_priv->agp_mem = drm_agp_bind_pages(dev,
2554 obj_priv->pages,
2555 obj->size >> PAGE_SHIFT,
2556 obj_priv->gtt_offset,
2557 obj_priv->agp_type);
2558 if (obj_priv->agp_mem == NULL) {
2559 i915_gem_object_put_pages(obj);
2560 drm_mm_put_block(obj_priv->gtt_space);
2561 obj_priv->gtt_space = NULL;
2563 ret = i915_gem_evict_something(dev, obj->size, alignment);
2564 if (ret)
2565 return ret;
2567 goto search_free;
2569 atomic_inc(&dev->gtt_count);
2570 atomic_add(obj->size, &dev->gtt_memory);
2572 /* keep track of bounds object by adding it to the inactive list */
2573 list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list);
2575 /* Assert that the object is not currently in any GPU domain. As it
2576 * wasn't in the GTT, there shouldn't be any way it could have been in
2577 * a GPU cache
2579 BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS);
2580 BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS);
2582 trace_i915_gem_object_bind(obj, obj_priv->gtt_offset);
2584 return 0;
2587 void
2588 i915_gem_clflush_object(struct drm_gem_object *obj)
2590 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2592 /* If we don't have a page list set up, then we're not pinned
2593 * to GPU, and we can ignore the cache flush because it'll happen
2594 * again at bind time.
2596 if (obj_priv->pages == NULL)
2597 return;
2599 trace_i915_gem_object_clflush(obj);
2601 drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE);
2604 /** Flushes any GPU write domain for the object if it's dirty. */
2605 static int
2606 i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj)
2608 struct drm_device *dev = obj->dev;
2609 uint32_t old_write_domain;
2610 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2612 if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
2613 return 0;
2615 /* Queue the GPU write cache flushing we need. */
2616 old_write_domain = obj->write_domain;
2617 i915_gem_flush(dev, 0, obj->write_domain);
2618 if (i915_add_request(dev, NULL, obj->write_domain, obj_priv->ring) == 0)
2619 return -ENOMEM;
2621 trace_i915_gem_object_change_domain(obj,
2622 obj->read_domains,
2623 old_write_domain);
2624 return 0;
2627 /** Flushes the GTT write domain for the object if it's dirty. */
2628 static void
2629 i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj)
2631 uint32_t old_write_domain;
2633 if (obj->write_domain != I915_GEM_DOMAIN_GTT)
2634 return;
2636 /* No actual flushing is required for the GTT write domain. Writes
2637 * to it immediately go to main memory as far as we know, so there's
2638 * no chipset flush. It also doesn't land in render cache.
2640 old_write_domain = obj->write_domain;
2641 obj->write_domain = 0;
2643 trace_i915_gem_object_change_domain(obj,
2644 obj->read_domains,
2645 old_write_domain);
2648 /** Flushes the CPU write domain for the object if it's dirty. */
2649 static void
2650 i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj)
2652 struct drm_device *dev = obj->dev;
2653 uint32_t old_write_domain;
2655 if (obj->write_domain != I915_GEM_DOMAIN_CPU)
2656 return;
2658 i915_gem_clflush_object(obj);
2659 drm_agp_chipset_flush(dev);
2660 old_write_domain = obj->write_domain;
2661 obj->write_domain = 0;
2663 trace_i915_gem_object_change_domain(obj,
2664 obj->read_domains,
2665 old_write_domain);
2669 i915_gem_object_flush_write_domain(struct drm_gem_object *obj)
2671 int ret = 0;
2673 switch (obj->write_domain) {
2674 case I915_GEM_DOMAIN_GTT:
2675 i915_gem_object_flush_gtt_write_domain(obj);
2676 break;
2677 case I915_GEM_DOMAIN_CPU:
2678 i915_gem_object_flush_cpu_write_domain(obj);
2679 break;
2680 default:
2681 ret = i915_gem_object_flush_gpu_write_domain(obj);
2682 break;
2685 return ret;
2689 * Moves a single object to the GTT read, and possibly write domain.
2691 * This function returns when the move is complete, including waiting on
2692 * flushes to occur.
2695 i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write)
2697 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2698 uint32_t old_write_domain, old_read_domains;
2699 int ret;
2701 /* Not valid to be called on unbound objects. */
2702 if (obj_priv->gtt_space == NULL)
2703 return -EINVAL;
2705 ret = i915_gem_object_flush_gpu_write_domain(obj);
2706 if (ret != 0)
2707 return ret;
2709 /* Wait on any GPU rendering and flushing to occur. */
2710 ret = i915_gem_object_wait_rendering(obj);
2711 if (ret != 0)
2712 return ret;
2714 old_write_domain = obj->write_domain;
2715 old_read_domains = obj->read_domains;
2717 /* If we're writing through the GTT domain, then CPU and GPU caches
2718 * will need to be invalidated at next use.
2720 if (write)
2721 obj->read_domains &= I915_GEM_DOMAIN_GTT;
2723 i915_gem_object_flush_cpu_write_domain(obj);
2725 /* It should now be out of any other write domains, and we can update
2726 * the domain values for our changes.
2728 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2729 obj->read_domains |= I915_GEM_DOMAIN_GTT;
2730 if (write) {
2731 obj->write_domain = I915_GEM_DOMAIN_GTT;
2732 obj_priv->dirty = 1;
2735 trace_i915_gem_object_change_domain(obj,
2736 old_read_domains,
2737 old_write_domain);
2739 return 0;
2743 * Prepare buffer for display plane. Use uninterruptible for possible flush
2744 * wait, as in modesetting process we're not supposed to be interrupted.
2747 i915_gem_object_set_to_display_plane(struct drm_gem_object *obj)
2749 struct drm_device *dev = obj->dev;
2750 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2751 uint32_t old_write_domain, old_read_domains;
2752 int ret;
2754 /* Not valid to be called on unbound objects. */
2755 if (obj_priv->gtt_space == NULL)
2756 return -EINVAL;
2758 ret = i915_gem_object_flush_gpu_write_domain(obj);
2759 if (ret)
2760 return ret;
2762 /* Wait on any GPU rendering and flushing to occur. */
2763 if (obj_priv->active) {
2764 #if WATCH_BUF
2765 DRM_INFO("%s: object %p wait for seqno %08x\n",
2766 __func__, obj, obj_priv->last_rendering_seqno);
2767 #endif
2768 ret = i915_do_wait_request(dev,
2769 obj_priv->last_rendering_seqno,
2771 obj_priv->ring);
2772 if (ret != 0)
2773 return ret;
2776 i915_gem_object_flush_cpu_write_domain(obj);
2778 old_write_domain = obj->write_domain;
2779 old_read_domains = obj->read_domains;
2781 /* It should now be out of any other write domains, and we can update
2782 * the domain values for our changes.
2784 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
2785 obj->read_domains = I915_GEM_DOMAIN_GTT;
2786 obj->write_domain = I915_GEM_DOMAIN_GTT;
2787 obj_priv->dirty = 1;
2789 trace_i915_gem_object_change_domain(obj,
2790 old_read_domains,
2791 old_write_domain);
2793 return 0;
2797 * Moves a single object to the CPU read, and possibly write domain.
2799 * This function returns when the move is complete, including waiting on
2800 * flushes to occur.
2802 static int
2803 i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write)
2805 uint32_t old_write_domain, old_read_domains;
2806 int ret;
2808 ret = i915_gem_object_flush_gpu_write_domain(obj);
2809 if (ret)
2810 return ret;
2812 /* Wait on any GPU rendering and flushing to occur. */
2813 ret = i915_gem_object_wait_rendering(obj);
2814 if (ret != 0)
2815 return ret;
2817 i915_gem_object_flush_gtt_write_domain(obj);
2819 /* If we have a partially-valid cache of the object in the CPU,
2820 * finish invalidating it and free the per-page flags.
2822 i915_gem_object_set_to_full_cpu_read_domain(obj);
2824 old_write_domain = obj->write_domain;
2825 old_read_domains = obj->read_domains;
2827 /* Flush the CPU cache if it's still invalid. */
2828 if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
2829 i915_gem_clflush_object(obj);
2831 obj->read_domains |= I915_GEM_DOMAIN_CPU;
2834 /* It should now be out of any other write domains, and we can update
2835 * the domain values for our changes.
2837 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
2839 /* If we're writing through the CPU, then the GPU read domains will
2840 * need to be invalidated at next use.
2842 if (write) {
2843 obj->read_domains &= I915_GEM_DOMAIN_CPU;
2844 obj->write_domain = I915_GEM_DOMAIN_CPU;
2847 trace_i915_gem_object_change_domain(obj,
2848 old_read_domains,
2849 old_write_domain);
2851 return 0;
2855 * Set the next domain for the specified object. This
2856 * may not actually perform the necessary flushing/invaliding though,
2857 * as that may want to be batched with other set_domain operations
2859 * This is (we hope) the only really tricky part of gem. The goal
2860 * is fairly simple -- track which caches hold bits of the object
2861 * and make sure they remain coherent. A few concrete examples may
2862 * help to explain how it works. For shorthand, we use the notation
2863 * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the
2864 * a pair of read and write domain masks.
2866 * Case 1: the batch buffer
2868 * 1. Allocated
2869 * 2. Written by CPU
2870 * 3. Mapped to GTT
2871 * 4. Read by GPU
2872 * 5. Unmapped from GTT
2873 * 6. Freed
2875 * Let's take these a step at a time
2877 * 1. Allocated
2878 * Pages allocated from the kernel may still have
2879 * cache contents, so we set them to (CPU, CPU) always.
2880 * 2. Written by CPU (using pwrite)
2881 * The pwrite function calls set_domain (CPU, CPU) and
2882 * this function does nothing (as nothing changes)
2883 * 3. Mapped by GTT
2884 * This function asserts that the object is not
2885 * currently in any GPU-based read or write domains
2886 * 4. Read by GPU
2887 * i915_gem_execbuffer calls set_domain (COMMAND, 0).
2888 * As write_domain is zero, this function adds in the
2889 * current read domains (CPU+COMMAND, 0).
2890 * flush_domains is set to CPU.
2891 * invalidate_domains is set to COMMAND
2892 * clflush is run to get data out of the CPU caches
2893 * then i915_dev_set_domain calls i915_gem_flush to
2894 * emit an MI_FLUSH and drm_agp_chipset_flush
2895 * 5. Unmapped from GTT
2896 * i915_gem_object_unbind calls set_domain (CPU, CPU)
2897 * flush_domains and invalidate_domains end up both zero
2898 * so no flushing/invalidating happens
2899 * 6. Freed
2900 * yay, done
2902 * Case 2: The shared render buffer
2904 * 1. Allocated
2905 * 2. Mapped to GTT
2906 * 3. Read/written by GPU
2907 * 4. set_domain to (CPU,CPU)
2908 * 5. Read/written by CPU
2909 * 6. Read/written by GPU
2911 * 1. Allocated
2912 * Same as last example, (CPU, CPU)
2913 * 2. Mapped to GTT
2914 * Nothing changes (assertions find that it is not in the GPU)
2915 * 3. Read/written by GPU
2916 * execbuffer calls set_domain (RENDER, RENDER)
2917 * flush_domains gets CPU
2918 * invalidate_domains gets GPU
2919 * clflush (obj)
2920 * MI_FLUSH and drm_agp_chipset_flush
2921 * 4. set_domain (CPU, CPU)
2922 * flush_domains gets GPU
2923 * invalidate_domains gets CPU
2924 * wait_rendering (obj) to make sure all drawing is complete.
2925 * This will include an MI_FLUSH to get the data from GPU
2926 * to memory
2927 * clflush (obj) to invalidate the CPU cache
2928 * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?)
2929 * 5. Read/written by CPU
2930 * cache lines are loaded and dirtied
2931 * 6. Read written by GPU
2932 * Same as last GPU access
2934 * Case 3: The constant buffer
2936 * 1. Allocated
2937 * 2. Written by CPU
2938 * 3. Read by GPU
2939 * 4. Updated (written) by CPU again
2940 * 5. Read by GPU
2942 * 1. Allocated
2943 * (CPU, CPU)
2944 * 2. Written by CPU
2945 * (CPU, CPU)
2946 * 3. Read by GPU
2947 * (CPU+RENDER, 0)
2948 * flush_domains = CPU
2949 * invalidate_domains = RENDER
2950 * clflush (obj)
2951 * MI_FLUSH
2952 * drm_agp_chipset_flush
2953 * 4. Updated (written) by CPU again
2954 * (CPU, CPU)
2955 * flush_domains = 0 (no previous write domain)
2956 * invalidate_domains = 0 (no new read domains)
2957 * 5. Read by GPU
2958 * (CPU+RENDER, 0)
2959 * flush_domains = CPU
2960 * invalidate_domains = RENDER
2961 * clflush (obj)
2962 * MI_FLUSH
2963 * drm_agp_chipset_flush
2965 static void
2966 i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj)
2968 struct drm_device *dev = obj->dev;
2969 drm_i915_private_t *dev_priv = dev->dev_private;
2970 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
2971 uint32_t invalidate_domains = 0;
2972 uint32_t flush_domains = 0;
2973 uint32_t old_read_domains;
2975 BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU);
2976 BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU);
2978 intel_mark_busy(dev, obj);
2980 #if WATCH_BUF
2981 DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n",
2982 __func__, obj,
2983 obj->read_domains, obj->pending_read_domains,
2984 obj->write_domain, obj->pending_write_domain);
2985 #endif
2987 * If the object isn't moving to a new write domain,
2988 * let the object stay in multiple read domains
2990 if (obj->pending_write_domain == 0)
2991 obj->pending_read_domains |= obj->read_domains;
2992 else
2993 obj_priv->dirty = 1;
2996 * Flush the current write domain if
2997 * the new read domains don't match. Invalidate
2998 * any read domains which differ from the old
2999 * write domain
3001 if (obj->write_domain &&
3002 obj->write_domain != obj->pending_read_domains) {
3003 flush_domains |= obj->write_domain;
3004 invalidate_domains |=
3005 obj->pending_read_domains & ~obj->write_domain;
3008 * Invalidate any read caches which may have
3009 * stale data. That is, any new read domains.
3011 invalidate_domains |= obj->pending_read_domains & ~obj->read_domains;
3012 if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) {
3013 #if WATCH_BUF
3014 DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n",
3015 __func__, flush_domains, invalidate_domains);
3016 #endif
3017 i915_gem_clflush_object(obj);
3020 old_read_domains = obj->read_domains;
3022 /* The actual obj->write_domain will be updated with
3023 * pending_write_domain after we emit the accumulated flush for all
3024 * of our domain changes in execbuffers (which clears objects'
3025 * write_domains). So if we have a current write domain that we
3026 * aren't changing, set pending_write_domain to that.
3028 if (flush_domains == 0 && obj->pending_write_domain == 0)
3029 obj->pending_write_domain = obj->write_domain;
3030 obj->read_domains = obj->pending_read_domains;
3032 if (flush_domains & I915_GEM_GPU_DOMAINS) {
3033 if (obj_priv->ring == &dev_priv->render_ring)
3034 dev_priv->flush_rings |= FLUSH_RENDER_RING;
3035 else if (obj_priv->ring == &dev_priv->bsd_ring)
3036 dev_priv->flush_rings |= FLUSH_BSD_RING;
3039 dev->invalidate_domains |= invalidate_domains;
3040 dev->flush_domains |= flush_domains;
3041 #if WATCH_BUF
3042 DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n",
3043 __func__,
3044 obj->read_domains, obj->write_domain,
3045 dev->invalidate_domains, dev->flush_domains);
3046 #endif
3048 trace_i915_gem_object_change_domain(obj,
3049 old_read_domains,
3050 obj->write_domain);
3054 * Moves the object from a partially CPU read to a full one.
3056 * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(),
3057 * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU).
3059 static void
3060 i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj)
3062 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3064 if (!obj_priv->page_cpu_valid)
3065 return;
3067 /* If we're partially in the CPU read domain, finish moving it in.
3069 if (obj->read_domains & I915_GEM_DOMAIN_CPU) {
3070 int i;
3072 for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) {
3073 if (obj_priv->page_cpu_valid[i])
3074 continue;
3075 drm_clflush_pages(obj_priv->pages + i, 1);
3079 /* Free the page_cpu_valid mappings which are now stale, whether
3080 * or not we've got I915_GEM_DOMAIN_CPU.
3082 kfree(obj_priv->page_cpu_valid);
3083 obj_priv->page_cpu_valid = NULL;
3087 * Set the CPU read domain on a range of the object.
3089 * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's
3090 * not entirely valid. The page_cpu_valid member of the object flags which
3091 * pages have been flushed, and will be respected by
3092 * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping
3093 * of the whole object.
3095 * This function returns when the move is complete, including waiting on
3096 * flushes to occur.
3098 static int
3099 i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj,
3100 uint64_t offset, uint64_t size)
3102 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3103 uint32_t old_read_domains;
3104 int i, ret;
3106 if (offset == 0 && size == obj->size)
3107 return i915_gem_object_set_to_cpu_domain(obj, 0);
3109 ret = i915_gem_object_flush_gpu_write_domain(obj);
3110 if (ret)
3111 return ret;
3113 /* Wait on any GPU rendering and flushing to occur. */
3114 ret = i915_gem_object_wait_rendering(obj);
3115 if (ret != 0)
3116 return ret;
3117 i915_gem_object_flush_gtt_write_domain(obj);
3119 /* If we're already fully in the CPU read domain, we're done. */
3120 if (obj_priv->page_cpu_valid == NULL &&
3121 (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0)
3122 return 0;
3124 /* Otherwise, create/clear the per-page CPU read domain flag if we're
3125 * newly adding I915_GEM_DOMAIN_CPU
3127 if (obj_priv->page_cpu_valid == NULL) {
3128 obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE,
3129 GFP_KERNEL);
3130 if (obj_priv->page_cpu_valid == NULL)
3131 return -ENOMEM;
3132 } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0)
3133 memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE);
3135 /* Flush the cache on any pages that are still invalid from the CPU's
3136 * perspective.
3138 for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE;
3139 i++) {
3140 if (obj_priv->page_cpu_valid[i])
3141 continue;
3143 drm_clflush_pages(obj_priv->pages + i, 1);
3145 obj_priv->page_cpu_valid[i] = 1;
3148 /* It should now be out of any other write domains, and we can update
3149 * the domain values for our changes.
3151 BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0);
3153 old_read_domains = obj->read_domains;
3154 obj->read_domains |= I915_GEM_DOMAIN_CPU;
3156 trace_i915_gem_object_change_domain(obj,
3157 old_read_domains,
3158 obj->write_domain);
3160 return 0;
3164 * Pin an object to the GTT and evaluate the relocations landing in it.
3166 static int
3167 i915_gem_object_pin_and_relocate(struct drm_gem_object *obj,
3168 struct drm_file *file_priv,
3169 struct drm_i915_gem_exec_object2 *entry,
3170 struct drm_i915_gem_relocation_entry *relocs)
3172 struct drm_device *dev = obj->dev;
3173 drm_i915_private_t *dev_priv = dev->dev_private;
3174 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3175 int i, ret;
3176 void __iomem *reloc_page;
3177 bool need_fence;
3179 need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
3180 obj_priv->tiling_mode != I915_TILING_NONE;
3182 /* Check fence reg constraints and rebind if necessary */
3183 if (need_fence &&
3184 !i915_gem_object_fence_offset_ok(obj,
3185 obj_priv->tiling_mode)) {
3186 ret = i915_gem_object_unbind(obj);
3187 if (ret)
3188 return ret;
3191 /* Choose the GTT offset for our buffer and put it there. */
3192 ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment);
3193 if (ret)
3194 return ret;
3197 * Pre-965 chips need a fence register set up in order to
3198 * properly handle blits to/from tiled surfaces.
3200 if (need_fence) {
3201 ret = i915_gem_object_get_fence_reg(obj);
3202 if (ret != 0) {
3203 i915_gem_object_unpin(obj);
3204 return ret;
3208 entry->offset = obj_priv->gtt_offset;
3210 /* Apply the relocations, using the GTT aperture to avoid cache
3211 * flushing requirements.
3213 for (i = 0; i < entry->relocation_count; i++) {
3214 struct drm_i915_gem_relocation_entry *reloc= &relocs[i];
3215 struct drm_gem_object *target_obj;
3216 struct drm_i915_gem_object *target_obj_priv;
3217 uint32_t reloc_val, reloc_offset;
3218 uint32_t __iomem *reloc_entry;
3220 target_obj = drm_gem_object_lookup(obj->dev, file_priv,
3221 reloc->target_handle);
3222 if (target_obj == NULL) {
3223 i915_gem_object_unpin(obj);
3224 return -ENOENT;
3226 target_obj_priv = to_intel_bo(target_obj);
3228 #if WATCH_RELOC
3229 DRM_INFO("%s: obj %p offset %08x target %d "
3230 "read %08x write %08x gtt %08x "
3231 "presumed %08x delta %08x\n",
3232 __func__,
3233 obj,
3234 (int) reloc->offset,
3235 (int) reloc->target_handle,
3236 (int) reloc->read_domains,
3237 (int) reloc->write_domain,
3238 (int) target_obj_priv->gtt_offset,
3239 (int) reloc->presumed_offset,
3240 reloc->delta);
3241 #endif
3243 /* The target buffer should have appeared before us in the
3244 * exec_object list, so it should have a GTT space bound by now.
3246 if (target_obj_priv->gtt_space == NULL) {
3247 DRM_ERROR("No GTT space found for object %d\n",
3248 reloc->target_handle);
3249 drm_gem_object_unreference(target_obj);
3250 i915_gem_object_unpin(obj);
3251 return -EINVAL;
3254 /* Validate that the target is in a valid r/w GPU domain */
3255 if (reloc->write_domain & (reloc->write_domain - 1)) {
3256 DRM_ERROR("reloc with multiple write domains: "
3257 "obj %p target %d offset %d "
3258 "read %08x write %08x",
3259 obj, reloc->target_handle,
3260 (int) reloc->offset,
3261 reloc->read_domains,
3262 reloc->write_domain);
3263 drm_gem_object_unreference(target_obj);
3264 i915_gem_object_unpin(obj);
3265 return -EINVAL;
3267 if (reloc->write_domain & I915_GEM_DOMAIN_CPU ||
3268 reloc->read_domains & I915_GEM_DOMAIN_CPU) {
3269 DRM_ERROR("reloc with read/write CPU domains: "
3270 "obj %p target %d offset %d "
3271 "read %08x write %08x",
3272 obj, reloc->target_handle,
3273 (int) reloc->offset,
3274 reloc->read_domains,
3275 reloc->write_domain);
3276 drm_gem_object_unreference(target_obj);
3277 i915_gem_object_unpin(obj);
3278 return -EINVAL;
3280 if (reloc->write_domain && target_obj->pending_write_domain &&
3281 reloc->write_domain != target_obj->pending_write_domain) {
3282 DRM_ERROR("Write domain conflict: "
3283 "obj %p target %d offset %d "
3284 "new %08x old %08x\n",
3285 obj, reloc->target_handle,
3286 (int) reloc->offset,
3287 reloc->write_domain,
3288 target_obj->pending_write_domain);
3289 drm_gem_object_unreference(target_obj);
3290 i915_gem_object_unpin(obj);
3291 return -EINVAL;
3294 target_obj->pending_read_domains |= reloc->read_domains;
3295 target_obj->pending_write_domain |= reloc->write_domain;
3297 /* If the relocation already has the right value in it, no
3298 * more work needs to be done.
3300 if (target_obj_priv->gtt_offset == reloc->presumed_offset) {
3301 drm_gem_object_unreference(target_obj);
3302 continue;
3305 /* Check that the relocation address is valid... */
3306 if (reloc->offset > obj->size - 4) {
3307 DRM_ERROR("Relocation beyond object bounds: "
3308 "obj %p target %d offset %d size %d.\n",
3309 obj, reloc->target_handle,
3310 (int) reloc->offset, (int) obj->size);
3311 drm_gem_object_unreference(target_obj);
3312 i915_gem_object_unpin(obj);
3313 return -EINVAL;
3315 if (reloc->offset & 3) {
3316 DRM_ERROR("Relocation not 4-byte aligned: "
3317 "obj %p target %d offset %d.\n",
3318 obj, reloc->target_handle,
3319 (int) reloc->offset);
3320 drm_gem_object_unreference(target_obj);
3321 i915_gem_object_unpin(obj);
3322 return -EINVAL;
3325 /* and points to somewhere within the target object. */
3326 if (reloc->delta >= target_obj->size) {
3327 DRM_ERROR("Relocation beyond target object bounds: "
3328 "obj %p target %d delta %d size %d.\n",
3329 obj, reloc->target_handle,
3330 (int) reloc->delta, (int) target_obj->size);
3331 drm_gem_object_unreference(target_obj);
3332 i915_gem_object_unpin(obj);
3333 return -EINVAL;
3336 ret = i915_gem_object_set_to_gtt_domain(obj, 1);
3337 if (ret != 0) {
3338 drm_gem_object_unreference(target_obj);
3339 i915_gem_object_unpin(obj);
3340 return -EINVAL;
3343 /* Map the page containing the relocation we're going to
3344 * perform.
3346 reloc_offset = obj_priv->gtt_offset + reloc->offset;
3347 reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
3348 (reloc_offset &
3349 ~(PAGE_SIZE - 1)));
3350 reloc_entry = (uint32_t __iomem *)(reloc_page +
3351 (reloc_offset & (PAGE_SIZE - 1)));
3352 reloc_val = target_obj_priv->gtt_offset + reloc->delta;
3354 #if WATCH_BUF
3355 DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n",
3356 obj, (unsigned int) reloc->offset,
3357 readl(reloc_entry), reloc_val);
3358 #endif
3359 writel(reloc_val, reloc_entry);
3360 io_mapping_unmap_atomic(reloc_page);
3362 /* The updated presumed offset for this entry will be
3363 * copied back out to the user.
3365 reloc->presumed_offset = target_obj_priv->gtt_offset;
3367 drm_gem_object_unreference(target_obj);
3370 #if WATCH_BUF
3371 if (0)
3372 i915_gem_dump_object(obj, 128, __func__, ~0);
3373 #endif
3374 return 0;
3377 /* Throttle our rendering by waiting until the ring has completed our requests
3378 * emitted over 20 msec ago.
3380 * Note that if we were to use the current jiffies each time around the loop,
3381 * we wouldn't escape the function with any frames outstanding if the time to
3382 * render a frame was over 20ms.
3384 * This should get us reasonable parallelism between CPU and GPU but also
3385 * relatively low latency when blocking on a particular request to finish.
3387 static int
3388 i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv)
3390 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
3391 int ret = 0;
3392 unsigned long recent_enough = jiffies - msecs_to_jiffies(20);
3394 mutex_lock(&dev->struct_mutex);
3395 while (!list_empty(&i915_file_priv->mm.request_list)) {
3396 struct drm_i915_gem_request *request;
3398 request = list_first_entry(&i915_file_priv->mm.request_list,
3399 struct drm_i915_gem_request,
3400 client_list);
3402 if (time_after_eq(request->emitted_jiffies, recent_enough))
3403 break;
3405 ret = i915_wait_request(dev, request->seqno, request->ring);
3406 if (ret != 0)
3407 break;
3409 mutex_unlock(&dev->struct_mutex);
3411 return ret;
3414 static int
3415 i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list,
3416 uint32_t buffer_count,
3417 struct drm_i915_gem_relocation_entry **relocs)
3419 uint32_t reloc_count = 0, reloc_index = 0, i;
3420 int ret;
3422 *relocs = NULL;
3423 for (i = 0; i < buffer_count; i++) {
3424 if (reloc_count + exec_list[i].relocation_count < reloc_count)
3425 return -EINVAL;
3426 reloc_count += exec_list[i].relocation_count;
3429 *relocs = drm_calloc_large(reloc_count, sizeof(**relocs));
3430 if (*relocs == NULL) {
3431 DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count);
3432 return -ENOMEM;
3435 for (i = 0; i < buffer_count; i++) {
3436 struct drm_i915_gem_relocation_entry __user *user_relocs;
3438 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3440 ret = copy_from_user(&(*relocs)[reloc_index],
3441 user_relocs,
3442 exec_list[i].relocation_count *
3443 sizeof(**relocs));
3444 if (ret != 0) {
3445 drm_free_large(*relocs);
3446 *relocs = NULL;
3447 return -EFAULT;
3450 reloc_index += exec_list[i].relocation_count;
3453 return 0;
3456 static int
3457 i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list,
3458 uint32_t buffer_count,
3459 struct drm_i915_gem_relocation_entry *relocs)
3461 uint32_t reloc_count = 0, i;
3462 int ret = 0;
3464 if (relocs == NULL)
3465 return 0;
3467 for (i = 0; i < buffer_count; i++) {
3468 struct drm_i915_gem_relocation_entry __user *user_relocs;
3469 int unwritten;
3471 user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr;
3473 unwritten = copy_to_user(user_relocs,
3474 &relocs[reloc_count],
3475 exec_list[i].relocation_count *
3476 sizeof(*relocs));
3478 if (unwritten) {
3479 ret = -EFAULT;
3480 goto err;
3483 reloc_count += exec_list[i].relocation_count;
3486 err:
3487 drm_free_large(relocs);
3489 return ret;
3492 static int
3493 i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec,
3494 uint64_t exec_offset)
3496 uint32_t exec_start, exec_len;
3498 exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
3499 exec_len = (uint32_t) exec->batch_len;
3501 if ((exec_start | exec_len) & 0x7)
3502 return -EINVAL;
3504 if (!exec_start)
3505 return -EINVAL;
3507 return 0;
3510 static int
3511 i915_gem_wait_for_pending_flip(struct drm_device *dev,
3512 struct drm_gem_object **object_list,
3513 int count)
3515 drm_i915_private_t *dev_priv = dev->dev_private;
3516 struct drm_i915_gem_object *obj_priv;
3517 DEFINE_WAIT(wait);
3518 int i, ret = 0;
3520 for (;;) {
3521 prepare_to_wait(&dev_priv->pending_flip_queue,
3522 &wait, TASK_INTERRUPTIBLE);
3523 for (i = 0; i < count; i++) {
3524 obj_priv = to_intel_bo(object_list[i]);
3525 if (atomic_read(&obj_priv->pending_flip) > 0)
3526 break;
3528 if (i == count)
3529 break;
3531 if (!signal_pending(current)) {
3532 mutex_unlock(&dev->struct_mutex);
3533 schedule();
3534 mutex_lock(&dev->struct_mutex);
3535 continue;
3537 ret = -ERESTARTSYS;
3538 break;
3540 finish_wait(&dev_priv->pending_flip_queue, &wait);
3542 return ret;
3547 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
3548 struct drm_file *file_priv,
3549 struct drm_i915_gem_execbuffer2 *args,
3550 struct drm_i915_gem_exec_object2 *exec_list)
3552 drm_i915_private_t *dev_priv = dev->dev_private;
3553 struct drm_gem_object **object_list = NULL;
3554 struct drm_gem_object *batch_obj;
3555 struct drm_i915_gem_object *obj_priv;
3556 struct drm_clip_rect *cliprects = NULL;
3557 struct drm_i915_gem_relocation_entry *relocs = NULL;
3558 int ret = 0, ret2, i, pinned = 0;
3559 uint64_t exec_offset;
3560 uint32_t seqno, flush_domains, reloc_index;
3561 int pin_tries, flips;
3563 struct intel_ring_buffer *ring = NULL;
3565 #if WATCH_EXEC
3566 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3567 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3568 #endif
3569 if (args->flags & I915_EXEC_BSD) {
3570 if (!HAS_BSD(dev)) {
3571 DRM_ERROR("execbuf with wrong flag\n");
3572 return -EINVAL;
3574 ring = &dev_priv->bsd_ring;
3575 } else {
3576 ring = &dev_priv->render_ring;
3579 if (args->buffer_count < 1) {
3580 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3581 return -EINVAL;
3583 object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count);
3584 if (object_list == NULL) {
3585 DRM_ERROR("Failed to allocate object list for %d buffers\n",
3586 args->buffer_count);
3587 ret = -ENOMEM;
3588 goto pre_mutex_err;
3591 if (args->num_cliprects != 0) {
3592 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
3593 GFP_KERNEL);
3594 if (cliprects == NULL) {
3595 ret = -ENOMEM;
3596 goto pre_mutex_err;
3599 ret = copy_from_user(cliprects,
3600 (struct drm_clip_rect __user *)
3601 (uintptr_t) args->cliprects_ptr,
3602 sizeof(*cliprects) * args->num_cliprects);
3603 if (ret != 0) {
3604 DRM_ERROR("copy %d cliprects failed: %d\n",
3605 args->num_cliprects, ret);
3606 ret = -EFAULT;
3607 goto pre_mutex_err;
3611 ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count,
3612 &relocs);
3613 if (ret != 0)
3614 goto pre_mutex_err;
3616 mutex_lock(&dev->struct_mutex);
3618 i915_verify_inactive(dev, __FILE__, __LINE__);
3620 if (atomic_read(&dev_priv->mm.wedged)) {
3621 mutex_unlock(&dev->struct_mutex);
3622 ret = -EIO;
3623 goto pre_mutex_err;
3626 if (dev_priv->mm.suspended) {
3627 mutex_unlock(&dev->struct_mutex);
3628 ret = -EBUSY;
3629 goto pre_mutex_err;
3632 /* Look up object handles */
3633 flips = 0;
3634 for (i = 0; i < args->buffer_count; i++) {
3635 object_list[i] = drm_gem_object_lookup(dev, file_priv,
3636 exec_list[i].handle);
3637 if (object_list[i] == NULL) {
3638 DRM_ERROR("Invalid object handle %d at index %d\n",
3639 exec_list[i].handle, i);
3640 /* prevent error path from reading uninitialized data */
3641 args->buffer_count = i + 1;
3642 ret = -ENOENT;
3643 goto err;
3646 obj_priv = to_intel_bo(object_list[i]);
3647 if (obj_priv->in_execbuffer) {
3648 DRM_ERROR("Object %p appears more than once in object list\n",
3649 object_list[i]);
3650 /* prevent error path from reading uninitialized data */
3651 args->buffer_count = i + 1;
3652 ret = -EINVAL;
3653 goto err;
3655 obj_priv->in_execbuffer = true;
3656 flips += atomic_read(&obj_priv->pending_flip);
3659 if (flips > 0) {
3660 ret = i915_gem_wait_for_pending_flip(dev, object_list,
3661 args->buffer_count);
3662 if (ret)
3663 goto err;
3666 /* Pin and relocate */
3667 for (pin_tries = 0; ; pin_tries++) {
3668 ret = 0;
3669 reloc_index = 0;
3671 for (i = 0; i < args->buffer_count; i++) {
3672 object_list[i]->pending_read_domains = 0;
3673 object_list[i]->pending_write_domain = 0;
3674 ret = i915_gem_object_pin_and_relocate(object_list[i],
3675 file_priv,
3676 &exec_list[i],
3677 &relocs[reloc_index]);
3678 if (ret)
3679 break;
3680 pinned = i + 1;
3681 reloc_index += exec_list[i].relocation_count;
3683 /* success */
3684 if (ret == 0)
3685 break;
3687 /* error other than GTT full, or we've already tried again */
3688 if (ret != -ENOSPC || pin_tries >= 1) {
3689 if (ret != -ERESTARTSYS) {
3690 unsigned long long total_size = 0;
3691 int num_fences = 0;
3692 for (i = 0; i < args->buffer_count; i++) {
3693 obj_priv = to_intel_bo(object_list[i]);
3695 total_size += object_list[i]->size;
3696 num_fences +=
3697 exec_list[i].flags & EXEC_OBJECT_NEEDS_FENCE &&
3698 obj_priv->tiling_mode != I915_TILING_NONE;
3700 DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n",
3701 pinned+1, args->buffer_count,
3702 total_size, num_fences,
3703 ret);
3704 DRM_ERROR("%d objects [%d pinned], "
3705 "%d object bytes [%d pinned], "
3706 "%d/%d gtt bytes\n",
3707 atomic_read(&dev->object_count),
3708 atomic_read(&dev->pin_count),
3709 atomic_read(&dev->object_memory),
3710 atomic_read(&dev->pin_memory),
3711 atomic_read(&dev->gtt_memory),
3712 dev->gtt_total);
3714 goto err;
3717 /* unpin all of our buffers */
3718 for (i = 0; i < pinned; i++)
3719 i915_gem_object_unpin(object_list[i]);
3720 pinned = 0;
3722 /* evict everyone we can from the aperture */
3723 ret = i915_gem_evict_everything(dev);
3724 if (ret && ret != -ENOSPC)
3725 goto err;
3728 /* Set the pending read domains for the batch buffer to COMMAND */
3729 batch_obj = object_list[args->buffer_count-1];
3730 if (batch_obj->pending_write_domain) {
3731 DRM_ERROR("Attempting to use self-modifying batch buffer\n");
3732 ret = -EINVAL;
3733 goto err;
3735 batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
3737 /* Sanity check the batch buffer, prior to moving objects */
3738 exec_offset = exec_list[args->buffer_count - 1].offset;
3739 ret = i915_gem_check_execbuffer (args, exec_offset);
3740 if (ret != 0) {
3741 DRM_ERROR("execbuf with invalid offset/length\n");
3742 goto err;
3745 i915_verify_inactive(dev, __FILE__, __LINE__);
3747 /* Zero the global flush/invalidate flags. These
3748 * will be modified as new domains are computed
3749 * for each object
3751 dev->invalidate_domains = 0;
3752 dev->flush_domains = 0;
3753 dev_priv->flush_rings = 0;
3755 for (i = 0; i < args->buffer_count; i++) {
3756 struct drm_gem_object *obj = object_list[i];
3758 /* Compute new gpu domains and update invalidate/flush */
3759 i915_gem_object_set_to_gpu_domain(obj);
3762 i915_verify_inactive(dev, __FILE__, __LINE__);
3764 if (dev->invalidate_domains | dev->flush_domains) {
3765 #if WATCH_EXEC
3766 DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n",
3767 __func__,
3768 dev->invalidate_domains,
3769 dev->flush_domains);
3770 #endif
3771 i915_gem_flush(dev,
3772 dev->invalidate_domains,
3773 dev->flush_domains);
3774 if (dev_priv->flush_rings & FLUSH_RENDER_RING)
3775 (void)i915_add_request(dev, file_priv,
3776 dev->flush_domains,
3777 &dev_priv->render_ring);
3778 if (dev_priv->flush_rings & FLUSH_BSD_RING)
3779 (void)i915_add_request(dev, file_priv,
3780 dev->flush_domains,
3781 &dev_priv->bsd_ring);
3784 for (i = 0; i < args->buffer_count; i++) {
3785 struct drm_gem_object *obj = object_list[i];
3786 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
3787 uint32_t old_write_domain = obj->write_domain;
3789 obj->write_domain = obj->pending_write_domain;
3790 if (obj->write_domain)
3791 list_move_tail(&obj_priv->gpu_write_list,
3792 &dev_priv->mm.gpu_write_list);
3793 else
3794 list_del_init(&obj_priv->gpu_write_list);
3796 trace_i915_gem_object_change_domain(obj,
3797 obj->read_domains,
3798 old_write_domain);
3801 i915_verify_inactive(dev, __FILE__, __LINE__);
3803 #if WATCH_COHERENCY
3804 for (i = 0; i < args->buffer_count; i++) {
3805 i915_gem_object_check_coherency(object_list[i],
3806 exec_list[i].handle);
3808 #endif
3810 #if WATCH_EXEC
3811 i915_gem_dump_object(batch_obj,
3812 args->batch_len,
3813 __func__,
3814 ~0);
3815 #endif
3817 /* Exec the batchbuffer */
3818 ret = ring->dispatch_gem_execbuffer(dev, ring, args,
3819 cliprects, exec_offset);
3820 if (ret) {
3821 DRM_ERROR("dispatch failed %d\n", ret);
3822 goto err;
3826 * Ensure that the commands in the batch buffer are
3827 * finished before the interrupt fires
3829 flush_domains = i915_retire_commands(dev, ring);
3831 i915_verify_inactive(dev, __FILE__, __LINE__);
3834 * Get a seqno representing the execution of the current buffer,
3835 * which we can wait on. We would like to mitigate these interrupts,
3836 * likely by only creating seqnos occasionally (so that we have
3837 * *some* interrupts representing completion of buffers that we can
3838 * wait on when trying to clear up gtt space).
3840 seqno = i915_add_request(dev, file_priv, flush_domains, ring);
3841 BUG_ON(seqno == 0);
3842 for (i = 0; i < args->buffer_count; i++) {
3843 struct drm_gem_object *obj = object_list[i];
3844 obj_priv = to_intel_bo(obj);
3846 i915_gem_object_move_to_active(obj, seqno, ring);
3847 #if WATCH_LRU
3848 DRM_INFO("%s: move to exec list %p\n", __func__, obj);
3849 #endif
3851 #if WATCH_LRU
3852 i915_dump_lru(dev, __func__);
3853 #endif
3855 i915_verify_inactive(dev, __FILE__, __LINE__);
3857 err:
3858 for (i = 0; i < pinned; i++)
3859 i915_gem_object_unpin(object_list[i]);
3861 for (i = 0; i < args->buffer_count; i++) {
3862 if (object_list[i]) {
3863 obj_priv = to_intel_bo(object_list[i]);
3864 obj_priv->in_execbuffer = false;
3866 drm_gem_object_unreference(object_list[i]);
3869 mutex_unlock(&dev->struct_mutex);
3871 pre_mutex_err:
3872 /* Copy the updated relocations out regardless of current error
3873 * state. Failure to update the relocs would mean that the next
3874 * time userland calls execbuf, it would do so with presumed offset
3875 * state that didn't match the actual object state.
3877 ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count,
3878 relocs);
3879 if (ret2 != 0) {
3880 DRM_ERROR("Failed to copy relocations back out: %d\n", ret2);
3882 if (ret == 0)
3883 ret = ret2;
3886 drm_free_large(object_list);
3887 kfree(cliprects);
3889 return ret;
3893 * Legacy execbuffer just creates an exec2 list from the original exec object
3894 * list array and passes it to the real function.
3897 i915_gem_execbuffer(struct drm_device *dev, void *data,
3898 struct drm_file *file_priv)
3900 struct drm_i915_gem_execbuffer *args = data;
3901 struct drm_i915_gem_execbuffer2 exec2;
3902 struct drm_i915_gem_exec_object *exec_list = NULL;
3903 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3904 int ret, i;
3906 #if WATCH_EXEC
3907 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3908 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3909 #endif
3911 if (args->buffer_count < 1) {
3912 DRM_ERROR("execbuf with %d buffers\n", args->buffer_count);
3913 return -EINVAL;
3916 /* Copy in the exec list from userland */
3917 exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count);
3918 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
3919 if (exec_list == NULL || exec2_list == NULL) {
3920 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
3921 args->buffer_count);
3922 drm_free_large(exec_list);
3923 drm_free_large(exec2_list);
3924 return -ENOMEM;
3926 ret = copy_from_user(exec_list,
3927 (struct drm_i915_relocation_entry __user *)
3928 (uintptr_t) args->buffers_ptr,
3929 sizeof(*exec_list) * args->buffer_count);
3930 if (ret != 0) {
3931 DRM_ERROR("copy %d exec entries failed %d\n",
3932 args->buffer_count, ret);
3933 drm_free_large(exec_list);
3934 drm_free_large(exec2_list);
3935 return -EFAULT;
3938 for (i = 0; i < args->buffer_count; i++) {
3939 exec2_list[i].handle = exec_list[i].handle;
3940 exec2_list[i].relocation_count = exec_list[i].relocation_count;
3941 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
3942 exec2_list[i].alignment = exec_list[i].alignment;
3943 exec2_list[i].offset = exec_list[i].offset;
3944 if (!IS_I965G(dev))
3945 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
3946 else
3947 exec2_list[i].flags = 0;
3950 exec2.buffers_ptr = args->buffers_ptr;
3951 exec2.buffer_count = args->buffer_count;
3952 exec2.batch_start_offset = args->batch_start_offset;
3953 exec2.batch_len = args->batch_len;
3954 exec2.DR1 = args->DR1;
3955 exec2.DR4 = args->DR4;
3956 exec2.num_cliprects = args->num_cliprects;
3957 exec2.cliprects_ptr = args->cliprects_ptr;
3958 exec2.flags = I915_EXEC_RENDER;
3960 ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list);
3961 if (!ret) {
3962 /* Copy the new buffer offsets back to the user's exec list. */
3963 for (i = 0; i < args->buffer_count; i++)
3964 exec_list[i].offset = exec2_list[i].offset;
3965 /* ... and back out to userspace */
3966 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
3967 (uintptr_t) args->buffers_ptr,
3968 exec_list,
3969 sizeof(*exec_list) * args->buffer_count);
3970 if (ret) {
3971 ret = -EFAULT;
3972 DRM_ERROR("failed to copy %d exec entries "
3973 "back to user (%d)\n",
3974 args->buffer_count, ret);
3978 drm_free_large(exec_list);
3979 drm_free_large(exec2_list);
3980 return ret;
3984 i915_gem_execbuffer2(struct drm_device *dev, void *data,
3985 struct drm_file *file_priv)
3987 struct drm_i915_gem_execbuffer2 *args = data;
3988 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
3989 int ret;
3991 #if WATCH_EXEC
3992 DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n",
3993 (int) args->buffers_ptr, args->buffer_count, args->batch_len);
3994 #endif
3996 if (args->buffer_count < 1) {
3997 DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count);
3998 return -EINVAL;
4001 exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count);
4002 if (exec2_list == NULL) {
4003 DRM_ERROR("Failed to allocate exec list for %d buffers\n",
4004 args->buffer_count);
4005 return -ENOMEM;
4007 ret = copy_from_user(exec2_list,
4008 (struct drm_i915_relocation_entry __user *)
4009 (uintptr_t) args->buffers_ptr,
4010 sizeof(*exec2_list) * args->buffer_count);
4011 if (ret != 0) {
4012 DRM_ERROR("copy %d exec entries failed %d\n",
4013 args->buffer_count, ret);
4014 drm_free_large(exec2_list);
4015 return -EFAULT;
4018 ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list);
4019 if (!ret) {
4020 /* Copy the new buffer offsets back to the user's exec list. */
4021 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
4022 (uintptr_t) args->buffers_ptr,
4023 exec2_list,
4024 sizeof(*exec2_list) * args->buffer_count);
4025 if (ret) {
4026 ret = -EFAULT;
4027 DRM_ERROR("failed to copy %d exec entries "
4028 "back to user (%d)\n",
4029 args->buffer_count, ret);
4033 drm_free_large(exec2_list);
4034 return ret;
4038 i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment)
4040 struct drm_device *dev = obj->dev;
4041 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4042 int ret;
4044 BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT);
4046 i915_verify_inactive(dev, __FILE__, __LINE__);
4048 if (obj_priv->gtt_space != NULL) {
4049 if (alignment == 0)
4050 alignment = i915_gem_get_gtt_alignment(obj);
4051 if (obj_priv->gtt_offset & (alignment - 1)) {
4052 WARN(obj_priv->pin_count,
4053 "bo is already pinned with incorrect alignment:"
4054 " offset=%x, req.alignment=%x\n",
4055 obj_priv->gtt_offset, alignment);
4056 ret = i915_gem_object_unbind(obj);
4057 if (ret)
4058 return ret;
4062 if (obj_priv->gtt_space == NULL) {
4063 ret = i915_gem_object_bind_to_gtt(obj, alignment);
4064 if (ret)
4065 return ret;
4068 obj_priv->pin_count++;
4070 /* If the object is not active and not pending a flush,
4071 * remove it from the inactive list
4073 if (obj_priv->pin_count == 1) {
4074 atomic_inc(&dev->pin_count);
4075 atomic_add(obj->size, &dev->pin_memory);
4076 if (!obj_priv->active &&
4077 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
4078 list_del_init(&obj_priv->list);
4080 i915_verify_inactive(dev, __FILE__, __LINE__);
4082 return 0;
4085 void
4086 i915_gem_object_unpin(struct drm_gem_object *obj)
4088 struct drm_device *dev = obj->dev;
4089 drm_i915_private_t *dev_priv = dev->dev_private;
4090 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4092 i915_verify_inactive(dev, __FILE__, __LINE__);
4093 obj_priv->pin_count--;
4094 BUG_ON(obj_priv->pin_count < 0);
4095 BUG_ON(obj_priv->gtt_space == NULL);
4097 /* If the object is no longer pinned, and is
4098 * neither active nor being flushed, then stick it on
4099 * the inactive list
4101 if (obj_priv->pin_count == 0) {
4102 if (!obj_priv->active &&
4103 (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0)
4104 list_move_tail(&obj_priv->list,
4105 &dev_priv->mm.inactive_list);
4106 atomic_dec(&dev->pin_count);
4107 atomic_sub(obj->size, &dev->pin_memory);
4109 i915_verify_inactive(dev, __FILE__, __LINE__);
4113 i915_gem_pin_ioctl(struct drm_device *dev, void *data,
4114 struct drm_file *file_priv)
4116 struct drm_i915_gem_pin *args = data;
4117 struct drm_gem_object *obj;
4118 struct drm_i915_gem_object *obj_priv;
4119 int ret;
4121 mutex_lock(&dev->struct_mutex);
4123 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4124 if (obj == NULL) {
4125 DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n",
4126 args->handle);
4127 mutex_unlock(&dev->struct_mutex);
4128 return -ENOENT;
4130 obj_priv = to_intel_bo(obj);
4132 if (obj_priv->madv != I915_MADV_WILLNEED) {
4133 DRM_ERROR("Attempting to pin a purgeable buffer\n");
4134 drm_gem_object_unreference(obj);
4135 mutex_unlock(&dev->struct_mutex);
4136 return -EINVAL;
4139 if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) {
4140 DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n",
4141 args->handle);
4142 drm_gem_object_unreference(obj);
4143 mutex_unlock(&dev->struct_mutex);
4144 return -EINVAL;
4147 obj_priv->user_pin_count++;
4148 obj_priv->pin_filp = file_priv;
4149 if (obj_priv->user_pin_count == 1) {
4150 ret = i915_gem_object_pin(obj, args->alignment);
4151 if (ret != 0) {
4152 drm_gem_object_unreference(obj);
4153 mutex_unlock(&dev->struct_mutex);
4154 return ret;
4158 /* XXX - flush the CPU caches for pinned objects
4159 * as the X server doesn't manage domains yet
4161 i915_gem_object_flush_cpu_write_domain(obj);
4162 args->offset = obj_priv->gtt_offset;
4163 drm_gem_object_unreference(obj);
4164 mutex_unlock(&dev->struct_mutex);
4166 return 0;
4170 i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
4171 struct drm_file *file_priv)
4173 struct drm_i915_gem_pin *args = data;
4174 struct drm_gem_object *obj;
4175 struct drm_i915_gem_object *obj_priv;
4177 mutex_lock(&dev->struct_mutex);
4179 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4180 if (obj == NULL) {
4181 DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n",
4182 args->handle);
4183 mutex_unlock(&dev->struct_mutex);
4184 return -ENOENT;
4187 obj_priv = to_intel_bo(obj);
4188 if (obj_priv->pin_filp != file_priv) {
4189 DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4190 args->handle);
4191 drm_gem_object_unreference(obj);
4192 mutex_unlock(&dev->struct_mutex);
4193 return -EINVAL;
4195 obj_priv->user_pin_count--;
4196 if (obj_priv->user_pin_count == 0) {
4197 obj_priv->pin_filp = NULL;
4198 i915_gem_object_unpin(obj);
4201 drm_gem_object_unreference(obj);
4202 mutex_unlock(&dev->struct_mutex);
4203 return 0;
4207 i915_gem_busy_ioctl(struct drm_device *dev, void *data,
4208 struct drm_file *file_priv)
4210 struct drm_i915_gem_busy *args = data;
4211 struct drm_gem_object *obj;
4212 struct drm_i915_gem_object *obj_priv;
4214 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4215 if (obj == NULL) {
4216 DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n",
4217 args->handle);
4218 return -ENOENT;
4221 mutex_lock(&dev->struct_mutex);
4223 /* Count all active objects as busy, even if they are currently not used
4224 * by the gpu. Users of this interface expect objects to eventually
4225 * become non-busy without any further actions, therefore emit any
4226 * necessary flushes here.
4228 obj_priv = to_intel_bo(obj);
4229 args->busy = obj_priv->active;
4230 if (args->busy) {
4231 /* Unconditionally flush objects, even when the gpu still uses this
4232 * object. Userspace calling this function indicates that it wants to
4233 * use this buffer rather sooner than later, so issuing the required
4234 * flush earlier is beneficial.
4236 if (obj->write_domain) {
4237 i915_gem_flush(dev, 0, obj->write_domain);
4238 (void)i915_add_request(dev, file_priv, obj->write_domain, obj_priv->ring);
4241 /* Update the active list for the hardware's current position.
4242 * Otherwise this only updates on a delayed timer or when irqs
4243 * are actually unmasked, and our working set ends up being
4244 * larger than required.
4246 i915_gem_retire_requests_ring(dev, obj_priv->ring);
4248 args->busy = obj_priv->active;
4251 drm_gem_object_unreference(obj);
4252 mutex_unlock(&dev->struct_mutex);
4253 return 0;
4257 i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
4258 struct drm_file *file_priv)
4260 return i915_gem_ring_throttle(dev, file_priv);
4264 i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
4265 struct drm_file *file_priv)
4267 struct drm_i915_gem_madvise *args = data;
4268 struct drm_gem_object *obj;
4269 struct drm_i915_gem_object *obj_priv;
4271 switch (args->madv) {
4272 case I915_MADV_DONTNEED:
4273 case I915_MADV_WILLNEED:
4274 break;
4275 default:
4276 return -EINVAL;
4279 obj = drm_gem_object_lookup(dev, file_priv, args->handle);
4280 if (obj == NULL) {
4281 DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n",
4282 args->handle);
4283 return -ENOENT;
4286 mutex_lock(&dev->struct_mutex);
4287 obj_priv = to_intel_bo(obj);
4289 if (obj_priv->pin_count) {
4290 drm_gem_object_unreference(obj);
4291 mutex_unlock(&dev->struct_mutex);
4293 DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n");
4294 return -EINVAL;
4297 if (obj_priv->madv != __I915_MADV_PURGED)
4298 obj_priv->madv = args->madv;
4300 /* if the object is no longer bound, discard its backing storage */
4301 if (i915_gem_object_is_purgeable(obj_priv) &&
4302 obj_priv->gtt_space == NULL)
4303 i915_gem_object_truncate(obj);
4305 args->retained = obj_priv->madv != __I915_MADV_PURGED;
4307 drm_gem_object_unreference(obj);
4308 mutex_unlock(&dev->struct_mutex);
4310 return 0;
4313 struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
4314 size_t size)
4316 struct drm_i915_gem_object *obj;
4318 obj = kzalloc(sizeof(*obj), GFP_KERNEL);
4319 if (obj == NULL)
4320 return NULL;
4322 if (drm_gem_object_init(dev, &obj->base, size) != 0) {
4323 kfree(obj);
4324 return NULL;
4327 obj->base.write_domain = I915_GEM_DOMAIN_CPU;
4328 obj->base.read_domains = I915_GEM_DOMAIN_CPU;
4330 obj->agp_type = AGP_USER_MEMORY;
4331 obj->base.driver_private = NULL;
4332 obj->fence_reg = I915_FENCE_REG_NONE;
4333 INIT_LIST_HEAD(&obj->list);
4334 INIT_LIST_HEAD(&obj->gpu_write_list);
4335 obj->madv = I915_MADV_WILLNEED;
4337 trace_i915_gem_object_create(&obj->base);
4339 return &obj->base;
4342 int i915_gem_init_object(struct drm_gem_object *obj)
4344 BUG();
4346 return 0;
4349 static void i915_gem_free_object_tail(struct drm_gem_object *obj)
4351 struct drm_device *dev = obj->dev;
4352 drm_i915_private_t *dev_priv = dev->dev_private;
4353 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4354 int ret;
4356 ret = i915_gem_object_unbind(obj);
4357 if (ret == -ERESTARTSYS) {
4358 list_move(&obj_priv->list,
4359 &dev_priv->mm.deferred_free_list);
4360 return;
4363 if (obj_priv->mmap_offset)
4364 i915_gem_free_mmap_offset(obj);
4366 drm_gem_object_release(obj);
4368 kfree(obj_priv->page_cpu_valid);
4369 kfree(obj_priv->bit_17);
4370 kfree(obj_priv);
4373 void i915_gem_free_object(struct drm_gem_object *obj)
4375 struct drm_device *dev = obj->dev;
4376 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4378 trace_i915_gem_object_destroy(obj);
4380 while (obj_priv->pin_count > 0)
4381 i915_gem_object_unpin(obj);
4383 if (obj_priv->phys_obj)
4384 i915_gem_detach_phys_object(dev, obj);
4386 i915_gem_free_object_tail(obj);
4390 i915_gem_idle(struct drm_device *dev)
4392 drm_i915_private_t *dev_priv = dev->dev_private;
4393 int ret;
4395 mutex_lock(&dev->struct_mutex);
4397 if (dev_priv->mm.suspended ||
4398 (dev_priv->render_ring.gem_object == NULL) ||
4399 (HAS_BSD(dev) &&
4400 dev_priv->bsd_ring.gem_object == NULL)) {
4401 mutex_unlock(&dev->struct_mutex);
4402 return 0;
4405 ret = i915_gpu_idle(dev);
4406 if (ret) {
4407 mutex_unlock(&dev->struct_mutex);
4408 return ret;
4411 /* Under UMS, be paranoid and evict. */
4412 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
4413 ret = i915_gem_evict_inactive(dev);
4414 if (ret) {
4415 mutex_unlock(&dev->struct_mutex);
4416 return ret;
4420 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4421 * We need to replace this with a semaphore, or something.
4422 * And not confound mm.suspended!
4424 dev_priv->mm.suspended = 1;
4425 del_timer(&dev_priv->hangcheck_timer);
4427 i915_kernel_lost_context(dev);
4428 i915_gem_cleanup_ringbuffer(dev);
4430 mutex_unlock(&dev->struct_mutex);
4432 /* Cancel the retire work handler, which should be idle now. */
4433 cancel_delayed_work_sync(&dev_priv->mm.retire_work);
4435 return 0;
4439 * 965+ support PIPE_CONTROL commands, which provide finer grained control
4440 * over cache flushing.
4442 static int
4443 i915_gem_init_pipe_control(struct drm_device *dev)
4445 drm_i915_private_t *dev_priv = dev->dev_private;
4446 struct drm_gem_object *obj;
4447 struct drm_i915_gem_object *obj_priv;
4448 int ret;
4450 obj = i915_gem_alloc_object(dev, 4096);
4451 if (obj == NULL) {
4452 DRM_ERROR("Failed to allocate seqno page\n");
4453 ret = -ENOMEM;
4454 goto err;
4456 obj_priv = to_intel_bo(obj);
4457 obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
4459 ret = i915_gem_object_pin(obj, 4096);
4460 if (ret)
4461 goto err_unref;
4463 dev_priv->seqno_gfx_addr = obj_priv->gtt_offset;
4464 dev_priv->seqno_page = kmap(obj_priv->pages[0]);
4465 if (dev_priv->seqno_page == NULL)
4466 goto err_unpin;
4468 dev_priv->seqno_obj = obj;
4469 memset(dev_priv->seqno_page, 0, PAGE_SIZE);
4471 return 0;
4473 err_unpin:
4474 i915_gem_object_unpin(obj);
4475 err_unref:
4476 drm_gem_object_unreference(obj);
4477 err:
4478 return ret;
4482 static void
4483 i915_gem_cleanup_pipe_control(struct drm_device *dev)
4485 drm_i915_private_t *dev_priv = dev->dev_private;
4486 struct drm_gem_object *obj;
4487 struct drm_i915_gem_object *obj_priv;
4489 obj = dev_priv->seqno_obj;
4490 obj_priv = to_intel_bo(obj);
4491 kunmap(obj_priv->pages[0]);
4492 i915_gem_object_unpin(obj);
4493 drm_gem_object_unreference(obj);
4494 dev_priv->seqno_obj = NULL;
4496 dev_priv->seqno_page = NULL;
4500 i915_gem_init_ringbuffer(struct drm_device *dev)
4502 drm_i915_private_t *dev_priv = dev->dev_private;
4503 int ret;
4505 dev_priv->render_ring = render_ring;
4507 if (!I915_NEED_GFX_HWS(dev)) {
4508 dev_priv->render_ring.status_page.page_addr
4509 = dev_priv->status_page_dmah->vaddr;
4510 memset(dev_priv->render_ring.status_page.page_addr,
4511 0, PAGE_SIZE);
4514 if (HAS_PIPE_CONTROL(dev)) {
4515 ret = i915_gem_init_pipe_control(dev);
4516 if (ret)
4517 return ret;
4520 ret = intel_init_ring_buffer(dev, &dev_priv->render_ring);
4521 if (ret)
4522 goto cleanup_pipe_control;
4524 if (HAS_BSD(dev)) {
4525 dev_priv->bsd_ring = bsd_ring;
4526 ret = intel_init_ring_buffer(dev, &dev_priv->bsd_ring);
4527 if (ret)
4528 goto cleanup_render_ring;
4531 dev_priv->next_seqno = 1;
4533 return 0;
4535 cleanup_render_ring:
4536 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
4537 cleanup_pipe_control:
4538 if (HAS_PIPE_CONTROL(dev))
4539 i915_gem_cleanup_pipe_control(dev);
4540 return ret;
4543 void
4544 i915_gem_cleanup_ringbuffer(struct drm_device *dev)
4546 drm_i915_private_t *dev_priv = dev->dev_private;
4548 intel_cleanup_ring_buffer(dev, &dev_priv->render_ring);
4549 if (HAS_BSD(dev))
4550 intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring);
4551 if (HAS_PIPE_CONTROL(dev))
4552 i915_gem_cleanup_pipe_control(dev);
4556 i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
4557 struct drm_file *file_priv)
4559 drm_i915_private_t *dev_priv = dev->dev_private;
4560 int ret;
4562 if (drm_core_check_feature(dev, DRIVER_MODESET))
4563 return 0;
4565 if (atomic_read(&dev_priv->mm.wedged)) {
4566 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4567 atomic_set(&dev_priv->mm.wedged, 0);
4570 mutex_lock(&dev->struct_mutex);
4571 dev_priv->mm.suspended = 0;
4573 ret = i915_gem_init_ringbuffer(dev);
4574 if (ret != 0) {
4575 mutex_unlock(&dev->struct_mutex);
4576 return ret;
4579 spin_lock(&dev_priv->mm.active_list_lock);
4580 BUG_ON(!list_empty(&dev_priv->render_ring.active_list));
4581 BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.active_list));
4582 spin_unlock(&dev_priv->mm.active_list_lock);
4584 BUG_ON(!list_empty(&dev_priv->mm.flushing_list));
4585 BUG_ON(!list_empty(&dev_priv->mm.inactive_list));
4586 BUG_ON(!list_empty(&dev_priv->render_ring.request_list));
4587 BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.request_list));
4588 mutex_unlock(&dev->struct_mutex);
4590 ret = drm_irq_install(dev);
4591 if (ret)
4592 goto cleanup_ringbuffer;
4594 return 0;
4596 cleanup_ringbuffer:
4597 mutex_lock(&dev->struct_mutex);
4598 i915_gem_cleanup_ringbuffer(dev);
4599 dev_priv->mm.suspended = 1;
4600 mutex_unlock(&dev->struct_mutex);
4602 return ret;
4606 i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
4607 struct drm_file *file_priv)
4609 if (drm_core_check_feature(dev, DRIVER_MODESET))
4610 return 0;
4612 drm_irq_uninstall(dev);
4613 return i915_gem_idle(dev);
4616 void
4617 i915_gem_lastclose(struct drm_device *dev)
4619 int ret;
4621 if (drm_core_check_feature(dev, DRIVER_MODESET))
4622 return;
4624 ret = i915_gem_idle(dev);
4625 if (ret)
4626 DRM_ERROR("failed to idle hardware: %d\n", ret);
4629 void
4630 i915_gem_load(struct drm_device *dev)
4632 int i;
4633 drm_i915_private_t *dev_priv = dev->dev_private;
4635 spin_lock_init(&dev_priv->mm.active_list_lock);
4636 INIT_LIST_HEAD(&dev_priv->mm.flushing_list);
4637 INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list);
4638 INIT_LIST_HEAD(&dev_priv->mm.inactive_list);
4639 INIT_LIST_HEAD(&dev_priv->mm.fence_list);
4640 INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list);
4641 INIT_LIST_HEAD(&dev_priv->render_ring.active_list);
4642 INIT_LIST_HEAD(&dev_priv->render_ring.request_list);
4643 if (HAS_BSD(dev)) {
4644 INIT_LIST_HEAD(&dev_priv->bsd_ring.active_list);
4645 INIT_LIST_HEAD(&dev_priv->bsd_ring.request_list);
4647 for (i = 0; i < 16; i++)
4648 INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list);
4649 INIT_DELAYED_WORK(&dev_priv->mm.retire_work,
4650 i915_gem_retire_work_handler);
4651 spin_lock(&shrink_list_lock);
4652 list_add(&dev_priv->mm.shrink_list, &shrink_list);
4653 spin_unlock(&shrink_list_lock);
4655 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4656 if (IS_GEN3(dev)) {
4657 u32 tmp = I915_READ(MI_ARB_STATE);
4658 if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) {
4659 /* arb state is a masked write, so set bit + bit in mask */
4660 tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT);
4661 I915_WRITE(MI_ARB_STATE, tmp);
4665 /* Old X drivers will take 0-2 for front, back, depth buffers */
4666 if (!drm_core_check_feature(dev, DRIVER_MODESET))
4667 dev_priv->fence_reg_start = 3;
4669 if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4670 dev_priv->num_fence_regs = 16;
4671 else
4672 dev_priv->num_fence_regs = 8;
4674 /* Initialize fence registers to zero */
4675 if (IS_I965G(dev)) {
4676 for (i = 0; i < 16; i++)
4677 I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
4678 } else {
4679 for (i = 0; i < 8; i++)
4680 I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
4681 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4682 for (i = 0; i < 8; i++)
4683 I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
4685 i915_gem_detect_bit_6_swizzle(dev);
4686 init_waitqueue_head(&dev_priv->pending_flip_queue);
4690 * Create a physically contiguous memory object for this object
4691 * e.g. for cursor + overlay regs
4693 int i915_gem_init_phys_object(struct drm_device *dev,
4694 int id, int size, int align)
4696 drm_i915_private_t *dev_priv = dev->dev_private;
4697 struct drm_i915_gem_phys_object *phys_obj;
4698 int ret;
4700 if (dev_priv->mm.phys_objs[id - 1] || !size)
4701 return 0;
4703 phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL);
4704 if (!phys_obj)
4705 return -ENOMEM;
4707 phys_obj->id = id;
4709 phys_obj->handle = drm_pci_alloc(dev, size, align);
4710 if (!phys_obj->handle) {
4711 ret = -ENOMEM;
4712 goto kfree_obj;
4714 #ifdef CONFIG_X86
4715 set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4716 #endif
4718 dev_priv->mm.phys_objs[id - 1] = phys_obj;
4720 return 0;
4721 kfree_obj:
4722 kfree(phys_obj);
4723 return ret;
4726 void i915_gem_free_phys_object(struct drm_device *dev, int id)
4728 drm_i915_private_t *dev_priv = dev->dev_private;
4729 struct drm_i915_gem_phys_object *phys_obj;
4731 if (!dev_priv->mm.phys_objs[id - 1])
4732 return;
4734 phys_obj = dev_priv->mm.phys_objs[id - 1];
4735 if (phys_obj->cur_obj) {
4736 i915_gem_detach_phys_object(dev, phys_obj->cur_obj);
4739 #ifdef CONFIG_X86
4740 set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE);
4741 #endif
4742 drm_pci_free(dev, phys_obj->handle);
4743 kfree(phys_obj);
4744 dev_priv->mm.phys_objs[id - 1] = NULL;
4747 void i915_gem_free_all_phys_object(struct drm_device *dev)
4749 int i;
4751 for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++)
4752 i915_gem_free_phys_object(dev, i);
4755 void i915_gem_detach_phys_object(struct drm_device *dev,
4756 struct drm_gem_object *obj)
4758 struct drm_i915_gem_object *obj_priv;
4759 int i;
4760 int ret;
4761 int page_count;
4763 obj_priv = to_intel_bo(obj);
4764 if (!obj_priv->phys_obj)
4765 return;
4767 ret = i915_gem_object_get_pages(obj, 0);
4768 if (ret)
4769 goto out;
4771 page_count = obj->size / PAGE_SIZE;
4773 for (i = 0; i < page_count; i++) {
4774 char *dst = kmap_atomic(obj_priv->pages[i]);
4775 char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4777 memcpy(dst, src, PAGE_SIZE);
4778 kunmap_atomic(dst);
4780 drm_clflush_pages(obj_priv->pages, page_count);
4781 drm_agp_chipset_flush(dev);
4783 i915_gem_object_put_pages(obj);
4784 out:
4785 obj_priv->phys_obj->cur_obj = NULL;
4786 obj_priv->phys_obj = NULL;
4790 i915_gem_attach_phys_object(struct drm_device *dev,
4791 struct drm_gem_object *obj,
4792 int id,
4793 int align)
4795 drm_i915_private_t *dev_priv = dev->dev_private;
4796 struct drm_i915_gem_object *obj_priv;
4797 int ret = 0;
4798 int page_count;
4799 int i;
4801 if (id > I915_MAX_PHYS_OBJECT)
4802 return -EINVAL;
4804 obj_priv = to_intel_bo(obj);
4806 if (obj_priv->phys_obj) {
4807 if (obj_priv->phys_obj->id == id)
4808 return 0;
4809 i915_gem_detach_phys_object(dev, obj);
4812 /* create a new object */
4813 if (!dev_priv->mm.phys_objs[id - 1]) {
4814 ret = i915_gem_init_phys_object(dev, id,
4815 obj->size, align);
4816 if (ret) {
4817 DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size);
4818 goto out;
4822 /* bind to the object */
4823 obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1];
4824 obj_priv->phys_obj->cur_obj = obj;
4826 ret = i915_gem_object_get_pages(obj, 0);
4827 if (ret) {
4828 DRM_ERROR("failed to get page list\n");
4829 goto out;
4832 page_count = obj->size / PAGE_SIZE;
4834 for (i = 0; i < page_count; i++) {
4835 char *src = kmap_atomic(obj_priv->pages[i]);
4836 char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE);
4838 memcpy(dst, src, PAGE_SIZE);
4839 kunmap_atomic(src);
4842 i915_gem_object_put_pages(obj);
4844 return 0;
4845 out:
4846 return ret;
4849 static int
4850 i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj,
4851 struct drm_i915_gem_pwrite *args,
4852 struct drm_file *file_priv)
4854 struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
4855 void *obj_addr;
4856 int ret;
4857 char __user *user_data;
4859 user_data = (char __user *) (uintptr_t) args->data_ptr;
4860 obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset;
4862 DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size);
4863 ret = copy_from_user(obj_addr, user_data, args->size);
4864 if (ret)
4865 return -EFAULT;
4867 drm_agp_chipset_flush(dev);
4868 return 0;
4871 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv)
4873 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
4875 /* Clean up our request list when the client is going away, so that
4876 * later retire_requests won't dereference our soon-to-be-gone
4877 * file_priv.
4879 mutex_lock(&dev->struct_mutex);
4880 while (!list_empty(&i915_file_priv->mm.request_list))
4881 list_del_init(i915_file_priv->mm.request_list.next);
4882 mutex_unlock(&dev->struct_mutex);
4885 static int
4886 i915_gpu_is_active(struct drm_device *dev)
4888 drm_i915_private_t *dev_priv = dev->dev_private;
4889 int lists_empty;
4891 spin_lock(&dev_priv->mm.active_list_lock);
4892 lists_empty = list_empty(&dev_priv->mm.flushing_list) &&
4893 list_empty(&dev_priv->render_ring.active_list);
4894 if (HAS_BSD(dev))
4895 lists_empty &= list_empty(&dev_priv->bsd_ring.active_list);
4896 spin_unlock(&dev_priv->mm.active_list_lock);
4898 return !lists_empty;
4901 static int
4902 i915_gem_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
4904 drm_i915_private_t *dev_priv, *next_dev;
4905 struct drm_i915_gem_object *obj_priv, *next_obj;
4906 int cnt = 0;
4907 int would_deadlock = 1;
4909 /* "fast-path" to count number of available objects */
4910 if (nr_to_scan == 0) {
4911 spin_lock(&shrink_list_lock);
4912 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4913 struct drm_device *dev = dev_priv->dev;
4915 if (mutex_trylock(&dev->struct_mutex)) {
4916 list_for_each_entry(obj_priv,
4917 &dev_priv->mm.inactive_list,
4918 list)
4919 cnt++;
4920 mutex_unlock(&dev->struct_mutex);
4923 spin_unlock(&shrink_list_lock);
4925 return (cnt / 100) * sysctl_vfs_cache_pressure;
4928 spin_lock(&shrink_list_lock);
4930 rescan:
4931 /* first scan for clean buffers */
4932 list_for_each_entry_safe(dev_priv, next_dev,
4933 &shrink_list, mm.shrink_list) {
4934 struct drm_device *dev = dev_priv->dev;
4936 if (! mutex_trylock(&dev->struct_mutex))
4937 continue;
4939 spin_unlock(&shrink_list_lock);
4940 i915_gem_retire_requests(dev);
4942 list_for_each_entry_safe(obj_priv, next_obj,
4943 &dev_priv->mm.inactive_list,
4944 list) {
4945 if (i915_gem_object_is_purgeable(obj_priv)) {
4946 i915_gem_object_unbind(&obj_priv->base);
4947 if (--nr_to_scan <= 0)
4948 break;
4952 spin_lock(&shrink_list_lock);
4953 mutex_unlock(&dev->struct_mutex);
4955 would_deadlock = 0;
4957 if (nr_to_scan <= 0)
4958 break;
4961 /* second pass, evict/count anything still on the inactive list */
4962 list_for_each_entry_safe(dev_priv, next_dev,
4963 &shrink_list, mm.shrink_list) {
4964 struct drm_device *dev = dev_priv->dev;
4966 if (! mutex_trylock(&dev->struct_mutex))
4967 continue;
4969 spin_unlock(&shrink_list_lock);
4971 list_for_each_entry_safe(obj_priv, next_obj,
4972 &dev_priv->mm.inactive_list,
4973 list) {
4974 if (nr_to_scan > 0) {
4975 i915_gem_object_unbind(&obj_priv->base);
4976 nr_to_scan--;
4977 } else
4978 cnt++;
4981 spin_lock(&shrink_list_lock);
4982 mutex_unlock(&dev->struct_mutex);
4984 would_deadlock = 0;
4987 if (nr_to_scan) {
4988 int active = 0;
4991 * We are desperate for pages, so as a last resort, wait
4992 * for the GPU to finish and discard whatever we can.
4993 * This has a dramatic impact to reduce the number of
4994 * OOM-killer events whilst running the GPU aggressively.
4996 list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) {
4997 struct drm_device *dev = dev_priv->dev;
4999 if (!mutex_trylock(&dev->struct_mutex))
5000 continue;
5002 spin_unlock(&shrink_list_lock);
5004 if (i915_gpu_is_active(dev)) {
5005 i915_gpu_idle(dev);
5006 active++;
5009 spin_lock(&shrink_list_lock);
5010 mutex_unlock(&dev->struct_mutex);
5013 if (active)
5014 goto rescan;
5017 spin_unlock(&shrink_list_lock);
5019 if (would_deadlock)
5020 return -1;
5021 else if (cnt > 0)
5022 return (cnt / 100) * sysctl_vfs_cache_pressure;
5023 else
5024 return 0;
5027 static struct shrinker shrinker = {
5028 .shrink = i915_gem_shrink,
5029 .seeks = DEFAULT_SEEKS,
5032 __init void
5033 i915_gem_shrinker_init(void)
5035 register_shrinker(&shrinker);
5038 __exit void
5039 i915_gem_shrinker_exit(void)
5041 unregister_shrinker(&shrinker);