2 * arch/arm/mm/highmem.c -- ARM highmem support
4 * Author: Nicolas Pitre
5 * Created: september 8, 2008
6 * Copyright: Marvell Semiconductors Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
13 #include <linux/module.h>
14 #include <linux/highmem.h>
15 #include <linux/interrupt.h>
16 #include <asm/fixmap.h>
17 #include <asm/cacheflush.h>
18 #include <asm/tlbflush.h>
21 void *kmap(struct page
*page
)
24 if (!PageHighMem(page
))
25 return page_address(page
);
26 return kmap_high(page
);
30 void kunmap(struct page
*page
)
32 BUG_ON(in_interrupt());
33 if (!PageHighMem(page
))
37 EXPORT_SYMBOL(kunmap
);
39 void *__kmap_atomic(struct page
*page
)
47 if (!PageHighMem(page
))
48 return page_address(page
);
50 #ifdef CONFIG_DEBUG_HIGHMEM
52 * There is no cache coherency issue when non VIVT, so force the
53 * dedicated kmap usage for better debugging purposes in that case.
59 kmap
= kmap_high_get(page
);
63 type
= kmap_atomic_idx_push();
65 idx
= type
+ KM_TYPE_NR
* smp_processor_id();
66 vaddr
= __fix_to_virt(FIX_KMAP_BEGIN
+ idx
);
67 #ifdef CONFIG_DEBUG_HIGHMEM
69 * With debugging enabled, kunmap_atomic forces that entry to 0.
70 * Make sure it was indeed properly unmapped.
72 BUG_ON(!pte_none(*(TOP_PTE(vaddr
))));
74 set_pte_ext(TOP_PTE(vaddr
), mk_pte(page
, kmap_prot
), 0);
76 * When debugging is off, kunmap_atomic leaves the previous mapping
77 * in place, so this TLB flush ensures the TLB is updated with the
80 local_flush_tlb_kernel_page(vaddr
);
84 EXPORT_SYMBOL(__kmap_atomic
);
86 void __kunmap_atomic(void *kvaddr
)
88 unsigned long vaddr
= (unsigned long) kvaddr
& PAGE_MASK
;
91 if (kvaddr
>= (void *)FIXADDR_START
) {
92 type
= kmap_atomic_idx_pop();
93 idx
= type
+ KM_TYPE_NR
* smp_processor_id();
96 __cpuc_flush_dcache_area((void *)vaddr
, PAGE_SIZE
);
97 #ifdef CONFIG_DEBUG_HIGHMEM
98 BUG_ON(vaddr
!= __fix_to_virt(FIX_KMAP_BEGIN
+ idx
));
99 set_pte_ext(TOP_PTE(vaddr
), __pte(0), 0);
100 local_flush_tlb_kernel_page(vaddr
);
102 (void) idx
; /* to kill a warning */
104 } else if (vaddr
>= PKMAP_ADDR(0) && vaddr
< PKMAP_ADDR(LAST_PKMAP
)) {
105 /* this address was obtained through kmap_high_get() */
106 kunmap_high(pte_page(pkmap_page_table
[PKMAP_NR(vaddr
)]));
110 EXPORT_SYMBOL(__kunmap_atomic
);
112 void *kmap_atomic_pfn(unsigned long pfn
)
119 type
= kmap_atomic_idx_push();
120 idx
= type
+ KM_TYPE_NR
* smp_processor_id();
121 vaddr
= __fix_to_virt(FIX_KMAP_BEGIN
+ idx
);
122 #ifdef CONFIG_DEBUG_HIGHMEM
123 BUG_ON(!pte_none(*(TOP_PTE(vaddr
))));
125 set_pte_ext(TOP_PTE(vaddr
), pfn_pte(pfn
, kmap_prot
), 0);
126 local_flush_tlb_kernel_page(vaddr
);
128 return (void *)vaddr
;
131 struct page
*kmap_atomic_to_page(const void *ptr
)
133 unsigned long vaddr
= (unsigned long)ptr
;
136 if (vaddr
< FIXADDR_START
)
137 return virt_to_page(ptr
);
139 pte
= TOP_PTE(vaddr
);
140 return pte_page(*pte
);
143 #ifdef CONFIG_CPU_CACHE_VIPT
145 #include <linux/percpu.h>
148 * The VIVT cache of a highmem page is always flushed before the page
149 * is unmapped. Hence unmapped highmem pages need no cache maintenance
152 * However unmapped pages may still be cached with a VIPT cache, and
153 * it is not possible to perform cache maintenance on them using physical
154 * addresses unfortunately. So we have no choice but to set up a temporary
155 * virtual mapping for that purpose.
157 * Yet this VIPT cache maintenance may be triggered from DMA support
158 * functions which are possibly called from interrupt context. As we don't
159 * want to keep interrupt disabled all the time when such maintenance is
160 * taking place, we therefore allow for some reentrancy by preserving and
161 * restoring the previous fixmap entry before the interrupted context is
162 * resumed. If the reentrancy depth is 0 then there is no need to restore
163 * the previous fixmap, and leaving the current one in place allow it to
164 * be reused the next time without a TLB flush (common with DMA).
167 static DEFINE_PER_CPU(int, kmap_high_l1_vipt_depth
);
169 void *kmap_high_l1_vipt(struct page
*page
, pte_t
*saved_pte
)
171 unsigned int idx
, cpu
;
173 unsigned long vaddr
, flags
;
179 cpu
= smp_processor_id();
180 depth
= &per_cpu(kmap_high_l1_vipt_depth
, cpu
);
182 idx
= KM_L1_CACHE
+ KM_TYPE_NR
* cpu
;
183 vaddr
= __fix_to_virt(FIX_KMAP_BEGIN
+ idx
);
184 ptep
= TOP_PTE(vaddr
);
185 pte
= mk_pte(page
, kmap_prot
);
187 raw_local_irq_save(flags
);
189 if (pte_val(*ptep
) == pte_val(pte
)) {
193 set_pte_ext(ptep
, pte
, 0);
194 local_flush_tlb_kernel_page(vaddr
);
196 raw_local_irq_restore(flags
);
198 return (void *)vaddr
;
201 void kunmap_high_l1_vipt(struct page
*page
, pte_t saved_pte
)
203 unsigned int idx
, cpu
= smp_processor_id();
204 int *depth
= &per_cpu(kmap_high_l1_vipt_depth
, cpu
);
205 unsigned long vaddr
, flags
;
208 idx
= KM_L1_CACHE
+ KM_TYPE_NR
* cpu
;
209 vaddr
= __fix_to_virt(FIX_KMAP_BEGIN
+ idx
);
210 ptep
= TOP_PTE(vaddr
);
211 pte
= mk_pte(page
, kmap_prot
);
213 BUG_ON(pte_val(*ptep
) != pte_val(pte
));
216 raw_local_irq_save(flags
);
218 if (*depth
!= 0 && pte_val(pte
) != pte_val(saved_pte
)) {
219 set_pte_ext(ptep
, saved_pte
, 0);
220 local_flush_tlb_kernel_page(vaddr
);
222 raw_local_irq_restore(flags
);
228 #endif /* CONFIG_CPU_CACHE_VIPT */