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be2net: Making die temperature ioctl call async
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / ethernet / emulex / benet / be_cmds.c
blob6e7b5218c784de07f77a2060280a96233c08aad4
1 /*
2 * Copyright (C) 2005 - 2011 Emulex
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
11 * linux-drivers@emulex.com
12 *
13 * Emulex
14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
16 */
17
18 #include "be.h"
19 #include "be_cmds.h"
20
21 /* Must be a power of 2 or else MODULO will BUG_ON */
22 static int be_get_temp_freq = 64;
23
24 static inline void *embedded_payload(struct be_mcc_wrb *wrb)
25 {
26 return wrb->payload.embedded_payload;
27 }
28
29 static void be_mcc_notify(struct be_adapter *adapter)
30 {
31 struct be_queue_info *mccq = &adapter->mcc_obj.q;
32 u32 val = 0;
33
34 if (adapter->eeh_err) {
35 dev_info(&adapter->pdev->dev,
36 "Error in Card Detected! Cannot issue commands\n");
37 return;
38 }
39
40 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
41 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
42
43 wmb();
44 iowrite32(val, adapter->db + DB_MCCQ_OFFSET);
45 }
46
47 /* To check if valid bit is set, check the entire word as we don't know
48 * the endianness of the data (old entry is host endian while a new entry is
49 * little endian) */
50 static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
51 {
52 if (compl->flags != 0) {
53 compl->flags = le32_to_cpu(compl->flags);
54 BUG_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
55 return true;
56 } else {
57 return false;
58 }
59 }
60
61 /* Need to reset the entire word that houses the valid bit */
62 static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
63 {
64 compl->flags = 0;
65 }
66
67 static int be_mcc_compl_process(struct be_adapter *adapter,
68 struct be_mcc_compl *compl)
69 {
70 u16 compl_status, extd_status;
71
72 /* Just swap the status to host endian; mcc tag is opaquely copied
73 * from mcc_wrb */
74 be_dws_le_to_cpu(compl, 4);
75
76 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
77 CQE_STATUS_COMPL_MASK;
78
79 if (((compl->tag0 == OPCODE_COMMON_WRITE_FLASHROM) ||
80 (compl->tag0 == OPCODE_COMMON_WRITE_OBJECT)) &&
81 (compl->tag1 == CMD_SUBSYSTEM_COMMON)) {
82 adapter->flash_status = compl_status;
83 complete(&adapter->flash_compl);
84 }
85
86 if (compl_status == MCC_STATUS_SUCCESS) {
87 if (((compl->tag0 == OPCODE_ETH_GET_STATISTICS) ||
88 (compl->tag0 == OPCODE_ETH_GET_PPORT_STATS)) &&
89 (compl->tag1 == CMD_SUBSYSTEM_ETH)) {
90 be_parse_stats(adapter);
91 adapter->stats_cmd_sent = false;
92 }
93 if (compl->tag0 ==
94 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES) {
95 struct be_mcc_wrb *mcc_wrb =
96 queue_index_node(&adapter->mcc_obj.q,
97 compl->tag1);
98 struct be_cmd_resp_get_cntl_addnl_attribs *resp =
99 embedded_payload(mcc_wrb);
100 adapter->drv_stats.be_on_die_temperature =
101 resp->on_die_temperature;
102 }
103 } else {
104 if (compl->tag0 == OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES)
105 be_get_temp_freq = 0;
106
107 if (compl_status == MCC_STATUS_NOT_SUPPORTED ||
108 compl_status == MCC_STATUS_ILLEGAL_REQUEST)
109 goto done;
110
111 if (compl_status == MCC_STATUS_UNAUTHORIZED_REQUEST) {
112 dev_warn(&adapter->pdev->dev, "This domain(VM) is not "
113 "permitted to execute this cmd (opcode %d)\n",
114 compl->tag0);
115 } else {
116 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
117 CQE_STATUS_EXTD_MASK;
118 dev_err(&adapter->pdev->dev, "Cmd (opcode %d) failed:"
119 "status %d, extd-status %d\n",
120 compl->tag0, compl_status, extd_status);
121 }
122 }
123 done:
124 return compl_status;
125 }
126
127 /* Link state evt is a string of bytes; no need for endian swapping */
128 static void be_async_link_state_process(struct be_adapter *adapter,
129 struct be_async_event_link_state *evt)
130 {
131 be_link_status_update(adapter, evt->port_link_status);
132 }
133
134 /* Grp5 CoS Priority evt */
135 static void be_async_grp5_cos_priority_process(struct be_adapter *adapter,
136 struct be_async_event_grp5_cos_priority *evt)
137 {
138 if (evt->valid) {
139 adapter->vlan_prio_bmap = evt->available_priority_bmap;
140 adapter->recommended_prio &= ~VLAN_PRIO_MASK;
141 adapter->recommended_prio =
142 evt->reco_default_priority << VLAN_PRIO_SHIFT;
143 }
144 }
145
146 /* Grp5 QOS Speed evt */
147 static void be_async_grp5_qos_speed_process(struct be_adapter *adapter,
148 struct be_async_event_grp5_qos_link_speed *evt)
149 {
150 if (evt->physical_port == adapter->port_num) {
151 /* qos_link_speed is in units of 10 Mbps */
152 adapter->link_speed = evt->qos_link_speed * 10;
153 }
154 }
155
156 /*Grp5 PVID evt*/
157 static void be_async_grp5_pvid_state_process(struct be_adapter *adapter,
158 struct be_async_event_grp5_pvid_state *evt)
159 {
160 if (evt->enabled)
161 adapter->pvid = le16_to_cpu(evt->tag) & VLAN_VID_MASK;
162 else
163 adapter->pvid = 0;
164 }
165
166 static void be_async_grp5_evt_process(struct be_adapter *adapter,
167 u32 trailer, struct be_mcc_compl *evt)
168 {
169 u8 event_type = 0;
170
171 event_type = (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
172 ASYNC_TRAILER_EVENT_TYPE_MASK;
173
174 switch (event_type) {
175 case ASYNC_EVENT_COS_PRIORITY:
176 be_async_grp5_cos_priority_process(adapter,
177 (struct be_async_event_grp5_cos_priority *)evt);
178 break;
179 case ASYNC_EVENT_QOS_SPEED:
180 be_async_grp5_qos_speed_process(adapter,
181 (struct be_async_event_grp5_qos_link_speed *)evt);
182 break;
183 case ASYNC_EVENT_PVID_STATE:
184 be_async_grp5_pvid_state_process(adapter,
185 (struct be_async_event_grp5_pvid_state *)evt);
186 break;
187 default:
188 dev_warn(&adapter->pdev->dev, "Unknown grp5 event!\n");
189 break;
190 }
191 }
192
193 static inline bool is_link_state_evt(u32 trailer)
194 {
195 return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
196 ASYNC_TRAILER_EVENT_CODE_MASK) ==
197 ASYNC_EVENT_CODE_LINK_STATE;
198 }
199
200 static inline bool is_grp5_evt(u32 trailer)
201 {
202 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
203 ASYNC_TRAILER_EVENT_CODE_MASK) ==
204 ASYNC_EVENT_CODE_GRP_5);
205 }
206
207 static struct be_mcc_compl *be_mcc_compl_get(struct be_adapter *adapter)
208 {
209 struct be_queue_info *mcc_cq = &adapter->mcc_obj.cq;
210 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
211
212 if (be_mcc_compl_is_new(compl)) {
213 queue_tail_inc(mcc_cq);
214 return compl;
215 }
216 return NULL;
217 }
218
219 void be_async_mcc_enable(struct be_adapter *adapter)
220 {
221 spin_lock_bh(&adapter->mcc_cq_lock);
222
223 be_cq_notify(adapter, adapter->mcc_obj.cq.id, true, 0);
224 adapter->mcc_obj.rearm_cq = true;
225
226 spin_unlock_bh(&adapter->mcc_cq_lock);
227 }
228
229 void be_async_mcc_disable(struct be_adapter *adapter)
230 {
231 adapter->mcc_obj.rearm_cq = false;
232 }
233
234 int be_process_mcc(struct be_adapter *adapter, int *status)
235 {
236 struct be_mcc_compl *compl;
237 int num = 0;
238 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
239
240 spin_lock_bh(&adapter->mcc_cq_lock);
241 while ((compl = be_mcc_compl_get(adapter))) {
242 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
243 /* Interpret flags as an async trailer */
244 if (is_link_state_evt(compl->flags))
245 be_async_link_state_process(adapter,
246 (struct be_async_event_link_state *) compl);
247 else if (is_grp5_evt(compl->flags))
248 be_async_grp5_evt_process(adapter,
249 compl->flags, compl);
250 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
251 *status = be_mcc_compl_process(adapter, compl);
252 atomic_dec(&mcc_obj->q.used);
253 }
254 be_mcc_compl_use(compl);
255 num++;
256 }
257
258 spin_unlock_bh(&adapter->mcc_cq_lock);
259 return num;
260 }
261
262 /* Wait till no more pending mcc requests are present */
263 static int be_mcc_wait_compl(struct be_adapter *adapter)
264 {
265 #define mcc_timeout 120000 /* 12s timeout */
266 int i, num, status = 0;
267 struct be_mcc_obj *mcc_obj = &adapter->mcc_obj;
268
269 if (adapter->eeh_err)
270 return -EIO;
271
272 for (i = 0; i < mcc_timeout; i++) {
273 num = be_process_mcc(adapter, &status);
274 if (num)
275 be_cq_notify(adapter, mcc_obj->cq.id,
276 mcc_obj->rearm_cq, num);
277
278 if (atomic_read(&mcc_obj->q.used) == 0)
279 break;
280 udelay(100);
281 }
282 if (i == mcc_timeout) {
283 dev_err(&adapter->pdev->dev, "mccq poll timed out\n");
284 return -1;
285 }
286 return status;
287 }
288
289 /* Notify MCC requests and wait for completion */
290 static int be_mcc_notify_wait(struct be_adapter *adapter)
291 {
292 be_mcc_notify(adapter);
293 return be_mcc_wait_compl(adapter);
294 }
295
296 static int be_mbox_db_ready_wait(struct be_adapter *adapter, void __iomem *db)
297 {
298 int msecs = 0;
299 u32 ready;
300
301 if (adapter->eeh_err) {
302 dev_err(&adapter->pdev->dev,
303 "Error detected in card.Cannot issue commands\n");
304 return -EIO;
305 }
306
307 do {
308 ready = ioread32(db);
309 if (ready == 0xffffffff) {
310 dev_err(&adapter->pdev->dev,
311 "pci slot disconnected\n");
312 return -1;
313 }
314
315 ready &= MPU_MAILBOX_DB_RDY_MASK;
316 if (ready)
317 break;
318
319 if (msecs > 4000) {
320 dev_err(&adapter->pdev->dev, "mbox poll timed out\n");
321 if (!lancer_chip(adapter))
322 be_detect_dump_ue(adapter);
323 return -1;
324 }
325
326 msleep(1);
327 msecs++;
328 } while (true);
329
330 return 0;
331 }
332
333 /*
334 * Insert the mailbox address into the doorbell in two steps
335 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
336 */
337 static int be_mbox_notify_wait(struct be_adapter *adapter)
338 {
339 int status;
340 u32 val = 0;
341 void __iomem *db = adapter->db + MPU_MAILBOX_DB_OFFSET;
342 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
343 struct be_mcc_mailbox *mbox = mbox_mem->va;
344 struct be_mcc_compl *compl = &mbox->compl;
345
346 /* wait for ready to be set */
347 status = be_mbox_db_ready_wait(adapter, db);
348 if (status != 0)
349 return status;
350
351 val |= MPU_MAILBOX_DB_HI_MASK;
352 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
353 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
354 iowrite32(val, db);
355
356 /* wait for ready to be set */
357 status = be_mbox_db_ready_wait(adapter, db);
358 if (status != 0)
359 return status;
360
361 val = 0;
362 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
363 val |= (u32)(mbox_mem->dma >> 4) << 2;
364 iowrite32(val, db);
365
366 status = be_mbox_db_ready_wait(adapter, db);
367 if (status != 0)
368 return status;
369
370 /* A cq entry has been made now */
371 if (be_mcc_compl_is_new(compl)) {
372 status = be_mcc_compl_process(adapter, &mbox->compl);
373 be_mcc_compl_use(compl);
374 if (status)
375 return status;
376 } else {
377 dev_err(&adapter->pdev->dev, "invalid mailbox completion\n");
378 return -1;
379 }
380 return 0;
381 }
382
383 static int be_POST_stage_get(struct be_adapter *adapter, u16 *stage)
384 {
385 u32 sem;
386
387 if (lancer_chip(adapter))
388 sem = ioread32(adapter->db + MPU_EP_SEMAPHORE_IF_TYPE2_OFFSET);
389 else
390 sem = ioread32(adapter->csr + MPU_EP_SEMAPHORE_OFFSET);
391
392 *stage = sem & EP_SEMAPHORE_POST_STAGE_MASK;
393 if ((sem >> EP_SEMAPHORE_POST_ERR_SHIFT) & EP_SEMAPHORE_POST_ERR_MASK)
394 return -1;
395 else
396 return 0;
397 }
398
399 int be_cmd_POST(struct be_adapter *adapter)
400 {
401 u16 stage;
402 int status, timeout = 0;
403 struct device *dev = &adapter->pdev->dev;
404
405 do {
406 status = be_POST_stage_get(adapter, &stage);
407 if (status) {
408 dev_err(dev, "POST error; stage=0x%x\n", stage);
409 return -1;
410 } else if (stage != POST_STAGE_ARMFW_RDY) {
411 if (msleep_interruptible(2000)) {
412 dev_err(dev, "Waiting for POST aborted\n");
413 return -EINTR;
414 }
415 timeout += 2;
416 } else {
417 return 0;
418 }
419 } while (timeout < 60);
420
421 dev_err(dev, "POST timeout; stage=0x%x\n", stage);
422 return -1;
423 }
424
425
426 static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
427 {
428 return &wrb->payload.sgl[0];
429 }
430
431 /* Don't touch the hdr after it's prepared */
432 static void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
433 bool embedded, u8 sge_cnt, u32 opcode)
434 {
435 if (embedded)
436 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
437 else
438 wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) <<
439 MCC_WRB_SGE_CNT_SHIFT;
440 wrb->payload_length = payload_len;
441 wrb->tag0 = opcode;
442 be_dws_cpu_to_le(wrb, 8);
443 }
444
445 /* Don't touch the hdr after it's prepared */
446 static void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
447 u8 subsystem, u8 opcode, int cmd_len)
448 {
449 req_hdr->opcode = opcode;
450 req_hdr->subsystem = subsystem;
451 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
452 req_hdr->version = 0;
453 }
454
455 static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
456 struct be_dma_mem *mem)
457 {
458 int i, buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
459 u64 dma = (u64)mem->dma;
460
461 for (i = 0; i < buf_pages; i++) {
462 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
463 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
464 dma += PAGE_SIZE_4K;
465 }
466 }
467
468 /* Converts interrupt delay in microseconds to multiplier value */
469 static u32 eq_delay_to_mult(u32 usec_delay)
470 {
471 #define MAX_INTR_RATE 651042
472 const u32 round = 10;
473 u32 multiplier;
474
475 if (usec_delay == 0)
476 multiplier = 0;
477 else {
478 u32 interrupt_rate = 1000000 / usec_delay;
479 /* Max delay, corresponding to the lowest interrupt rate */
480 if (interrupt_rate == 0)
481 multiplier = 1023;
482 else {
483 multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
484 multiplier /= interrupt_rate;
485 /* Round the multiplier to the closest value.*/
486 multiplier = (multiplier + round/2) / round;
487 multiplier = min(multiplier, (u32)1023);
488 }
489 }
490 return multiplier;
491 }
492
493 static inline struct be_mcc_wrb *wrb_from_mbox(struct be_adapter *adapter)
494 {
495 struct be_dma_mem *mbox_mem = &adapter->mbox_mem;
496 struct be_mcc_wrb *wrb
497 = &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
498 memset(wrb, 0, sizeof(*wrb));
499 return wrb;
500 }
501
502 static struct be_mcc_wrb *wrb_from_mccq(struct be_adapter *adapter)
503 {
504 struct be_queue_info *mccq = &adapter->mcc_obj.q;
505 struct be_mcc_wrb *wrb;
506
507 if (atomic_read(&mccq->used) >= mccq->len) {
508 dev_err(&adapter->pdev->dev, "Out of MCCQ wrbs\n");
509 return NULL;
510 }
511
512 wrb = queue_head_node(mccq);
513 queue_head_inc(mccq);
514 atomic_inc(&mccq->used);
515 memset(wrb, 0, sizeof(*wrb));
516 return wrb;
517 }
518
519 /* Tell fw we're about to start firing cmds by writing a
520 * special pattern across the wrb hdr; uses mbox
521 */
522 int be_cmd_fw_init(struct be_adapter *adapter)
523 {
524 u8 *wrb;
525 int status;
526
527 if (mutex_lock_interruptible(&adapter->mbox_lock))
528 return -1;
529
530 wrb = (u8 *)wrb_from_mbox(adapter);
531 *wrb++ = 0xFF;
532 *wrb++ = 0x12;
533 *wrb++ = 0x34;
534 *wrb++ = 0xFF;
535 *wrb++ = 0xFF;
536 *wrb++ = 0x56;
537 *wrb++ = 0x78;
538 *wrb = 0xFF;
539
540 status = be_mbox_notify_wait(adapter);
541
542 mutex_unlock(&adapter->mbox_lock);
543 return status;
544 }
545
546 /* Tell fw we're done with firing cmds by writing a
547 * special pattern across the wrb hdr; uses mbox
548 */
549 int be_cmd_fw_clean(struct be_adapter *adapter)
550 {
551 u8 *wrb;
552 int status;
553
554 if (adapter->eeh_err)
555 return -EIO;
556
557 if (mutex_lock_interruptible(&adapter->mbox_lock))
558 return -1;
559
560 wrb = (u8 *)wrb_from_mbox(adapter);
561 *wrb++ = 0xFF;
562 *wrb++ = 0xAA;
563 *wrb++ = 0xBB;
564 *wrb++ = 0xFF;
565 *wrb++ = 0xFF;
566 *wrb++ = 0xCC;
567 *wrb++ = 0xDD;
568 *wrb = 0xFF;
569
570 status = be_mbox_notify_wait(adapter);
571
572 mutex_unlock(&adapter->mbox_lock);
573 return status;
574 }
575 int be_cmd_eq_create(struct be_adapter *adapter,
576 struct be_queue_info *eq, int eq_delay)
577 {
578 struct be_mcc_wrb *wrb;
579 struct be_cmd_req_eq_create *req;
580 struct be_dma_mem *q_mem = &eq->dma_mem;
581 int status;
582
583 if (mutex_lock_interruptible(&adapter->mbox_lock))
584 return -1;
585
586 wrb = wrb_from_mbox(adapter);
587 req = embedded_payload(wrb);
588
589 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_COMMON_EQ_CREATE);
590
591 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
592 OPCODE_COMMON_EQ_CREATE, sizeof(*req));
593
594 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
595
596 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
597 /* 4byte eqe*/
598 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
599 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
600 __ilog2_u32(eq->len/256));
601 AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
602 eq_delay_to_mult(eq_delay));
603 be_dws_cpu_to_le(req->context, sizeof(req->context));
604
605 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
606
607 status = be_mbox_notify_wait(adapter);
608 if (!status) {
609 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
610 eq->id = le16_to_cpu(resp->eq_id);
611 eq->created = true;
612 }
613
614 mutex_unlock(&adapter->mbox_lock);
615 return status;
616 }
617
618 /* Uses mbox */
619 int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
620 u8 type, bool permanent, u32 if_handle)
621 {
622 struct be_mcc_wrb *wrb;
623 struct be_cmd_req_mac_query *req;
624 int status;
625
626 if (mutex_lock_interruptible(&adapter->mbox_lock))
627 return -1;
628
629 wrb = wrb_from_mbox(adapter);
630 req = embedded_payload(wrb);
631
632 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
633 OPCODE_COMMON_NTWK_MAC_QUERY);
634
635 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
636 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req));
637
638 req->type = type;
639 if (permanent) {
640 req->permanent = 1;
641 } else {
642 req->if_id = cpu_to_le16((u16) if_handle);
643 req->permanent = 0;
644 }
645
646 status = be_mbox_notify_wait(adapter);
647 if (!status) {
648 struct be_cmd_resp_mac_query *resp = embedded_payload(wrb);
649 memcpy(mac_addr, resp->mac.addr, ETH_ALEN);
650 }
651
652 mutex_unlock(&adapter->mbox_lock);
653 return status;
654 }
655
656 /* Uses synchronous MCCQ */
657 int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
658 u32 if_id, u32 *pmac_id, u32 domain)
659 {
660 struct be_mcc_wrb *wrb;
661 struct be_cmd_req_pmac_add *req;
662 int status;
663
664 spin_lock_bh(&adapter->mcc_lock);
665
666 wrb = wrb_from_mccq(adapter);
667 if (!wrb) {
668 status = -EBUSY;
669 goto err;
670 }
671 req = embedded_payload(wrb);
672
673 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
674 OPCODE_COMMON_NTWK_PMAC_ADD);
675
676 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
677 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req));
678
679 req->hdr.domain = domain;
680 req->if_id = cpu_to_le32(if_id);
681 memcpy(req->mac_address, mac_addr, ETH_ALEN);
682
683 status = be_mcc_notify_wait(adapter);
684 if (!status) {
685 struct be_cmd_resp_pmac_add *resp = embedded_payload(wrb);
686 *pmac_id = le32_to_cpu(resp->pmac_id);
687 }
688
689 err:
690 spin_unlock_bh(&adapter->mcc_lock);
691 return status;
692 }
693
694 /* Uses synchronous MCCQ */
695 int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id, u32 dom)
696 {
697 struct be_mcc_wrb *wrb;
698 struct be_cmd_req_pmac_del *req;
699 int status;
700
701 spin_lock_bh(&adapter->mcc_lock);
702
703 wrb = wrb_from_mccq(adapter);
704 if (!wrb) {
705 status = -EBUSY;
706 goto err;
707 }
708 req = embedded_payload(wrb);
709
710 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
711 OPCODE_COMMON_NTWK_PMAC_DEL);
712
713 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
714 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req));
715
716 req->hdr.domain = dom;
717 req->if_id = cpu_to_le32(if_id);
718 req->pmac_id = cpu_to_le32(pmac_id);
719
720 status = be_mcc_notify_wait(adapter);
721
722 err:
723 spin_unlock_bh(&adapter->mcc_lock);
724 return status;
725 }
726
727 /* Uses Mbox */
728 int be_cmd_cq_create(struct be_adapter *adapter,
729 struct be_queue_info *cq, struct be_queue_info *eq,
730 bool sol_evts, bool no_delay, int coalesce_wm)
731 {
732 struct be_mcc_wrb *wrb;
733 struct be_cmd_req_cq_create *req;
734 struct be_dma_mem *q_mem = &cq->dma_mem;
735 void *ctxt;
736 int status;
737
738 if (mutex_lock_interruptible(&adapter->mbox_lock))
739 return -1;
740
741 wrb = wrb_from_mbox(adapter);
742 req = embedded_payload(wrb);
743 ctxt = &req->context;
744
745 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
746 OPCODE_COMMON_CQ_CREATE);
747
748 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
749 OPCODE_COMMON_CQ_CREATE, sizeof(*req));
750
751 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
752 if (lancer_chip(adapter)) {
753 req->hdr.version = 2;
754 req->page_size = 1; /* 1 for 4K */
755 AMAP_SET_BITS(struct amap_cq_context_lancer, nodelay, ctxt,
756 no_delay);
757 AMAP_SET_BITS(struct amap_cq_context_lancer, count, ctxt,
758 __ilog2_u32(cq->len/256));
759 AMAP_SET_BITS(struct amap_cq_context_lancer, valid, ctxt, 1);
760 AMAP_SET_BITS(struct amap_cq_context_lancer, eventable,
761 ctxt, 1);
762 AMAP_SET_BITS(struct amap_cq_context_lancer, eqid,
763 ctxt, eq->id);
764 AMAP_SET_BITS(struct amap_cq_context_lancer, armed, ctxt, 1);
765 } else {
766 AMAP_SET_BITS(struct amap_cq_context_be, coalescwm, ctxt,
767 coalesce_wm);
768 AMAP_SET_BITS(struct amap_cq_context_be, nodelay,
769 ctxt, no_delay);
770 AMAP_SET_BITS(struct amap_cq_context_be, count, ctxt,
771 __ilog2_u32(cq->len/256));
772 AMAP_SET_BITS(struct amap_cq_context_be, valid, ctxt, 1);
773 AMAP_SET_BITS(struct amap_cq_context_be, solevent,
774 ctxt, sol_evts);
775 AMAP_SET_BITS(struct amap_cq_context_be, eventable, ctxt, 1);
776 AMAP_SET_BITS(struct amap_cq_context_be, eqid, ctxt, eq->id);
777 AMAP_SET_BITS(struct amap_cq_context_be, armed, ctxt, 1);
778 }
779
780 be_dws_cpu_to_le(ctxt, sizeof(req->context));
781
782 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
783
784 status = be_mbox_notify_wait(adapter);
785 if (!status) {
786 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
787 cq->id = le16_to_cpu(resp->cq_id);
788 cq->created = true;
789 }
790
791 mutex_unlock(&adapter->mbox_lock);
792
793 return status;
794 }
795
796 static u32 be_encoded_q_len(int q_len)
797 {
798 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
799 if (len_encoded == 16)
800 len_encoded = 0;
801 return len_encoded;
802 }
803
804 int be_cmd_mccq_ext_create(struct be_adapter *adapter,
805 struct be_queue_info *mccq,
806 struct be_queue_info *cq)
807 {
808 struct be_mcc_wrb *wrb;
809 struct be_cmd_req_mcc_ext_create *req;
810 struct be_dma_mem *q_mem = &mccq->dma_mem;
811 void *ctxt;
812 int status;
813
814 if (mutex_lock_interruptible(&adapter->mbox_lock))
815 return -1;
816
817 wrb = wrb_from_mbox(adapter);
818 req = embedded_payload(wrb);
819 ctxt = &req->context;
820
821 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
822 OPCODE_COMMON_MCC_CREATE_EXT);
823
824 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
825 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req));
826
827 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
828 if (lancer_chip(adapter)) {
829 req->hdr.version = 1;
830 req->cq_id = cpu_to_le16(cq->id);
831
832 AMAP_SET_BITS(struct amap_mcc_context_lancer, ring_size, ctxt,
833 be_encoded_q_len(mccq->len));
834 AMAP_SET_BITS(struct amap_mcc_context_lancer, valid, ctxt, 1);
835 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_id,
836 ctxt, cq->id);
837 AMAP_SET_BITS(struct amap_mcc_context_lancer, async_cq_valid,
838 ctxt, 1);
839
840 } else {
841 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
842 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
843 be_encoded_q_len(mccq->len));
844 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
845 }
846
847 /* Subscribe to Link State and Group 5 Events(bits 1 and 5 set) */
848 req->async_event_bitmap[0] = cpu_to_le32(0x00000022);
849 be_dws_cpu_to_le(ctxt, sizeof(req->context));
850
851 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
852
853 status = be_mbox_notify_wait(adapter);
854 if (!status) {
855 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
856 mccq->id = le16_to_cpu(resp->id);
857 mccq->created = true;
858 }
859 mutex_unlock(&adapter->mbox_lock);
860
861 return status;
862 }
863
864 int be_cmd_mccq_org_create(struct be_adapter *adapter,
865 struct be_queue_info *mccq,
866 struct be_queue_info *cq)
867 {
868 struct be_mcc_wrb *wrb;
869 struct be_cmd_req_mcc_create *req;
870 struct be_dma_mem *q_mem = &mccq->dma_mem;
871 void *ctxt;
872 int status;
873
874 if (mutex_lock_interruptible(&adapter->mbox_lock))
875 return -1;
876
877 wrb = wrb_from_mbox(adapter);
878 req = embedded_payload(wrb);
879 ctxt = &req->context;
880
881 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
882 OPCODE_COMMON_MCC_CREATE);
883
884 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
885 OPCODE_COMMON_MCC_CREATE, sizeof(*req));
886
887 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
888
889 AMAP_SET_BITS(struct amap_mcc_context_be, valid, ctxt, 1);
890 AMAP_SET_BITS(struct amap_mcc_context_be, ring_size, ctxt,
891 be_encoded_q_len(mccq->len));
892 AMAP_SET_BITS(struct amap_mcc_context_be, cq_id, ctxt, cq->id);
893
894 be_dws_cpu_to_le(ctxt, sizeof(req->context));
895
896 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
897
898 status = be_mbox_notify_wait(adapter);
899 if (!status) {
900 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
901 mccq->id = le16_to_cpu(resp->id);
902 mccq->created = true;
903 }
904
905 mutex_unlock(&adapter->mbox_lock);
906 return status;
907 }
908
909 int be_cmd_mccq_create(struct be_adapter *adapter,
910 struct be_queue_info *mccq,
911 struct be_queue_info *cq)
912 {
913 int status;
914
915 status = be_cmd_mccq_ext_create(adapter, mccq, cq);
916 if (status && !lancer_chip(adapter)) {
917 dev_warn(&adapter->pdev->dev, "Upgrade to F/W ver 2.102.235.0 "
918 "or newer to avoid conflicting priorities between NIC "
919 "and FCoE traffic");
920 status = be_cmd_mccq_org_create(adapter, mccq, cq);
921 }
922 return status;
923 }
924
925 int be_cmd_txq_create(struct be_adapter *adapter,
926 struct be_queue_info *txq,
927 struct be_queue_info *cq)
928 {
929 struct be_mcc_wrb *wrb;
930 struct be_cmd_req_eth_tx_create *req;
931 struct be_dma_mem *q_mem = &txq->dma_mem;
932 void *ctxt;
933 int status;
934
935 if (mutex_lock_interruptible(&adapter->mbox_lock))
936 return -1;
937
938 wrb = wrb_from_mbox(adapter);
939 req = embedded_payload(wrb);
940 ctxt = &req->context;
941
942 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
943 OPCODE_ETH_TX_CREATE);
944
945 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_TX_CREATE,
946 sizeof(*req));
947
948 if (lancer_chip(adapter)) {
949 req->hdr.version = 1;
950 AMAP_SET_BITS(struct amap_tx_context, if_id, ctxt,
951 adapter->if_handle);
952 }
953
954 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
955 req->ulp_num = BE_ULP1_NUM;
956 req->type = BE_ETH_TX_RING_TYPE_STANDARD;
957
958 AMAP_SET_BITS(struct amap_tx_context, tx_ring_size, ctxt,
959 be_encoded_q_len(txq->len));
960 AMAP_SET_BITS(struct amap_tx_context, ctx_valid, ctxt, 1);
961 AMAP_SET_BITS(struct amap_tx_context, cq_id_send, ctxt, cq->id);
962
963 be_dws_cpu_to_le(ctxt, sizeof(req->context));
964
965 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
966
967 status = be_mbox_notify_wait(adapter);
968 if (!status) {
969 struct be_cmd_resp_eth_tx_create *resp = embedded_payload(wrb);
970 txq->id = le16_to_cpu(resp->cid);
971 txq->created = true;
972 }
973
974 mutex_unlock(&adapter->mbox_lock);
975
976 return status;
977 }
978
979 /* Uses MCC */
980 int be_cmd_rxq_create(struct be_adapter *adapter,
981 struct be_queue_info *rxq, u16 cq_id, u16 frag_size,
982 u16 max_frame_size, u32 if_id, u32 rss, u8 *rss_id)
983 {
984 struct be_mcc_wrb *wrb;
985 struct be_cmd_req_eth_rx_create *req;
986 struct be_dma_mem *q_mem = &rxq->dma_mem;
987 int status;
988
989 spin_lock_bh(&adapter->mcc_lock);
990
991 wrb = wrb_from_mccq(adapter);
992 if (!wrb) {
993 status = -EBUSY;
994 goto err;
995 }
996 req = embedded_payload(wrb);
997
998 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
999 OPCODE_ETH_RX_CREATE);
1000
1001 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_RX_CREATE,
1002 sizeof(*req));
1003
1004 req->cq_id = cpu_to_le16(cq_id);
1005 req->frag_size = fls(frag_size) - 1;
1006 req->num_pages = 2;
1007 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1008 req->interface_id = cpu_to_le32(if_id);
1009 req->max_frame_size = cpu_to_le16(max_frame_size);
1010 req->rss_queue = cpu_to_le32(rss);
1011
1012 status = be_mcc_notify_wait(adapter);
1013 if (!status) {
1014 struct be_cmd_resp_eth_rx_create *resp = embedded_payload(wrb);
1015 rxq->id = le16_to_cpu(resp->id);
1016 rxq->created = true;
1017 *rss_id = resp->rss_id;
1018 }
1019
1020 err:
1021 spin_unlock_bh(&adapter->mcc_lock);
1022 return status;
1023 }
1024
1025 /* Generic destroyer function for all types of queues
1026 * Uses Mbox
1027 */
1028 int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1029 int queue_type)
1030 {
1031 struct be_mcc_wrb *wrb;
1032 struct be_cmd_req_q_destroy *req;
1033 u8 subsys = 0, opcode = 0;
1034 int status;
1035
1036 if (adapter->eeh_err)
1037 return -EIO;
1038
1039 if (mutex_lock_interruptible(&adapter->mbox_lock))
1040 return -1;
1041
1042 wrb = wrb_from_mbox(adapter);
1043 req = embedded_payload(wrb);
1044
1045 switch (queue_type) {
1046 case QTYPE_EQ:
1047 subsys = CMD_SUBSYSTEM_COMMON;
1048 opcode = OPCODE_COMMON_EQ_DESTROY;
1049 break;
1050 case QTYPE_CQ:
1051 subsys = CMD_SUBSYSTEM_COMMON;
1052 opcode = OPCODE_COMMON_CQ_DESTROY;
1053 break;
1054 case QTYPE_TXQ:
1055 subsys = CMD_SUBSYSTEM_ETH;
1056 opcode = OPCODE_ETH_TX_DESTROY;
1057 break;
1058 case QTYPE_RXQ:
1059 subsys = CMD_SUBSYSTEM_ETH;
1060 opcode = OPCODE_ETH_RX_DESTROY;
1061 break;
1062 case QTYPE_MCCQ:
1063 subsys = CMD_SUBSYSTEM_COMMON;
1064 opcode = OPCODE_COMMON_MCC_DESTROY;
1065 break;
1066 default:
1067 BUG();
1068 }
1069
1070 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, opcode);
1071
1072 be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
1073 req->id = cpu_to_le16(q->id);
1074
1075 status = be_mbox_notify_wait(adapter);
1076 if (!status)
1077 q->created = false;
1078
1079 mutex_unlock(&adapter->mbox_lock);
1080 return status;
1081 }
1082
1083 /* Uses MCC */
1084 int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1085 {
1086 struct be_mcc_wrb *wrb;
1087 struct be_cmd_req_q_destroy *req;
1088 int status;
1089
1090 spin_lock_bh(&adapter->mcc_lock);
1091
1092 wrb = wrb_from_mccq(adapter);
1093 if (!wrb) {
1094 status = -EBUSY;
1095 goto err;
1096 }
1097 req = embedded_payload(wrb);
1098
1099 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_ETH_RX_DESTROY);
1100 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_RX_DESTROY,
1101 sizeof(*req));
1102 req->id = cpu_to_le16(q->id);
1103
1104 status = be_mcc_notify_wait(adapter);
1105 if (!status)
1106 q->created = false;
1107
1108 err:
1109 spin_unlock_bh(&adapter->mcc_lock);
1110 return status;
1111 }
1112
1113 /* Create an rx filtering policy configuration on an i/f
1114 * Uses mbox
1115 */
1116 int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1117 u8 *mac, bool pmac_invalid, u32 *if_handle, u32 *pmac_id,
1118 u32 domain)
1119 {
1120 struct be_mcc_wrb *wrb;
1121 struct be_cmd_req_if_create *req;
1122 int status;
1123
1124 if (mutex_lock_interruptible(&adapter->mbox_lock))
1125 return -1;
1126
1127 wrb = wrb_from_mbox(adapter);
1128 req = embedded_payload(wrb);
1129
1130 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1131 OPCODE_COMMON_NTWK_INTERFACE_CREATE);
1132
1133 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1134 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req));
1135
1136 req->hdr.domain = domain;
1137 req->capability_flags = cpu_to_le32(cap_flags);
1138 req->enable_flags = cpu_to_le32(en_flags);
1139 req->pmac_invalid = pmac_invalid;
1140 if (!pmac_invalid)
1141 memcpy(req->mac_addr, mac, ETH_ALEN);
1142
1143 status = be_mbox_notify_wait(adapter);
1144 if (!status) {
1145 struct be_cmd_resp_if_create *resp = embedded_payload(wrb);
1146 *if_handle = le32_to_cpu(resp->interface_id);
1147 if (!pmac_invalid)
1148 *pmac_id = le32_to_cpu(resp->pmac_id);
1149 }
1150
1151 mutex_unlock(&adapter->mbox_lock);
1152 return status;
1153 }
1154
1155 /* Uses mbox */
1156 int be_cmd_if_destroy(struct be_adapter *adapter, u32 interface_id, u32 domain)
1157 {
1158 struct be_mcc_wrb *wrb;
1159 struct be_cmd_req_if_destroy *req;
1160 int status;
1161
1162 if (adapter->eeh_err)
1163 return -EIO;
1164
1165 if (mutex_lock_interruptible(&adapter->mbox_lock))
1166 return -1;
1167
1168 wrb = wrb_from_mbox(adapter);
1169 req = embedded_payload(wrb);
1170
1171 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1172 OPCODE_COMMON_NTWK_INTERFACE_DESTROY);
1173
1174 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1175 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req));
1176
1177 req->hdr.domain = domain;
1178 req->interface_id = cpu_to_le32(interface_id);
1179
1180 status = be_mbox_notify_wait(adapter);
1181
1182 mutex_unlock(&adapter->mbox_lock);
1183
1184 return status;
1185 }
1186
1187 /* Get stats is a non embedded command: the request is not embedded inside
1188 * WRB but is a separate dma memory block
1189 * Uses asynchronous MCC
1190 */
1191 int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1192 {
1193 struct be_mcc_wrb *wrb;
1194 struct be_cmd_req_hdr *hdr;
1195 struct be_sge *sge;
1196 int status = 0;
1197
1198 if (MODULO(adapter->work_counter, be_get_temp_freq) == 0)
1199 be_cmd_get_die_temperature(adapter);
1200
1201 spin_lock_bh(&adapter->mcc_lock);
1202
1203 wrb = wrb_from_mccq(adapter);
1204 if (!wrb) {
1205 status = -EBUSY;
1206 goto err;
1207 }
1208 hdr = nonemb_cmd->va;
1209 sge = nonembedded_sgl(wrb);
1210
1211 be_wrb_hdr_prepare(wrb, nonemb_cmd->size, false, 1,
1212 OPCODE_ETH_GET_STATISTICS);
1213
1214 be_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1215 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size);
1216
1217 if (adapter->generation == BE_GEN3)
1218 hdr->version = 1;
1219
1220 wrb->tag1 = CMD_SUBSYSTEM_ETH;
1221 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1222 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1223 sge->len = cpu_to_le32(nonemb_cmd->size);
1224
1225 be_mcc_notify(adapter);
1226 adapter->stats_cmd_sent = true;
1227
1228 err:
1229 spin_unlock_bh(&adapter->mcc_lock);
1230 return status;
1231 }
1232
1233 /* Lancer Stats */
1234 int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1235 struct be_dma_mem *nonemb_cmd)
1236 {
1237
1238 struct be_mcc_wrb *wrb;
1239 struct lancer_cmd_req_pport_stats *req;
1240 struct be_sge *sge;
1241 int status = 0;
1242
1243 spin_lock_bh(&adapter->mcc_lock);
1244
1245 wrb = wrb_from_mccq(adapter);
1246 if (!wrb) {
1247 status = -EBUSY;
1248 goto err;
1249 }
1250 req = nonemb_cmd->va;
1251 sge = nonembedded_sgl(wrb);
1252
1253 be_wrb_hdr_prepare(wrb, nonemb_cmd->size, false, 1,
1254 OPCODE_ETH_GET_PPORT_STATS);
1255
1256 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1257 OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size);
1258
1259
1260 req->cmd_params.params.pport_num = cpu_to_le16(adapter->port_num);
1261 req->cmd_params.params.reset_stats = 0;
1262
1263 wrb->tag1 = CMD_SUBSYSTEM_ETH;
1264 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1265 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1266 sge->len = cpu_to_le32(nonemb_cmd->size);
1267
1268 be_mcc_notify(adapter);
1269 adapter->stats_cmd_sent = true;
1270
1271 err:
1272 spin_unlock_bh(&adapter->mcc_lock);
1273 return status;
1274 }
1275
1276 /* Uses synchronous mcc */
1277 int be_cmd_link_status_query(struct be_adapter *adapter, u8 *mac_speed,
1278 u16 *link_speed, u32 dom)
1279 {
1280 struct be_mcc_wrb *wrb;
1281 struct be_cmd_req_link_status *req;
1282 int status;
1283
1284 spin_lock_bh(&adapter->mcc_lock);
1285
1286 wrb = wrb_from_mccq(adapter);
1287 if (!wrb) {
1288 status = -EBUSY;
1289 goto err;
1290 }
1291 req = embedded_payload(wrb);
1292
1293 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1294 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY);
1295
1296 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1297 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req));
1298
1299 status = be_mcc_notify_wait(adapter);
1300 if (!status) {
1301 struct be_cmd_resp_link_status *resp = embedded_payload(wrb);
1302 if (resp->mac_speed != PHY_LINK_SPEED_ZERO) {
1303 *link_speed = le16_to_cpu(resp->link_speed);
1304 *mac_speed = resp->mac_speed;
1305 }
1306 }
1307
1308 err:
1309 spin_unlock_bh(&adapter->mcc_lock);
1310 return status;
1311 }
1312
1313 /* Uses synchronous mcc */
1314 int be_cmd_get_die_temperature(struct be_adapter *adapter)
1315 {
1316 struct be_mcc_wrb *wrb;
1317 struct be_cmd_req_get_cntl_addnl_attribs *req;
1318 u16 mccq_index;
1319 int status;
1320
1321 spin_lock_bh(&adapter->mcc_lock);
1322
1323 mccq_index = adapter->mcc_obj.q.head;
1324
1325 wrb = wrb_from_mccq(adapter);
1326 if (!wrb) {
1327 status = -EBUSY;
1328 goto err;
1329 }
1330 req = embedded_payload(wrb);
1331
1332 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1333 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES);
1334
1335 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1336 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req));
1337
1338 wrb->tag1 = mccq_index;
1339
1340 be_mcc_notify(adapter);
1341
1342 err:
1343 spin_unlock_bh(&adapter->mcc_lock);
1344 return status;
1345 }
1346
1347 /* Uses synchronous mcc */
1348 int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1349 {
1350 struct be_mcc_wrb *wrb;
1351 struct be_cmd_req_get_fat *req;
1352 int status;
1353
1354 spin_lock_bh(&adapter->mcc_lock);
1355
1356 wrb = wrb_from_mccq(adapter);
1357 if (!wrb) {
1358 status = -EBUSY;
1359 goto err;
1360 }
1361 req = embedded_payload(wrb);
1362
1363 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1364 OPCODE_COMMON_MANAGE_FAT);
1365
1366 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1367 OPCODE_COMMON_MANAGE_FAT, sizeof(*req));
1368 req->fat_operation = cpu_to_le32(QUERY_FAT);
1369 status = be_mcc_notify_wait(adapter);
1370 if (!status) {
1371 struct be_cmd_resp_get_fat *resp = embedded_payload(wrb);
1372 if (log_size && resp->log_size)
1373 *log_size = le32_to_cpu(resp->log_size) -
1374 sizeof(u32);
1375 }
1376 err:
1377 spin_unlock_bh(&adapter->mcc_lock);
1378 return status;
1379 }
1380
1381 void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1382 {
1383 struct be_dma_mem get_fat_cmd;
1384 struct be_mcc_wrb *wrb;
1385 struct be_cmd_req_get_fat *req;
1386 struct be_sge *sge;
1387 u32 offset = 0, total_size, buf_size,
1388 log_offset = sizeof(u32), payload_len;
1389 int status;
1390
1391 if (buf_len == 0)
1392 return;
1393
1394 total_size = buf_len;
1395
1396 get_fat_cmd.size = sizeof(struct be_cmd_req_get_fat) + 60*1024;
1397 get_fat_cmd.va = pci_alloc_consistent(adapter->pdev,
1398 get_fat_cmd.size,
1399 &get_fat_cmd.dma);
1400 if (!get_fat_cmd.va) {
1401 status = -ENOMEM;
1402 dev_err(&adapter->pdev->dev,
1403 "Memory allocation failure while retrieving FAT data\n");
1404 return;
1405 }
1406
1407 spin_lock_bh(&adapter->mcc_lock);
1408
1409 while (total_size) {
1410 buf_size = min(total_size, (u32)60*1024);
1411 total_size -= buf_size;
1412
1413 wrb = wrb_from_mccq(adapter);
1414 if (!wrb) {
1415 status = -EBUSY;
1416 goto err;
1417 }
1418 req = get_fat_cmd.va;
1419 sge = nonembedded_sgl(wrb);
1420
1421 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
1422 be_wrb_hdr_prepare(wrb, payload_len, false, 1,
1423 OPCODE_COMMON_MANAGE_FAT);
1424
1425 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1426 OPCODE_COMMON_MANAGE_FAT, payload_len);
1427
1428 sge->pa_hi = cpu_to_le32(upper_32_bits(get_fat_cmd.dma));
1429 sge->pa_lo = cpu_to_le32(get_fat_cmd.dma & 0xFFFFFFFF);
1430 sge->len = cpu_to_le32(get_fat_cmd.size);
1431
1432 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1433 req->read_log_offset = cpu_to_le32(log_offset);
1434 req->read_log_length = cpu_to_le32(buf_size);
1435 req->data_buffer_size = cpu_to_le32(buf_size);
1436
1437 status = be_mcc_notify_wait(adapter);
1438 if (!status) {
1439 struct be_cmd_resp_get_fat *resp = get_fat_cmd.va;
1440 memcpy(buf + offset,
1441 resp->data_buffer,
1442 le32_to_cpu(resp->read_log_length));
1443 } else {
1444 dev_err(&adapter->pdev->dev, "FAT Table Retrieve error\n");
1445 goto err;
1446 }
1447 offset += buf_size;
1448 log_offset += buf_size;
1449 }
1450 err:
1451 pci_free_consistent(adapter->pdev, get_fat_cmd.size,
1452 get_fat_cmd.va,
1453 get_fat_cmd.dma);
1454 spin_unlock_bh(&adapter->mcc_lock);
1455 }
1456
1457 /* Uses synchronous mcc */
1458 int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver,
1459 char *fw_on_flash)
1460 {
1461 struct be_mcc_wrb *wrb;
1462 struct be_cmd_req_get_fw_version *req;
1463 int status;
1464
1465 spin_lock_bh(&adapter->mcc_lock);
1466
1467 wrb = wrb_from_mccq(adapter);
1468 if (!wrb) {
1469 status = -EBUSY;
1470 goto err;
1471 }
1472
1473 req = embedded_payload(wrb);
1474 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1475 OPCODE_COMMON_GET_FW_VERSION);
1476 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1477 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req));
1478
1479 status = be_mcc_notify_wait(adapter);
1480 if (!status) {
1481 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
1482 strcpy(fw_ver, resp->firmware_version_string);
1483 if (fw_on_flash)
1484 strcpy(fw_on_flash, resp->fw_on_flash_version_string);
1485 }
1486 err:
1487 spin_unlock_bh(&adapter->mcc_lock);
1488 return status;
1489 }
1490
1491 /* set the EQ delay interval of an EQ to specified value
1492 * Uses async mcc
1493 */
1494 int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
1495 {
1496 struct be_mcc_wrb *wrb;
1497 struct be_cmd_req_modify_eq_delay *req;
1498 int status = 0;
1499
1500 spin_lock_bh(&adapter->mcc_lock);
1501
1502 wrb = wrb_from_mccq(adapter);
1503 if (!wrb) {
1504 status = -EBUSY;
1505 goto err;
1506 }
1507 req = embedded_payload(wrb);
1508
1509 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1510 OPCODE_COMMON_MODIFY_EQ_DELAY);
1511
1512 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1513 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req));
1514
1515 req->num_eq = cpu_to_le32(1);
1516 req->delay[0].eq_id = cpu_to_le32(eq_id);
1517 req->delay[0].phase = 0;
1518 req->delay[0].delay_multiplier = cpu_to_le32(eqd);
1519
1520 be_mcc_notify(adapter);
1521
1522 err:
1523 spin_unlock_bh(&adapter->mcc_lock);
1524 return status;
1525 }
1526
1527 /* Uses sycnhronous mcc */
1528 int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1529 u32 num, bool untagged, bool promiscuous)
1530 {
1531 struct be_mcc_wrb *wrb;
1532 struct be_cmd_req_vlan_config *req;
1533 int status;
1534
1535 spin_lock_bh(&adapter->mcc_lock);
1536
1537 wrb = wrb_from_mccq(adapter);
1538 if (!wrb) {
1539 status = -EBUSY;
1540 goto err;
1541 }
1542 req = embedded_payload(wrb);
1543
1544 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1545 OPCODE_COMMON_NTWK_VLAN_CONFIG);
1546
1547 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1548 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req));
1549
1550 req->interface_id = if_id;
1551 req->promiscuous = promiscuous;
1552 req->untagged = untagged;
1553 req->num_vlan = num;
1554 if (!promiscuous) {
1555 memcpy(req->normal_vlan, vtag_array,
1556 req->num_vlan * sizeof(vtag_array[0]));
1557 }
1558
1559 status = be_mcc_notify_wait(adapter);
1560
1561 err:
1562 spin_unlock_bh(&adapter->mcc_lock);
1563 return status;
1564 }
1565
1566 int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1567 {
1568 struct be_mcc_wrb *wrb;
1569 struct be_dma_mem *mem = &adapter->rx_filter;
1570 struct be_cmd_req_rx_filter *req = mem->va;
1571 struct be_sge *sge;
1572 int status;
1573
1574 spin_lock_bh(&adapter->mcc_lock);
1575
1576 wrb = wrb_from_mccq(adapter);
1577 if (!wrb) {
1578 status = -EBUSY;
1579 goto err;
1580 }
1581 sge = nonembedded_sgl(wrb);
1582 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
1583 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
1584 sge->len = cpu_to_le32(mem->size);
1585 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1586 OPCODE_COMMON_NTWK_RX_FILTER);
1587
1588 memset(req, 0, sizeof(*req));
1589 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1590 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req));
1591
1592 req->if_id = cpu_to_le32(adapter->if_handle);
1593 if (flags & IFF_PROMISC) {
1594 req->if_flags_mask = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1595 BE_IF_FLAGS_VLAN_PROMISCUOUS);
1596 if (value == ON)
1597 req->if_flags = cpu_to_le32(BE_IF_FLAGS_PROMISCUOUS |
1598 BE_IF_FLAGS_VLAN_PROMISCUOUS);
1599 } else if (flags & IFF_ALLMULTI) {
1600 req->if_flags_mask = req->if_flags =
1601 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS);
1602 } else {
1603 struct netdev_hw_addr *ha;
1604 int i = 0;
1605
1606 req->if_flags_mask = req->if_flags =
1607 cpu_to_le32(BE_IF_FLAGS_MULTICAST);
1608 req->mcast_num = cpu_to_le16(netdev_mc_count(adapter->netdev));
1609 netdev_for_each_mc_addr(ha, adapter->netdev)
1610 memcpy(req->mcast_mac[i++].byte, ha->addr, ETH_ALEN);
1611 }
1612
1613 status = be_mcc_notify_wait(adapter);
1614 err:
1615 spin_unlock_bh(&adapter->mcc_lock);
1616 return status;
1617 }
1618
1619 /* Uses synchrounous mcc */
1620 int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1621 {
1622 struct be_mcc_wrb *wrb;
1623 struct be_cmd_req_set_flow_control *req;
1624 int status;
1625
1626 spin_lock_bh(&adapter->mcc_lock);
1627
1628 wrb = wrb_from_mccq(adapter);
1629 if (!wrb) {
1630 status = -EBUSY;
1631 goto err;
1632 }
1633 req = embedded_payload(wrb);
1634
1635 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1636 OPCODE_COMMON_SET_FLOW_CONTROL);
1637
1638 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1639 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req));
1640
1641 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1642 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
1643
1644 status = be_mcc_notify_wait(adapter);
1645
1646 err:
1647 spin_unlock_bh(&adapter->mcc_lock);
1648 return status;
1649 }
1650
1651 /* Uses sycn mcc */
1652 int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1653 {
1654 struct be_mcc_wrb *wrb;
1655 struct be_cmd_req_get_flow_control *req;
1656 int status;
1657
1658 spin_lock_bh(&adapter->mcc_lock);
1659
1660 wrb = wrb_from_mccq(adapter);
1661 if (!wrb) {
1662 status = -EBUSY;
1663 goto err;
1664 }
1665 req = embedded_payload(wrb);
1666
1667 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1668 OPCODE_COMMON_GET_FLOW_CONTROL);
1669
1670 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1671 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req));
1672
1673 status = be_mcc_notify_wait(adapter);
1674 if (!status) {
1675 struct be_cmd_resp_get_flow_control *resp =
1676 embedded_payload(wrb);
1677 *tx_fc = le16_to_cpu(resp->tx_flow_control);
1678 *rx_fc = le16_to_cpu(resp->rx_flow_control);
1679 }
1680
1681 err:
1682 spin_unlock_bh(&adapter->mcc_lock);
1683 return status;
1684 }
1685
1686 /* Uses mbox */
1687 int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1688 u32 *mode, u32 *caps)
1689 {
1690 struct be_mcc_wrb *wrb;
1691 struct be_cmd_req_query_fw_cfg *req;
1692 int status;
1693
1694 if (mutex_lock_interruptible(&adapter->mbox_lock))
1695 return -1;
1696
1697 wrb = wrb_from_mbox(adapter);
1698 req = embedded_payload(wrb);
1699
1700 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1701 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG);
1702
1703 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1704 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req));
1705
1706 status = be_mbox_notify_wait(adapter);
1707 if (!status) {
1708 struct be_cmd_resp_query_fw_cfg *resp = embedded_payload(wrb);
1709 *port_num = le32_to_cpu(resp->phys_port);
1710 *mode = le32_to_cpu(resp->function_mode);
1711 *caps = le32_to_cpu(resp->function_caps);
1712 }
1713
1714 mutex_unlock(&adapter->mbox_lock);
1715 return status;
1716 }
1717
1718 /* Uses mbox */
1719 int be_cmd_reset_function(struct be_adapter *adapter)
1720 {
1721 struct be_mcc_wrb *wrb;
1722 struct be_cmd_req_hdr *req;
1723 int status;
1724
1725 if (mutex_lock_interruptible(&adapter->mbox_lock))
1726 return -1;
1727
1728 wrb = wrb_from_mbox(adapter);
1729 req = embedded_payload(wrb);
1730
1731 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1732 OPCODE_COMMON_FUNCTION_RESET);
1733
1734 be_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1735 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req));
1736
1737 status = be_mbox_notify_wait(adapter);
1738
1739 mutex_unlock(&adapter->mbox_lock);
1740 return status;
1741 }
1742
1743 int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, u16 table_size)
1744 {
1745 struct be_mcc_wrb *wrb;
1746 struct be_cmd_req_rss_config *req;
1747 u32 myhash[10] = {0x0123, 0x4567, 0x89AB, 0xCDEF, 0x01EF,
1748 0x0123, 0x4567, 0x89AB, 0xCDEF, 0x01EF};
1749 int status;
1750
1751 if (mutex_lock_interruptible(&adapter->mbox_lock))
1752 return -1;
1753
1754 wrb = wrb_from_mbox(adapter);
1755 req = embedded_payload(wrb);
1756
1757 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1758 OPCODE_ETH_RSS_CONFIG);
1759
1760 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1761 OPCODE_ETH_RSS_CONFIG, sizeof(*req));
1762
1763 req->if_id = cpu_to_le32(adapter->if_handle);
1764 req->enable_rss = cpu_to_le16(RSS_ENABLE_TCP_IPV4 | RSS_ENABLE_IPV4);
1765 req->cpu_table_size_log2 = cpu_to_le16(fls(table_size) - 1);
1766 memcpy(req->cpu_table, rsstable, table_size);
1767 memcpy(req->hash, myhash, sizeof(myhash));
1768 be_dws_cpu_to_le(req->hash, sizeof(req->hash));
1769
1770 status = be_mbox_notify_wait(adapter);
1771
1772 mutex_unlock(&adapter->mbox_lock);
1773 return status;
1774 }
1775
1776 /* Uses sync mcc */
1777 int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1778 u8 bcn, u8 sts, u8 state)
1779 {
1780 struct be_mcc_wrb *wrb;
1781 struct be_cmd_req_enable_disable_beacon *req;
1782 int status;
1783
1784 spin_lock_bh(&adapter->mcc_lock);
1785
1786 wrb = wrb_from_mccq(adapter);
1787 if (!wrb) {
1788 status = -EBUSY;
1789 goto err;
1790 }
1791 req = embedded_payload(wrb);
1792
1793 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1794 OPCODE_COMMON_ENABLE_DISABLE_BEACON);
1795
1796 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1797 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req));
1798
1799 req->port_num = port_num;
1800 req->beacon_state = state;
1801 req->beacon_duration = bcn;
1802 req->status_duration = sts;
1803
1804 status = be_mcc_notify_wait(adapter);
1805
1806 err:
1807 spin_unlock_bh(&adapter->mcc_lock);
1808 return status;
1809 }
1810
1811 /* Uses sync mcc */
1812 int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
1813 {
1814 struct be_mcc_wrb *wrb;
1815 struct be_cmd_req_get_beacon_state *req;
1816 int status;
1817
1818 spin_lock_bh(&adapter->mcc_lock);
1819
1820 wrb = wrb_from_mccq(adapter);
1821 if (!wrb) {
1822 status = -EBUSY;
1823 goto err;
1824 }
1825 req = embedded_payload(wrb);
1826
1827 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1828 OPCODE_COMMON_GET_BEACON_STATE);
1829
1830 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1831 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req));
1832
1833 req->port_num = port_num;
1834
1835 status = be_mcc_notify_wait(adapter);
1836 if (!status) {
1837 struct be_cmd_resp_get_beacon_state *resp =
1838 embedded_payload(wrb);
1839 *state = resp->beacon_state;
1840 }
1841
1842 err:
1843 spin_unlock_bh(&adapter->mcc_lock);
1844 return status;
1845 }
1846
1847 int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
1848 u32 data_size, u32 data_offset, const char *obj_name,
1849 u32 *data_written, u8 *addn_status)
1850 {
1851 struct be_mcc_wrb *wrb;
1852 struct lancer_cmd_req_write_object *req;
1853 struct lancer_cmd_resp_write_object *resp;
1854 void *ctxt = NULL;
1855 int status;
1856
1857 spin_lock_bh(&adapter->mcc_lock);
1858 adapter->flash_status = 0;
1859
1860 wrb = wrb_from_mccq(adapter);
1861 if (!wrb) {
1862 status = -EBUSY;
1863 goto err_unlock;
1864 }
1865
1866 req = embedded_payload(wrb);
1867
1868 be_wrb_hdr_prepare(wrb, sizeof(struct lancer_cmd_req_write_object),
1869 true, 1, OPCODE_COMMON_WRITE_OBJECT);
1870 wrb->tag1 = CMD_SUBSYSTEM_COMMON;
1871
1872 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1873 OPCODE_COMMON_WRITE_OBJECT,
1874 sizeof(struct lancer_cmd_req_write_object));
1875
1876 ctxt = &req->context;
1877 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1878 write_length, ctxt, data_size);
1879
1880 if (data_size == 0)
1881 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1882 eof, ctxt, 1);
1883 else
1884 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
1885 eof, ctxt, 0);
1886
1887 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1888 req->write_offset = cpu_to_le32(data_offset);
1889 strcpy(req->object_name, obj_name);
1890 req->descriptor_count = cpu_to_le32(1);
1891 req->buf_len = cpu_to_le32(data_size);
1892 req->addr_low = cpu_to_le32((cmd->dma +
1893 sizeof(struct lancer_cmd_req_write_object))
1894 & 0xFFFFFFFF);
1895 req->addr_high = cpu_to_le32(upper_32_bits(cmd->dma +
1896 sizeof(struct lancer_cmd_req_write_object)));
1897
1898 be_mcc_notify(adapter);
1899 spin_unlock_bh(&adapter->mcc_lock);
1900
1901 if (!wait_for_completion_timeout(&adapter->flash_compl,
1902 msecs_to_jiffies(12000)))
1903 status = -1;
1904 else
1905 status = adapter->flash_status;
1906
1907 resp = embedded_payload(wrb);
1908 if (!status) {
1909 *data_written = le32_to_cpu(resp->actual_write_len);
1910 } else {
1911 *addn_status = resp->additional_status;
1912 status = resp->status;
1913 }
1914
1915 return status;
1916
1917 err_unlock:
1918 spin_unlock_bh(&adapter->mcc_lock);
1919 return status;
1920 }
1921
1922 int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
1923 u32 flash_type, u32 flash_opcode, u32 buf_size)
1924 {
1925 struct be_mcc_wrb *wrb;
1926 struct be_cmd_write_flashrom *req;
1927 struct be_sge *sge;
1928 int status;
1929
1930 spin_lock_bh(&adapter->mcc_lock);
1931 adapter->flash_status = 0;
1932
1933 wrb = wrb_from_mccq(adapter);
1934 if (!wrb) {
1935 status = -EBUSY;
1936 goto err_unlock;
1937 }
1938 req = cmd->va;
1939 sge = nonembedded_sgl(wrb);
1940
1941 be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1942 OPCODE_COMMON_WRITE_FLASHROM);
1943 wrb->tag1 = CMD_SUBSYSTEM_COMMON;
1944
1945 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1946 OPCODE_COMMON_WRITE_FLASHROM, cmd->size);
1947 sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1948 sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1949 sge->len = cpu_to_le32(cmd->size);
1950
1951 req->params.op_type = cpu_to_le32(flash_type);
1952 req->params.op_code = cpu_to_le32(flash_opcode);
1953 req->params.data_buf_size = cpu_to_le32(buf_size);
1954
1955 be_mcc_notify(adapter);
1956 spin_unlock_bh(&adapter->mcc_lock);
1957
1958 if (!wait_for_completion_timeout(&adapter->flash_compl,
1959 msecs_to_jiffies(40000)))
1960 status = -1;
1961 else
1962 status = adapter->flash_status;
1963
1964 return status;
1965
1966 err_unlock:
1967 spin_unlock_bh(&adapter->mcc_lock);
1968 return status;
1969 }
1970
1971 int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1972 int offset)
1973 {
1974 struct be_mcc_wrb *wrb;
1975 struct be_cmd_write_flashrom *req;
1976 int status;
1977
1978 spin_lock_bh(&adapter->mcc_lock);
1979
1980 wrb = wrb_from_mccq(adapter);
1981 if (!wrb) {
1982 status = -EBUSY;
1983 goto err;
1984 }
1985 req = embedded_payload(wrb);
1986
1987 be_wrb_hdr_prepare(wrb, sizeof(*req)+4, true, 0,
1988 OPCODE_COMMON_READ_FLASHROM);
1989
1990 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1991 OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4);
1992
1993 req->params.op_type = cpu_to_le32(IMG_TYPE_REDBOOT);
1994 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
1995 req->params.offset = cpu_to_le32(offset);
1996 req->params.data_buf_size = cpu_to_le32(0x4);
1997
1998 status = be_mcc_notify_wait(adapter);
1999 if (!status)
2000 memcpy(flashed_crc, req->params.data_buf, 4);
2001
2002 err:
2003 spin_unlock_bh(&adapter->mcc_lock);
2004 return status;
2005 }
2006
2007 int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
2008 struct be_dma_mem *nonemb_cmd)
2009 {
2010 struct be_mcc_wrb *wrb;
2011 struct be_cmd_req_acpi_wol_magic_config *req;
2012 struct be_sge *sge;
2013 int status;
2014
2015 spin_lock_bh(&adapter->mcc_lock);
2016
2017 wrb = wrb_from_mccq(adapter);
2018 if (!wrb) {
2019 status = -EBUSY;
2020 goto err;
2021 }
2022 req = nonemb_cmd->va;
2023 sge = nonembedded_sgl(wrb);
2024
2025 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
2026 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG);
2027
2028 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2029 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req));
2030 memcpy(req->magic_mac, mac, ETH_ALEN);
2031
2032 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
2033 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
2034 sge->len = cpu_to_le32(nonemb_cmd->size);
2035
2036 status = be_mcc_notify_wait(adapter);
2037
2038 err:
2039 spin_unlock_bh(&adapter->mcc_lock);
2040 return status;
2041 }
2042
2043 int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2044 u8 loopback_type, u8 enable)
2045 {
2046 struct be_mcc_wrb *wrb;
2047 struct be_cmd_req_set_lmode *req;
2048 int status;
2049
2050 spin_lock_bh(&adapter->mcc_lock);
2051
2052 wrb = wrb_from_mccq(adapter);
2053 if (!wrb) {
2054 status = -EBUSY;
2055 goto err;
2056 }
2057
2058 req = embedded_payload(wrb);
2059
2060 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
2061 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE);
2062
2063 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2064 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
2065 sizeof(*req));
2066
2067 req->src_port = port_num;
2068 req->dest_port = port_num;
2069 req->loopback_type = loopback_type;
2070 req->loopback_state = enable;
2071
2072 status = be_mcc_notify_wait(adapter);
2073 err:
2074 spin_unlock_bh(&adapter->mcc_lock);
2075 return status;
2076 }
2077
2078 int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2079 u32 loopback_type, u32 pkt_size, u32 num_pkts, u64 pattern)
2080 {
2081 struct be_mcc_wrb *wrb;
2082 struct be_cmd_req_loopback_test *req;
2083 int status;
2084
2085 spin_lock_bh(&adapter->mcc_lock);
2086
2087 wrb = wrb_from_mccq(adapter);
2088 if (!wrb) {
2089 status = -EBUSY;
2090 goto err;
2091 }
2092
2093 req = embedded_payload(wrb);
2094
2095 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
2096 OPCODE_LOWLEVEL_LOOPBACK_TEST);
2097
2098 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2099 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req));
2100 req->hdr.timeout = cpu_to_le32(4);
2101
2102 req->pattern = cpu_to_le64(pattern);
2103 req->src_port = cpu_to_le32(port_num);
2104 req->dest_port = cpu_to_le32(port_num);
2105 req->pkt_size = cpu_to_le32(pkt_size);
2106 req->num_pkts = cpu_to_le32(num_pkts);
2107 req->loopback_type = cpu_to_le32(loopback_type);
2108
2109 status = be_mcc_notify_wait(adapter);
2110 if (!status) {
2111 struct be_cmd_resp_loopback_test *resp = embedded_payload(wrb);
2112 status = le32_to_cpu(resp->status);
2113 }
2114
2115 err:
2116 spin_unlock_bh(&adapter->mcc_lock);
2117 return status;
2118 }
2119
2120 int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
2121 u32 byte_cnt, struct be_dma_mem *cmd)
2122 {
2123 struct be_mcc_wrb *wrb;
2124 struct be_cmd_req_ddrdma_test *req;
2125 struct be_sge *sge;
2126 int status;
2127 int i, j = 0;
2128
2129 spin_lock_bh(&adapter->mcc_lock);
2130
2131 wrb = wrb_from_mccq(adapter);
2132 if (!wrb) {
2133 status = -EBUSY;
2134 goto err;
2135 }
2136 req = cmd->va;
2137 sge = nonembedded_sgl(wrb);
2138 be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
2139 OPCODE_LOWLEVEL_HOST_DDR_DMA);
2140 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2141 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size);
2142
2143 sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
2144 sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
2145 sge->len = cpu_to_le32(cmd->size);
2146
2147 req->pattern = cpu_to_le64(pattern);
2148 req->byte_count = cpu_to_le32(byte_cnt);
2149 for (i = 0; i < byte_cnt; i++) {
2150 req->snd_buff[i] = (u8)(pattern >> (j*8));
2151 j++;
2152 if (j > 7)
2153 j = 0;
2154 }
2155
2156 status = be_mcc_notify_wait(adapter);
2157
2158 if (!status) {
2159 struct be_cmd_resp_ddrdma_test *resp;
2160 resp = cmd->va;
2161 if ((memcmp(resp->rcv_buff, req->snd_buff, byte_cnt) != 0) ||
2162 resp->snd_err) {
2163 status = -1;
2164 }
2165 }
2166
2167 err:
2168 spin_unlock_bh(&adapter->mcc_lock);
2169 return status;
2170 }
2171
2172 int be_cmd_get_seeprom_data(struct be_adapter *adapter,
2173 struct be_dma_mem *nonemb_cmd)
2174 {
2175 struct be_mcc_wrb *wrb;
2176 struct be_cmd_req_seeprom_read *req;
2177 struct be_sge *sge;
2178 int status;
2179
2180 spin_lock_bh(&adapter->mcc_lock);
2181
2182 wrb = wrb_from_mccq(adapter);
2183 if (!wrb) {
2184 status = -EBUSY;
2185 goto err;
2186 }
2187 req = nonemb_cmd->va;
2188 sge = nonembedded_sgl(wrb);
2189
2190 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
2191 OPCODE_COMMON_SEEPROM_READ);
2192
2193 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2194 OPCODE_COMMON_SEEPROM_READ, sizeof(*req));
2195
2196 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
2197 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
2198 sge->len = cpu_to_le32(nonemb_cmd->size);
2199
2200 status = be_mcc_notify_wait(adapter);
2201
2202 err:
2203 spin_unlock_bh(&adapter->mcc_lock);
2204 return status;
2205 }
2206
2207 int be_cmd_get_phy_info(struct be_adapter *adapter,
2208 struct be_phy_info *phy_info)
2209 {
2210 struct be_mcc_wrb *wrb;
2211 struct be_cmd_req_get_phy_info *req;
2212 struct be_sge *sge;
2213 struct be_dma_mem cmd;
2214 int status;
2215
2216 spin_lock_bh(&adapter->mcc_lock);
2217
2218 wrb = wrb_from_mccq(adapter);
2219 if (!wrb) {
2220 status = -EBUSY;
2221 goto err;
2222 }
2223 cmd.size = sizeof(struct be_cmd_req_get_phy_info);
2224 cmd.va = pci_alloc_consistent(adapter->pdev, cmd.size,
2225 &cmd.dma);
2226 if (!cmd.va) {
2227 dev_err(&adapter->pdev->dev, "Memory alloc failure\n");
2228 status = -ENOMEM;
2229 goto err;
2230 }
2231
2232 req = cmd.va;
2233 sge = nonembedded_sgl(wrb);
2234
2235 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
2236 OPCODE_COMMON_GET_PHY_DETAILS);
2237
2238 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2239 OPCODE_COMMON_GET_PHY_DETAILS,
2240 sizeof(*req));
2241
2242 sge->pa_hi = cpu_to_le32(upper_32_bits(cmd.dma));
2243 sge->pa_lo = cpu_to_le32(cmd.dma & 0xFFFFFFFF);
2244 sge->len = cpu_to_le32(cmd.size);
2245
2246 status = be_mcc_notify_wait(adapter);
2247 if (!status) {
2248 struct be_phy_info *resp_phy_info =
2249 cmd.va + sizeof(struct be_cmd_req_hdr);
2250 phy_info->phy_type = le16_to_cpu(resp_phy_info->phy_type);
2251 phy_info->interface_type =
2252 le16_to_cpu(resp_phy_info->interface_type);
2253 }
2254 pci_free_consistent(adapter->pdev, cmd.size,
2255 cmd.va, cmd.dma);
2256 err:
2257 spin_unlock_bh(&adapter->mcc_lock);
2258 return status;
2259 }
2260
2261 int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
2262 {
2263 struct be_mcc_wrb *wrb;
2264 struct be_cmd_req_set_qos *req;
2265 int status;
2266
2267 spin_lock_bh(&adapter->mcc_lock);
2268
2269 wrb = wrb_from_mccq(adapter);
2270 if (!wrb) {
2271 status = -EBUSY;
2272 goto err;
2273 }
2274
2275 req = embedded_payload(wrb);
2276
2277 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
2278 OPCODE_COMMON_SET_QOS);
2279
2280 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2281 OPCODE_COMMON_SET_QOS, sizeof(*req));
2282
2283 req->hdr.domain = domain;
2284 req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
2285 req->max_bps_nic = cpu_to_le32(bps);
2286
2287 status = be_mcc_notify_wait(adapter);
2288
2289 err:
2290 spin_unlock_bh(&adapter->mcc_lock);
2291 return status;
2292 }
2293
2294 int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2295 {
2296 struct be_mcc_wrb *wrb;
2297 struct be_cmd_req_cntl_attribs *req;
2298 struct be_cmd_resp_cntl_attribs *resp;
2299 struct be_sge *sge;
2300 int status;
2301 int payload_len = max(sizeof(*req), sizeof(*resp));
2302 struct mgmt_controller_attrib *attribs;
2303 struct be_dma_mem attribs_cmd;
2304
2305 memset(&attribs_cmd, 0, sizeof(struct be_dma_mem));
2306 attribs_cmd.size = sizeof(struct be_cmd_resp_cntl_attribs);
2307 attribs_cmd.va = pci_alloc_consistent(adapter->pdev, attribs_cmd.size,
2308 &attribs_cmd.dma);
2309 if (!attribs_cmd.va) {
2310 dev_err(&adapter->pdev->dev,
2311 "Memory allocation failure\n");
2312 return -ENOMEM;
2313 }
2314
2315 if (mutex_lock_interruptible(&adapter->mbox_lock))
2316 return -1;
2317
2318 wrb = wrb_from_mbox(adapter);
2319 if (!wrb) {
2320 status = -EBUSY;
2321 goto err;
2322 }
2323 req = attribs_cmd.va;
2324 sge = nonembedded_sgl(wrb);
2325
2326 be_wrb_hdr_prepare(wrb, payload_len, false, 1,
2327 OPCODE_COMMON_GET_CNTL_ATTRIBUTES);
2328 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2329 OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len);
2330 sge->pa_hi = cpu_to_le32(upper_32_bits(attribs_cmd.dma));
2331 sge->pa_lo = cpu_to_le32(attribs_cmd.dma & 0xFFFFFFFF);
2332 sge->len = cpu_to_le32(attribs_cmd.size);
2333
2334 status = be_mbox_notify_wait(adapter);
2335 if (!status) {
2336 attribs = attribs_cmd.va + sizeof(struct be_cmd_resp_hdr);
2337 adapter->hba_port_num = attribs->hba_attribs.phy_port;
2338 }
2339
2340 err:
2341 mutex_unlock(&adapter->mbox_lock);
2342 pci_free_consistent(adapter->pdev, attribs_cmd.size, attribs_cmd.va,
2343 attribs_cmd.dma);
2344 return status;
2345 }
2346
2347 /* Uses mbox */
2348 int be_cmd_req_native_mode(struct be_adapter *adapter)
2349 {
2350 struct be_mcc_wrb *wrb;
2351 struct be_cmd_req_set_func_cap *req;
2352 int status;
2353
2354 if (mutex_lock_interruptible(&adapter->mbox_lock))
2355 return -1;
2356
2357 wrb = wrb_from_mbox(adapter);
2358 if (!wrb) {
2359 status = -EBUSY;
2360 goto err;
2361 }
2362
2363 req = embedded_payload(wrb);
2364
2365 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
2366 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP);
2367
2368 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2369 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req));
2370
2371 req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2372 CAPABILITY_BE3_NATIVE_ERX_API);
2373 req->cap_flags = cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API);
2374
2375 status = be_mbox_notify_wait(adapter);
2376 if (!status) {
2377 struct be_cmd_resp_set_func_cap *resp = embedded_payload(wrb);
2378 adapter->be3_native = le32_to_cpu(resp->cap_flags) &
2379 CAPABILITY_BE3_NATIVE_ERX_API;
2380 }
2381 err:
2382 mutex_unlock(&adapter->mbox_lock);
2383 return status;
2384 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree