arch/x86/oprofile/nmi_int.c

   1 /**
   2  * @file nmi_int.c
   3  *
   4  * @remark Copyright 2002-2009 OProfile authors
   5  * @remark Read the file COPYING
   6  *
   7  * @author John Levon <levon@movementarian.org>
   8  * @author Robert Richter <robert.richter@amd.com>
   9  * @author Barry Kasindorf <barry.kasindorf@amd.com>
  10  * @author Jason Yeh <jason.yeh@amd.com>
  11  * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
  12  */
  13
  14 #include <linux/init.h>
  15 #include <linux/notifier.h>
  16 #include <linux/smp.h>
  17 #include <linux/oprofile.h>
  18 #include <linux/sysdev.h>
  19 #include <linux/slab.h>
  20 #include <linux/moduleparam.h>
  21 #include <linux/kdebug.h>
  22 #include <linux/cpu.h>
  23 #include <asm/nmi.h>
  24 #include <asm/msr.h>
  25 #include <asm/apic.h>
  26
  27 #include "op_counter.h"
  28 #include "op_x86_model.h"
  29
  30 static struct op_x86_model_spec *model;
  31 static DEFINE_PER_CPU(struct op_msrs, cpu_msrs);
  32 static DEFINE_PER_CPU(unsigned long, saved_lvtpc);
  33
  34 /* 0 == registered but off, 1 == registered and on */
  35 static int nmi_enabled = 0;
  36
  37 struct op_counter_config counter_config[OP_MAX_COUNTER];
  38
  39 /* common functions */
  40
  41 u64 op_x86_get_ctrl(struct op_x86_model_spec const *model,
  42                     struct op_counter_config *counter_config)
  43 {
  44         u64 val = 0;
  45         u16 event = (u16)counter_config->event;
  46
  47         val |= ARCH_PERFMON_EVENTSEL_INT;
  48         val |= counter_config->user ? ARCH_PERFMON_EVENTSEL_USR : 0;
  49         val |= counter_config->kernel ? ARCH_PERFMON_EVENTSEL_OS : 0;
  50         val |= (counter_config->unit_mask & 0xFF) << 8;
  51         event &= model->event_mask ? model->event_mask : 0xFF;
  52         val |= event & 0xFF;
  53         val |= (event & 0x0F00) << 24;
  54
  55         return val;
  56 }
  57
  58
  59 static int profile_exceptions_notify(struct notifier_block *self,
  60                                      unsigned long val, void *data)
  61 {
  62         struct die_args *args = (struct die_args *)data;
  63         int ret = NOTIFY_DONE;
  64         int cpu = smp_processor_id();
  65
  66         switch (val) {
  67         case DIE_NMI:
  68         case DIE_NMI_IPI:
  69                 model->check_ctrs(args->regs, &per_cpu(cpu_msrs, cpu));
  70                 ret = NOTIFY_STOP;
  71                 break;
  72         default:
  73                 break;
  74         }
  75         return ret;
  76 }
  77
  78 static void nmi_cpu_save_registers(struct op_msrs *msrs)
  79 {
  80         struct op_msr *counters = msrs->counters;
  81         struct op_msr *controls = msrs->controls;
  82         unsigned int i;
  83
  84         for (i = 0; i < model->num_counters; ++i) {
  85                 if (counters[i].addr)
  86                         rdmsrl(counters[i].addr, counters[i].saved);
  87         }
  88
  89         for (i = 0; i < model->num_controls; ++i) {
  90                 if (controls[i].addr)
  91                         rdmsrl(controls[i].addr, controls[i].saved);
  92         }
  93 }
  94
  95 static void nmi_cpu_start(void *dummy)
  96 {
  97         struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
  98         if (!msrs->controls)
  99                 WARN_ON_ONCE(1);
 100         else
 101                 model->start(msrs);
 102 }
 103
 104 static int nmi_start(void)
 105 {
 106         on_each_cpu(nmi_cpu_start, NULL, 1);
 107         return 0;
 108 }
 109
 110 static void nmi_cpu_stop(void *dummy)
 111 {
 112         struct op_msrs const *msrs = &__get_cpu_var(cpu_msrs);
 113         if (!msrs->controls)
 114                 WARN_ON_ONCE(1);
 115         else
 116                 model->stop(msrs);
 117 }
 118
 119 static void nmi_stop(void)
 120 {
 121         on_each_cpu(nmi_cpu_stop, NULL, 1);
 122 }
 123
 124 #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX
 125
 126 static DEFINE_PER_CPU(int, switch_index);
 127
 128 static inline int has_mux(void)
 129 {
 130         return !!model->switch_ctrl;
 131 }
 132
 133 inline int op_x86_phys_to_virt(int phys)
 134 {
 135         return __get_cpu_var(switch_index) + phys;
 136 }
 137
 138 inline int op_x86_virt_to_phys(int virt)
 139 {
 140         return virt % model->num_counters;
 141 }
 142
 143 static void nmi_shutdown_mux(void)
 144 {
 145         int i;
 146
 147         if (!has_mux())
 148                 return;
 149
 150         for_each_possible_cpu(i) {
 151                 kfree(per_cpu(cpu_msrs, i).multiplex);
 152                 per_cpu(cpu_msrs, i).multiplex = NULL;
 153                 per_cpu(switch_index, i) = 0;
 154         }
 155 }
 156
 157 static int nmi_setup_mux(void)
 158 {
 159         size_t multiplex_size =
 160                 sizeof(struct op_msr) * model->num_virt_counters;
 161         int i;
 162
 163         if (!has_mux())
 164                 return 1;
 165
 166         for_each_possible_cpu(i) {
 167                 per_cpu(cpu_msrs, i).multiplex =
 168                         kzalloc(multiplex_size, GFP_KERNEL);
 169                 if (!per_cpu(cpu_msrs, i).multiplex)
 170                         return 0;
 171         }
 172
 173         return 1;
 174 }
 175
 176 static void nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs)
 177 {
 178         int i;
 179         struct op_msr *multiplex = msrs->multiplex;
 180
 181         if (!has_mux())
 182                 return;
 183
 184         for (i = 0; i < model->num_virt_counters; ++i) {
 185                 if (counter_config[i].enabled) {
 186                         multiplex[i].saved = -(u64)counter_config[i].count;
 187                 } else {
 188                         multiplex[i].saved = 0;
 189                 }
 190         }
 191
 192         per_cpu(switch_index, cpu) = 0;
 193 }
 194
 195 static void nmi_cpu_save_mpx_registers(struct op_msrs *msrs)
 196 {
 197         struct op_msr *counters = msrs->counters;
 198         struct op_msr *multiplex = msrs->multiplex;
 199         int i;
 200
 201         for (i = 0; i < model->num_counters; ++i) {
 202                 int virt = op_x86_phys_to_virt(i);
 203                 if (counters[i].addr)
 204                         rdmsrl(counters[i].addr, multiplex[virt].saved);
 205         }
 206 }
 207
 208 static void nmi_cpu_restore_mpx_registers(struct op_msrs *msrs)
 209 {
 210         struct op_msr *counters = msrs->counters;
 211         struct op_msr *multiplex = msrs->multiplex;
 212         int i;
 213
 214         for (i = 0; i < model->num_counters; ++i) {
 215                 int virt = op_x86_phys_to_virt(i);
 216                 if (counters[i].addr)
 217                         wrmsrl(counters[i].addr, multiplex[virt].saved);
 218         }
 219 }
 220
 221 static void nmi_cpu_switch(void *dummy)
 222 {
 223         int cpu = smp_processor_id();
 224         int si = per_cpu(switch_index, cpu);
 225         struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
 226
 227         nmi_cpu_stop(NULL);
 228         nmi_cpu_save_mpx_registers(msrs);
 229
 230         /* move to next set */
 231         si += model->num_counters;
 232         if ((si >= model->num_virt_counters) || (counter_config[si].count == 0))
 233                 per_cpu(switch_index, cpu) = 0;
 234         else
 235                 per_cpu(switch_index, cpu) = si;
 236
 237         model->switch_ctrl(model, msrs);
 238         nmi_cpu_restore_mpx_registers(msrs);
 239
 240         nmi_cpu_start(NULL);
 241 }
 242
 243
 244 /*
 245  * Quick check to see if multiplexing is necessary.
 246  * The check should be sufficient since counters are used
 247  * in ordre.
 248  */
 249 static int nmi_multiplex_on(void)
 250 {
 251         return counter_config[model->num_counters].count ? 0 : -EINVAL;
 252 }
 253
 254 static int nmi_switch_event(void)
 255 {
 256         if (!has_mux())
 257                 return -ENOSYS;         /* not implemented */
 258         if (nmi_multiplex_on() < 0)
 259                 return -EINVAL;         /* not necessary */
 260
 261         on_each_cpu(nmi_cpu_switch, NULL, 1);
 262
 263         return 0;
 264 }
 265
 266 static inline void mux_init(struct oprofile_operations *ops)
 267 {
 268         if (has_mux())
 269                 ops->switch_events = nmi_switch_event;
 270 }
 271
 272 static void mux_clone(int cpu)
 273 {
 274         if (!has_mux())
 275                 return;
 276
 277         memcpy(per_cpu(cpu_msrs, cpu).multiplex,
 278                per_cpu(cpu_msrs, 0).multiplex,
 279                sizeof(struct op_msr) * model->num_virt_counters);
 280 }
 281
 282 #else
 283
 284 inline int op_x86_phys_to_virt(int phys) { return phys; }
 285 inline int op_x86_virt_to_phys(int virt) { return virt; }
 286 static inline void nmi_shutdown_mux(void) { }
 287 static inline int nmi_setup_mux(void) { return 1; }
 288 static inline void
 289 nmi_cpu_setup_mux(int cpu, struct op_msrs const * const msrs) { }
 290 static inline void mux_init(struct oprofile_operations *ops) { }
 291 static void mux_clone(int cpu) { }
 292
 293 #endif
 294
 295 static void free_msrs(void)
 296 {
 297         int i;
 298         for_each_possible_cpu(i) {
 299                 kfree(per_cpu(cpu_msrs, i).counters);
 300                 per_cpu(cpu_msrs, i).counters = NULL;
 301                 kfree(per_cpu(cpu_msrs, i).controls);
 302                 per_cpu(cpu_msrs, i).controls = NULL;
 303         }
 304 }
 305
 306 static int allocate_msrs(void)
 307 {
 308         size_t controls_size = sizeof(struct op_msr) * model->num_controls;
 309         size_t counters_size = sizeof(struct op_msr) * model->num_counters;
 310
 311         int i;
 312         for_each_possible_cpu(i) {
 313                 per_cpu(cpu_msrs, i).counters = kzalloc(counters_size,
 314                                                         GFP_KERNEL);
 315                 if (!per_cpu(cpu_msrs, i).counters)
 316                         return 0;
 317                 per_cpu(cpu_msrs, i).controls = kzalloc(controls_size,
 318                                                         GFP_KERNEL);
 319                 if (!per_cpu(cpu_msrs, i).controls)
 320                         return 0;
 321         }
 322
 323         return 1;
 324 }
 325
 326 static void nmi_cpu_setup(void *dummy)
 327 {
 328         int cpu = smp_processor_id();
 329         struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
 330         nmi_cpu_save_registers(msrs);
 331         spin_lock(&oprofilefs_lock);
 332         model->setup_ctrs(model, msrs);
 333         nmi_cpu_setup_mux(cpu, msrs);
 334         spin_unlock(&oprofilefs_lock);
 335         per_cpu(saved_lvtpc, cpu) = apic_read(APIC_LVTPC);
 336         apic_write(APIC_LVTPC, APIC_DM_NMI);
 337 }
 338
 339 static struct notifier_block profile_exceptions_nb = {
 340         .notifier_call = profile_exceptions_notify,
 341         .next = NULL,
 342         .priority = 2
 343 };
 344
 345 static int nmi_setup(void)
 346 {
 347         int err = 0;
 348         int cpu;
 349
 350         if (!allocate_msrs())
 351                 err = -ENOMEM;
 352         else if (!nmi_setup_mux())
 353                 err = -ENOMEM;
 354         else
 355                 err = register_die_notifier(&profile_exceptions_nb);
 356
 357         if (err) {
 358                 free_msrs();
 359                 nmi_shutdown_mux();
 360                 return err;
 361         }
 362
 363         /* We need to serialize save and setup for HT because the subset
 364          * of msrs are distinct for save and setup operations
 365          */
 366
 367         /* Assume saved/restored counters are the same on all CPUs */
 368         model->fill_in_addresses(&per_cpu(cpu_msrs, 0));
 369         for_each_possible_cpu(cpu) {
 370                 if (!cpu)
 371                         continue;
 372
 373                 memcpy(per_cpu(cpu_msrs, cpu).counters,
 374                        per_cpu(cpu_msrs, 0).counters,
 375                        sizeof(struct op_msr) * model->num_counters);
 376
 377                 memcpy(per_cpu(cpu_msrs, cpu).controls,
 378                        per_cpu(cpu_msrs, 0).controls,
 379                        sizeof(struct op_msr) * model->num_controls);
 380
 381                 mux_clone(cpu);
 382         }
 383         on_each_cpu(nmi_cpu_setup, NULL, 1);
 384         nmi_enabled = 1;
 385         return 0;
 386 }
 387
 388 static void nmi_cpu_restore_registers(struct op_msrs *msrs)
 389 {
 390         struct op_msr *counters = msrs->counters;
 391         struct op_msr *controls = msrs->controls;
 392         unsigned int i;
 393
 394         for (i = 0; i < model->num_controls; ++i) {
 395                 if (controls[i].addr)
 396                         wrmsrl(controls[i].addr, controls[i].saved);
 397         }
 398
 399         for (i = 0; i < model->num_counters; ++i) {
 400                 if (counters[i].addr)
 401                         wrmsrl(counters[i].addr, counters[i].saved);
 402         }
 403 }
 404
 405 static void nmi_cpu_shutdown(void *dummy)
 406 {
 407         unsigned int v;
 408         int cpu = smp_processor_id();
 409         struct op_msrs *msrs = &per_cpu(cpu_msrs, cpu);
 410
 411         /* restoring APIC_LVTPC can trigger an apic error because the delivery
 412          * mode and vector nr combination can be illegal. That's by design: on
 413          * power on apic lvt contain a zero vector nr which are legal only for
 414          * NMI delivery mode. So inhibit apic err before restoring lvtpc
 415          */
 416         v = apic_read(APIC_LVTERR);
 417         apic_write(APIC_LVTERR, v | APIC_LVT_MASKED);
 418         apic_write(APIC_LVTPC, per_cpu(saved_lvtpc, cpu));
 419         apic_write(APIC_LVTERR, v);
 420         nmi_cpu_restore_registers(msrs);
 421 }
 422
 423 static void nmi_shutdown(void)
 424 {
 425         struct op_msrs *msrs;
 426
 427         nmi_enabled = 0;
 428         on_each_cpu(nmi_cpu_shutdown, NULL, 1);
 429         unregister_die_notifier(&profile_exceptions_nb);
 430         nmi_shutdown_mux();
 431         msrs = &get_cpu_var(cpu_msrs);
 432         model->shutdown(msrs);
 433         free_msrs();
 434         put_cpu_var(cpu_msrs);
 435 }
 436
 437 static int nmi_create_files(struct super_block *sb, struct dentry *root)
 438 {
 439         unsigned int i;
 440
 441         for (i = 0; i < model->num_virt_counters; ++i) {
 442                 struct dentry *dir;
 443                 char buf[4];
 444
 445                 /* quick little hack to _not_ expose a counter if it is not
 446                  * available for use.  This should protect userspace app.
 447                  * NOTE:  assumes 1:1 mapping here (that counters are organized
 448                  *        sequentially in their struct assignment).
 449                  */
 450                 if (!avail_to_resrv_perfctr_nmi_bit(op_x86_virt_to_phys(i)))
 451                         continue;
 452
 453                 snprintf(buf,  sizeof(buf), "%d", i);
 454                 dir = oprofilefs_mkdir(sb, root, buf);
 455                 oprofilefs_create_ulong(sb, dir, "enabled", &counter_config[i].enabled);
 456                 oprofilefs_create_ulong(sb, dir, "event", &counter_config[i].event);
 457                 oprofilefs_create_ulong(sb, dir, "count", &counter_config[i].count);
 458                 oprofilefs_create_ulong(sb, dir, "unit_mask", &counter_config[i].unit_mask);
 459                 oprofilefs_create_ulong(sb, dir, "kernel", &counter_config[i].kernel);
 460                 oprofilefs_create_ulong(sb, dir, "user", &counter_config[i].user);
 461         }
 462
 463         return 0;
 464 }
 465
 466 #ifdef CONFIG_SMP
 467 static int oprofile_cpu_notifier(struct notifier_block *b, unsigned long action,
 468                                  void *data)
 469 {
 470         int cpu = (unsigned long)data;
 471         switch (action) {
 472         case CPU_DOWN_FAILED:
 473         case CPU_ONLINE:
 474                 smp_call_function_single(cpu, nmi_cpu_start, NULL, 0);
 475                 break;
 476         case CPU_DOWN_PREPARE:
 477                 smp_call_function_single(cpu, nmi_cpu_stop, NULL, 1);
 478                 break;
 479         }
 480         return NOTIFY_DONE;
 481 }
 482
 483 static struct notifier_block oprofile_cpu_nb = {
 484         .notifier_call = oprofile_cpu_notifier
 485 };
 486 #endif
 487
 488 #ifdef CONFIG_PM
 489
 490 static int nmi_suspend(struct sys_device *dev, pm_message_t state)
 491 {
 492         /* Only one CPU left, just stop that one */
 493         if (nmi_enabled == 1)
 494                 nmi_cpu_stop(NULL);
 495         return 0;
 496 }
 497
 498 static int nmi_resume(struct sys_device *dev)
 499 {
 500         if (nmi_enabled == 1)
 501                 nmi_cpu_start(NULL);
 502         return 0;
 503 }
 504
 505 static struct sysdev_class oprofile_sysclass = {
 506         .name           = "oprofile",
 507         .resume         = nmi_resume,
 508         .suspend        = nmi_suspend,
 509 };
 510
 511 static struct sys_device device_oprofile = {
 512         .id     = 0,
 513         .cls    = &oprofile_sysclass,
 514 };
 515
 516 static int __init init_sysfs(void)
 517 {
 518         int error;
 519
 520         error = sysdev_class_register(&oprofile_sysclass);
 521         if (!error)
 522                 error = sysdev_register(&device_oprofile);
 523         return error;
 524 }
 525
 526 static void exit_sysfs(void)
 527 {
 528         sysdev_unregister(&device_oprofile);
 529         sysdev_class_unregister(&oprofile_sysclass);
 530 }
 531
 532 #else
 533 #define init_sysfs() do { } while (0)
 534 #define exit_sysfs() do { } while (0)
 535 #endif /* CONFIG_PM */
 536
 537 static int __init p4_init(char **cpu_type)
 538 {
 539         __u8 cpu_model = boot_cpu_data.x86_model;
 540
 541         if (cpu_model > 6 || cpu_model == 5)
 542                 return 0;
 543
 544 #ifndef CONFIG_SMP
 545         *cpu_type = "i386/p4";
 546         model = &op_p4_spec;
 547         return 1;
 548 #else
 549         switch (smp_num_siblings) {
 550         case 1:
 551                 *cpu_type = "i386/p4";
 552                 model = &op_p4_spec;
 553                 return 1;
 554
 555         case 2:
 556                 *cpu_type = "i386/p4-ht";
 557                 model = &op_p4_ht2_spec;
 558                 return 1;
 559         }
 560 #endif
 561
 562         printk(KERN_INFO "oprofile: P4 HyperThreading detected with > 2 threads\n");
 563         printk(KERN_INFO "oprofile: Reverting to timer mode.\n");
 564         return 0;
 565 }
 566
 567 static int force_arch_perfmon;
 568 static int force_cpu_type(const char *str, struct kernel_param *kp)
 569 {
 570         if (!strcmp(str, "arch_perfmon")) {
 571                 force_arch_perfmon = 1;
 572                 printk(KERN_INFO "oprofile: forcing architectural perfmon\n");
 573         }
 574
 575         return 0;
 576 }
 577 module_param_call(cpu_type, force_cpu_type, NULL, NULL, 0);
 578
 579 static int __init ppro_init(char **cpu_type)
 580 {
 581         __u8 cpu_model = boot_cpu_data.x86_model;
 582         struct op_x86_model_spec *spec = &op_ppro_spec; /* default */
 583
 584         if (force_arch_perfmon && cpu_has_arch_perfmon)
 585                 return 0;
 586
 587         switch (cpu_model) {
 588         case 0 ... 2:
 589                 *cpu_type = "i386/ppro";
 590                 break;
 591         case 3 ... 5:
 592                 *cpu_type = "i386/pii";
 593                 break;
 594         case 6 ... 8:
 595         case 10 ... 11:
 596                 *cpu_type = "i386/piii";
 597                 break;
 598         case 9:
 599         case 13:
 600                 *cpu_type = "i386/p6_mobile";
 601                 break;
 602         case 14:
 603                 *cpu_type = "i386/core";
 604                 break;
 605         case 15: case 23:
 606                 *cpu_type = "i386/core_2";
 607                 break;
 608         case 0x2e:
 609         case 26:
 610                 spec = &op_arch_perfmon_spec;
 611                 *cpu_type = "i386/core_i7";
 612                 break;
 613         case 28:
 614                 *cpu_type = "i386/atom";
 615                 break;
 616         default:
 617                 /* Unknown */
 618                 return 0;
 619         }
 620
 621         model = spec;
 622         return 1;
 623 }
 624
 625 /* in order to get sysfs right */
 626 static int using_nmi;
 627
 628 int __init op_nmi_init(struct oprofile_operations *ops)
 629 {
 630         __u8 vendor = boot_cpu_data.x86_vendor;
 631         __u8 family = boot_cpu_data.x86;
 632         char *cpu_type = NULL;
 633         int ret = 0;
 634
 635         if (!cpu_has_apic)
 636                 return -ENODEV;
 637
 638         switch (vendor) {
 639         case X86_VENDOR_AMD:
 640                 /* Needs to be at least an Athlon (or hammer in 32bit mode) */
 641
 642                 switch (family) {
 643                 case 6:
 644                         cpu_type = "i386/athlon";
 645                         break;
 646                 case 0xf:
 647                         /*
 648                          * Actually it could be i386/hammer too, but
 649                          * give user space an consistent name.
 650                          */
 651                         cpu_type = "x86-64/hammer";
 652                         break;
 653                 case 0x10:
 654                         cpu_type = "x86-64/family10";
 655                         break;
 656                 case 0x11:
 657                         cpu_type = "x86-64/family11h";
 658                         break;
 659                 default:
 660                         return -ENODEV;
 661                 }
 662                 model = &op_amd_spec;
 663                 break;
 664
 665         case X86_VENDOR_INTEL:
 666                 switch (family) {
 667                         /* Pentium IV */
 668                 case 0xf:
 669                         p4_init(&cpu_type);
 670                         break;
 671
 672                         /* A P6-class processor */
 673                 case 6:
 674                         ppro_init(&cpu_type);
 675                         break;
 676
 677                 default:
 678                         break;
 679                 }
 680
 681                 if (cpu_type)
 682                         break;
 683
 684                 if (!cpu_has_arch_perfmon)
 685                         return -ENODEV;
 686
 687                 /* use arch perfmon as fallback */
 688                 cpu_type = "i386/arch_perfmon";
 689                 model = &op_arch_perfmon_spec;
 690                 break;
 691
 692         default:
 693                 return -ENODEV;
 694         }
 695
 696 #ifdef CONFIG_SMP
 697         register_cpu_notifier(&oprofile_cpu_nb);
 698 #endif
 699         /* default values, can be overwritten by model */
 700         ops->create_files       = nmi_create_files;
 701         ops->setup              = nmi_setup;
 702         ops->shutdown           = nmi_shutdown;
 703         ops->start              = nmi_start;
 704         ops->stop               = nmi_stop;
 705         ops->cpu_type           = cpu_type;
 706
 707         if (model->init)
 708                 ret = model->init(ops);
 709         if (ret)
 710                 return ret;
 711
 712         if (!model->num_virt_counters)
 713                 model->num_virt_counters = model->num_counters;
 714
 715         mux_init(ops);
 716
 717         init_sysfs();
 718         using_nmi = 1;
 719         printk(KERN_INFO "oprofile: using NMI interrupt.\n");
 720         return 0;
 721 }
 722
 723 void op_nmi_exit(void)
 724 {
 725         if (using_nmi) {
 726                 exit_sysfs();
 727 #ifdef CONFIG_SMP
 728                 unregister_cpu_notifier(&oprofile_cpu_nb);
 729 #endif
 730         }
 731         if (model->exit)
 732                 model->exit();
 733 }