avr32: nmi_enter() without nmi_exit()
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / ata / pata_it821x.c
blob0221c9a46769ad5e826485691d2718f863795eeb
1 /*
2 * pata_it821x.c - IT821x PATA for new ATA layer
3 * (C) 2005 Red Hat Inc
4 * Alan Cox <alan@redhat.com>
5 * (C) 2007 Bartlomiej Zolnierkiewicz
7 * based upon
9 * it821x.c
11 * linux/drivers/ide/pci/it821x.c Version 0.09 December 2004
13 * Copyright (C) 2004 Red Hat <alan@redhat.com>
15 * May be copied or modified under the terms of the GNU General Public License
16 * Based in part on the ITE vendor provided SCSI driver.
18 * Documentation available from
19 * http://www.ite.com.tw/pc/IT8212F_V04.pdf
20 * Some other documents are NDA.
22 * The ITE8212 isn't exactly a standard IDE controller. It has two
23 * modes. In pass through mode then it is an IDE controller. In its smart
24 * mode its actually quite a capable hardware raid controller disguised
25 * as an IDE controller. Smart mode only understands DMA read/write and
26 * identify, none of the fancier commands apply. The IT8211 is identical
27 * in other respects but lacks the raid mode.
29 * Errata:
30 * o Rev 0x10 also requires master/slave hold the same DMA timings and
31 * cannot do ATAPI MWDMA.
32 * o The identify data for raid volumes lacks CHS info (technically ok)
33 * but also fails to set the LBA28 and other bits. We fix these in
34 * the IDE probe quirk code.
35 * o If you write LBA48 sized I/O's (ie > 256 sector) in smart mode
36 * raid then the controller firmware dies
37 * o Smart mode without RAID doesn't clear all the necessary identify
38 * bits to reduce the command set to the one used
40 * This has a few impacts on the driver
41 * - In pass through mode we do all the work you would expect
42 * - In smart mode the clocking set up is done by the controller generally
43 * but we must watch the other limits and filter.
44 * - There are a few extra vendor commands that actually talk to the
45 * controller but only work PIO with no IRQ.
47 * Vendor areas of the identify block in smart mode are used for the
48 * timing and policy set up. Each HDD in raid mode also has a serial
49 * block on the disk. The hardware extra commands are get/set chip status,
50 * rebuild, get rebuild status.
52 * In Linux the driver supports pass through mode as if the device was
53 * just another IDE controller. If the smart mode is running then
54 * volumes are managed by the controller firmware and each IDE "disk"
55 * is a raid volume. Even more cute - the controller can do automated
56 * hotplug and rebuild.
58 * The pass through controller itself is a little demented. It has a
59 * flaw that it has a single set of PIO/MWDMA timings per channel so
60 * non UDMA devices restrict each others performance. It also has a
61 * single clock source per channel so mixed UDMA100/133 performance
62 * isn't perfect and we have to pick a clock. Thankfully none of this
63 * matters in smart mode. ATAPI DMA is not currently supported.
65 * It seems the smart mode is a win for RAID1/RAID10 but otherwise not.
67 * TODO
68 * - ATAPI and other speed filtering
69 * - RAID configuration ioctls
72 #include <linux/kernel.h>
73 #include <linux/module.h>
74 #include <linux/pci.h>
75 #include <linux/init.h>
76 #include <linux/blkdev.h>
77 #include <linux/delay.h>
78 #include <scsi/scsi_host.h>
79 #include <linux/libata.h>
82 #define DRV_NAME "pata_it821x"
83 #define DRV_VERSION "0.4.0"
85 struct it821x_dev
87 unsigned int smart:1, /* Are we in smart raid mode */
88 timing10:1; /* Rev 0x10 */
89 u8 clock_mode; /* 0, ATA_50 or ATA_66 */
90 u8 want[2][2]; /* Mode/Pri log for master slave */
91 /* We need these for switching the clock when DMA goes on/off
92 The high byte is the 66Mhz timing */
93 u16 pio[2]; /* Cached PIO values */
94 u16 mwdma[2]; /* Cached MWDMA values */
95 u16 udma[2]; /* Cached UDMA values (per drive) */
96 u16 last_device; /* Master or slave loaded ? */
99 #define ATA_66 0
100 #define ATA_50 1
101 #define ATA_ANY 2
103 #define UDMA_OFF 0
104 #define MWDMA_OFF 0
107 * We allow users to force the card into non raid mode without
108 * flashing the alternative BIOS. This is also necessary right now
109 * for embedded platforms that cannot run a PC BIOS but are using this
110 * device.
113 static int it8212_noraid;
116 * it821x_program - program the PIO/MWDMA registers
117 * @ap: ATA port
118 * @adev: Device to program
119 * @timing: Timing value (66Mhz in top 8bits, 50 in the low 8)
121 * Program the PIO/MWDMA timing for this channel according to the
122 * current clock. These share the same register so are managed by
123 * the DMA start/stop sequence as with the old driver.
126 static void it821x_program(struct ata_port *ap, struct ata_device *adev, u16 timing)
128 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
129 struct it821x_dev *itdev = ap->private_data;
130 int channel = ap->port_no;
131 u8 conf;
133 /* Program PIO/MWDMA timing bits */
134 if (itdev->clock_mode == ATA_66)
135 conf = timing >> 8;
136 else
137 conf = timing & 0xFF;
138 pci_write_config_byte(pdev, 0x54 + 4 * channel, conf);
143 * it821x_program_udma - program the UDMA registers
144 * @ap: ATA port
145 * @adev: ATA device to update
146 * @timing: Timing bits. Top 8 are for 66Mhz bottom for 50Mhz
148 * Program the UDMA timing for this drive according to the
149 * current clock. Handles the dual clocks and also knows about
150 * the errata on the 0x10 revision. The UDMA errata is partly handled
151 * here and partly in start_dma.
154 static void it821x_program_udma(struct ata_port *ap, struct ata_device *adev, u16 timing)
156 struct it821x_dev *itdev = ap->private_data;
157 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
158 int channel = ap->port_no;
159 int unit = adev->devno;
160 u8 conf;
162 /* Program UDMA timing bits */
163 if (itdev->clock_mode == ATA_66)
164 conf = timing >> 8;
165 else
166 conf = timing & 0xFF;
167 if (itdev->timing10 == 0)
168 pci_write_config_byte(pdev, 0x56 + 4 * channel + unit, conf);
169 else {
170 /* Early revision must be programmed for both together */
171 pci_write_config_byte(pdev, 0x56 + 4 * channel, conf);
172 pci_write_config_byte(pdev, 0x56 + 4 * channel + 1, conf);
177 * it821x_clock_strategy
178 * @ap: ATA interface
179 * @adev: ATA device being updated
181 * Select between the 50 and 66Mhz base clocks to get the best
182 * results for this interface.
185 static void it821x_clock_strategy(struct ata_port *ap, struct ata_device *adev)
187 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
188 struct it821x_dev *itdev = ap->private_data;
189 u8 unit = adev->devno;
190 struct ata_device *pair = ata_dev_pair(adev);
192 int clock, altclock;
193 u8 v;
194 int sel = 0;
196 /* Look for the most wanted clocking */
197 if (itdev->want[0][0] > itdev->want[1][0]) {
198 clock = itdev->want[0][1];
199 altclock = itdev->want[1][1];
200 } else {
201 clock = itdev->want[1][1];
202 altclock = itdev->want[0][1];
205 /* Master doesn't care does the slave ? */
206 if (clock == ATA_ANY)
207 clock = altclock;
209 /* Nobody cares - keep the same clock */
210 if (clock == ATA_ANY)
211 return;
212 /* No change */
213 if (clock == itdev->clock_mode)
214 return;
216 /* Load this into the controller */
217 if (clock == ATA_66)
218 itdev->clock_mode = ATA_66;
219 else {
220 itdev->clock_mode = ATA_50;
221 sel = 1;
223 pci_read_config_byte(pdev, 0x50, &v);
224 v &= ~(1 << (1 + ap->port_no));
225 v |= sel << (1 + ap->port_no);
226 pci_write_config_byte(pdev, 0x50, v);
229 * Reprogram the UDMA/PIO of the pair drive for the switch
230 * MWDMA will be dealt with by the dma switcher
232 if (pair && itdev->udma[1-unit] != UDMA_OFF) {
233 it821x_program_udma(ap, pair, itdev->udma[1-unit]);
234 it821x_program(ap, pair, itdev->pio[1-unit]);
237 * Reprogram the UDMA/PIO of our drive for the switch.
238 * MWDMA will be dealt with by the dma switcher
240 if (itdev->udma[unit] != UDMA_OFF) {
241 it821x_program_udma(ap, adev, itdev->udma[unit]);
242 it821x_program(ap, adev, itdev->pio[unit]);
247 * it821x_passthru_set_piomode - set PIO mode data
248 * @ap: ATA interface
249 * @adev: ATA device
251 * Configure for PIO mode. This is complicated as the register is
252 * shared by PIO and MWDMA and for both channels.
255 static void it821x_passthru_set_piomode(struct ata_port *ap, struct ata_device *adev)
257 /* Spec says 89 ref driver uses 88 */
258 static const u16 pio[] = { 0xAA88, 0xA382, 0xA181, 0x3332, 0x3121 };
259 static const u8 pio_want[] = { ATA_66, ATA_66, ATA_66, ATA_66, ATA_ANY };
261 struct it821x_dev *itdev = ap->private_data;
262 int unit = adev->devno;
263 int mode_wanted = adev->pio_mode - XFER_PIO_0;
265 /* We prefer 66Mhz clock for PIO 0-3, don't care for PIO4 */
266 itdev->want[unit][1] = pio_want[mode_wanted];
267 itdev->want[unit][0] = 1; /* PIO is lowest priority */
268 itdev->pio[unit] = pio[mode_wanted];
269 it821x_clock_strategy(ap, adev);
270 it821x_program(ap, adev, itdev->pio[unit]);
274 * it821x_passthru_set_dmamode - set initial DMA mode data
275 * @ap: ATA interface
276 * @adev: ATA device
278 * Set up the DMA modes. The actions taken depend heavily on the mode
279 * to use. If UDMA is used as is hopefully the usual case then the
280 * timing register is private and we need only consider the clock. If
281 * we are using MWDMA then we have to manage the setting ourself as
282 * we switch devices and mode.
285 static void it821x_passthru_set_dmamode(struct ata_port *ap, struct ata_device *adev)
287 static const u16 dma[] = { 0x8866, 0x3222, 0x3121 };
288 static const u8 mwdma_want[] = { ATA_ANY, ATA_66, ATA_ANY };
289 static const u16 udma[] = { 0x4433, 0x4231, 0x3121, 0x2121, 0x1111, 0x2211, 0x1111 };
290 static const u8 udma_want[] = { ATA_ANY, ATA_50, ATA_ANY, ATA_66, ATA_66, ATA_50, ATA_66 };
292 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
293 struct it821x_dev *itdev = ap->private_data;
294 int channel = ap->port_no;
295 int unit = adev->devno;
296 u8 conf;
298 if (adev->dma_mode >= XFER_UDMA_0) {
299 int mode_wanted = adev->dma_mode - XFER_UDMA_0;
301 itdev->want[unit][1] = udma_want[mode_wanted];
302 itdev->want[unit][0] = 3; /* UDMA is high priority */
303 itdev->mwdma[unit] = MWDMA_OFF;
304 itdev->udma[unit] = udma[mode_wanted];
305 if (mode_wanted >= 5)
306 itdev->udma[unit] |= 0x8080; /* UDMA 5/6 select on */
308 /* UDMA on. Again revision 0x10 must do the pair */
309 pci_read_config_byte(pdev, 0x50, &conf);
310 if (itdev->timing10)
311 conf &= channel ? 0x9F: 0xE7;
312 else
313 conf &= ~ (1 << (3 + 2 * channel + unit));
314 pci_write_config_byte(pdev, 0x50, conf);
315 it821x_clock_strategy(ap, adev);
316 it821x_program_udma(ap, adev, itdev->udma[unit]);
317 } else {
318 int mode_wanted = adev->dma_mode - XFER_MW_DMA_0;
320 itdev->want[unit][1] = mwdma_want[mode_wanted];
321 itdev->want[unit][0] = 2; /* MWDMA is low priority */
322 itdev->mwdma[unit] = dma[mode_wanted];
323 itdev->udma[unit] = UDMA_OFF;
325 /* UDMA bits off - Revision 0x10 do them in pairs */
326 pci_read_config_byte(pdev, 0x50, &conf);
327 if (itdev->timing10)
328 conf |= channel ? 0x60: 0x18;
329 else
330 conf |= 1 << (3 + 2 * channel + unit);
331 pci_write_config_byte(pdev, 0x50, conf);
332 it821x_clock_strategy(ap, adev);
337 * it821x_passthru_dma_start - DMA start callback
338 * @qc: Command in progress
340 * Usually drivers set the DMA timing at the point the set_dmamode call
341 * is made. IT821x however requires we load new timings on the
342 * transitions in some cases.
345 static void it821x_passthru_bmdma_start(struct ata_queued_cmd *qc)
347 struct ata_port *ap = qc->ap;
348 struct ata_device *adev = qc->dev;
349 struct it821x_dev *itdev = ap->private_data;
350 int unit = adev->devno;
352 if (itdev->mwdma[unit] != MWDMA_OFF)
353 it821x_program(ap, adev, itdev->mwdma[unit]);
354 else if (itdev->udma[unit] != UDMA_OFF && itdev->timing10)
355 it821x_program_udma(ap, adev, itdev->udma[unit]);
356 ata_bmdma_start(qc);
360 * it821x_passthru_dma_stop - DMA stop callback
361 * @qc: ATA command
363 * We loaded new timings in dma_start, as a result we need to restore
364 * the PIO timings in dma_stop so that the next command issue gets the
365 * right clock values.
368 static void it821x_passthru_bmdma_stop(struct ata_queued_cmd *qc)
370 struct ata_port *ap = qc->ap;
371 struct ata_device *adev = qc->dev;
372 struct it821x_dev *itdev = ap->private_data;
373 int unit = adev->devno;
375 ata_bmdma_stop(qc);
376 if (itdev->mwdma[unit] != MWDMA_OFF)
377 it821x_program(ap, adev, itdev->pio[unit]);
382 * it821x_passthru_dev_select - Select master/slave
383 * @ap: ATA port
384 * @device: Device number (not pointer)
386 * Device selection hook. If necessary perform clock switching
389 static void it821x_passthru_dev_select(struct ata_port *ap,
390 unsigned int device)
392 struct it821x_dev *itdev = ap->private_data;
393 if (itdev && device != itdev->last_device) {
394 struct ata_device *adev = &ap->link.device[device];
395 it821x_program(ap, adev, itdev->pio[adev->devno]);
396 itdev->last_device = device;
398 ata_sff_dev_select(ap, device);
402 * it821x_smart_qc_issue - wrap qc issue prot
403 * @qc: command
405 * Wrap the command issue sequence for the IT821x. We need to
406 * perform out own device selection timing loads before the
407 * usual happenings kick off
410 static unsigned int it821x_smart_qc_issue(struct ata_queued_cmd *qc)
412 switch(qc->tf.command)
414 /* Commands the firmware supports */
415 case ATA_CMD_READ:
416 case ATA_CMD_READ_EXT:
417 case ATA_CMD_WRITE:
418 case ATA_CMD_WRITE_EXT:
419 case ATA_CMD_PIO_READ:
420 case ATA_CMD_PIO_READ_EXT:
421 case ATA_CMD_PIO_WRITE:
422 case ATA_CMD_PIO_WRITE_EXT:
423 case ATA_CMD_READ_MULTI:
424 case ATA_CMD_READ_MULTI_EXT:
425 case ATA_CMD_WRITE_MULTI:
426 case ATA_CMD_WRITE_MULTI_EXT:
427 case ATA_CMD_ID_ATA:
428 case ATA_CMD_INIT_DEV_PARAMS:
429 case 0xFC: /* Internal 'report rebuild state' */
430 /* Arguably should just no-op this one */
431 case ATA_CMD_SET_FEATURES:
432 return ata_sff_qc_issue(qc);
434 printk(KERN_DEBUG "it821x: can't process command 0x%02X\n", qc->tf.command);
435 return AC_ERR_DEV;
439 * it821x_passthru_qc_issue - wrap qc issue prot
440 * @qc: command
442 * Wrap the command issue sequence for the IT821x. We need to
443 * perform out own device selection timing loads before the
444 * usual happenings kick off
447 static unsigned int it821x_passthru_qc_issue(struct ata_queued_cmd *qc)
449 it821x_passthru_dev_select(qc->ap, qc->dev->devno);
450 return ata_sff_qc_issue(qc);
454 * it821x_smart_set_mode - mode setting
455 * @link: interface to set up
456 * @unused: device that failed (error only)
458 * Use a non standard set_mode function. We don't want to be tuned.
459 * The BIOS configured everything. Our job is not to fiddle. We
460 * read the dma enabled bits from the PCI configuration of the device
461 * and respect them.
464 static int it821x_smart_set_mode(struct ata_link *link, struct ata_device **unused)
466 struct ata_device *dev;
468 ata_link_for_each_dev(dev, link) {
469 if (ata_dev_enabled(dev)) {
470 /* We don't really care */
471 dev->pio_mode = XFER_PIO_0;
472 dev->dma_mode = XFER_MW_DMA_0;
473 /* We do need the right mode information for DMA or PIO
474 and this comes from the current configuration flags */
475 if (ata_id_has_dma(dev->id)) {
476 ata_dev_printk(dev, KERN_INFO, "configured for DMA\n");
477 dev->xfer_mode = XFER_MW_DMA_0;
478 dev->xfer_shift = ATA_SHIFT_MWDMA;
479 dev->flags &= ~ATA_DFLAG_PIO;
480 } else {
481 ata_dev_printk(dev, KERN_INFO, "configured for PIO\n");
482 dev->xfer_mode = XFER_PIO_0;
483 dev->xfer_shift = ATA_SHIFT_PIO;
484 dev->flags |= ATA_DFLAG_PIO;
488 return 0;
492 * it821x_dev_config - Called each device identify
493 * @adev: Device that has just been identified
495 * Perform the initial setup needed for each device that is chip
496 * special. In our case we need to lock the sector count to avoid
497 * blowing the brains out of the firmware with large LBA48 requests
499 * FIXME: When FUA appears we need to block FUA too. And SMART and
500 * basically we need to filter commands for this chip.
503 static void it821x_dev_config(struct ata_device *adev)
505 unsigned char model_num[ATA_ID_PROD_LEN + 1];
507 ata_id_c_string(adev->id, model_num, ATA_ID_PROD, sizeof(model_num));
509 if (adev->max_sectors > 255)
510 adev->max_sectors = 255;
512 if (strstr(model_num, "Integrated Technology Express")) {
513 /* RAID mode */
514 ata_dev_printk(adev, KERN_INFO, "%sRAID%d volume",
515 adev->id[147]?"Bootable ":"",
516 adev->id[129]);
517 if (adev->id[129] != 1)
518 printk("(%dK stripe)", adev->id[146]);
519 printk(".\n");
521 /* This is a controller firmware triggered funny, don't
522 report the drive faulty! */
523 adev->horkage &= ~ATA_HORKAGE_DIAGNOSTIC;
524 /* No HPA in 'smart' mode */
525 adev->horkage |= ATA_HORKAGE_BROKEN_HPA;
529 * it821x_read_id - Hack identify data up
530 * @adev: device to read
531 * @tf: proposed taskfile
532 * @id: buffer for returned ident data
534 * Query the devices on this firmware driven port and slightly
535 * mash the identify data to stop us and common tools trying to
536 * use features not firmware supported. The firmware itself does
537 * some masking (eg SMART) but not enough.
540 static unsigned int it821x_read_id(struct ata_device *adev,
541 struct ata_taskfile *tf, u16 *id)
543 unsigned int err_mask;
544 unsigned char model_num[ATA_ID_PROD_LEN + 1];
546 err_mask = ata_do_dev_read_id(adev, tf, id);
547 if (err_mask)
548 return err_mask;
549 ata_id_c_string(id, model_num, ATA_ID_PROD, sizeof(model_num));
551 id[83] &= ~(1 << 12); /* Cache flush is firmware handled */
552 id[83] &= ~(1 << 13); /* Ditto for LBA48 flushes */
553 id[84] &= ~(1 << 6); /* No FUA */
554 id[85] &= ~(1 << 10); /* No HPA */
555 id[76] = 0; /* No NCQ/AN etc */
557 if (strstr(model_num, "Integrated Technology Express")) {
558 /* Set feature bits the firmware neglects */
559 id[49] |= 0x0300; /* LBA, DMA */
560 id[82] |= 0x0400; /* LBA48 */
561 id[83] &= 0x7FFF;
562 id[83] |= 0x4000; /* Word 83 is valid */
563 id[86] |= 0x0400; /* LBA48 on */
564 id[ATA_ID_MAJOR_VER] |= 0x1F;
566 return err_mask;
570 * it821x_check_atapi_dma - ATAPI DMA handler
571 * @qc: Command we are about to issue
573 * Decide if this ATAPI command can be issued by DMA on this
574 * controller. Return 0 if it can be.
577 static int it821x_check_atapi_dma(struct ata_queued_cmd *qc)
579 struct ata_port *ap = qc->ap;
580 struct it821x_dev *itdev = ap->private_data;
582 /* Only use dma for transfers to/from the media. */
583 if (ata_qc_raw_nbytes(qc) < 2048)
584 return -EOPNOTSUPP;
586 /* No ATAPI DMA in smart mode */
587 if (itdev->smart)
588 return -EOPNOTSUPP;
589 /* No ATAPI DMA on rev 10 */
590 if (itdev->timing10)
591 return -EOPNOTSUPP;
592 /* Cool */
593 return 0;
597 * it821x_display_disk - display disk setup
598 * @n: Device number
599 * @buf: Buffer block from firmware
601 * Produce a nice informative display of the device setup as provided
602 * by the firmware.
605 static void it821x_display_disk(int n, u8 *buf)
607 unsigned char id[41];
608 int mode = 0;
609 char *mtype = "";
610 char mbuf[8];
611 char *cbl = "(40 wire cable)";
613 static const char *types[5] = {
614 "RAID0", "RAID1" "RAID 0+1", "JBOD", "DISK"
617 if (buf[52] > 4) /* No Disk */
618 return;
620 ata_id_c_string((u16 *)buf, id, 0, 41);
622 if (buf[51]) {
623 mode = ffs(buf[51]);
624 mtype = "UDMA";
625 } else if (buf[49]) {
626 mode = ffs(buf[49]);
627 mtype = "MWDMA";
630 if (buf[76])
631 cbl = "";
633 if (mode)
634 snprintf(mbuf, 8, "%5s%d", mtype, mode - 1);
635 else
636 strcpy(mbuf, "PIO");
637 if (buf[52] == 4)
638 printk(KERN_INFO "%d: %-6s %-8s %s %s\n",
639 n, mbuf, types[buf[52]], id, cbl);
640 else
641 printk(KERN_INFO "%d: %-6s %-8s Volume: %1d %s %s\n",
642 n, mbuf, types[buf[52]], buf[53], id, cbl);
643 if (buf[125] < 100)
644 printk(KERN_INFO "%d: Rebuilding: %d%%\n", n, buf[125]);
648 * it821x_firmware_command - issue firmware command
649 * @ap: IT821x port to interrogate
650 * @cmd: command
651 * @len: length
653 * Issue firmware commands expecting data back from the controller. We
654 * use this to issue commands that do not go via the normal paths. Other
655 * commands such as 0xFC can be issued normally.
658 static u8 *it821x_firmware_command(struct ata_port *ap, u8 cmd, int len)
660 u8 status;
661 int n = 0;
662 u16 *buf = kmalloc(len, GFP_KERNEL);
663 if (buf == NULL) {
664 printk(KERN_ERR "it821x_firmware_command: Out of memory\n");
665 return NULL;
667 /* This isn't quite a normal ATA command as we are talking to the
668 firmware not the drives */
669 ap->ctl |= ATA_NIEN;
670 iowrite8(ap->ctl, ap->ioaddr.ctl_addr);
671 ata_wait_idle(ap);
672 iowrite8(ATA_DEVICE_OBS, ap->ioaddr.device_addr);
673 iowrite8(cmd, ap->ioaddr.command_addr);
674 udelay(1);
675 /* This should be almost immediate but a little paranoia goes a long
676 way. */
677 while(n++ < 10) {
678 status = ioread8(ap->ioaddr.status_addr);
679 if (status & ATA_ERR) {
680 kfree(buf);
681 printk(KERN_ERR "it821x_firmware_command: rejected\n");
682 return NULL;
684 if (status & ATA_DRQ) {
685 ioread16_rep(ap->ioaddr.data_addr, buf, len/2);
686 return (u8 *)buf;
688 mdelay(1);
690 kfree(buf);
691 printk(KERN_ERR "it821x_firmware_command: timeout\n");
692 return NULL;
696 * it821x_probe_firmware - firmware reporting/setup
697 * @ap: IT821x port being probed
699 * Probe the firmware of the controller by issuing firmware command
700 * 0xFA and analysing the returned data.
703 static void it821x_probe_firmware(struct ata_port *ap)
705 u8 *buf;
706 int i;
708 /* This is a bit ugly as we can't just issue a task file to a device
709 as this is controller magic */
711 buf = it821x_firmware_command(ap, 0xFA, 512);
713 if (buf != NULL) {
714 printk(KERN_INFO "pata_it821x: Firmware %02X/%02X/%02X%02X\n",
715 buf[505],
716 buf[506],
717 buf[507],
718 buf[508]);
719 for (i = 0; i < 4; i++)
720 it821x_display_disk(i, buf + 128 * i);
721 kfree(buf);
728 * it821x_port_start - port setup
729 * @ap: ATA port being set up
731 * The it821x needs to maintain private data structures and also to
732 * use the standard PCI interface which lacks support for this
733 * functionality. We instead set up the private data on the port
734 * start hook, and tear it down on port stop
737 static int it821x_port_start(struct ata_port *ap)
739 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
740 struct it821x_dev *itdev;
741 u8 conf;
743 int ret = ata_sff_port_start(ap);
744 if (ret < 0)
745 return ret;
747 itdev = devm_kzalloc(&pdev->dev, sizeof(struct it821x_dev), GFP_KERNEL);
748 if (itdev == NULL)
749 return -ENOMEM;
750 ap->private_data = itdev;
752 pci_read_config_byte(pdev, 0x50, &conf);
754 if (conf & 1) {
755 itdev->smart = 1;
756 /* Long I/O's although allowed in LBA48 space cause the
757 onboard firmware to enter the twighlight zone */
758 /* No ATAPI DMA in this mode either */
759 if (ap->port_no == 0)
760 it821x_probe_firmware(ap);
762 /* Pull the current clocks from 0x50 */
763 if (conf & (1 << (1 + ap->port_no)))
764 itdev->clock_mode = ATA_50;
765 else
766 itdev->clock_mode = ATA_66;
768 itdev->want[0][1] = ATA_ANY;
769 itdev->want[1][1] = ATA_ANY;
770 itdev->last_device = -1;
772 if (pdev->revision == 0x10) {
773 itdev->timing10 = 1;
774 /* Need to disable ATAPI DMA for this case */
775 if (!itdev->smart)
776 printk(KERN_WARNING DRV_NAME": Revision 0x10, workarounds activated.\n");
779 return 0;
783 * it821x_rdc_cable - Cable detect for RDC1010
784 * @ap: port we are checking
786 * Return the RDC1010 cable type. Unlike the IT821x we know how to do
787 * this and can do host side cable detect
790 static int it821x_rdc_cable(struct ata_port *ap)
792 u16 r40;
793 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
795 pci_read_config_word(pdev, 0x40, &r40);
796 if (r40 & (1 << (2 + ap->port_no)))
797 return ATA_CBL_PATA40;
798 return ATA_CBL_PATA80;
801 static struct scsi_host_template it821x_sht = {
802 ATA_BMDMA_SHT(DRV_NAME),
805 static struct ata_port_operations it821x_smart_port_ops = {
806 .inherits = &ata_bmdma_port_ops,
808 .check_atapi_dma= it821x_check_atapi_dma,
809 .qc_issue = it821x_smart_qc_issue,
811 .cable_detect = ata_cable_80wire,
812 .set_mode = it821x_smart_set_mode,
813 .dev_config = it821x_dev_config,
814 .read_id = it821x_read_id,
816 .port_start = it821x_port_start,
819 static struct ata_port_operations it821x_passthru_port_ops = {
820 .inherits = &ata_bmdma_port_ops,
822 .check_atapi_dma= it821x_check_atapi_dma,
823 .sff_dev_select = it821x_passthru_dev_select,
824 .bmdma_start = it821x_passthru_bmdma_start,
825 .bmdma_stop = it821x_passthru_bmdma_stop,
826 .qc_issue = it821x_passthru_qc_issue,
828 .cable_detect = ata_cable_unknown,
829 .set_piomode = it821x_passthru_set_piomode,
830 .set_dmamode = it821x_passthru_set_dmamode,
832 .port_start = it821x_port_start,
835 static struct ata_port_operations it821x_rdc_port_ops = {
836 .inherits = &ata_bmdma_port_ops,
838 .check_atapi_dma= it821x_check_atapi_dma,
839 .sff_dev_select = it821x_passthru_dev_select,
840 .bmdma_start = it821x_passthru_bmdma_start,
841 .bmdma_stop = it821x_passthru_bmdma_stop,
842 .qc_issue = it821x_passthru_qc_issue,
844 .cable_detect = it821x_rdc_cable,
845 .set_piomode = it821x_passthru_set_piomode,
846 .set_dmamode = it821x_passthru_set_dmamode,
848 .port_start = it821x_port_start,
851 static void it821x_disable_raid(struct pci_dev *pdev)
853 /* Neither the RDC nor the IT8211 */
854 if (pdev->vendor != PCI_VENDOR_ID_ITE ||
855 pdev->device != PCI_DEVICE_ID_ITE_8212)
856 return;
858 /* Reset local CPU, and set BIOS not ready */
859 pci_write_config_byte(pdev, 0x5E, 0x01);
861 /* Set to bypass mode, and reset PCI bus */
862 pci_write_config_byte(pdev, 0x50, 0x00);
863 pci_write_config_word(pdev, PCI_COMMAND,
864 PCI_COMMAND_PARITY | PCI_COMMAND_IO |
865 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
866 pci_write_config_word(pdev, 0x40, 0xA0F3);
868 pci_write_config_dword(pdev,0x4C, 0x02040204);
869 pci_write_config_byte(pdev, 0x42, 0x36);
870 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20);
874 static int it821x_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
876 u8 conf;
878 static const struct ata_port_info info_smart = {
879 .flags = ATA_FLAG_SLAVE_POSS,
880 .pio_mask = 0x1f,
881 .mwdma_mask = 0x07,
882 .udma_mask = ATA_UDMA6,
883 .port_ops = &it821x_smart_port_ops
885 static const struct ata_port_info info_passthru = {
886 .flags = ATA_FLAG_SLAVE_POSS,
887 .pio_mask = 0x1f,
888 .mwdma_mask = 0x07,
889 .udma_mask = ATA_UDMA6,
890 .port_ops = &it821x_passthru_port_ops
892 static const struct ata_port_info info_rdc = {
893 .flags = ATA_FLAG_SLAVE_POSS,
894 .pio_mask = 0x1f,
895 .mwdma_mask = 0x07,
896 /* No UDMA */
897 .port_ops = &it821x_rdc_port_ops
900 const struct ata_port_info *ppi[] = { NULL, NULL };
901 static char *mode[2] = { "pass through", "smart" };
902 int rc;
904 rc = pcim_enable_device(pdev);
905 if (rc)
906 return rc;
908 if (pdev->vendor == PCI_VENDOR_ID_RDC) {
909 ppi[0] = &info_rdc;
910 } else {
911 /* Force the card into bypass mode if so requested */
912 if (it8212_noraid) {
913 printk(KERN_INFO DRV_NAME ": forcing bypass mode.\n");
914 it821x_disable_raid(pdev);
916 pci_read_config_byte(pdev, 0x50, &conf);
917 conf &= 1;
919 printk(KERN_INFO DRV_NAME": controller in %s mode.\n",
920 mode[conf]);
921 if (conf == 0)
922 ppi[0] = &info_passthru;
923 else
924 ppi[0] = &info_smart;
926 return ata_pci_sff_init_one(pdev, ppi, &it821x_sht, NULL);
929 #ifdef CONFIG_PM
930 static int it821x_reinit_one(struct pci_dev *pdev)
932 struct ata_host *host = dev_get_drvdata(&pdev->dev);
933 int rc;
935 rc = ata_pci_device_do_resume(pdev);
936 if (rc)
937 return rc;
938 /* Resume - turn raid back off if need be */
939 if (it8212_noraid)
940 it821x_disable_raid(pdev);
941 ata_host_resume(host);
942 return rc;
944 #endif
946 static const struct pci_device_id it821x[] = {
947 { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8211), },
948 { PCI_VDEVICE(ITE, PCI_DEVICE_ID_ITE_8212), },
949 { PCI_VDEVICE(RDC, 0x1010), },
951 { },
954 static struct pci_driver it821x_pci_driver = {
955 .name = DRV_NAME,
956 .id_table = it821x,
957 .probe = it821x_init_one,
958 .remove = ata_pci_remove_one,
959 #ifdef CONFIG_PM
960 .suspend = ata_pci_device_suspend,
961 .resume = it821x_reinit_one,
962 #endif
965 static int __init it821x_init(void)
967 return pci_register_driver(&it821x_pci_driver);
970 static void __exit it821x_exit(void)
972 pci_unregister_driver(&it821x_pci_driver);
975 MODULE_AUTHOR("Alan Cox");
976 MODULE_DESCRIPTION("low-level driver for the IT8211/IT8212 IDE RAID controller");
977 MODULE_LICENSE("GPL");
978 MODULE_DEVICE_TABLE(pci, it821x);
979 MODULE_VERSION(DRV_VERSION);
982 module_param_named(noraid, it8212_noraid, int, S_IRUGO);
983 MODULE_PARM_DESC(noraid, "Force card into bypass mode");
985 module_init(it821x_init);
986 module_exit(it821x_exit);