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dm: fix idr leak on module removal
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / firewire / ohci.c
blob8e7a100a4b6d8c2174016abe8787b55f81008fc8
1 /*
2 * Driver for OHCI 1394 controllers
3 *
4 * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software Foundation,
18 * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19 */
20
21 #include <linux/compiler.h>
22 #include <linux/delay.h>
23 #include <linux/device.h>
24 #include <linux/dma-mapping.h>
25 #include <linux/firewire.h>
26 #include <linux/firewire-constants.h>
27 #include <linux/gfp.h>
28 #include <linux/init.h>
29 #include <linux/interrupt.h>
30 #include <linux/io.h>
31 #include <linux/kernel.h>
32 #include <linux/list.h>
33 #include <linux/mm.h>
34 #include <linux/module.h>
35 #include <linux/moduleparam.h>
36 #include <linux/pci.h>
37 #include <linux/pci_ids.h>
38 #include <linux/spinlock.h>
39 #include <linux/string.h>
40
41 #include <asm/atomic.h>
42 #include <asm/byteorder.h>
43 #include <asm/page.h>
44 #include <asm/system.h>
45
46 #ifdef CONFIG_PPC_PMAC
47 #include <asm/pmac_feature.h>
48 #endif
49
50 #include "core.h"
51 #include "ohci.h"
52
53 #define DESCRIPTOR_OUTPUT_MORE 0
54 #define DESCRIPTOR_OUTPUT_LAST (1 << 12)
55 #define DESCRIPTOR_INPUT_MORE (2 << 12)
56 #define DESCRIPTOR_INPUT_LAST (3 << 12)
57 #define DESCRIPTOR_STATUS (1 << 11)
58 #define DESCRIPTOR_KEY_IMMEDIATE (2 << 8)
59 #define DESCRIPTOR_PING (1 << 7)
60 #define DESCRIPTOR_YY (1 << 6)
61 #define DESCRIPTOR_NO_IRQ (0 << 4)
62 #define DESCRIPTOR_IRQ_ERROR (1 << 4)
63 #define DESCRIPTOR_IRQ_ALWAYS (3 << 4)
64 #define DESCRIPTOR_BRANCH_ALWAYS (3 << 2)
65 #define DESCRIPTOR_WAIT (3 << 0)
66
67 struct descriptor {
68 __le16 req_count;
69 __le16 control;
70 __le32 data_address;
71 __le32 branch_address;
72 __le16 res_count;
73 __le16 transfer_status;
74 } __attribute__((aligned(16)));
75
76 struct db_descriptor {
77 __le16 first_size;
78 __le16 control;
79 __le16 second_req_count;
80 __le16 first_req_count;
81 __le32 branch_address;
82 __le16 second_res_count;
83 __le16 first_res_count;
84 __le32 reserved0;
85 __le32 first_buffer;
86 __le32 second_buffer;
87 __le32 reserved1;
88 } __attribute__((aligned(16)));
89
90 #define CONTROL_SET(regs) (regs)
91 #define CONTROL_CLEAR(regs) ((regs) + 4)
92 #define COMMAND_PTR(regs) ((regs) + 12)
93 #define CONTEXT_MATCH(regs) ((regs) + 16)
94
95 struct ar_buffer {
96 struct descriptor descriptor;
97 struct ar_buffer *next;
98 __le32 data[0];
99 };
100
101 struct ar_context {
102 struct fw_ohci *ohci;
103 struct ar_buffer *current_buffer;
104 struct ar_buffer *last_buffer;
105 void *pointer;
106 u32 regs;
107 struct tasklet_struct tasklet;
108 };
109
110 struct context;
111
112 typedef int (*descriptor_callback_t)(struct context *ctx,
113 struct descriptor *d,
114 struct descriptor *last);
115
116 /*
117 * A buffer that contains a block of DMA-able coherent memory used for
118 * storing a portion of a DMA descriptor program.
119 */
120 struct descriptor_buffer {
121 struct list_head list;
122 dma_addr_t buffer_bus;
123 size_t buffer_size;
124 size_t used;
125 struct descriptor buffer[0];
126 };
127
128 struct context {
129 struct fw_ohci *ohci;
130 u32 regs;
131 int total_allocation;
132
133 /*
134 * List of page-sized buffers for storing DMA descriptors.
135 * Head of list contains buffers in use and tail of list contains
136 * free buffers.
137 */
138 struct list_head buffer_list;
139
140 /*
141 * Pointer to a buffer inside buffer_list that contains the tail
142 * end of the current DMA program.
143 */
144 struct descriptor_buffer *buffer_tail;
145
146 /*
147 * The descriptor containing the branch address of the first
148 * descriptor that has not yet been filled by the device.
149 */
150 struct descriptor *last;
151
152 /*
153 * The last descriptor in the DMA program. It contains the branch
154 * address that must be updated upon appending a new descriptor.
155 */
156 struct descriptor *prev;
157
158 descriptor_callback_t callback;
159
160 struct tasklet_struct tasklet;
161 };
162
163 #define IT_HEADER_SY(v) ((v) << 0)
164 #define IT_HEADER_TCODE(v) ((v) << 4)
165 #define IT_HEADER_CHANNEL(v) ((v) << 8)
166 #define IT_HEADER_TAG(v) ((v) << 14)
167 #define IT_HEADER_SPEED(v) ((v) << 16)
168 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
169
170 struct iso_context {
171 struct fw_iso_context base;
172 struct context context;
173 int excess_bytes;
174 void *header;
175 size_t header_length;
176 };
177
178 #define CONFIG_ROM_SIZE 1024
179
180 struct fw_ohci {
181 struct fw_card card;
182
183 __iomem char *registers;
184 dma_addr_t self_id_bus;
185 __le32 *self_id_cpu;
186 struct tasklet_struct bus_reset_tasklet;
187 int node_id;
188 int generation;
189 int request_generation; /* for timestamping incoming requests */
190 atomic_t bus_seconds;
191
192 bool use_dualbuffer;
193 bool old_uninorth;
194 bool bus_reset_packet_quirk;
195
196 /*
197 * Spinlock for accessing fw_ohci data. Never call out of
198 * this driver with this lock held.
199 */
200 spinlock_t lock;
201 u32 self_id_buffer[512];
202
203 /* Config rom buffers */
204 __be32 *config_rom;
205 dma_addr_t config_rom_bus;
206 __be32 *next_config_rom;
207 dma_addr_t next_config_rom_bus;
208 u32 next_header;
209
210 struct ar_context ar_request_ctx;
211 struct ar_context ar_response_ctx;
212 struct context at_request_ctx;
213 struct context at_response_ctx;
214
215 u32 it_context_mask;
216 struct iso_context *it_context_list;
217 u64 ir_context_channels;
218 u32 ir_context_mask;
219 struct iso_context *ir_context_list;
220 };
221
222 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
223 {
224 return container_of(card, struct fw_ohci, card);
225 }
226
227 #define IT_CONTEXT_CYCLE_MATCH_ENABLE 0x80000000
228 #define IR_CONTEXT_BUFFER_FILL 0x80000000
229 #define IR_CONTEXT_ISOCH_HEADER 0x40000000
230 #define IR_CONTEXT_CYCLE_MATCH_ENABLE 0x20000000
231 #define IR_CONTEXT_MULTI_CHANNEL_MODE 0x10000000
232 #define IR_CONTEXT_DUAL_BUFFER_MODE 0x08000000
233
234 #define CONTEXT_RUN 0x8000
235 #define CONTEXT_WAKE 0x1000
236 #define CONTEXT_DEAD 0x0800
237 #define CONTEXT_ACTIVE 0x0400
238
239 #define OHCI1394_MAX_AT_REQ_RETRIES 0xf
240 #define OHCI1394_MAX_AT_RESP_RETRIES 0x2
241 #define OHCI1394_MAX_PHYS_RESP_RETRIES 0x8
242
243 #define OHCI1394_REGISTER_SIZE 0x800
244 #define OHCI_LOOP_COUNT 500
245 #define OHCI1394_PCI_HCI_Control 0x40
246 #define SELF_ID_BUF_SIZE 0x800
247 #define OHCI_TCODE_PHY_PACKET 0x0e
248 #define OHCI_VERSION_1_1 0x010010
249
250 static char ohci_driver_name[] = KBUILD_MODNAME;
251
252 #ifdef CONFIG_FIREWIRE_OHCI_DEBUG
253
254 #define OHCI_PARAM_DEBUG_AT_AR 1
255 #define OHCI_PARAM_DEBUG_SELFIDS 2
256 #define OHCI_PARAM_DEBUG_IRQS 4
257 #define OHCI_PARAM_DEBUG_BUSRESETS 8 /* only effective before chip init */
258
259 static int param_debug;
260 module_param_named(debug, param_debug, int, 0644);
261 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
262 ", AT/AR events = " __stringify(OHCI_PARAM_DEBUG_AT_AR)
263 ", self-IDs = " __stringify(OHCI_PARAM_DEBUG_SELFIDS)
264 ", IRQs = " __stringify(OHCI_PARAM_DEBUG_IRQS)
265 ", busReset events = " __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
266 ", or a combination, or all = -1)");
267
268 static void log_irqs(u32 evt)
269 {
270 if (likely(!(param_debug &
271 (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
272 return;
273
274 if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
275 !(evt & OHCI1394_busReset))
276 return;
277
278 fw_notify("IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
279 evt & OHCI1394_selfIDComplete ? " selfID" : "",
280 evt & OHCI1394_RQPkt ? " AR_req" : "",
281 evt & OHCI1394_RSPkt ? " AR_resp" : "",
282 evt & OHCI1394_reqTxComplete ? " AT_req" : "",
283 evt & OHCI1394_respTxComplete ? " AT_resp" : "",
284 evt & OHCI1394_isochRx ? " IR" : "",
285 evt & OHCI1394_isochTx ? " IT" : "",
286 evt & OHCI1394_postedWriteErr ? " postedWriteErr" : "",
287 evt & OHCI1394_cycleTooLong ? " cycleTooLong" : "",
288 evt & OHCI1394_cycle64Seconds ? " cycle64Seconds" : "",
289 evt & OHCI1394_cycleInconsistent ? " cycleInconsistent" : "",
290 evt & OHCI1394_regAccessFail ? " regAccessFail" : "",
291 evt & OHCI1394_busReset ? " busReset" : "",
292 evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
293 OHCI1394_RSPkt | OHCI1394_reqTxComplete |
294 OHCI1394_respTxComplete | OHCI1394_isochRx |
295 OHCI1394_isochTx | OHCI1394_postedWriteErr |
296 OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
297 OHCI1394_cycleInconsistent |
298 OHCI1394_regAccessFail | OHCI1394_busReset)
299 ? " ?" : "");
300 }
301
302 static const char *speed[] = {
303 [0] = "S100", [1] = "S200", [2] = "S400", [3] = "beta",
304 };
305 static const char *power[] = {
306 [0] = "+0W", [1] = "+15W", [2] = "+30W", [3] = "+45W",
307 [4] = "-3W", [5] = " ?W", [6] = "-3..-6W", [7] = "-3..-10W",
308 };
309 static const char port[] = { '.', '-', 'p', 'c', };
310
311 static char _p(u32 *s, int shift)
312 {
313 return port[*s >> shift & 3];
314 }
315
316 static void log_selfids(int node_id, int generation, int self_id_count, u32 *s)
317 {
318 if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
319 return;
320
321 fw_notify("%d selfIDs, generation %d, local node ID %04x\n",
322 self_id_count, generation, node_id);
323
324 for (; self_id_count--; ++s)
325 if ((*s & 1 << 23) == 0)
326 fw_notify("selfID 0: %08x, phy %d [%c%c%c] "
327 "%s gc=%d %s %s%s%s\n",
328 *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
329 speed[*s >> 14 & 3], *s >> 16 & 63,
330 power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
331 *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
332 else
333 fw_notify("selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
334 *s, *s >> 24 & 63,
335 _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
336 _p(s, 8), _p(s, 6), _p(s, 4), _p(s, 2));
337 }
338
339 static const char *evts[] = {
340 [0x00] = "evt_no_status", [0x01] = "-reserved-",
341 [0x02] = "evt_long_packet", [0x03] = "evt_missing_ack",
342 [0x04] = "evt_underrun", [0x05] = "evt_overrun",
343 [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
344 [0x08] = "evt_data_write", [0x09] = "evt_bus_reset",
345 [0x0a] = "evt_timeout", [0x0b] = "evt_tcode_err",
346 [0x0c] = "-reserved-", [0x0d] = "-reserved-",
347 [0x0e] = "evt_unknown", [0x0f] = "evt_flushed",
348 [0x10] = "-reserved-", [0x11] = "ack_complete",
349 [0x12] = "ack_pending ", [0x13] = "-reserved-",
350 [0x14] = "ack_busy_X", [0x15] = "ack_busy_A",
351 [0x16] = "ack_busy_B", [0x17] = "-reserved-",
352 [0x18] = "-reserved-", [0x19] = "-reserved-",
353 [0x1a] = "-reserved-", [0x1b] = "ack_tardy",
354 [0x1c] = "-reserved-", [0x1d] = "ack_data_error",
355 [0x1e] = "ack_type_error", [0x1f] = "-reserved-",
356 [0x20] = "pending/cancelled",
357 };
358 static const char *tcodes[] = {
359 [0x0] = "QW req", [0x1] = "BW req",
360 [0x2] = "W resp", [0x3] = "-reserved-",
361 [0x4] = "QR req", [0x5] = "BR req",
362 [0x6] = "QR resp", [0x7] = "BR resp",
363 [0x8] = "cycle start", [0x9] = "Lk req",
364 [0xa] = "async stream packet", [0xb] = "Lk resp",
365 [0xc] = "-reserved-", [0xd] = "-reserved-",
366 [0xe] = "link internal", [0xf] = "-reserved-",
367 };
368 static const char *phys[] = {
369 [0x0] = "phy config packet", [0x1] = "link-on packet",
370 [0x2] = "self-id packet", [0x3] = "-reserved-",
371 };
372
373 static void log_ar_at_event(char dir, int speed, u32 *header, int evt)
374 {
375 int tcode = header[0] >> 4 & 0xf;
376 char specific[12];
377
378 if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
379 return;
380
381 if (unlikely(evt >= ARRAY_SIZE(evts)))
382 evt = 0x1f;
383
384 if (evt == OHCI1394_evt_bus_reset) {
385 fw_notify("A%c evt_bus_reset, generation %d\n",
386 dir, (header[2] >> 16) & 0xff);
387 return;
388 }
389
390 if (header[0] == ~header[1]) {
391 fw_notify("A%c %s, %s, %08x\n",
392 dir, evts[evt], phys[header[0] >> 30 & 0x3], header[0]);
393 return;
394 }
395
396 switch (tcode) {
397 case 0x0: case 0x6: case 0x8:
398 snprintf(specific, sizeof(specific), " = %08x",
399 be32_to_cpu((__force __be32)header[3]));
400 break;
401 case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
402 snprintf(specific, sizeof(specific), " %x,%x",
403 header[3] >> 16, header[3] & 0xffff);
404 break;
405 default:
406 specific[0] = '\0';
407 }
408
409 switch (tcode) {
410 case 0xe: case 0xa:
411 fw_notify("A%c %s, %s\n", dir, evts[evt], tcodes[tcode]);
412 break;
413 case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
414 fw_notify("A%c spd %x tl %02x, "
415 "%04x -> %04x, %s, "
416 "%s, %04x%08x%s\n",
417 dir, speed, header[0] >> 10 & 0x3f,
418 header[1] >> 16, header[0] >> 16, evts[evt],
419 tcodes[tcode], header[1] & 0xffff, header[2], specific);
420 break;
421 default:
422 fw_notify("A%c spd %x tl %02x, "
423 "%04x -> %04x, %s, "
424 "%s%s\n",
425 dir, speed, header[0] >> 10 & 0x3f,
426 header[1] >> 16, header[0] >> 16, evts[evt],
427 tcodes[tcode], specific);
428 }
429 }
430
431 #else
432
433 #define log_irqs(evt)
434 #define log_selfids(node_id, generation, self_id_count, sid)
435 #define log_ar_at_event(dir, speed, header, evt)
436
437 #endif /* CONFIG_FIREWIRE_OHCI_DEBUG */
438
439 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
440 {
441 writel(data, ohci->registers + offset);
442 }
443
444 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
445 {
446 return readl(ohci->registers + offset);
447 }
448
449 static inline void flush_writes(const struct fw_ohci *ohci)
450 {
451 /* Do a dummy read to flush writes. */
452 reg_read(ohci, OHCI1394_Version);
453 }
454
455 static int ohci_update_phy_reg(struct fw_card *card, int addr,
456 int clear_bits, int set_bits)
457 {
458 struct fw_ohci *ohci = fw_ohci(card);
459 u32 val, old;
460
461 reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
462 flush_writes(ohci);
463 msleep(2);
464 val = reg_read(ohci, OHCI1394_PhyControl);
465 if ((val & OHCI1394_PhyControl_ReadDone) == 0) {
466 fw_error("failed to set phy reg bits.\n");
467 return -EBUSY;
468 }
469
470 old = OHCI1394_PhyControl_ReadData(val);
471 old = (old & ~clear_bits) | set_bits;
472 reg_write(ohci, OHCI1394_PhyControl,
473 OHCI1394_PhyControl_Write(addr, old));
474
475 return 0;
476 }
477
478 static int ar_context_add_page(struct ar_context *ctx)
479 {
480 struct device *dev = ctx->ohci->card.device;
481 struct ar_buffer *ab;
482 dma_addr_t uninitialized_var(ab_bus);
483 size_t offset;
484
485 ab = dma_alloc_coherent(dev, PAGE_SIZE, &ab_bus, GFP_ATOMIC);
486 if (ab == NULL)
487 return -ENOMEM;
488
489 ab->next = NULL;
490 memset(&ab->descriptor, 0, sizeof(ab->descriptor));
491 ab->descriptor.control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
492 DESCRIPTOR_STATUS |
493 DESCRIPTOR_BRANCH_ALWAYS);
494 offset = offsetof(struct ar_buffer, data);
495 ab->descriptor.req_count = cpu_to_le16(PAGE_SIZE - offset);
496 ab->descriptor.data_address = cpu_to_le32(ab_bus + offset);
497 ab->descriptor.res_count = cpu_to_le16(PAGE_SIZE - offset);
498 ab->descriptor.branch_address = 0;
499
500 ctx->last_buffer->descriptor.branch_address = cpu_to_le32(ab_bus | 1);
501 ctx->last_buffer->next = ab;
502 ctx->last_buffer = ab;
503
504 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
505 flush_writes(ctx->ohci);
506
507 return 0;
508 }
509
510 static void ar_context_release(struct ar_context *ctx)
511 {
512 struct ar_buffer *ab, *ab_next;
513 size_t offset;
514 dma_addr_t ab_bus;
515
516 for (ab = ctx->current_buffer; ab; ab = ab_next) {
517 ab_next = ab->next;
518 offset = offsetof(struct ar_buffer, data);
519 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
520 dma_free_coherent(ctx->ohci->card.device, PAGE_SIZE,
521 ab, ab_bus);
522 }
523 }
524
525 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
526 #define cond_le32_to_cpu(v) \
527 (ohci->old_uninorth ? (__force __u32)(v) : le32_to_cpu(v))
528 #else
529 #define cond_le32_to_cpu(v) le32_to_cpu(v)
530 #endif
531
532 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
533 {
534 struct fw_ohci *ohci = ctx->ohci;
535 struct fw_packet p;
536 u32 status, length, tcode;
537 int evt;
538
539 p.header[0] = cond_le32_to_cpu(buffer[0]);
540 p.header[1] = cond_le32_to_cpu(buffer[1]);
541 p.header[2] = cond_le32_to_cpu(buffer[2]);
542
543 tcode = (p.header[0] >> 4) & 0x0f;
544 switch (tcode) {
545 case TCODE_WRITE_QUADLET_REQUEST:
546 case TCODE_READ_QUADLET_RESPONSE:
547 p.header[3] = (__force __u32) buffer[3];
548 p.header_length = 16;
549 p.payload_length = 0;
550 break;
551
552 case TCODE_READ_BLOCK_REQUEST :
553 p.header[3] = cond_le32_to_cpu(buffer[3]);
554 p.header_length = 16;
555 p.payload_length = 0;
556 break;
557
558 case TCODE_WRITE_BLOCK_REQUEST:
559 case TCODE_READ_BLOCK_RESPONSE:
560 case TCODE_LOCK_REQUEST:
561 case TCODE_LOCK_RESPONSE:
562 p.header[3] = cond_le32_to_cpu(buffer[3]);
563 p.header_length = 16;
564 p.payload_length = p.header[3] >> 16;
565 break;
566
567 case TCODE_WRITE_RESPONSE:
568 case TCODE_READ_QUADLET_REQUEST:
569 case OHCI_TCODE_PHY_PACKET:
570 p.header_length = 12;
571 p.payload_length = 0;
572 break;
573
574 default:
575 /* FIXME: Stop context, discard everything, and restart? */
576 p.header_length = 0;
577 p.payload_length = 0;
578 }
579
580 p.payload = (void *) buffer + p.header_length;
581
582 /* FIXME: What to do about evt_* errors? */
583 length = (p.header_length + p.payload_length + 3) / 4;
584 status = cond_le32_to_cpu(buffer[length]);
585 evt = (status >> 16) & 0x1f;
586
587 p.ack = evt - 16;
588 p.speed = (status >> 21) & 0x7;
589 p.timestamp = status & 0xffff;
590 p.generation = ohci->request_generation;
591
592 log_ar_at_event('R', p.speed, p.header, evt);
593
594 /*
595 * The OHCI bus reset handler synthesizes a phy packet with
596 * the new generation number when a bus reset happens (see
597 * section 8.4.2.3). This helps us determine when a request
598 * was received and make sure we send the response in the same
599 * generation. We only need this for requests; for responses
600 * we use the unique tlabel for finding the matching
601 * request.
602 *
603 * Alas some chips sometimes emit bus reset packets with a
604 * wrong generation. We set the correct generation for these
605 * at a slightly incorrect time (in bus_reset_tasklet).
606 */
607 if (evt == OHCI1394_evt_bus_reset) {
608 if (!ohci->bus_reset_packet_quirk)
609 ohci->request_generation = (p.header[2] >> 16) & 0xff;
610 } else if (ctx == &ohci->ar_request_ctx) {
611 fw_core_handle_request(&ohci->card, &p);
612 } else {
613 fw_core_handle_response(&ohci->card, &p);
614 }
615
616 return buffer + length + 1;
617 }
618
619 static void ar_context_tasklet(unsigned long data)
620 {
621 struct ar_context *ctx = (struct ar_context *)data;
622 struct fw_ohci *ohci = ctx->ohci;
623 struct ar_buffer *ab;
624 struct descriptor *d;
625 void *buffer, *end;
626
627 ab = ctx->current_buffer;
628 d = &ab->descriptor;
629
630 if (d->res_count == 0) {
631 size_t size, size2, rest, pktsize, size3, offset;
632 dma_addr_t start_bus;
633 void *start;
634
635 /*
636 * This descriptor is finished and we may have a
637 * packet split across this and the next buffer. We
638 * reuse the page for reassembling the split packet.
639 */
640
641 offset = offsetof(struct ar_buffer, data);
642 start = ab;
643 start_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
644 buffer = ab->data;
645
646 ab = ab->next;
647 d = &ab->descriptor;
648 size = start + PAGE_SIZE - ctx->pointer;
649 /* valid buffer data in the next page */
650 rest = le16_to_cpu(d->req_count) - le16_to_cpu(d->res_count);
651 /* what actually fits in this page */
652 size2 = min(rest, (size_t)PAGE_SIZE - offset - size);
653 memmove(buffer, ctx->pointer, size);
654 memcpy(buffer + size, ab->data, size2);
655
656 while (size > 0) {
657 void *next = handle_ar_packet(ctx, buffer);
658 pktsize = next - buffer;
659 if (pktsize >= size) {
660 /*
661 * We have handled all the data that was
662 * originally in this page, so we can now
663 * continue in the next page.
664 */
665 buffer = next;
666 break;
667 }
668 /* move the next packet to the start of the buffer */
669 memmove(buffer, next, size + size2 - pktsize);
670 size -= pktsize;
671 /* fill up this page again */
672 size3 = min(rest - size2,
673 (size_t)PAGE_SIZE - offset - size - size2);
674 memcpy(buffer + size + size2,
675 (void *) ab->data + size2, size3);
676 size2 += size3;
677 }
678
679 if (rest > 0) {
680 /* handle the packets that are fully in the next page */
681 buffer = (void *) ab->data +
682 (buffer - (start + offset + size));
683 end = (void *) ab->data + rest;
684
685 while (buffer < end)
686 buffer = handle_ar_packet(ctx, buffer);
687
688 ctx->current_buffer = ab;
689 ctx->pointer = end;
690
691 dma_free_coherent(ohci->card.device, PAGE_SIZE,
692 start, start_bus);
693 ar_context_add_page(ctx);
694 } else {
695 ctx->pointer = start + PAGE_SIZE;
696 }
697 } else {
698 buffer = ctx->pointer;
699 ctx->pointer = end =
700 (void *) ab + PAGE_SIZE - le16_to_cpu(d->res_count);
701
702 while (buffer < end)
703 buffer = handle_ar_packet(ctx, buffer);
704 }
705 }
706
707 static int ar_context_init(struct ar_context *ctx,
708 struct fw_ohci *ohci, u32 regs)
709 {
710 struct ar_buffer ab;
711
712 ctx->regs = regs;
713 ctx->ohci = ohci;
714 ctx->last_buffer = &ab;
715 tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
716
717 ar_context_add_page(ctx);
718 ar_context_add_page(ctx);
719 ctx->current_buffer = ab.next;
720 ctx->pointer = ctx->current_buffer->data;
721
722 return 0;
723 }
724
725 static void ar_context_run(struct ar_context *ctx)
726 {
727 struct ar_buffer *ab = ctx->current_buffer;
728 dma_addr_t ab_bus;
729 size_t offset;
730
731 offset = offsetof(struct ar_buffer, data);
732 ab_bus = le32_to_cpu(ab->descriptor.data_address) - offset;
733
734 reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ab_bus | 1);
735 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
736 flush_writes(ctx->ohci);
737 }
738
739 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
740 {
741 int b, key;
742
743 b = (le16_to_cpu(d->control) & DESCRIPTOR_BRANCH_ALWAYS) >> 2;
744 key = (le16_to_cpu(d->control) & DESCRIPTOR_KEY_IMMEDIATE) >> 8;
745
746 /* figure out which descriptor the branch address goes in */
747 if (z == 2 && (b == 3 || key == 2))
748 return d;
749 else
750 return d + z - 1;
751 }
752
753 static void context_tasklet(unsigned long data)
754 {
755 struct context *ctx = (struct context *) data;
756 struct descriptor *d, *last;
757 u32 address;
758 int z;
759 struct descriptor_buffer *desc;
760
761 desc = list_entry(ctx->buffer_list.next,
762 struct descriptor_buffer, list);
763 last = ctx->last;
764 while (last->branch_address != 0) {
765 struct descriptor_buffer *old_desc = desc;
766 address = le32_to_cpu(last->branch_address);
767 z = address & 0xf;
768 address &= ~0xf;
769
770 /* If the branch address points to a buffer outside of the
771 * current buffer, advance to the next buffer. */
772 if (address < desc->buffer_bus ||
773 address >= desc->buffer_bus + desc->used)
774 desc = list_entry(desc->list.next,
775 struct descriptor_buffer, list);
776 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
777 last = find_branch_descriptor(d, z);
778
779 if (!ctx->callback(ctx, d, last))
780 break;
781
782 if (old_desc != desc) {
783 /* If we've advanced to the next buffer, move the
784 * previous buffer to the free list. */
785 unsigned long flags;
786 old_desc->used = 0;
787 spin_lock_irqsave(&ctx->ohci->lock, flags);
788 list_move_tail(&old_desc->list, &ctx->buffer_list);
789 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
790 }
791 ctx->last = last;
792 }
793 }
794
795 /*
796 * Allocate a new buffer and add it to the list of free buffers for this
797 * context. Must be called with ohci->lock held.
798 */
799 static int context_add_buffer(struct context *ctx)
800 {
801 struct descriptor_buffer *desc;
802 dma_addr_t uninitialized_var(bus_addr);
803 int offset;
804
805 /*
806 * 16MB of descriptors should be far more than enough for any DMA
807 * program. This will catch run-away userspace or DoS attacks.
808 */
809 if (ctx->total_allocation >= 16*1024*1024)
810 return -ENOMEM;
811
812 desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
813 &bus_addr, GFP_ATOMIC);
814 if (!desc)
815 return -ENOMEM;
816
817 offset = (void *)&desc->buffer - (void *)desc;
818 desc->buffer_size = PAGE_SIZE - offset;
819 desc->buffer_bus = bus_addr + offset;
820 desc->used = 0;
821
822 list_add_tail(&desc->list, &ctx->buffer_list);
823 ctx->total_allocation += PAGE_SIZE;
824
825 return 0;
826 }
827
828 static int context_init(struct context *ctx, struct fw_ohci *ohci,
829 u32 regs, descriptor_callback_t callback)
830 {
831 ctx->ohci = ohci;
832 ctx->regs = regs;
833 ctx->total_allocation = 0;
834
835 INIT_LIST_HEAD(&ctx->buffer_list);
836 if (context_add_buffer(ctx) < 0)
837 return -ENOMEM;
838
839 ctx->buffer_tail = list_entry(ctx->buffer_list.next,
840 struct descriptor_buffer, list);
841
842 tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
843 ctx->callback = callback;
844
845 /*
846 * We put a dummy descriptor in the buffer that has a NULL
847 * branch address and looks like it's been sent. That way we
848 * have a descriptor to append DMA programs to.
849 */
850 memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
851 ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
852 ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
853 ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
854 ctx->last = ctx->buffer_tail->buffer;
855 ctx->prev = ctx->buffer_tail->buffer;
856
857 return 0;
858 }
859
860 static void context_release(struct context *ctx)
861 {
862 struct fw_card *card = &ctx->ohci->card;
863 struct descriptor_buffer *desc, *tmp;
864
865 list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
866 dma_free_coherent(card->device, PAGE_SIZE, desc,
867 desc->buffer_bus -
868 ((void *)&desc->buffer - (void *)desc));
869 }
870
871 /* Must be called with ohci->lock held */
872 static struct descriptor *context_get_descriptors(struct context *ctx,
873 int z, dma_addr_t *d_bus)
874 {
875 struct descriptor *d = NULL;
876 struct descriptor_buffer *desc = ctx->buffer_tail;
877
878 if (z * sizeof(*d) > desc->buffer_size)
879 return NULL;
880
881 if (z * sizeof(*d) > desc->buffer_size - desc->used) {
882 /* No room for the descriptor in this buffer, so advance to the
883 * next one. */
884
885 if (desc->list.next == &ctx->buffer_list) {
886 /* If there is no free buffer next in the list,
887 * allocate one. */
888 if (context_add_buffer(ctx) < 0)
889 return NULL;
890 }
891 desc = list_entry(desc->list.next,
892 struct descriptor_buffer, list);
893 ctx->buffer_tail = desc;
894 }
895
896 d = desc->buffer + desc->used / sizeof(*d);
897 memset(d, 0, z * sizeof(*d));
898 *d_bus = desc->buffer_bus + desc->used;
899
900 return d;
901 }
902
903 static void context_run(struct context *ctx, u32 extra)
904 {
905 struct fw_ohci *ohci = ctx->ohci;
906
907 reg_write(ohci, COMMAND_PTR(ctx->regs),
908 le32_to_cpu(ctx->last->branch_address));
909 reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
910 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
911 flush_writes(ohci);
912 }
913
914 static void context_append(struct context *ctx,
915 struct descriptor *d, int z, int extra)
916 {
917 dma_addr_t d_bus;
918 struct descriptor_buffer *desc = ctx->buffer_tail;
919
920 d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
921
922 desc->used += (z + extra) * sizeof(*d);
923 ctx->prev->branch_address = cpu_to_le32(d_bus | z);
924 ctx->prev = find_branch_descriptor(d, z);
925
926 reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
927 flush_writes(ctx->ohci);
928 }
929
930 static void context_stop(struct context *ctx)
931 {
932 u32 reg;
933 int i;
934
935 reg_write(ctx->ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
936 flush_writes(ctx->ohci);
937
938 for (i = 0; i < 10; i++) {
939 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
940 if ((reg & CONTEXT_ACTIVE) == 0)
941 return;
942
943 mdelay(1);
944 }
945 fw_error("Error: DMA context still active (0x%08x)\n", reg);
946 }
947
948 struct driver_data {
949 struct fw_packet *packet;
950 };
951
952 /*
953 * This function apppends a packet to the DMA queue for transmission.
954 * Must always be called with the ochi->lock held to ensure proper
955 * generation handling and locking around packet queue manipulation.
956 */
957 static int at_context_queue_packet(struct context *ctx,
958 struct fw_packet *packet)
959 {
960 struct fw_ohci *ohci = ctx->ohci;
961 dma_addr_t d_bus, uninitialized_var(payload_bus);
962 struct driver_data *driver_data;
963 struct descriptor *d, *last;
964 __le32 *header;
965 int z, tcode;
966 u32 reg;
967
968 d = context_get_descriptors(ctx, 4, &d_bus);
969 if (d == NULL) {
970 packet->ack = RCODE_SEND_ERROR;
971 return -1;
972 }
973
974 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
975 d[0].res_count = cpu_to_le16(packet->timestamp);
976
977 /*
978 * The DMA format for asyncronous link packets is different
979 * from the IEEE1394 layout, so shift the fields around
980 * accordingly. If header_length is 8, it's a PHY packet, to
981 * which we need to prepend an extra quadlet.
982 */
983
984 header = (__le32 *) &d[1];
985 switch (packet->header_length) {
986 case 16:
987 case 12:
988 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
989 (packet->speed << 16));
990 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
991 (packet->header[0] & 0xffff0000));
992 header[2] = cpu_to_le32(packet->header[2]);
993
994 tcode = (packet->header[0] >> 4) & 0x0f;
995 if (TCODE_IS_BLOCK_PACKET(tcode))
996 header[3] = cpu_to_le32(packet->header[3]);
997 else
998 header[3] = (__force __le32) packet->header[3];
999
1000 d[0].req_count = cpu_to_le16(packet->header_length);
1001 break;
1002
1003 case 8:
1004 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1005 (packet->speed << 16));
1006 header[1] = cpu_to_le32(packet->header[0]);
1007 header[2] = cpu_to_le32(packet->header[1]);
1008 d[0].req_count = cpu_to_le16(12);
1009 break;
1010
1011 case 4:
1012 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1013 (packet->speed << 16));
1014 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1015 d[0].req_count = cpu_to_le16(8);
1016 break;
1017
1018 default:
1019 /* BUG(); */
1020 packet->ack = RCODE_SEND_ERROR;
1021 return -1;
1022 }
1023
1024 driver_data = (struct driver_data *) &d[3];
1025 driver_data->packet = packet;
1026 packet->driver_data = driver_data;
1027
1028 if (packet->payload_length > 0) {
1029 payload_bus =
1030 dma_map_single(ohci->card.device, packet->payload,
1031 packet->payload_length, DMA_TO_DEVICE);
1032 if (dma_mapping_error(ohci->card.device, payload_bus)) {
1033 packet->ack = RCODE_SEND_ERROR;
1034 return -1;
1035 }
1036 packet->payload_bus = payload_bus;
1037
1038 d[2].req_count = cpu_to_le16(packet->payload_length);
1039 d[2].data_address = cpu_to_le32(payload_bus);
1040 last = &d[2];
1041 z = 3;
1042 } else {
1043 last = &d[0];
1044 z = 2;
1045 }
1046
1047 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1048 DESCRIPTOR_IRQ_ALWAYS |
1049 DESCRIPTOR_BRANCH_ALWAYS);
1050
1051 /*
1052 * If the controller and packet generations don't match, we need to
1053 * bail out and try again. If IntEvent.busReset is set, the AT context
1054 * is halted, so appending to the context and trying to run it is
1055 * futile. Most controllers do the right thing and just flush the AT
1056 * queue (per section 7.2.3.2 of the OHCI 1.1 specification), but
1057 * some controllers (like a JMicron JMB381 PCI-e) misbehave and wind
1058 * up stalling out. So we just bail out in software and try again
1059 * later, and everyone is happy.
1060 * FIXME: Document how the locking works.
1061 */
1062 if (ohci->generation != packet->generation ||
1063 reg_read(ohci, OHCI1394_IntEventSet) & OHCI1394_busReset) {
1064 if (packet->payload_length > 0)
1065 dma_unmap_single(ohci->card.device, payload_bus,
1066 packet->payload_length, DMA_TO_DEVICE);
1067 packet->ack = RCODE_GENERATION;
1068 return -1;
1069 }
1070
1071 context_append(ctx, d, z, 4 - z);
1072
1073 /* If the context isn't already running, start it up. */
1074 reg = reg_read(ctx->ohci, CONTROL_SET(ctx->regs));
1075 if ((reg & CONTEXT_RUN) == 0)
1076 context_run(ctx, 0);
1077
1078 return 0;
1079 }
1080
1081 static int handle_at_packet(struct context *context,
1082 struct descriptor *d,
1083 struct descriptor *last)
1084 {
1085 struct driver_data *driver_data;
1086 struct fw_packet *packet;
1087 struct fw_ohci *ohci = context->ohci;
1088 int evt;
1089
1090 if (last->transfer_status == 0)
1091 /* This descriptor isn't done yet, stop iteration. */
1092 return 0;
1093
1094 driver_data = (struct driver_data *) &d[3];
1095 packet = driver_data->packet;
1096 if (packet == NULL)
1097 /* This packet was cancelled, just continue. */
1098 return 1;
1099
1100 if (packet->payload_bus)
1101 dma_unmap_single(ohci->card.device, packet->payload_bus,
1102 packet->payload_length, DMA_TO_DEVICE);
1103
1104 evt = le16_to_cpu(last->transfer_status) & 0x1f;
1105 packet->timestamp = le16_to_cpu(last->res_count);
1106
1107 log_ar_at_event('T', packet->speed, packet->header, evt);
1108
1109 switch (evt) {
1110 case OHCI1394_evt_timeout:
1111 /* Async response transmit timed out. */
1112 packet->ack = RCODE_CANCELLED;
1113 break;
1114
1115 case OHCI1394_evt_flushed:
1116 /*
1117 * The packet was flushed should give same error as
1118 * when we try to use a stale generation count.
1119 */
1120 packet->ack = RCODE_GENERATION;
1121 break;
1122
1123 case OHCI1394_evt_missing_ack:
1124 /*
1125 * Using a valid (current) generation count, but the
1126 * node is not on the bus or not sending acks.
1127 */
1128 packet->ack = RCODE_NO_ACK;
1129 break;
1130
1131 case ACK_COMPLETE + 0x10:
1132 case ACK_PENDING + 0x10:
1133 case ACK_BUSY_X + 0x10:
1134 case ACK_BUSY_A + 0x10:
1135 case ACK_BUSY_B + 0x10:
1136 case ACK_DATA_ERROR + 0x10:
1137 case ACK_TYPE_ERROR + 0x10:
1138 packet->ack = evt - 0x10;
1139 break;
1140
1141 default:
1142 packet->ack = RCODE_SEND_ERROR;
1143 break;
1144 }
1145
1146 packet->callback(packet, &ohci->card, packet->ack);
1147
1148 return 1;
1149 }
1150
1151 #define HEADER_GET_DESTINATION(q) (((q) >> 16) & 0xffff)
1152 #define HEADER_GET_TCODE(q) (((q) >> 4) & 0x0f)
1153 #define HEADER_GET_OFFSET_HIGH(q) (((q) >> 0) & 0xffff)
1154 #define HEADER_GET_DATA_LENGTH(q) (((q) >> 16) & 0xffff)
1155 #define HEADER_GET_EXTENDED_TCODE(q) (((q) >> 0) & 0xffff)
1156
1157 static void handle_local_rom(struct fw_ohci *ohci,
1158 struct fw_packet *packet, u32 csr)
1159 {
1160 struct fw_packet response;
1161 int tcode, length, i;
1162
1163 tcode = HEADER_GET_TCODE(packet->header[0]);
1164 if (TCODE_IS_BLOCK_PACKET(tcode))
1165 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1166 else
1167 length = 4;
1168
1169 i = csr - CSR_CONFIG_ROM;
1170 if (i + length > CONFIG_ROM_SIZE) {
1171 fw_fill_response(&response, packet->header,
1172 RCODE_ADDRESS_ERROR, NULL, 0);
1173 } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1174 fw_fill_response(&response, packet->header,
1175 RCODE_TYPE_ERROR, NULL, 0);
1176 } else {
1177 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1178 (void *) ohci->config_rom + i, length);
1179 }
1180
1181 fw_core_handle_response(&ohci->card, &response);
1182 }
1183
1184 static void handle_local_lock(struct fw_ohci *ohci,
1185 struct fw_packet *packet, u32 csr)
1186 {
1187 struct fw_packet response;
1188 int tcode, length, ext_tcode, sel;
1189 __be32 *payload, lock_old;
1190 u32 lock_arg, lock_data;
1191
1192 tcode = HEADER_GET_TCODE(packet->header[0]);
1193 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1194 payload = packet->payload;
1195 ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1196
1197 if (tcode == TCODE_LOCK_REQUEST &&
1198 ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1199 lock_arg = be32_to_cpu(payload[0]);
1200 lock_data = be32_to_cpu(payload[1]);
1201 } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1202 lock_arg = 0;
1203 lock_data = 0;
1204 } else {
1205 fw_fill_response(&response, packet->header,
1206 RCODE_TYPE_ERROR, NULL, 0);
1207 goto out;
1208 }
1209
1210 sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1211 reg_write(ohci, OHCI1394_CSRData, lock_data);
1212 reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1213 reg_write(ohci, OHCI1394_CSRControl, sel);
1214
1215 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000)
1216 lock_old = cpu_to_be32(reg_read(ohci, OHCI1394_CSRData));
1217 else
1218 fw_notify("swap not done yet\n");
1219
1220 fw_fill_response(&response, packet->header,
1221 RCODE_COMPLETE, &lock_old, sizeof(lock_old));
1222 out:
1223 fw_core_handle_response(&ohci->card, &response);
1224 }
1225
1226 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1227 {
1228 u64 offset;
1229 u32 csr;
1230
1231 if (ctx == &ctx->ohci->at_request_ctx) {
1232 packet->ack = ACK_PENDING;
1233 packet->callback(packet, &ctx->ohci->card, packet->ack);
1234 }
1235
1236 offset =
1237 ((unsigned long long)
1238 HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1239 packet->header[2];
1240 csr = offset - CSR_REGISTER_BASE;
1241
1242 /* Handle config rom reads. */
1243 if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1244 handle_local_rom(ctx->ohci, packet, csr);
1245 else switch (csr) {
1246 case CSR_BUS_MANAGER_ID:
1247 case CSR_BANDWIDTH_AVAILABLE:
1248 case CSR_CHANNELS_AVAILABLE_HI:
1249 case CSR_CHANNELS_AVAILABLE_LO:
1250 handle_local_lock(ctx->ohci, packet, csr);
1251 break;
1252 default:
1253 if (ctx == &ctx->ohci->at_request_ctx)
1254 fw_core_handle_request(&ctx->ohci->card, packet);
1255 else
1256 fw_core_handle_response(&ctx->ohci->card, packet);
1257 break;
1258 }
1259
1260 if (ctx == &ctx->ohci->at_response_ctx) {
1261 packet->ack = ACK_COMPLETE;
1262 packet->callback(packet, &ctx->ohci->card, packet->ack);
1263 }
1264 }
1265
1266 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1267 {
1268 unsigned long flags;
1269 int ret;
1270
1271 spin_lock_irqsave(&ctx->ohci->lock, flags);
1272
1273 if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1274 ctx->ohci->generation == packet->generation) {
1275 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1276 handle_local_request(ctx, packet);
1277 return;
1278 }
1279
1280 ret = at_context_queue_packet(ctx, packet);
1281 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1282
1283 if (ret < 0)
1284 packet->callback(packet, &ctx->ohci->card, packet->ack);
1285
1286 }
1287
1288 static void bus_reset_tasklet(unsigned long data)
1289 {
1290 struct fw_ohci *ohci = (struct fw_ohci *)data;
1291 int self_id_count, i, j, reg;
1292 int generation, new_generation;
1293 unsigned long flags;
1294 void *free_rom = NULL;
1295 dma_addr_t free_rom_bus = 0;
1296
1297 reg = reg_read(ohci, OHCI1394_NodeID);
1298 if (!(reg & OHCI1394_NodeID_idValid)) {
1299 fw_notify("node ID not valid, new bus reset in progress\n");
1300 return;
1301 }
1302 if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1303 fw_notify("malconfigured bus\n");
1304 return;
1305 }
1306 ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1307 OHCI1394_NodeID_nodeNumber);
1308
1309 reg = reg_read(ohci, OHCI1394_SelfIDCount);
1310 if (reg & OHCI1394_SelfIDCount_selfIDError) {
1311 fw_notify("inconsistent self IDs\n");
1312 return;
1313 }
1314 /*
1315 * The count in the SelfIDCount register is the number of
1316 * bytes in the self ID receive buffer. Since we also receive
1317 * the inverted quadlets and a header quadlet, we shift one
1318 * bit extra to get the actual number of self IDs.
1319 */
1320 self_id_count = (reg >> 3) & 0xff;
1321 if (self_id_count == 0 || self_id_count > 252) {
1322 fw_notify("inconsistent self IDs\n");
1323 return;
1324 }
1325 generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1326 rmb();
1327
1328 for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1329 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1330 fw_notify("inconsistent self IDs\n");
1331 return;
1332 }
1333 ohci->self_id_buffer[j] =
1334 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1335 }
1336 rmb();
1337
1338 /*
1339 * Check the consistency of the self IDs we just read. The
1340 * problem we face is that a new bus reset can start while we
1341 * read out the self IDs from the DMA buffer. If this happens,
1342 * the DMA buffer will be overwritten with new self IDs and we
1343 * will read out inconsistent data. The OHCI specification
1344 * (section 11.2) recommends a technique similar to
1345 * linux/seqlock.h, where we remember the generation of the
1346 * self IDs in the buffer before reading them out and compare
1347 * it to the current generation after reading them out. If
1348 * the two generations match we know we have a consistent set
1349 * of self IDs.
1350 */
1351
1352 new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1353 if (new_generation != generation) {
1354 fw_notify("recursive bus reset detected, "
1355 "discarding self ids\n");
1356 return;
1357 }
1358
1359 /* FIXME: Document how the locking works. */
1360 spin_lock_irqsave(&ohci->lock, flags);
1361
1362 ohci->generation = generation;
1363 context_stop(&ohci->at_request_ctx);
1364 context_stop(&ohci->at_response_ctx);
1365 reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1366
1367 if (ohci->bus_reset_packet_quirk)
1368 ohci->request_generation = generation;
1369
1370 /*
1371 * This next bit is unrelated to the AT context stuff but we
1372 * have to do it under the spinlock also. If a new config rom
1373 * was set up before this reset, the old one is now no longer
1374 * in use and we can free it. Update the config rom pointers
1375 * to point to the current config rom and clear the
1376 * next_config_rom pointer so a new udpate can take place.
1377 */
1378
1379 if (ohci->next_config_rom != NULL) {
1380 if (ohci->next_config_rom != ohci->config_rom) {
1381 free_rom = ohci->config_rom;
1382 free_rom_bus = ohci->config_rom_bus;
1383 }
1384 ohci->config_rom = ohci->next_config_rom;
1385 ohci->config_rom_bus = ohci->next_config_rom_bus;
1386 ohci->next_config_rom = NULL;
1387
1388 /*
1389 * Restore config_rom image and manually update
1390 * config_rom registers. Writing the header quadlet
1391 * will indicate that the config rom is ready, so we
1392 * do that last.
1393 */
1394 reg_write(ohci, OHCI1394_BusOptions,
1395 be32_to_cpu(ohci->config_rom[2]));
1396 ohci->config_rom[0] = cpu_to_be32(ohci->next_header);
1397 reg_write(ohci, OHCI1394_ConfigROMhdr, ohci->next_header);
1398 }
1399
1400 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1401 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1402 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1403 #endif
1404
1405 spin_unlock_irqrestore(&ohci->lock, flags);
1406
1407 if (free_rom)
1408 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1409 free_rom, free_rom_bus);
1410
1411 log_selfids(ohci->node_id, generation,
1412 self_id_count, ohci->self_id_buffer);
1413
1414 fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1415 self_id_count, ohci->self_id_buffer);
1416 }
1417
1418 static irqreturn_t irq_handler(int irq, void *data)
1419 {
1420 struct fw_ohci *ohci = data;
1421 u32 event, iso_event, cycle_time;
1422 int i;
1423
1424 event = reg_read(ohci, OHCI1394_IntEventClear);
1425
1426 if (!event || !~event)
1427 return IRQ_NONE;
1428
1429 /* busReset must not be cleared yet, see OHCI 1.1 clause 7.2.3.2 */
1430 reg_write(ohci, OHCI1394_IntEventClear, event & ~OHCI1394_busReset);
1431 log_irqs(event);
1432
1433 if (event & OHCI1394_selfIDComplete)
1434 tasklet_schedule(&ohci->bus_reset_tasklet);
1435
1436 if (event & OHCI1394_RQPkt)
1437 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
1438
1439 if (event & OHCI1394_RSPkt)
1440 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
1441
1442 if (event & OHCI1394_reqTxComplete)
1443 tasklet_schedule(&ohci->at_request_ctx.tasklet);
1444
1445 if (event & OHCI1394_respTxComplete)
1446 tasklet_schedule(&ohci->at_response_ctx.tasklet);
1447
1448 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
1449 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
1450
1451 while (iso_event) {
1452 i = ffs(iso_event) - 1;
1453 tasklet_schedule(&ohci->ir_context_list[i].context.tasklet);
1454 iso_event &= ~(1 << i);
1455 }
1456
1457 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
1458 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
1459
1460 while (iso_event) {
1461 i = ffs(iso_event) - 1;
1462 tasklet_schedule(&ohci->it_context_list[i].context.tasklet);
1463 iso_event &= ~(1 << i);
1464 }
1465
1466 if (unlikely(event & OHCI1394_regAccessFail))
1467 fw_error("Register access failure - "
1468 "please notify linux1394-devel@lists.sf.net\n");
1469
1470 if (unlikely(event & OHCI1394_postedWriteErr))
1471 fw_error("PCI posted write error\n");
1472
1473 if (unlikely(event & OHCI1394_cycleTooLong)) {
1474 if (printk_ratelimit())
1475 fw_notify("isochronous cycle too long\n");
1476 reg_write(ohci, OHCI1394_LinkControlSet,
1477 OHCI1394_LinkControl_cycleMaster);
1478 }
1479
1480 if (unlikely(event & OHCI1394_cycleInconsistent)) {
1481 /*
1482 * We need to clear this event bit in order to make
1483 * cycleMatch isochronous I/O work. In theory we should
1484 * stop active cycleMatch iso contexts now and restart
1485 * them at least two cycles later. (FIXME?)
1486 */
1487 if (printk_ratelimit())
1488 fw_notify("isochronous cycle inconsistent\n");
1489 }
1490
1491 if (event & OHCI1394_cycle64Seconds) {
1492 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1493 if ((cycle_time & 0x80000000) == 0)
1494 atomic_inc(&ohci->bus_seconds);
1495 }
1496
1497 return IRQ_HANDLED;
1498 }
1499
1500 static int software_reset(struct fw_ohci *ohci)
1501 {
1502 int i;
1503
1504 reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
1505
1506 for (i = 0; i < OHCI_LOOP_COUNT; i++) {
1507 if ((reg_read(ohci, OHCI1394_HCControlSet) &
1508 OHCI1394_HCControl_softReset) == 0)
1509 return 0;
1510 msleep(1);
1511 }
1512
1513 return -EBUSY;
1514 }
1515
1516 static int ohci_enable(struct fw_card *card, u32 *config_rom, size_t length)
1517 {
1518 struct fw_ohci *ohci = fw_ohci(card);
1519 struct pci_dev *dev = to_pci_dev(card->device);
1520 u32 lps;
1521 int i;
1522
1523 if (software_reset(ohci)) {
1524 fw_error("Failed to reset ohci card.\n");
1525 return -EBUSY;
1526 }
1527
1528 /*
1529 * Now enable LPS, which we need in order to start accessing
1530 * most of the registers. In fact, on some cards (ALI M5251),
1531 * accessing registers in the SClk domain without LPS enabled
1532 * will lock up the machine. Wait 50msec to make sure we have
1533 * full link enabled. However, with some cards (well, at least
1534 * a JMicron PCIe card), we have to try again sometimes.
1535 */
1536 reg_write(ohci, OHCI1394_HCControlSet,
1537 OHCI1394_HCControl_LPS |
1538 OHCI1394_HCControl_postedWriteEnable);
1539 flush_writes(ohci);
1540
1541 for (lps = 0, i = 0; !lps && i < 3; i++) {
1542 msleep(50);
1543 lps = reg_read(ohci, OHCI1394_HCControlSet) &
1544 OHCI1394_HCControl_LPS;
1545 }
1546
1547 if (!lps) {
1548 fw_error("Failed to set Link Power Status\n");
1549 return -EIO;
1550 }
1551
1552 reg_write(ohci, OHCI1394_HCControlClear,
1553 OHCI1394_HCControl_noByteSwapData);
1554
1555 reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
1556 reg_write(ohci, OHCI1394_LinkControlClear,
1557 OHCI1394_LinkControl_rcvPhyPkt);
1558 reg_write(ohci, OHCI1394_LinkControlSet,
1559 OHCI1394_LinkControl_rcvSelfID |
1560 OHCI1394_LinkControl_cycleTimerEnable |
1561 OHCI1394_LinkControl_cycleMaster);
1562
1563 reg_write(ohci, OHCI1394_ATRetries,
1564 OHCI1394_MAX_AT_REQ_RETRIES |
1565 (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
1566 (OHCI1394_MAX_PHYS_RESP_RETRIES << 8));
1567
1568 ar_context_run(&ohci->ar_request_ctx);
1569 ar_context_run(&ohci->ar_response_ctx);
1570
1571 reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
1572 reg_write(ohci, OHCI1394_IntEventClear, ~0);
1573 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
1574 reg_write(ohci, OHCI1394_IntMaskSet,
1575 OHCI1394_selfIDComplete |
1576 OHCI1394_RQPkt | OHCI1394_RSPkt |
1577 OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
1578 OHCI1394_isochRx | OHCI1394_isochTx |
1579 OHCI1394_postedWriteErr | OHCI1394_cycleTooLong |
1580 OHCI1394_cycleInconsistent |
1581 OHCI1394_cycle64Seconds | OHCI1394_regAccessFail |
1582 OHCI1394_masterIntEnable);
1583 if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
1584 reg_write(ohci, OHCI1394_IntMaskSet, OHCI1394_busReset);
1585
1586 /* Activate link_on bit and contender bit in our self ID packets.*/
1587 if (ohci_update_phy_reg(card, 4, 0,
1588 PHY_LINK_ACTIVE | PHY_CONTENDER) < 0)
1589 return -EIO;
1590
1591 /*
1592 * When the link is not yet enabled, the atomic config rom
1593 * update mechanism described below in ohci_set_config_rom()
1594 * is not active. We have to update ConfigRomHeader and
1595 * BusOptions manually, and the write to ConfigROMmap takes
1596 * effect immediately. We tie this to the enabling of the
1597 * link, so we have a valid config rom before enabling - the
1598 * OHCI requires that ConfigROMhdr and BusOptions have valid
1599 * values before enabling.
1600 *
1601 * However, when the ConfigROMmap is written, some controllers
1602 * always read back quadlets 0 and 2 from the config rom to
1603 * the ConfigRomHeader and BusOptions registers on bus reset.
1604 * They shouldn't do that in this initial case where the link
1605 * isn't enabled. This means we have to use the same
1606 * workaround here, setting the bus header to 0 and then write
1607 * the right values in the bus reset tasklet.
1608 */
1609
1610 if (config_rom) {
1611 ohci->next_config_rom =
1612 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1613 &ohci->next_config_rom_bus,
1614 GFP_KERNEL);
1615 if (ohci->next_config_rom == NULL)
1616 return -ENOMEM;
1617
1618 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1619 fw_memcpy_to_be32(ohci->next_config_rom, config_rom, length * 4);
1620 } else {
1621 /*
1622 * In the suspend case, config_rom is NULL, which
1623 * means that we just reuse the old config rom.
1624 */
1625 ohci->next_config_rom = ohci->config_rom;
1626 ohci->next_config_rom_bus = ohci->config_rom_bus;
1627 }
1628
1629 ohci->next_header = be32_to_cpu(ohci->next_config_rom[0]);
1630 ohci->next_config_rom[0] = 0;
1631 reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
1632 reg_write(ohci, OHCI1394_BusOptions,
1633 be32_to_cpu(ohci->next_config_rom[2]));
1634 reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
1635
1636 reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
1637
1638 if (request_irq(dev->irq, irq_handler,
1639 IRQF_SHARED, ohci_driver_name, ohci)) {
1640 fw_error("Failed to allocate shared interrupt %d.\n",
1641 dev->irq);
1642 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1643 ohci->config_rom, ohci->config_rom_bus);
1644 return -EIO;
1645 }
1646
1647 reg_write(ohci, OHCI1394_HCControlSet,
1648 OHCI1394_HCControl_linkEnable |
1649 OHCI1394_HCControl_BIBimageValid);
1650 flush_writes(ohci);
1651
1652 /*
1653 * We are ready to go, initiate bus reset to finish the
1654 * initialization.
1655 */
1656
1657 fw_core_initiate_bus_reset(&ohci->card, 1);
1658
1659 return 0;
1660 }
1661
1662 static int ohci_set_config_rom(struct fw_card *card,
1663 u32 *config_rom, size_t length)
1664 {
1665 struct fw_ohci *ohci;
1666 unsigned long flags;
1667 int ret = -EBUSY;
1668 __be32 *next_config_rom;
1669 dma_addr_t uninitialized_var(next_config_rom_bus);
1670
1671 ohci = fw_ohci(card);
1672
1673 /*
1674 * When the OHCI controller is enabled, the config rom update
1675 * mechanism is a bit tricky, but easy enough to use. See
1676 * section 5.5.6 in the OHCI specification.
1677 *
1678 * The OHCI controller caches the new config rom address in a
1679 * shadow register (ConfigROMmapNext) and needs a bus reset
1680 * for the changes to take place. When the bus reset is
1681 * detected, the controller loads the new values for the
1682 * ConfigRomHeader and BusOptions registers from the specified
1683 * config rom and loads ConfigROMmap from the ConfigROMmapNext
1684 * shadow register. All automatically and atomically.
1685 *
1686 * Now, there's a twist to this story. The automatic load of
1687 * ConfigRomHeader and BusOptions doesn't honor the
1688 * noByteSwapData bit, so with a be32 config rom, the
1689 * controller will load be32 values in to these registers
1690 * during the atomic update, even on litte endian
1691 * architectures. The workaround we use is to put a 0 in the
1692 * header quadlet; 0 is endian agnostic and means that the
1693 * config rom isn't ready yet. In the bus reset tasklet we
1694 * then set up the real values for the two registers.
1695 *
1696 * We use ohci->lock to avoid racing with the code that sets
1697 * ohci->next_config_rom to NULL (see bus_reset_tasklet).
1698 */
1699
1700 next_config_rom =
1701 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1702 &next_config_rom_bus, GFP_KERNEL);
1703 if (next_config_rom == NULL)
1704 return -ENOMEM;
1705
1706 spin_lock_irqsave(&ohci->lock, flags);
1707
1708 if (ohci->next_config_rom == NULL) {
1709 ohci->next_config_rom = next_config_rom;
1710 ohci->next_config_rom_bus = next_config_rom_bus;
1711
1712 memset(ohci->next_config_rom, 0, CONFIG_ROM_SIZE);
1713 fw_memcpy_to_be32(ohci->next_config_rom, config_rom,
1714 length * 4);
1715
1716 ohci->next_header = config_rom[0];
1717 ohci->next_config_rom[0] = 0;
1718
1719 reg_write(ohci, OHCI1394_ConfigROMmap,
1720 ohci->next_config_rom_bus);
1721 ret = 0;
1722 }
1723
1724 spin_unlock_irqrestore(&ohci->lock, flags);
1725
1726 /*
1727 * Now initiate a bus reset to have the changes take
1728 * effect. We clean up the old config rom memory and DMA
1729 * mappings in the bus reset tasklet, since the OHCI
1730 * controller could need to access it before the bus reset
1731 * takes effect.
1732 */
1733 if (ret == 0)
1734 fw_core_initiate_bus_reset(&ohci->card, 1);
1735 else
1736 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1737 next_config_rom, next_config_rom_bus);
1738
1739 return ret;
1740 }
1741
1742 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
1743 {
1744 struct fw_ohci *ohci = fw_ohci(card);
1745
1746 at_context_transmit(&ohci->at_request_ctx, packet);
1747 }
1748
1749 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
1750 {
1751 struct fw_ohci *ohci = fw_ohci(card);
1752
1753 at_context_transmit(&ohci->at_response_ctx, packet);
1754 }
1755
1756 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
1757 {
1758 struct fw_ohci *ohci = fw_ohci(card);
1759 struct context *ctx = &ohci->at_request_ctx;
1760 struct driver_data *driver_data = packet->driver_data;
1761 int ret = -ENOENT;
1762
1763 tasklet_disable(&ctx->tasklet);
1764
1765 if (packet->ack != 0)
1766 goto out;
1767
1768 if (packet->payload_bus)
1769 dma_unmap_single(ohci->card.device, packet->payload_bus,
1770 packet->payload_length, DMA_TO_DEVICE);
1771
1772 log_ar_at_event('T', packet->speed, packet->header, 0x20);
1773 driver_data->packet = NULL;
1774 packet->ack = RCODE_CANCELLED;
1775 packet->callback(packet, &ohci->card, packet->ack);
1776 ret = 0;
1777 out:
1778 tasklet_enable(&ctx->tasklet);
1779
1780 return ret;
1781 }
1782
1783 static int ohci_enable_phys_dma(struct fw_card *card,
1784 int node_id, int generation)
1785 {
1786 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1787 return 0;
1788 #else
1789 struct fw_ohci *ohci = fw_ohci(card);
1790 unsigned long flags;
1791 int n, ret = 0;
1792
1793 /*
1794 * FIXME: Make sure this bitmask is cleared when we clear the busReset
1795 * interrupt bit. Clear physReqResourceAllBuses on bus reset.
1796 */
1797
1798 spin_lock_irqsave(&ohci->lock, flags);
1799
1800 if (ohci->generation != generation) {
1801 ret = -ESTALE;
1802 goto out;
1803 }
1804
1805 /*
1806 * Note, if the node ID contains a non-local bus ID, physical DMA is
1807 * enabled for _all_ nodes on remote buses.
1808 */
1809
1810 n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
1811 if (n < 32)
1812 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
1813 else
1814 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
1815
1816 flush_writes(ohci);
1817 out:
1818 spin_unlock_irqrestore(&ohci->lock, flags);
1819
1820 return ret;
1821 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
1822 }
1823
1824 static u64 ohci_get_bus_time(struct fw_card *card)
1825 {
1826 struct fw_ohci *ohci = fw_ohci(card);
1827 u32 cycle_time;
1828 u64 bus_time;
1829
1830 cycle_time = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1831 bus_time = ((u64)atomic_read(&ohci->bus_seconds) << 32) | cycle_time;
1832
1833 return bus_time;
1834 }
1835
1836 static void copy_iso_headers(struct iso_context *ctx, void *p)
1837 {
1838 int i = ctx->header_length;
1839
1840 if (i + ctx->base.header_size > PAGE_SIZE)
1841 return;
1842
1843 /*
1844 * The iso header is byteswapped to little endian by
1845 * the controller, but the remaining header quadlets
1846 * are big endian. We want to present all the headers
1847 * as big endian, so we have to swap the first quadlet.
1848 */
1849 if (ctx->base.header_size > 0)
1850 *(u32 *) (ctx->header + i) = __swab32(*(u32 *) (p + 4));
1851 if (ctx->base.header_size > 4)
1852 *(u32 *) (ctx->header + i + 4) = __swab32(*(u32 *) p);
1853 if (ctx->base.header_size > 8)
1854 memcpy(ctx->header + i + 8, p + 8, ctx->base.header_size - 8);
1855 ctx->header_length += ctx->base.header_size;
1856 }
1857
1858 static int handle_ir_dualbuffer_packet(struct context *context,
1859 struct descriptor *d,
1860 struct descriptor *last)
1861 {
1862 struct iso_context *ctx =
1863 container_of(context, struct iso_context, context);
1864 struct db_descriptor *db = (struct db_descriptor *) d;
1865 __le32 *ir_header;
1866 size_t header_length;
1867 void *p, *end;
1868
1869 if (db->first_res_count != 0 && db->second_res_count != 0) {
1870 if (ctx->excess_bytes <= le16_to_cpu(db->second_req_count)) {
1871 /* This descriptor isn't done yet, stop iteration. */
1872 return 0;
1873 }
1874 ctx->excess_bytes -= le16_to_cpu(db->second_req_count);
1875 }
1876
1877 header_length = le16_to_cpu(db->first_req_count) -
1878 le16_to_cpu(db->first_res_count);
1879
1880 p = db + 1;
1881 end = p + header_length;
1882 while (p < end) {
1883 copy_iso_headers(ctx, p);
1884 ctx->excess_bytes +=
1885 (le32_to_cpu(*(__le32 *)(p + 4)) >> 16) & 0xffff;
1886 p += max(ctx->base.header_size, (size_t)8);
1887 }
1888
1889 ctx->excess_bytes -= le16_to_cpu(db->second_req_count) -
1890 le16_to_cpu(db->second_res_count);
1891
1892 if (le16_to_cpu(db->control) & DESCRIPTOR_IRQ_ALWAYS) {
1893 ir_header = (__le32 *) (db + 1);
1894 ctx->base.callback(&ctx->base,
1895 le32_to_cpu(ir_header[0]) & 0xffff,
1896 ctx->header_length, ctx->header,
1897 ctx->base.callback_data);
1898 ctx->header_length = 0;
1899 }
1900
1901 return 1;
1902 }
1903
1904 static int handle_ir_packet_per_buffer(struct context *context,
1905 struct descriptor *d,
1906 struct descriptor *last)
1907 {
1908 struct iso_context *ctx =
1909 container_of(context, struct iso_context, context);
1910 struct descriptor *pd;
1911 __le32 *ir_header;
1912 void *p;
1913
1914 for (pd = d; pd <= last; pd++) {
1915 if (pd->transfer_status)
1916 break;
1917 }
1918 if (pd > last)
1919 /* Descriptor(s) not done yet, stop iteration */
1920 return 0;
1921
1922 p = last + 1;
1923 copy_iso_headers(ctx, p);
1924
1925 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
1926 ir_header = (__le32 *) p;
1927 ctx->base.callback(&ctx->base,
1928 le32_to_cpu(ir_header[0]) & 0xffff,
1929 ctx->header_length, ctx->header,
1930 ctx->base.callback_data);
1931 ctx->header_length = 0;
1932 }
1933
1934 return 1;
1935 }
1936
1937 static int handle_it_packet(struct context *context,
1938 struct descriptor *d,
1939 struct descriptor *last)
1940 {
1941 struct iso_context *ctx =
1942 container_of(context, struct iso_context, context);
1943 int i;
1944 struct descriptor *pd;
1945
1946 for (pd = d; pd <= last; pd++)
1947 if (pd->transfer_status)
1948 break;
1949 if (pd > last)
1950 /* Descriptor(s) not done yet, stop iteration */
1951 return 0;
1952
1953 i = ctx->header_length;
1954 if (i + 4 < PAGE_SIZE) {
1955 /* Present this value as big-endian to match the receive code */
1956 *(__be32 *)(ctx->header + i) = cpu_to_be32(
1957 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
1958 le16_to_cpu(pd->res_count));
1959 ctx->header_length += 4;
1960 }
1961 if (le16_to_cpu(last->control) & DESCRIPTOR_IRQ_ALWAYS) {
1962 ctx->base.callback(&ctx->base, le16_to_cpu(last->res_count),
1963 ctx->header_length, ctx->header,
1964 ctx->base.callback_data);
1965 ctx->header_length = 0;
1966 }
1967 return 1;
1968 }
1969
1970 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
1971 int type, int channel, size_t header_size)
1972 {
1973 struct fw_ohci *ohci = fw_ohci(card);
1974 struct iso_context *ctx, *list;
1975 descriptor_callback_t callback;
1976 u64 *channels, dont_care = ~0ULL;
1977 u32 *mask, regs;
1978 unsigned long flags;
1979 int index, ret = -ENOMEM;
1980
1981 if (type == FW_ISO_CONTEXT_TRANSMIT) {
1982 channels = &dont_care;
1983 mask = &ohci->it_context_mask;
1984 list = ohci->it_context_list;
1985 callback = handle_it_packet;
1986 } else {
1987 channels = &ohci->ir_context_channels;
1988 mask = &ohci->ir_context_mask;
1989 list = ohci->ir_context_list;
1990 if (ohci->use_dualbuffer)
1991 callback = handle_ir_dualbuffer_packet;
1992 else
1993 callback = handle_ir_packet_per_buffer;
1994 }
1995
1996 spin_lock_irqsave(&ohci->lock, flags);
1997 index = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
1998 if (index >= 0) {
1999 *channels &= ~(1ULL << channel);
2000 *mask &= ~(1 << index);
2001 }
2002 spin_unlock_irqrestore(&ohci->lock, flags);
2003
2004 if (index < 0)
2005 return ERR_PTR(-EBUSY);
2006
2007 if (type == FW_ISO_CONTEXT_TRANSMIT)
2008 regs = OHCI1394_IsoXmitContextBase(index);
2009 else
2010 regs = OHCI1394_IsoRcvContextBase(index);
2011
2012 ctx = &list[index];
2013 memset(ctx, 0, sizeof(*ctx));
2014 ctx->header_length = 0;
2015 ctx->header = (void *) __get_free_page(GFP_KERNEL);
2016 if (ctx->header == NULL)
2017 goto out;
2018
2019 ret = context_init(&ctx->context, ohci, regs, callback);
2020 if (ret < 0)
2021 goto out_with_header;
2022
2023 return &ctx->base;
2024
2025 out_with_header:
2026 free_page((unsigned long)ctx->header);
2027 out:
2028 spin_lock_irqsave(&ohci->lock, flags);
2029 *mask |= 1 << index;
2030 spin_unlock_irqrestore(&ohci->lock, flags);
2031
2032 return ERR_PTR(ret);
2033 }
2034
2035 static int ohci_start_iso(struct fw_iso_context *base,
2036 s32 cycle, u32 sync, u32 tags)
2037 {
2038 struct iso_context *ctx = container_of(base, struct iso_context, base);
2039 struct fw_ohci *ohci = ctx->context.ohci;
2040 u32 control, match;
2041 int index;
2042
2043 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2044 index = ctx - ohci->it_context_list;
2045 match = 0;
2046 if (cycle >= 0)
2047 match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
2048 (cycle & 0x7fff) << 16;
2049
2050 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2051 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
2052 context_run(&ctx->context, match);
2053 } else {
2054 index = ctx - ohci->ir_context_list;
2055 control = IR_CONTEXT_ISOCH_HEADER;
2056 if (ohci->use_dualbuffer)
2057 control |= IR_CONTEXT_DUAL_BUFFER_MODE;
2058 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2059 if (cycle >= 0) {
2060 match |= (cycle & 0x07fff) << 12;
2061 control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2062 }
2063
2064 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2065 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2066 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2067 context_run(&ctx->context, control);
2068 }
2069
2070 return 0;
2071 }
2072
2073 static int ohci_stop_iso(struct fw_iso_context *base)
2074 {
2075 struct fw_ohci *ohci = fw_ohci(base->card);
2076 struct iso_context *ctx = container_of(base, struct iso_context, base);
2077 int index;
2078
2079 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2080 index = ctx - ohci->it_context_list;
2081 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
2082 } else {
2083 index = ctx - ohci->ir_context_list;
2084 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
2085 }
2086 flush_writes(ohci);
2087 context_stop(&ctx->context);
2088
2089 return 0;
2090 }
2091
2092 static void ohci_free_iso_context(struct fw_iso_context *base)
2093 {
2094 struct fw_ohci *ohci = fw_ohci(base->card);
2095 struct iso_context *ctx = container_of(base, struct iso_context, base);
2096 unsigned long flags;
2097 int index;
2098
2099 ohci_stop_iso(base);
2100 context_release(&ctx->context);
2101 free_page((unsigned long)ctx->header);
2102
2103 spin_lock_irqsave(&ohci->lock, flags);
2104
2105 if (ctx->base.type == FW_ISO_CONTEXT_TRANSMIT) {
2106 index = ctx - ohci->it_context_list;
2107 ohci->it_context_mask |= 1 << index;
2108 } else {
2109 index = ctx - ohci->ir_context_list;
2110 ohci->ir_context_mask |= 1 << index;
2111 ohci->ir_context_channels |= 1ULL << base->channel;
2112 }
2113
2114 spin_unlock_irqrestore(&ohci->lock, flags);
2115 }
2116
2117 static int ohci_queue_iso_transmit(struct fw_iso_context *base,
2118 struct fw_iso_packet *packet,
2119 struct fw_iso_buffer *buffer,
2120 unsigned long payload)
2121 {
2122 struct iso_context *ctx = container_of(base, struct iso_context, base);
2123 struct descriptor *d, *last, *pd;
2124 struct fw_iso_packet *p;
2125 __le32 *header;
2126 dma_addr_t d_bus, page_bus;
2127 u32 z, header_z, payload_z, irq;
2128 u32 payload_index, payload_end_index, next_page_index;
2129 int page, end_page, i, length, offset;
2130
2131 /*
2132 * FIXME: Cycle lost behavior should be configurable: lose
2133 * packet, retransmit or terminate..
2134 */
2135
2136 p = packet;
2137 payload_index = payload;
2138
2139 if (p->skip)
2140 z = 1;
2141 else
2142 z = 2;
2143 if (p->header_length > 0)
2144 z++;
2145
2146 /* Determine the first page the payload isn't contained in. */
2147 end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
2148 if (p->payload_length > 0)
2149 payload_z = end_page - (payload_index >> PAGE_SHIFT);
2150 else
2151 payload_z = 0;
2152
2153 z += payload_z;
2154
2155 /* Get header size in number of descriptors. */
2156 header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
2157
2158 d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
2159 if (d == NULL)
2160 return -ENOMEM;
2161
2162 if (!p->skip) {
2163 d[0].control = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
2164 d[0].req_count = cpu_to_le16(8);
2165
2166 header = (__le32 *) &d[1];
2167 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
2168 IT_HEADER_TAG(p->tag) |
2169 IT_HEADER_TCODE(TCODE_STREAM_DATA) |
2170 IT_HEADER_CHANNEL(ctx->base.channel) |
2171 IT_HEADER_SPEED(ctx->base.speed));
2172 header[1] =
2173 cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
2174 p->payload_length));
2175 }
2176
2177 if (p->header_length > 0) {
2178 d[2].req_count = cpu_to_le16(p->header_length);
2179 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
2180 memcpy(&d[z], p->header, p->header_length);
2181 }
2182
2183 pd = d + z - payload_z;
2184 payload_end_index = payload_index + p->payload_length;
2185 for (i = 0; i < payload_z; i++) {
2186 page = payload_index >> PAGE_SHIFT;
2187 offset = payload_index & ~PAGE_MASK;
2188 next_page_index = (page + 1) << PAGE_SHIFT;
2189 length =
2190 min(next_page_index, payload_end_index) - payload_index;
2191 pd[i].req_count = cpu_to_le16(length);
2192
2193 page_bus = page_private(buffer->pages[page]);
2194 pd[i].data_address = cpu_to_le32(page_bus + offset);
2195
2196 payload_index += length;
2197 }
2198
2199 if (p->interrupt)
2200 irq = DESCRIPTOR_IRQ_ALWAYS;
2201 else
2202 irq = DESCRIPTOR_NO_IRQ;
2203
2204 last = z == 2 ? d : d + z - 1;
2205 last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
2206 DESCRIPTOR_STATUS |
2207 DESCRIPTOR_BRANCH_ALWAYS |
2208 irq);
2209
2210 context_append(&ctx->context, d, z, header_z);
2211
2212 return 0;
2213 }
2214
2215 static int ohci_queue_iso_receive_dualbuffer(struct fw_iso_context *base,
2216 struct fw_iso_packet *packet,
2217 struct fw_iso_buffer *buffer,
2218 unsigned long payload)
2219 {
2220 struct iso_context *ctx = container_of(base, struct iso_context, base);
2221 struct db_descriptor *db = NULL;
2222 struct descriptor *d;
2223 struct fw_iso_packet *p;
2224 dma_addr_t d_bus, page_bus;
2225 u32 z, header_z, length, rest;
2226 int page, offset, packet_count, header_size;
2227
2228 /*
2229 * FIXME: Cycle lost behavior should be configurable: lose
2230 * packet, retransmit or terminate..
2231 */
2232
2233 p = packet;
2234 z = 2;
2235
2236 /*
2237 * The OHCI controller puts the isochronous header and trailer in the
2238 * buffer, so we need at least 8 bytes.
2239 */
2240 packet_count = p->header_length / ctx->base.header_size;
2241 header_size = packet_count * max(ctx->base.header_size, (size_t)8);
2242
2243 /* Get header size in number of descriptors. */
2244 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2245 page = payload >> PAGE_SHIFT;
2246 offset = payload & ~PAGE_MASK;
2247 rest = p->payload_length;
2248 /*
2249 * The controllers I've tested have not worked correctly when
2250 * second_req_count is zero. Rather than do something we know won't
2251 * work, return an error
2252 */
2253 if (rest == 0)
2254 return -EINVAL;
2255
2256 /* FIXME: make packet-per-buffer/dual-buffer a context option */
2257 while (rest > 0) {
2258 d = context_get_descriptors(&ctx->context,
2259 z + header_z, &d_bus);
2260 if (d == NULL)
2261 return -ENOMEM;
2262
2263 db = (struct db_descriptor *) d;
2264 db->control = cpu_to_le16(DESCRIPTOR_STATUS |
2265 DESCRIPTOR_BRANCH_ALWAYS);
2266 db->first_size =
2267 cpu_to_le16(max(ctx->base.header_size, (size_t)8));
2268 if (p->skip && rest == p->payload_length) {
2269 db->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2270 db->first_req_count = db->first_size;
2271 } else {
2272 db->first_req_count = cpu_to_le16(header_size);
2273 }
2274 db->first_res_count = db->first_req_count;
2275 db->first_buffer = cpu_to_le32(d_bus + sizeof(*db));
2276
2277 if (p->skip && rest == p->payload_length)
2278 length = 4;
2279 else if (offset + rest < PAGE_SIZE)
2280 length = rest;
2281 else
2282 length = PAGE_SIZE - offset;
2283
2284 db->second_req_count = cpu_to_le16(length);
2285 db->second_res_count = db->second_req_count;
2286 page_bus = page_private(buffer->pages[page]);
2287 db->second_buffer = cpu_to_le32(page_bus + offset);
2288
2289 if (p->interrupt && length == rest)
2290 db->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2291
2292 context_append(&ctx->context, d, z, header_z);
2293 offset = (offset + length) & ~PAGE_MASK;
2294 rest -= length;
2295 if (offset == 0)
2296 page++;
2297 }
2298
2299 return 0;
2300 }
2301
2302 static int ohci_queue_iso_receive_packet_per_buffer(struct fw_iso_context *base,
2303 struct fw_iso_packet *packet,
2304 struct fw_iso_buffer *buffer,
2305 unsigned long payload)
2306 {
2307 struct iso_context *ctx = container_of(base, struct iso_context, base);
2308 struct descriptor *d, *pd;
2309 struct fw_iso_packet *p = packet;
2310 dma_addr_t d_bus, page_bus;
2311 u32 z, header_z, rest;
2312 int i, j, length;
2313 int page, offset, packet_count, header_size, payload_per_buffer;
2314
2315 /*
2316 * The OHCI controller puts the isochronous header and trailer in the
2317 * buffer, so we need at least 8 bytes.
2318 */
2319 packet_count = p->header_length / ctx->base.header_size;
2320 header_size = max(ctx->base.header_size, (size_t)8);
2321
2322 /* Get header size in number of descriptors. */
2323 header_z = DIV_ROUND_UP(header_size, sizeof(*d));
2324 page = payload >> PAGE_SHIFT;
2325 offset = payload & ~PAGE_MASK;
2326 payload_per_buffer = p->payload_length / packet_count;
2327
2328 for (i = 0; i < packet_count; i++) {
2329 /* d points to the header descriptor */
2330 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
2331 d = context_get_descriptors(&ctx->context,
2332 z + header_z, &d_bus);
2333 if (d == NULL)
2334 return -ENOMEM;
2335
2336 d->control = cpu_to_le16(DESCRIPTOR_STATUS |
2337 DESCRIPTOR_INPUT_MORE);
2338 if (p->skip && i == 0)
2339 d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
2340 d->req_count = cpu_to_le16(header_size);
2341 d->res_count = d->req_count;
2342 d->transfer_status = 0;
2343 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
2344
2345 rest = payload_per_buffer;
2346 pd = d;
2347 for (j = 1; j < z; j++) {
2348 pd++;
2349 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2350 DESCRIPTOR_INPUT_MORE);
2351
2352 if (offset + rest < PAGE_SIZE)
2353 length = rest;
2354 else
2355 length = PAGE_SIZE - offset;
2356 pd->req_count = cpu_to_le16(length);
2357 pd->res_count = pd->req_count;
2358 pd->transfer_status = 0;
2359
2360 page_bus = page_private(buffer->pages[page]);
2361 pd->data_address = cpu_to_le32(page_bus + offset);
2362
2363 offset = (offset + length) & ~PAGE_MASK;
2364 rest -= length;
2365 if (offset == 0)
2366 page++;
2367 }
2368 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
2369 DESCRIPTOR_INPUT_LAST |
2370 DESCRIPTOR_BRANCH_ALWAYS);
2371 if (p->interrupt && i == packet_count - 1)
2372 pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
2373
2374 context_append(&ctx->context, d, z, header_z);
2375 }
2376
2377 return 0;
2378 }
2379
2380 static int ohci_queue_iso(struct fw_iso_context *base,
2381 struct fw_iso_packet *packet,
2382 struct fw_iso_buffer *buffer,
2383 unsigned long payload)
2384 {
2385 struct iso_context *ctx = container_of(base, struct iso_context, base);
2386 unsigned long flags;
2387 int ret;
2388
2389 spin_lock_irqsave(&ctx->context.ohci->lock, flags);
2390 if (base->type == FW_ISO_CONTEXT_TRANSMIT)
2391 ret = ohci_queue_iso_transmit(base, packet, buffer, payload);
2392 else if (ctx->context.ohci->use_dualbuffer)
2393 ret = ohci_queue_iso_receive_dualbuffer(base, packet,
2394 buffer, payload);
2395 else
2396 ret = ohci_queue_iso_receive_packet_per_buffer(base, packet,
2397 buffer, payload);
2398 spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
2399
2400 return ret;
2401 }
2402
2403 static const struct fw_card_driver ohci_driver = {
2404 .enable = ohci_enable,
2405 .update_phy_reg = ohci_update_phy_reg,
2406 .set_config_rom = ohci_set_config_rom,
2407 .send_request = ohci_send_request,
2408 .send_response = ohci_send_response,
2409 .cancel_packet = ohci_cancel_packet,
2410 .enable_phys_dma = ohci_enable_phys_dma,
2411 .get_bus_time = ohci_get_bus_time,
2412
2413 .allocate_iso_context = ohci_allocate_iso_context,
2414 .free_iso_context = ohci_free_iso_context,
2415 .queue_iso = ohci_queue_iso,
2416 .start_iso = ohci_start_iso,
2417 .stop_iso = ohci_stop_iso,
2418 };
2419
2420 #ifdef CONFIG_PPC_PMAC
2421 static void ohci_pmac_on(struct pci_dev *dev)
2422 {
2423 if (machine_is(powermac)) {
2424 struct device_node *ofn = pci_device_to_OF_node(dev);
2425
2426 if (ofn) {
2427 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
2428 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
2429 }
2430 }
2431 }
2432
2433 static void ohci_pmac_off(struct pci_dev *dev)
2434 {
2435 if (machine_is(powermac)) {
2436 struct device_node *ofn = pci_device_to_OF_node(dev);
2437
2438 if (ofn) {
2439 pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
2440 pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
2441 }
2442 }
2443 }
2444 #else
2445 #define ohci_pmac_on(dev)
2446 #define ohci_pmac_off(dev)
2447 #endif /* CONFIG_PPC_PMAC */
2448
2449 #define PCI_VENDOR_ID_AGERE PCI_VENDOR_ID_ATT
2450 #define PCI_DEVICE_ID_AGERE_FW643 0x5901
2451 #define PCI_DEVICE_ID_TI_TSB43AB23 0x8024
2452
2453 static int __devinit pci_probe(struct pci_dev *dev,
2454 const struct pci_device_id *ent)
2455 {
2456 struct fw_ohci *ohci;
2457 u32 bus_options, max_receive, link_speed, version;
2458 u64 guid;
2459 int err;
2460 size_t size;
2461
2462 ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
2463 if (ohci == NULL) {
2464 err = -ENOMEM;
2465 goto fail;
2466 }
2467
2468 fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
2469
2470 ohci_pmac_on(dev);
2471
2472 err = pci_enable_device(dev);
2473 if (err) {
2474 fw_error("Failed to enable OHCI hardware\n");
2475 goto fail_free;
2476 }
2477
2478 pci_set_master(dev);
2479 pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
2480 pci_set_drvdata(dev, ohci);
2481
2482 spin_lock_init(&ohci->lock);
2483
2484 tasklet_init(&ohci->bus_reset_tasklet,
2485 bus_reset_tasklet, (unsigned long)ohci);
2486
2487 err = pci_request_region(dev, 0, ohci_driver_name);
2488 if (err) {
2489 fw_error("MMIO resource unavailable\n");
2490 goto fail_disable;
2491 }
2492
2493 ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
2494 if (ohci->registers == NULL) {
2495 fw_error("Failed to remap registers\n");
2496 err = -ENXIO;
2497 goto fail_iomem;
2498 }
2499
2500 version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2501 ohci->use_dualbuffer = version >= OHCI_VERSION_1_1;
2502
2503 /* dual-buffer mode is broken if more than one IR context is active */
2504 if (dev->vendor == PCI_VENDOR_ID_AGERE &&
2505 dev->device == PCI_DEVICE_ID_AGERE_FW643)
2506 ohci->use_dualbuffer = false;
2507
2508 /* dual-buffer mode is broken */
2509 if (dev->vendor == PCI_VENDOR_ID_RICOH &&
2510 dev->device == PCI_DEVICE_ID_RICOH_R5C832)
2511 ohci->use_dualbuffer = false;
2512
2513 /* x86-32 currently doesn't use highmem for dma_alloc_coherent */
2514 #if !defined(CONFIG_X86_32)
2515 /* dual-buffer mode is broken with descriptor addresses above 2G */
2516 if (dev->vendor == PCI_VENDOR_ID_TI &&
2517 (dev->device == PCI_DEVICE_ID_TI_TSB43AB22 ||
2518 dev->device == PCI_DEVICE_ID_TI_TSB43AB23))
2519 ohci->use_dualbuffer = false;
2520 #endif
2521
2522 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
2523 ohci->old_uninorth = dev->vendor == PCI_VENDOR_ID_APPLE &&
2524 dev->device == PCI_DEVICE_ID_APPLE_UNI_N_FW;
2525 #endif
2526 ohci->bus_reset_packet_quirk = dev->vendor == PCI_VENDOR_ID_TI;
2527
2528 ar_context_init(&ohci->ar_request_ctx, ohci,
2529 OHCI1394_AsReqRcvContextControlSet);
2530
2531 ar_context_init(&ohci->ar_response_ctx, ohci,
2532 OHCI1394_AsRspRcvContextControlSet);
2533
2534 context_init(&ohci->at_request_ctx, ohci,
2535 OHCI1394_AsReqTrContextControlSet, handle_at_packet);
2536
2537 context_init(&ohci->at_response_ctx, ohci,
2538 OHCI1394_AsRspTrContextControlSet, handle_at_packet);
2539
2540 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
2541 ohci->it_context_mask = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
2542 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
2543 size = sizeof(struct iso_context) * hweight32(ohci->it_context_mask);
2544 ohci->it_context_list = kzalloc(size, GFP_KERNEL);
2545
2546 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
2547 ohci->ir_context_channels = ~0ULL;
2548 ohci->ir_context_mask = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
2549 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
2550 size = sizeof(struct iso_context) * hweight32(ohci->ir_context_mask);
2551 ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
2552
2553 if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
2554 err = -ENOMEM;
2555 goto fail_contexts;
2556 }
2557
2558 /* self-id dma buffer allocation */
2559 ohci->self_id_cpu = dma_alloc_coherent(ohci->card.device,
2560 SELF_ID_BUF_SIZE,
2561 &ohci->self_id_bus,
2562 GFP_KERNEL);
2563 if (ohci->self_id_cpu == NULL) {
2564 err = -ENOMEM;
2565 goto fail_contexts;
2566 }
2567
2568 bus_options = reg_read(ohci, OHCI1394_BusOptions);
2569 max_receive = (bus_options >> 12) & 0xf;
2570 link_speed = bus_options & 0x7;
2571 guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
2572 reg_read(ohci, OHCI1394_GUIDLo);
2573
2574 err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
2575 if (err)
2576 goto fail_self_id;
2577
2578 fw_notify("Added fw-ohci device %s, OHCI version %x.%x\n",
2579 dev_name(&dev->dev), version >> 16, version & 0xff);
2580
2581 return 0;
2582
2583 fail_self_id:
2584 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2585 ohci->self_id_cpu, ohci->self_id_bus);
2586 fail_contexts:
2587 kfree(ohci->ir_context_list);
2588 kfree(ohci->it_context_list);
2589 context_release(&ohci->at_response_ctx);
2590 context_release(&ohci->at_request_ctx);
2591 ar_context_release(&ohci->ar_response_ctx);
2592 ar_context_release(&ohci->ar_request_ctx);
2593 pci_iounmap(dev, ohci->registers);
2594 fail_iomem:
2595 pci_release_region(dev, 0);
2596 fail_disable:
2597 pci_disable_device(dev);
2598 fail_free:
2599 kfree(&ohci->card);
2600 ohci_pmac_off(dev);
2601 fail:
2602 if (err == -ENOMEM)
2603 fw_error("Out of memory\n");
2604
2605 return err;
2606 }
2607
2608 static void pci_remove(struct pci_dev *dev)
2609 {
2610 struct fw_ohci *ohci;
2611
2612 ohci = pci_get_drvdata(dev);
2613 reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2614 flush_writes(ohci);
2615 fw_core_remove_card(&ohci->card);
2616
2617 /*
2618 * FIXME: Fail all pending packets here, now that the upper
2619 * layers can't queue any more.
2620 */
2621
2622 software_reset(ohci);
2623 free_irq(dev->irq, ohci);
2624
2625 if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
2626 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2627 ohci->next_config_rom, ohci->next_config_rom_bus);
2628 if (ohci->config_rom)
2629 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2630 ohci->config_rom, ohci->config_rom_bus);
2631 dma_free_coherent(ohci->card.device, SELF_ID_BUF_SIZE,
2632 ohci->self_id_cpu, ohci->self_id_bus);
2633 ar_context_release(&ohci->ar_request_ctx);
2634 ar_context_release(&ohci->ar_response_ctx);
2635 context_release(&ohci->at_request_ctx);
2636 context_release(&ohci->at_response_ctx);
2637 kfree(ohci->it_context_list);
2638 kfree(ohci->ir_context_list);
2639 pci_iounmap(dev, ohci->registers);
2640 pci_release_region(dev, 0);
2641 pci_disable_device(dev);
2642 kfree(&ohci->card);
2643 ohci_pmac_off(dev);
2644
2645 fw_notify("Removed fw-ohci device.\n");
2646 }
2647
2648 #ifdef CONFIG_PM
2649 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
2650 {
2651 struct fw_ohci *ohci = pci_get_drvdata(dev);
2652 int err;
2653
2654 software_reset(ohci);
2655 free_irq(dev->irq, ohci);
2656 err = pci_save_state(dev);
2657 if (err) {
2658 fw_error("pci_save_state failed\n");
2659 return err;
2660 }
2661 err = pci_set_power_state(dev, pci_choose_state(dev, state));
2662 if (err)
2663 fw_error("pci_set_power_state failed with %d\n", err);
2664 ohci_pmac_off(dev);
2665
2666 return 0;
2667 }
2668
2669 static int pci_resume(struct pci_dev *dev)
2670 {
2671 struct fw_ohci *ohci = pci_get_drvdata(dev);
2672 int err;
2673
2674 ohci_pmac_on(dev);
2675 pci_set_power_state(dev, PCI_D0);
2676 pci_restore_state(dev);
2677 err = pci_enable_device(dev);
2678 if (err) {
2679 fw_error("pci_enable_device failed\n");
2680 return err;
2681 }
2682
2683 return ohci_enable(&ohci->card, NULL, 0);
2684 }
2685 #endif
2686
2687 static struct pci_device_id pci_table[] = {
2688 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
2689 { }
2690 };
2691
2692 MODULE_DEVICE_TABLE(pci, pci_table);
2693
2694 static struct pci_driver fw_ohci_pci_driver = {
2695 .name = ohci_driver_name,
2696 .id_table = pci_table,
2697 .probe = pci_probe,
2698 .remove = pci_remove,
2699 #ifdef CONFIG_PM
2700 .resume = pci_resume,
2701 .suspend = pci_suspend,
2702 #endif
2703 };
2704
2705 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
2706 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
2707 MODULE_LICENSE("GPL");
2708
2709 /* Provide a module alias so root-on-sbp2 initrds don't break. */
2710 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
2711 MODULE_ALIAS("ohci1394");
2712 #endif
2713
2714 static int __init fw_ohci_init(void)
2715 {
2716 return pci_register_driver(&fw_ohci_pci_driver);
2717 }
2718
2719 static void __exit fw_ohci_cleanup(void)
2720 {
2721 pci_unregister_driver(&fw_ohci_pci_driver);
2722 }
2723
2724 module_init(fw_ohci_init);
2725 module_exit(fw_ohci_cleanup);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree