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ARM: perf: add _init() functions to PMUs
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / arm / kernel / perf_event.c
blobacc4e91dd300e6ac840bb6b9921c90e2a5479c0f
1 #undef DEBUG
2
3 /*
4 * ARM performance counter support.
5 *
6 * Copyright (C) 2009 picoChip Designs, Ltd., Jamie Iles
7 *
8 * ARMv7 support: Jean Pihet <jpihet@mvista.com>
9 * 2010 (c) MontaVista Software, LLC.
10 *
11 * This code is based on the sparc64 perf event code, which is in turn based
12 * on the x86 code. Callchain code is based on the ARM OProfile backtrace
13 * code.
14 */
15 #define pr_fmt(fmt) "hw perfevents: " fmt
16
17 #include <linux/interrupt.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
20 #include <linux/perf_event.h>
21 #include <linux/platform_device.h>
22 #include <linux/spinlock.h>
23 #include <linux/uaccess.h>
24
25 #include <asm/cputype.h>
26 #include <asm/irq.h>
27 #include <asm/irq_regs.h>
28 #include <asm/pmu.h>
29 #include <asm/stacktrace.h>
30
31 static struct platform_device *pmu_device;
32
33 /*
34 * Hardware lock to serialize accesses to PMU registers. Needed for the
35 * read/modify/write sequences.
36 */
37 DEFINE_SPINLOCK(pmu_lock);
38
39 /*
40 * ARMv6 supports a maximum of 3 events, starting from index 1. If we add
41 * another platform that supports more, we need to increase this to be the
42 * largest of all platforms.
43 *
44 * ARMv7 supports up to 32 events:
45 * cycle counter CCNT + 31 events counters CNT0..30.
46 * Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters.
47 */
48 #define ARMPMU_MAX_HWEVENTS 33
49
50 /* The events for a given CPU. */
51 struct cpu_hw_events {
52 /*
53 * The events that are active on the CPU for the given index. Index 0
54 * is reserved.
55 */
56 struct perf_event *events[ARMPMU_MAX_HWEVENTS];
57
58 /*
59 * A 1 bit for an index indicates that the counter is being used for
60 * an event. A 0 means that the counter can be used.
61 */
62 unsigned long used_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)];
63
64 /*
65 * A 1 bit for an index indicates that the counter is actively being
66 * used.
67 */
68 unsigned long active_mask[BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)];
69 };
70 DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
71
72 /* PMU names. */
73 static const char *arm_pmu_names[] = {
74 [ARM_PERF_PMU_ID_XSCALE1] = "xscale1",
75 [ARM_PERF_PMU_ID_XSCALE2] = "xscale2",
76 [ARM_PERF_PMU_ID_V6] = "v6",
77 [ARM_PERF_PMU_ID_V6MP] = "v6mpcore",
78 [ARM_PERF_PMU_ID_CA8] = "ARMv7 Cortex-A8",
79 [ARM_PERF_PMU_ID_CA9] = "ARMv7 Cortex-A9",
80 };
81
82 struct arm_pmu {
83 enum arm_perf_pmu_ids id;
84 irqreturn_t (*handle_irq)(int irq_num, void *dev);
85 void (*enable)(struct hw_perf_event *evt, int idx);
86 void (*disable)(struct hw_perf_event *evt, int idx);
87 int (*get_event_idx)(struct cpu_hw_events *cpuc,
88 struct hw_perf_event *hwc);
89 u32 (*read_counter)(int idx);
90 void (*write_counter)(int idx, u32 val);
91 void (*start)(void);
92 void (*stop)(void);
93 const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX]
94 [PERF_COUNT_HW_CACHE_OP_MAX]
95 [PERF_COUNT_HW_CACHE_RESULT_MAX];
96 const unsigned (*event_map)[PERF_COUNT_HW_MAX];
97 u32 raw_event_mask;
98 int num_events;
99 u64 max_period;
100 };
101
102 /* Set at runtime when we know what CPU type we are. */
103 static const struct arm_pmu *armpmu;
104
105 enum arm_perf_pmu_ids
106 armpmu_get_pmu_id(void)
107 {
108 int id = -ENODEV;
109
110 if (armpmu != NULL)
111 id = armpmu->id;
112
113 return id;
114 }
115 EXPORT_SYMBOL_GPL(armpmu_get_pmu_id);
116
117 int
118 armpmu_get_max_events(void)
119 {
120 int max_events = 0;
121
122 if (armpmu != NULL)
123 max_events = armpmu->num_events;
124
125 return max_events;
126 }
127 EXPORT_SYMBOL_GPL(armpmu_get_max_events);
128
129 int perf_num_counters(void)
130 {
131 return armpmu_get_max_events();
132 }
133 EXPORT_SYMBOL_GPL(perf_num_counters);
134
135 #define HW_OP_UNSUPPORTED 0xFFFF
136
137 #define C(_x) \
138 PERF_COUNT_HW_CACHE_##_x
139
140 #define CACHE_OP_UNSUPPORTED 0xFFFF
141
142 static int
143 armpmu_map_cache_event(u64 config)
144 {
145 unsigned int cache_type, cache_op, cache_result, ret;
146
147 cache_type = (config >> 0) & 0xff;
148 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
149 return -EINVAL;
150
151 cache_op = (config >> 8) & 0xff;
152 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
153 return -EINVAL;
154
155 cache_result = (config >> 16) & 0xff;
156 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
157 return -EINVAL;
158
159 ret = (int)(*armpmu->cache_map)[cache_type][cache_op][cache_result];
160
161 if (ret == CACHE_OP_UNSUPPORTED)
162 return -ENOENT;
163
164 return ret;
165 }
166
167 static int
168 armpmu_map_event(u64 config)
169 {
170 int mapping = (*armpmu->event_map)[config];
171 return mapping == HW_OP_UNSUPPORTED ? -EOPNOTSUPP : mapping;
172 }
173
174 static int
175 armpmu_map_raw_event(u64 config)
176 {
177 return (int)(config & armpmu->raw_event_mask);
178 }
179
180 static int
181 armpmu_event_set_period(struct perf_event *event,
182 struct hw_perf_event *hwc,
183 int idx)
184 {
185 s64 left = local64_read(&hwc->period_left);
186 s64 period = hwc->sample_period;
187 int ret = 0;
188
189 if (unlikely(left <= -period)) {
190 left = period;
191 local64_set(&hwc->period_left, left);
192 hwc->last_period = period;
193 ret = 1;
194 }
195
196 if (unlikely(left <= 0)) {
197 left += period;
198 local64_set(&hwc->period_left, left);
199 hwc->last_period = period;
200 ret = 1;
201 }
202
203 if (left > (s64)armpmu->max_period)
204 left = armpmu->max_period;
205
206 local64_set(&hwc->prev_count, (u64)-left);
207
208 armpmu->write_counter(idx, (u64)(-left) & 0xffffffff);
209
210 perf_event_update_userpage(event);
211
212 return ret;
213 }
214
215 static u64
216 armpmu_event_update(struct perf_event *event,
217 struct hw_perf_event *hwc,
218 int idx)
219 {
220 int shift = 64 - 32;
221 s64 prev_raw_count, new_raw_count;
222 u64 delta;
223
224 again:
225 prev_raw_count = local64_read(&hwc->prev_count);
226 new_raw_count = armpmu->read_counter(idx);
227
228 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
229 new_raw_count) != prev_raw_count)
230 goto again;
231
232 delta = (new_raw_count << shift) - (prev_raw_count << shift);
233 delta >>= shift;
234
235 local64_add(delta, &event->count);
236 local64_sub(delta, &hwc->period_left);
237
238 return new_raw_count;
239 }
240
241 static void
242 armpmu_read(struct perf_event *event)
243 {
244 struct hw_perf_event *hwc = &event->hw;
245
246 /* Don't read disabled counters! */
247 if (hwc->idx < 0)
248 return;
249
250 armpmu_event_update(event, hwc, hwc->idx);
251 }
252
253 static void
254 armpmu_stop(struct perf_event *event, int flags)
255 {
256 struct hw_perf_event *hwc = &event->hw;
257
258 if (!armpmu)
259 return;
260
261 /*
262 * ARM pmu always has to update the counter, so ignore
263 * PERF_EF_UPDATE, see comments in armpmu_start().
264 */
265 if (!(hwc->state & PERF_HES_STOPPED)) {
266 armpmu->disable(hwc, hwc->idx);
267 barrier(); /* why? */
268 armpmu_event_update(event, hwc, hwc->idx);
269 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
270 }
271 }
272
273 static void
274 armpmu_start(struct perf_event *event, int flags)
275 {
276 struct hw_perf_event *hwc = &event->hw;
277
278 if (!armpmu)
279 return;
280
281 /*
282 * ARM pmu always has to reprogram the period, so ignore
283 * PERF_EF_RELOAD, see the comment below.
284 */
285 if (flags & PERF_EF_RELOAD)
286 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
287
288 hwc->state = 0;
289 /*
290 * Set the period again. Some counters can't be stopped, so when we
291 * were stopped we simply disabled the IRQ source and the counter
292 * may have been left counting. If we don't do this step then we may
293 * get an interrupt too soon or *way* too late if the overflow has
294 * happened since disabling.
295 */
296 armpmu_event_set_period(event, hwc, hwc->idx);
297 armpmu->enable(hwc, hwc->idx);
298 }
299
300 static void
301 armpmu_del(struct perf_event *event, int flags)
302 {
303 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
304 struct hw_perf_event *hwc = &event->hw;
305 int idx = hwc->idx;
306
307 WARN_ON(idx < 0);
308
309 clear_bit(idx, cpuc->active_mask);
310 armpmu_stop(event, PERF_EF_UPDATE);
311 cpuc->events[idx] = NULL;
312 clear_bit(idx, cpuc->used_mask);
313
314 perf_event_update_userpage(event);
315 }
316
317 static int
318 armpmu_add(struct perf_event *event, int flags)
319 {
320 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
321 struct hw_perf_event *hwc = &event->hw;
322 int idx;
323 int err = 0;
324
325 perf_pmu_disable(event->pmu);
326
327 /* If we don't have a space for the counter then finish early. */
328 idx = armpmu->get_event_idx(cpuc, hwc);
329 if (idx < 0) {
330 err = idx;
331 goto out;
332 }
333
334 /*
335 * If there is an event in the counter we are going to use then make
336 * sure it is disabled.
337 */
338 event->hw.idx = idx;
339 armpmu->disable(hwc, idx);
340 cpuc->events[idx] = event;
341 set_bit(idx, cpuc->active_mask);
342
343 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
344 if (flags & PERF_EF_START)
345 armpmu_start(event, PERF_EF_RELOAD);
346
347 /* Propagate our changes to the userspace mapping. */
348 perf_event_update_userpage(event);
349
350 out:
351 perf_pmu_enable(event->pmu);
352 return err;
353 }
354
355 static struct pmu pmu;
356
357 static int
358 validate_event(struct cpu_hw_events *cpuc,
359 struct perf_event *event)
360 {
361 struct hw_perf_event fake_event = event->hw;
362
363 if (event->pmu != &pmu || event->state <= PERF_EVENT_STATE_OFF)
364 return 1;
365
366 return armpmu->get_event_idx(cpuc, &fake_event) >= 0;
367 }
368
369 static int
370 validate_group(struct perf_event *event)
371 {
372 struct perf_event *sibling, *leader = event->group_leader;
373 struct cpu_hw_events fake_pmu;
374
375 memset(&fake_pmu, 0, sizeof(fake_pmu));
376
377 if (!validate_event(&fake_pmu, leader))
378 return -ENOSPC;
379
380 list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
381 if (!validate_event(&fake_pmu, sibling))
382 return -ENOSPC;
383 }
384
385 if (!validate_event(&fake_pmu, event))
386 return -ENOSPC;
387
388 return 0;
389 }
390
391 static int
392 armpmu_reserve_hardware(void)
393 {
394 int i, err = -ENODEV, irq;
395
396 pmu_device = reserve_pmu(ARM_PMU_DEVICE_CPU);
397 if (IS_ERR(pmu_device)) {
398 pr_warning("unable to reserve pmu\n");
399 return PTR_ERR(pmu_device);
400 }
401
402 init_pmu(ARM_PMU_DEVICE_CPU);
403
404 if (pmu_device->num_resources < 1) {
405 pr_err("no irqs for PMUs defined\n");
406 return -ENODEV;
407 }
408
409 for (i = 0; i < pmu_device->num_resources; ++i) {
410 irq = platform_get_irq(pmu_device, i);
411 if (irq < 0)
412 continue;
413
414 err = request_irq(irq, armpmu->handle_irq,
415 IRQF_DISABLED | IRQF_NOBALANCING,
416 "armpmu", NULL);
417 if (err) {
418 pr_warning("unable to request IRQ%d for ARM perf "
419 "counters\n", irq);
420 break;
421 }
422 }
423
424 if (err) {
425 for (i = i - 1; i >= 0; --i) {
426 irq = platform_get_irq(pmu_device, i);
427 if (irq >= 0)
428 free_irq(irq, NULL);
429 }
430 release_pmu(pmu_device);
431 pmu_device = NULL;
432 }
433
434 return err;
435 }
436
437 static void
438 armpmu_release_hardware(void)
439 {
440 int i, irq;
441
442 for (i = pmu_device->num_resources - 1; i >= 0; --i) {
443 irq = platform_get_irq(pmu_device, i);
444 if (irq >= 0)
445 free_irq(irq, NULL);
446 }
447 armpmu->stop();
448
449 release_pmu(pmu_device);
450 pmu_device = NULL;
451 }
452
453 static atomic_t active_events = ATOMIC_INIT(0);
454 static DEFINE_MUTEX(pmu_reserve_mutex);
455
456 static void
457 hw_perf_event_destroy(struct perf_event *event)
458 {
459 if (atomic_dec_and_mutex_lock(&active_events, &pmu_reserve_mutex)) {
460 armpmu_release_hardware();
461 mutex_unlock(&pmu_reserve_mutex);
462 }
463 }
464
465 static int
466 __hw_perf_event_init(struct perf_event *event)
467 {
468 struct hw_perf_event *hwc = &event->hw;
469 int mapping, err;
470
471 /* Decode the generic type into an ARM event identifier. */
472 if (PERF_TYPE_HARDWARE == event->attr.type) {
473 mapping = armpmu_map_event(event->attr.config);
474 } else if (PERF_TYPE_HW_CACHE == event->attr.type) {
475 mapping = armpmu_map_cache_event(event->attr.config);
476 } else if (PERF_TYPE_RAW == event->attr.type) {
477 mapping = armpmu_map_raw_event(event->attr.config);
478 } else {
479 pr_debug("event type %x not supported\n", event->attr.type);
480 return -EOPNOTSUPP;
481 }
482
483 if (mapping < 0) {
484 pr_debug("event %x:%llx not supported\n", event->attr.type,
485 event->attr.config);
486 return mapping;
487 }
488
489 /*
490 * Check whether we need to exclude the counter from certain modes.
491 * The ARM performance counters are on all of the time so if someone
492 * has asked us for some excludes then we have to fail.
493 */
494 if (event->attr.exclude_kernel || event->attr.exclude_user ||
495 event->attr.exclude_hv || event->attr.exclude_idle) {
496 pr_debug("ARM performance counters do not support "
497 "mode exclusion\n");
498 return -EPERM;
499 }
500
501 /*
502 * We don't assign an index until we actually place the event onto
503 * hardware. Use -1 to signify that we haven't decided where to put it
504 * yet. For SMP systems, each core has it's own PMU so we can't do any
505 * clever allocation or constraints checking at this point.
506 */
507 hwc->idx = -1;
508
509 /*
510 * Store the event encoding into the config_base field. config and
511 * event_base are unused as the only 2 things we need to know are
512 * the event mapping and the counter to use. The counter to use is
513 * also the indx and the config_base is the event type.
514 */
515 hwc->config_base = (unsigned long)mapping;
516 hwc->config = 0;
517 hwc->event_base = 0;
518
519 if (!hwc->sample_period) {
520 hwc->sample_period = armpmu->max_period;
521 hwc->last_period = hwc->sample_period;
522 local64_set(&hwc->period_left, hwc->sample_period);
523 }
524
525 err = 0;
526 if (event->group_leader != event) {
527 err = validate_group(event);
528 if (err)
529 return -EINVAL;
530 }
531
532 return err;
533 }
534
535 static int armpmu_event_init(struct perf_event *event)
536 {
537 int err = 0;
538
539 switch (event->attr.type) {
540 case PERF_TYPE_RAW:
541 case PERF_TYPE_HARDWARE:
542 case PERF_TYPE_HW_CACHE:
543 break;
544
545 default:
546 return -ENOENT;
547 }
548
549 if (!armpmu)
550 return -ENODEV;
551
552 event->destroy = hw_perf_event_destroy;
553
554 if (!atomic_inc_not_zero(&active_events)) {
555 if (atomic_read(&active_events) > armpmu->num_events) {
556 atomic_dec(&active_events);
557 return -ENOSPC;
558 }
559
560 mutex_lock(&pmu_reserve_mutex);
561 if (atomic_read(&active_events) == 0) {
562 err = armpmu_reserve_hardware();
563 }
564
565 if (!err)
566 atomic_inc(&active_events);
567 mutex_unlock(&pmu_reserve_mutex);
568 }
569
570 if (err)
571 return err;
572
573 err = __hw_perf_event_init(event);
574 if (err)
575 hw_perf_event_destroy(event);
576
577 return err;
578 }
579
580 static void armpmu_enable(struct pmu *pmu)
581 {
582 /* Enable all of the perf events on hardware. */
583 int idx;
584 struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
585
586 if (!armpmu)
587 return;
588
589 for (idx = 0; idx <= armpmu->num_events; ++idx) {
590 struct perf_event *event = cpuc->events[idx];
591
592 if (!event)
593 continue;
594
595 armpmu->enable(&event->hw, idx);
596 }
597
598 armpmu->start();
599 }
600
601 static void armpmu_disable(struct pmu *pmu)
602 {
603 if (armpmu)
604 armpmu->stop();
605 }
606
607 static struct pmu pmu = {
608 .pmu_enable = armpmu_enable,
609 .pmu_disable = armpmu_disable,
610 .event_init = armpmu_event_init,
611 .add = armpmu_add,
612 .del = armpmu_del,
613 .start = armpmu_start,
614 .stop = armpmu_stop,
615 .read = armpmu_read,
616 };
617
618 /*
619 * ARMv6 Performance counter handling code.
620 *
621 * ARMv6 has 2 configurable performance counters and a single cycle counter.
622 * They all share a single reset bit but can be written to zero so we can use
623 * that for a reset.
624 *
625 * The counters can't be individually enabled or disabled so when we remove
626 * one event and replace it with another we could get spurious counts from the
627 * wrong event. However, we can take advantage of the fact that the
628 * performance counters can export events to the event bus, and the event bus
629 * itself can be monitored. This requires that we *don't* export the events to
630 * the event bus. The procedure for disabling a configurable counter is:
631 * - change the counter to count the ETMEXTOUT[0] signal (0x20). This
632 * effectively stops the counter from counting.
633 * - disable the counter's interrupt generation (each counter has it's
634 * own interrupt enable bit).
635 * Once stopped, the counter value can be written as 0 to reset.
636 *
637 * To enable a counter:
638 * - enable the counter's interrupt generation.
639 * - set the new event type.
640 *
641 * Note: the dedicated cycle counter only counts cycles and can't be
642 * enabled/disabled independently of the others. When we want to disable the
643 * cycle counter, we have to just disable the interrupt reporting and start
644 * ignoring that counter. When re-enabling, we have to reset the value and
645 * enable the interrupt.
646 */
647
648 enum armv6_perf_types {
649 ARMV6_PERFCTR_ICACHE_MISS = 0x0,
650 ARMV6_PERFCTR_IBUF_STALL = 0x1,
651 ARMV6_PERFCTR_DDEP_STALL = 0x2,
652 ARMV6_PERFCTR_ITLB_MISS = 0x3,
653 ARMV6_PERFCTR_DTLB_MISS = 0x4,
654 ARMV6_PERFCTR_BR_EXEC = 0x5,
655 ARMV6_PERFCTR_BR_MISPREDICT = 0x6,
656 ARMV6_PERFCTR_INSTR_EXEC = 0x7,
657 ARMV6_PERFCTR_DCACHE_HIT = 0x9,
658 ARMV6_PERFCTR_DCACHE_ACCESS = 0xA,
659 ARMV6_PERFCTR_DCACHE_MISS = 0xB,
660 ARMV6_PERFCTR_DCACHE_WBACK = 0xC,
661 ARMV6_PERFCTR_SW_PC_CHANGE = 0xD,
662 ARMV6_PERFCTR_MAIN_TLB_MISS = 0xF,
663 ARMV6_PERFCTR_EXPL_D_ACCESS = 0x10,
664 ARMV6_PERFCTR_LSU_FULL_STALL = 0x11,
665 ARMV6_PERFCTR_WBUF_DRAINED = 0x12,
666 ARMV6_PERFCTR_CPU_CYCLES = 0xFF,
667 ARMV6_PERFCTR_NOP = 0x20,
668 };
669
670 enum armv6_counters {
671 ARMV6_CYCLE_COUNTER = 1,
672 ARMV6_COUNTER0,
673 ARMV6_COUNTER1,
674 };
675
676 /*
677 * The hardware events that we support. We do support cache operations but
678 * we have harvard caches and no way to combine instruction and data
679 * accesses/misses in hardware.
680 */
681 static const unsigned armv6_perf_map[PERF_COUNT_HW_MAX] = {
682 [PERF_COUNT_HW_CPU_CYCLES] = ARMV6_PERFCTR_CPU_CYCLES,
683 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV6_PERFCTR_INSTR_EXEC,
684 [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED,
685 [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED,
686 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6_PERFCTR_BR_EXEC,
687 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV6_PERFCTR_BR_MISPREDICT,
688 [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
689 };
690
691 static const unsigned armv6_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
692 [PERF_COUNT_HW_CACHE_OP_MAX]
693 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
694 [C(L1D)] = {
695 /*
696 * The performance counters don't differentiate between read
697 * and write accesses/misses so this isn't strictly correct,
698 * but it's the best we can do. Writes and reads get
699 * combined.
700 */
701 [C(OP_READ)] = {
702 [C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS,
703 [C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS,
704 },
705 [C(OP_WRITE)] = {
706 [C(RESULT_ACCESS)] = ARMV6_PERFCTR_DCACHE_ACCESS,
707 [C(RESULT_MISS)] = ARMV6_PERFCTR_DCACHE_MISS,
708 },
709 [C(OP_PREFETCH)] = {
710 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
711 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
712 },
713 },
714 [C(L1I)] = {
715 [C(OP_READ)] = {
716 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
717 [C(RESULT_MISS)] = ARMV6_PERFCTR_ICACHE_MISS,
718 },
719 [C(OP_WRITE)] = {
720 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
721 [C(RESULT_MISS)] = ARMV6_PERFCTR_ICACHE_MISS,
722 },
723 [C(OP_PREFETCH)] = {
724 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
725 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
726 },
727 },
728 [C(LL)] = {
729 [C(OP_READ)] = {
730 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
731 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
732 },
733 [C(OP_WRITE)] = {
734 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
735 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
736 },
737 [C(OP_PREFETCH)] = {
738 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
739 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
740 },
741 },
742 [C(DTLB)] = {
743 /*
744 * The ARM performance counters can count micro DTLB misses,
745 * micro ITLB misses and main TLB misses. There isn't an event
746 * for TLB misses, so use the micro misses here and if users
747 * want the main TLB misses they can use a raw counter.
748 */
749 [C(OP_READ)] = {
750 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
751 [C(RESULT_MISS)] = ARMV6_PERFCTR_DTLB_MISS,
752 },
753 [C(OP_WRITE)] = {
754 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
755 [C(RESULT_MISS)] = ARMV6_PERFCTR_DTLB_MISS,
756 },
757 [C(OP_PREFETCH)] = {
758 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
759 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
760 },
761 },
762 [C(ITLB)] = {
763 [C(OP_READ)] = {
764 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
765 [C(RESULT_MISS)] = ARMV6_PERFCTR_ITLB_MISS,
766 },
767 [C(OP_WRITE)] = {
768 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
769 [C(RESULT_MISS)] = ARMV6_PERFCTR_ITLB_MISS,
770 },
771 [C(OP_PREFETCH)] = {
772 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
773 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
774 },
775 },
776 [C(BPU)] = {
777 [C(OP_READ)] = {
778 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
779 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
780 },
781 [C(OP_WRITE)] = {
782 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
783 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
784 },
785 [C(OP_PREFETCH)] = {
786 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
787 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
788 },
789 },
790 };
791
792 enum armv6mpcore_perf_types {
793 ARMV6MPCORE_PERFCTR_ICACHE_MISS = 0x0,
794 ARMV6MPCORE_PERFCTR_IBUF_STALL = 0x1,
795 ARMV6MPCORE_PERFCTR_DDEP_STALL = 0x2,
796 ARMV6MPCORE_PERFCTR_ITLB_MISS = 0x3,
797 ARMV6MPCORE_PERFCTR_DTLB_MISS = 0x4,
798 ARMV6MPCORE_PERFCTR_BR_EXEC = 0x5,
799 ARMV6MPCORE_PERFCTR_BR_NOTPREDICT = 0x6,
800 ARMV6MPCORE_PERFCTR_BR_MISPREDICT = 0x7,
801 ARMV6MPCORE_PERFCTR_INSTR_EXEC = 0x8,
802 ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS = 0xA,
803 ARMV6MPCORE_PERFCTR_DCACHE_RDMISS = 0xB,
804 ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS = 0xC,
805 ARMV6MPCORE_PERFCTR_DCACHE_WRMISS = 0xD,
806 ARMV6MPCORE_PERFCTR_DCACHE_EVICTION = 0xE,
807 ARMV6MPCORE_PERFCTR_SW_PC_CHANGE = 0xF,
808 ARMV6MPCORE_PERFCTR_MAIN_TLB_MISS = 0x10,
809 ARMV6MPCORE_PERFCTR_EXPL_MEM_ACCESS = 0x11,
810 ARMV6MPCORE_PERFCTR_LSU_FULL_STALL = 0x12,
811 ARMV6MPCORE_PERFCTR_WBUF_DRAINED = 0x13,
812 ARMV6MPCORE_PERFCTR_CPU_CYCLES = 0xFF,
813 };
814
815 /*
816 * The hardware events that we support. We do support cache operations but
817 * we have harvard caches and no way to combine instruction and data
818 * accesses/misses in hardware.
819 */
820 static const unsigned armv6mpcore_perf_map[PERF_COUNT_HW_MAX] = {
821 [PERF_COUNT_HW_CPU_CYCLES] = ARMV6MPCORE_PERFCTR_CPU_CYCLES,
822 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_INSTR_EXEC,
823 [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED,
824 [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED,
825 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV6MPCORE_PERFCTR_BR_EXEC,
826 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV6MPCORE_PERFCTR_BR_MISPREDICT,
827 [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
828 };
829
830 static const unsigned armv6mpcore_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
831 [PERF_COUNT_HW_CACHE_OP_MAX]
832 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
833 [C(L1D)] = {
834 [C(OP_READ)] = {
835 [C(RESULT_ACCESS)] =
836 ARMV6MPCORE_PERFCTR_DCACHE_RDACCESS,
837 [C(RESULT_MISS)] =
838 ARMV6MPCORE_PERFCTR_DCACHE_RDMISS,
839 },
840 [C(OP_WRITE)] = {
841 [C(RESULT_ACCESS)] =
842 ARMV6MPCORE_PERFCTR_DCACHE_WRACCESS,
843 [C(RESULT_MISS)] =
844 ARMV6MPCORE_PERFCTR_DCACHE_WRMISS,
845 },
846 [C(OP_PREFETCH)] = {
847 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
848 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
849 },
850 },
851 [C(L1I)] = {
852 [C(OP_READ)] = {
853 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
854 [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ICACHE_MISS,
855 },
856 [C(OP_WRITE)] = {
857 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
858 [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ICACHE_MISS,
859 },
860 [C(OP_PREFETCH)] = {
861 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
862 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
863 },
864 },
865 [C(LL)] = {
866 [C(OP_READ)] = {
867 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
868 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
869 },
870 [C(OP_WRITE)] = {
871 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
872 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
873 },
874 [C(OP_PREFETCH)] = {
875 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
876 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
877 },
878 },
879 [C(DTLB)] = {
880 /*
881 * The ARM performance counters can count micro DTLB misses,
882 * micro ITLB misses and main TLB misses. There isn't an event
883 * for TLB misses, so use the micro misses here and if users
884 * want the main TLB misses they can use a raw counter.
885 */
886 [C(OP_READ)] = {
887 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
888 [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DTLB_MISS,
889 },
890 [C(OP_WRITE)] = {
891 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
892 [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_DTLB_MISS,
893 },
894 [C(OP_PREFETCH)] = {
895 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
896 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
897 },
898 },
899 [C(ITLB)] = {
900 [C(OP_READ)] = {
901 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
902 [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ITLB_MISS,
903 },
904 [C(OP_WRITE)] = {
905 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
906 [C(RESULT_MISS)] = ARMV6MPCORE_PERFCTR_ITLB_MISS,
907 },
908 [C(OP_PREFETCH)] = {
909 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
910 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
911 },
912 },
913 [C(BPU)] = {
914 [C(OP_READ)] = {
915 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
916 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
917 },
918 [C(OP_WRITE)] = {
919 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
920 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
921 },
922 [C(OP_PREFETCH)] = {
923 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
924 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
925 },
926 },
927 };
928
929 static inline unsigned long
930 armv6_pmcr_read(void)
931 {
932 u32 val;
933 asm volatile("mrc p15, 0, %0, c15, c12, 0" : "=r"(val));
934 return val;
935 }
936
937 static inline void
938 armv6_pmcr_write(unsigned long val)
939 {
940 asm volatile("mcr p15, 0, %0, c15, c12, 0" : : "r"(val));
941 }
942
943 #define ARMV6_PMCR_ENABLE (1 << 0)
944 #define ARMV6_PMCR_CTR01_RESET (1 << 1)
945 #define ARMV6_PMCR_CCOUNT_RESET (1 << 2)
946 #define ARMV6_PMCR_CCOUNT_DIV (1 << 3)
947 #define ARMV6_PMCR_COUNT0_IEN (1 << 4)
948 #define ARMV6_PMCR_COUNT1_IEN (1 << 5)
949 #define ARMV6_PMCR_CCOUNT_IEN (1 << 6)
950 #define ARMV6_PMCR_COUNT0_OVERFLOW (1 << 8)
951 #define ARMV6_PMCR_COUNT1_OVERFLOW (1 << 9)
952 #define ARMV6_PMCR_CCOUNT_OVERFLOW (1 << 10)
953 #define ARMV6_PMCR_EVT_COUNT0_SHIFT 20
954 #define ARMV6_PMCR_EVT_COUNT0_MASK (0xFF << ARMV6_PMCR_EVT_COUNT0_SHIFT)
955 #define ARMV6_PMCR_EVT_COUNT1_SHIFT 12
956 #define ARMV6_PMCR_EVT_COUNT1_MASK (0xFF << ARMV6_PMCR_EVT_COUNT1_SHIFT)
957
958 #define ARMV6_PMCR_OVERFLOWED_MASK \
959 (ARMV6_PMCR_COUNT0_OVERFLOW | ARMV6_PMCR_COUNT1_OVERFLOW | \
960 ARMV6_PMCR_CCOUNT_OVERFLOW)
961
962 static inline int
963 armv6_pmcr_has_overflowed(unsigned long pmcr)
964 {
965 return (pmcr & ARMV6_PMCR_OVERFLOWED_MASK);
966 }
967
968 static inline int
969 armv6_pmcr_counter_has_overflowed(unsigned long pmcr,
970 enum armv6_counters counter)
971 {
972 int ret = 0;
973
974 if (ARMV6_CYCLE_COUNTER == counter)
975 ret = pmcr & ARMV6_PMCR_CCOUNT_OVERFLOW;
976 else if (ARMV6_COUNTER0 == counter)
977 ret = pmcr & ARMV6_PMCR_COUNT0_OVERFLOW;
978 else if (ARMV6_COUNTER1 == counter)
979 ret = pmcr & ARMV6_PMCR_COUNT1_OVERFLOW;
980 else
981 WARN_ONCE(1, "invalid counter number (%d)\n", counter);
982
983 return ret;
984 }
985
986 static inline u32
987 armv6pmu_read_counter(int counter)
988 {
989 unsigned long value = 0;
990
991 if (ARMV6_CYCLE_COUNTER == counter)
992 asm volatile("mrc p15, 0, %0, c15, c12, 1" : "=r"(value));
993 else if (ARMV6_COUNTER0 == counter)
994 asm volatile("mrc p15, 0, %0, c15, c12, 2" : "=r"(value));
995 else if (ARMV6_COUNTER1 == counter)
996 asm volatile("mrc p15, 0, %0, c15, c12, 3" : "=r"(value));
997 else
998 WARN_ONCE(1, "invalid counter number (%d)\n", counter);
999
1000 return value;
1001 }
1002
1003 static inline void
1004 armv6pmu_write_counter(int counter,
1005 u32 value)
1006 {
1007 if (ARMV6_CYCLE_COUNTER == counter)
1008 asm volatile("mcr p15, 0, %0, c15, c12, 1" : : "r"(value));
1009 else if (ARMV6_COUNTER0 == counter)
1010 asm volatile("mcr p15, 0, %0, c15, c12, 2" : : "r"(value));
1011 else if (ARMV6_COUNTER1 == counter)
1012 asm volatile("mcr p15, 0, %0, c15, c12, 3" : : "r"(value));
1013 else
1014 WARN_ONCE(1, "invalid counter number (%d)\n", counter);
1015 }
1016
1017 void
1018 armv6pmu_enable_event(struct hw_perf_event *hwc,
1019 int idx)
1020 {
1021 unsigned long val, mask, evt, flags;
1022
1023 if (ARMV6_CYCLE_COUNTER == idx) {
1024 mask = 0;
1025 evt = ARMV6_PMCR_CCOUNT_IEN;
1026 } else if (ARMV6_COUNTER0 == idx) {
1027 mask = ARMV6_PMCR_EVT_COUNT0_MASK;
1028 evt = (hwc->config_base << ARMV6_PMCR_EVT_COUNT0_SHIFT) |
1029 ARMV6_PMCR_COUNT0_IEN;
1030 } else if (ARMV6_COUNTER1 == idx) {
1031 mask = ARMV6_PMCR_EVT_COUNT1_MASK;
1032 evt = (hwc->config_base << ARMV6_PMCR_EVT_COUNT1_SHIFT) |
1033 ARMV6_PMCR_COUNT1_IEN;
1034 } else {
1035 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
1036 return;
1037 }
1038
1039 /*
1040 * Mask out the current event and set the counter to count the event
1041 * that we're interested in.
1042 */
1043 spin_lock_irqsave(&pmu_lock, flags);
1044 val = armv6_pmcr_read();
1045 val &= ~mask;
1046 val |= evt;
1047 armv6_pmcr_write(val);
1048 spin_unlock_irqrestore(&pmu_lock, flags);
1049 }
1050
1051 static irqreturn_t
1052 armv6pmu_handle_irq(int irq_num,
1053 void *dev)
1054 {
1055 unsigned long pmcr = armv6_pmcr_read();
1056 struct perf_sample_data data;
1057 struct cpu_hw_events *cpuc;
1058 struct pt_regs *regs;
1059 int idx;
1060
1061 if (!armv6_pmcr_has_overflowed(pmcr))
1062 return IRQ_NONE;
1063
1064 regs = get_irq_regs();
1065
1066 /*
1067 * The interrupts are cleared by writing the overflow flags back to
1068 * the control register. All of the other bits don't have any effect
1069 * if they are rewritten, so write the whole value back.
1070 */
1071 armv6_pmcr_write(pmcr);
1072
1073 perf_sample_data_init(&data, 0);
1074
1075 cpuc = &__get_cpu_var(cpu_hw_events);
1076 for (idx = 0; idx <= armpmu->num_events; ++idx) {
1077 struct perf_event *event = cpuc->events[idx];
1078 struct hw_perf_event *hwc;
1079
1080 if (!test_bit(idx, cpuc->active_mask))
1081 continue;
1082
1083 /*
1084 * We have a single interrupt for all counters. Check that
1085 * each counter has overflowed before we process it.
1086 */
1087 if (!armv6_pmcr_counter_has_overflowed(pmcr, idx))
1088 continue;
1089
1090 hwc = &event->hw;
1091 armpmu_event_update(event, hwc, idx);
1092 data.period = event->hw.last_period;
1093 if (!armpmu_event_set_period(event, hwc, idx))
1094 continue;
1095
1096 if (perf_event_overflow(event, 0, &data, regs))
1097 armpmu->disable(hwc, idx);
1098 }
1099
1100 /*
1101 * Handle the pending perf events.
1102 *
1103 * Note: this call *must* be run with interrupts disabled. For
1104 * platforms that can have the PMU interrupts raised as an NMI, this
1105 * will not work.
1106 */
1107 irq_work_run();
1108
1109 return IRQ_HANDLED;
1110 }
1111
1112 static void
1113 armv6pmu_start(void)
1114 {
1115 unsigned long flags, val;
1116
1117 spin_lock_irqsave(&pmu_lock, flags);
1118 val = armv6_pmcr_read();
1119 val |= ARMV6_PMCR_ENABLE;
1120 armv6_pmcr_write(val);
1121 spin_unlock_irqrestore(&pmu_lock, flags);
1122 }
1123
1124 static void
1125 armv6pmu_stop(void)
1126 {
1127 unsigned long flags, val;
1128
1129 spin_lock_irqsave(&pmu_lock, flags);
1130 val = armv6_pmcr_read();
1131 val &= ~ARMV6_PMCR_ENABLE;
1132 armv6_pmcr_write(val);
1133 spin_unlock_irqrestore(&pmu_lock, flags);
1134 }
1135
1136 static int
1137 armv6pmu_get_event_idx(struct cpu_hw_events *cpuc,
1138 struct hw_perf_event *event)
1139 {
1140 /* Always place a cycle counter into the cycle counter. */
1141 if (ARMV6_PERFCTR_CPU_CYCLES == event->config_base) {
1142 if (test_and_set_bit(ARMV6_CYCLE_COUNTER, cpuc->used_mask))
1143 return -EAGAIN;
1144
1145 return ARMV6_CYCLE_COUNTER;
1146 } else {
1147 /*
1148 * For anything other than a cycle counter, try and use
1149 * counter0 and counter1.
1150 */
1151 if (!test_and_set_bit(ARMV6_COUNTER1, cpuc->used_mask)) {
1152 return ARMV6_COUNTER1;
1153 }
1154
1155 if (!test_and_set_bit(ARMV6_COUNTER0, cpuc->used_mask)) {
1156 return ARMV6_COUNTER0;
1157 }
1158
1159 /* The counters are all in use. */
1160 return -EAGAIN;
1161 }
1162 }
1163
1164 static void
1165 armv6pmu_disable_event(struct hw_perf_event *hwc,
1166 int idx)
1167 {
1168 unsigned long val, mask, evt, flags;
1169
1170 if (ARMV6_CYCLE_COUNTER == idx) {
1171 mask = ARMV6_PMCR_CCOUNT_IEN;
1172 evt = 0;
1173 } else if (ARMV6_COUNTER0 == idx) {
1174 mask = ARMV6_PMCR_COUNT0_IEN | ARMV6_PMCR_EVT_COUNT0_MASK;
1175 evt = ARMV6_PERFCTR_NOP << ARMV6_PMCR_EVT_COUNT0_SHIFT;
1176 } else if (ARMV6_COUNTER1 == idx) {
1177 mask = ARMV6_PMCR_COUNT1_IEN | ARMV6_PMCR_EVT_COUNT1_MASK;
1178 evt = ARMV6_PERFCTR_NOP << ARMV6_PMCR_EVT_COUNT1_SHIFT;
1179 } else {
1180 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
1181 return;
1182 }
1183
1184 /*
1185 * Mask out the current event and set the counter to count the number
1186 * of ETM bus signal assertion cycles. The external reporting should
1187 * be disabled and so this should never increment.
1188 */
1189 spin_lock_irqsave(&pmu_lock, flags);
1190 val = armv6_pmcr_read();
1191 val &= ~mask;
1192 val |= evt;
1193 armv6_pmcr_write(val);
1194 spin_unlock_irqrestore(&pmu_lock, flags);
1195 }
1196
1197 static void
1198 armv6mpcore_pmu_disable_event(struct hw_perf_event *hwc,
1199 int idx)
1200 {
1201 unsigned long val, mask, flags, evt = 0;
1202
1203 if (ARMV6_CYCLE_COUNTER == idx) {
1204 mask = ARMV6_PMCR_CCOUNT_IEN;
1205 } else if (ARMV6_COUNTER0 == idx) {
1206 mask = ARMV6_PMCR_COUNT0_IEN;
1207 } else if (ARMV6_COUNTER1 == idx) {
1208 mask = ARMV6_PMCR_COUNT1_IEN;
1209 } else {
1210 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
1211 return;
1212 }
1213
1214 /*
1215 * Unlike UP ARMv6, we don't have a way of stopping the counters. We
1216 * simply disable the interrupt reporting.
1217 */
1218 spin_lock_irqsave(&pmu_lock, flags);
1219 val = armv6_pmcr_read();
1220 val &= ~mask;
1221 val |= evt;
1222 armv6_pmcr_write(val);
1223 spin_unlock_irqrestore(&pmu_lock, flags);
1224 }
1225
1226 static const struct arm_pmu armv6pmu = {
1227 .id = ARM_PERF_PMU_ID_V6,
1228 .handle_irq = armv6pmu_handle_irq,
1229 .enable = armv6pmu_enable_event,
1230 .disable = armv6pmu_disable_event,
1231 .read_counter = armv6pmu_read_counter,
1232 .write_counter = armv6pmu_write_counter,
1233 .get_event_idx = armv6pmu_get_event_idx,
1234 .start = armv6pmu_start,
1235 .stop = armv6pmu_stop,
1236 .cache_map = &armv6_perf_cache_map,
1237 .event_map = &armv6_perf_map,
1238 .raw_event_mask = 0xFF,
1239 .num_events = 3,
1240 .max_period = (1LLU << 32) - 1,
1241 };
1242
1243 const struct arm_pmu *__init armv6pmu_init(void)
1244 {
1245 return &armv6pmu;
1246 }
1247
1248 /*
1249 * ARMv6mpcore is almost identical to single core ARMv6 with the exception
1250 * that some of the events have different enumerations and that there is no
1251 * *hack* to stop the programmable counters. To stop the counters we simply
1252 * disable the interrupt reporting and update the event. When unthrottling we
1253 * reset the period and enable the interrupt reporting.
1254 */
1255 static const struct arm_pmu armv6mpcore_pmu = {
1256 .id = ARM_PERF_PMU_ID_V6MP,
1257 .handle_irq = armv6pmu_handle_irq,
1258 .enable = armv6pmu_enable_event,
1259 .disable = armv6mpcore_pmu_disable_event,
1260 .read_counter = armv6pmu_read_counter,
1261 .write_counter = armv6pmu_write_counter,
1262 .get_event_idx = armv6pmu_get_event_idx,
1263 .start = armv6pmu_start,
1264 .stop = armv6pmu_stop,
1265 .cache_map = &armv6mpcore_perf_cache_map,
1266 .event_map = &armv6mpcore_perf_map,
1267 .raw_event_mask = 0xFF,
1268 .num_events = 3,
1269 .max_period = (1LLU << 32) - 1,
1270 };
1271
1272 const struct arm_pmu *__init armv6mpcore_pmu_init(void)
1273 {
1274 return &armv6mpcore_pmu;
1275 }
1276
1277 /*
1278 * ARMv7 Cortex-A8 and Cortex-A9 Performance Events handling code.
1279 *
1280 * Copied from ARMv6 code, with the low level code inspired
1281 * by the ARMv7 Oprofile code.
1282 *
1283 * Cortex-A8 has up to 4 configurable performance counters and
1284 * a single cycle counter.
1285 * Cortex-A9 has up to 31 configurable performance counters and
1286 * a single cycle counter.
1287 *
1288 * All counters can be enabled/disabled and IRQ masked separately. The cycle
1289 * counter and all 4 performance counters together can be reset separately.
1290 */
1291
1292 /* Common ARMv7 event types */
1293 enum armv7_perf_types {
1294 ARMV7_PERFCTR_PMNC_SW_INCR = 0x00,
1295 ARMV7_PERFCTR_IFETCH_MISS = 0x01,
1296 ARMV7_PERFCTR_ITLB_MISS = 0x02,
1297 ARMV7_PERFCTR_DCACHE_REFILL = 0x03,
1298 ARMV7_PERFCTR_DCACHE_ACCESS = 0x04,
1299 ARMV7_PERFCTR_DTLB_REFILL = 0x05,
1300 ARMV7_PERFCTR_DREAD = 0x06,
1301 ARMV7_PERFCTR_DWRITE = 0x07,
1302
1303 ARMV7_PERFCTR_EXC_TAKEN = 0x09,
1304 ARMV7_PERFCTR_EXC_EXECUTED = 0x0A,
1305 ARMV7_PERFCTR_CID_WRITE = 0x0B,
1306 /* ARMV7_PERFCTR_PC_WRITE is equivalent to HW_BRANCH_INSTRUCTIONS.
1307 * It counts:
1308 * - all branch instructions,
1309 * - instructions that explicitly write the PC,
1310 * - exception generating instructions.
1311 */
1312 ARMV7_PERFCTR_PC_WRITE = 0x0C,
1313 ARMV7_PERFCTR_PC_IMM_BRANCH = 0x0D,
1314 ARMV7_PERFCTR_UNALIGNED_ACCESS = 0x0F,
1315 ARMV7_PERFCTR_PC_BRANCH_MIS_PRED = 0x10,
1316 ARMV7_PERFCTR_CLOCK_CYCLES = 0x11,
1317
1318 ARMV7_PERFCTR_PC_BRANCH_MIS_USED = 0x12,
1319
1320 ARMV7_PERFCTR_CPU_CYCLES = 0xFF
1321 };
1322
1323 /* ARMv7 Cortex-A8 specific event types */
1324 enum armv7_a8_perf_types {
1325 ARMV7_PERFCTR_INSTR_EXECUTED = 0x08,
1326
1327 ARMV7_PERFCTR_PC_PROC_RETURN = 0x0E,
1328
1329 ARMV7_PERFCTR_WRITE_BUFFER_FULL = 0x40,
1330 ARMV7_PERFCTR_L2_STORE_MERGED = 0x41,
1331 ARMV7_PERFCTR_L2_STORE_BUFF = 0x42,
1332 ARMV7_PERFCTR_L2_ACCESS = 0x43,
1333 ARMV7_PERFCTR_L2_CACH_MISS = 0x44,
1334 ARMV7_PERFCTR_AXI_READ_CYCLES = 0x45,
1335 ARMV7_PERFCTR_AXI_WRITE_CYCLES = 0x46,
1336 ARMV7_PERFCTR_MEMORY_REPLAY = 0x47,
1337 ARMV7_PERFCTR_UNALIGNED_ACCESS_REPLAY = 0x48,
1338 ARMV7_PERFCTR_L1_DATA_MISS = 0x49,
1339 ARMV7_PERFCTR_L1_INST_MISS = 0x4A,
1340 ARMV7_PERFCTR_L1_DATA_COLORING = 0x4B,
1341 ARMV7_PERFCTR_L1_NEON_DATA = 0x4C,
1342 ARMV7_PERFCTR_L1_NEON_CACH_DATA = 0x4D,
1343 ARMV7_PERFCTR_L2_NEON = 0x4E,
1344 ARMV7_PERFCTR_L2_NEON_HIT = 0x4F,
1345 ARMV7_PERFCTR_L1_INST = 0x50,
1346 ARMV7_PERFCTR_PC_RETURN_MIS_PRED = 0x51,
1347 ARMV7_PERFCTR_PC_BRANCH_FAILED = 0x52,
1348 ARMV7_PERFCTR_PC_BRANCH_TAKEN = 0x53,
1349 ARMV7_PERFCTR_PC_BRANCH_EXECUTED = 0x54,
1350 ARMV7_PERFCTR_OP_EXECUTED = 0x55,
1351 ARMV7_PERFCTR_CYCLES_INST_STALL = 0x56,
1352 ARMV7_PERFCTR_CYCLES_INST = 0x57,
1353 ARMV7_PERFCTR_CYCLES_NEON_DATA_STALL = 0x58,
1354 ARMV7_PERFCTR_CYCLES_NEON_INST_STALL = 0x59,
1355 ARMV7_PERFCTR_NEON_CYCLES = 0x5A,
1356
1357 ARMV7_PERFCTR_PMU0_EVENTS = 0x70,
1358 ARMV7_PERFCTR_PMU1_EVENTS = 0x71,
1359 ARMV7_PERFCTR_PMU_EVENTS = 0x72,
1360 };
1361
1362 /* ARMv7 Cortex-A9 specific event types */
1363 enum armv7_a9_perf_types {
1364 ARMV7_PERFCTR_JAVA_HW_BYTECODE_EXEC = 0x40,
1365 ARMV7_PERFCTR_JAVA_SW_BYTECODE_EXEC = 0x41,
1366 ARMV7_PERFCTR_JAZELLE_BRANCH_EXEC = 0x42,
1367
1368 ARMV7_PERFCTR_COHERENT_LINE_MISS = 0x50,
1369 ARMV7_PERFCTR_COHERENT_LINE_HIT = 0x51,
1370
1371 ARMV7_PERFCTR_ICACHE_DEP_STALL_CYCLES = 0x60,
1372 ARMV7_PERFCTR_DCACHE_DEP_STALL_CYCLES = 0x61,
1373 ARMV7_PERFCTR_TLB_MISS_DEP_STALL_CYCLES = 0x62,
1374 ARMV7_PERFCTR_STREX_EXECUTED_PASSED = 0x63,
1375 ARMV7_PERFCTR_STREX_EXECUTED_FAILED = 0x64,
1376 ARMV7_PERFCTR_DATA_EVICTION = 0x65,
1377 ARMV7_PERFCTR_ISSUE_STAGE_NO_INST = 0x66,
1378 ARMV7_PERFCTR_ISSUE_STAGE_EMPTY = 0x67,
1379 ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE = 0x68,
1380
1381 ARMV7_PERFCTR_PREDICTABLE_FUNCT_RETURNS = 0x6E,
1382
1383 ARMV7_PERFCTR_MAIN_UNIT_EXECUTED_INST = 0x70,
1384 ARMV7_PERFCTR_SECOND_UNIT_EXECUTED_INST = 0x71,
1385 ARMV7_PERFCTR_LD_ST_UNIT_EXECUTED_INST = 0x72,
1386 ARMV7_PERFCTR_FP_EXECUTED_INST = 0x73,
1387 ARMV7_PERFCTR_NEON_EXECUTED_INST = 0x74,
1388
1389 ARMV7_PERFCTR_PLD_FULL_DEP_STALL_CYCLES = 0x80,
1390 ARMV7_PERFCTR_DATA_WR_DEP_STALL_CYCLES = 0x81,
1391 ARMV7_PERFCTR_ITLB_MISS_DEP_STALL_CYCLES = 0x82,
1392 ARMV7_PERFCTR_DTLB_MISS_DEP_STALL_CYCLES = 0x83,
1393 ARMV7_PERFCTR_MICRO_ITLB_MISS_DEP_STALL_CYCLES = 0x84,
1394 ARMV7_PERFCTR_MICRO_DTLB_MISS_DEP_STALL_CYCLES = 0x85,
1395 ARMV7_PERFCTR_DMB_DEP_STALL_CYCLES = 0x86,
1396
1397 ARMV7_PERFCTR_INTGR_CLK_ENABLED_CYCLES = 0x8A,
1398 ARMV7_PERFCTR_DATA_ENGINE_CLK_EN_CYCLES = 0x8B,
1399
1400 ARMV7_PERFCTR_ISB_INST = 0x90,
1401 ARMV7_PERFCTR_DSB_INST = 0x91,
1402 ARMV7_PERFCTR_DMB_INST = 0x92,
1403 ARMV7_PERFCTR_EXT_INTERRUPTS = 0x93,
1404
1405 ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_COMPLETED = 0xA0,
1406 ARMV7_PERFCTR_PLE_CACHE_LINE_RQST_SKIPPED = 0xA1,
1407 ARMV7_PERFCTR_PLE_FIFO_FLUSH = 0xA2,
1408 ARMV7_PERFCTR_PLE_RQST_COMPLETED = 0xA3,
1409 ARMV7_PERFCTR_PLE_FIFO_OVERFLOW = 0xA4,
1410 ARMV7_PERFCTR_PLE_RQST_PROG = 0xA5
1411 };
1412
1413 /*
1414 * Cortex-A8 HW events mapping
1415 *
1416 * The hardware events that we support. We do support cache operations but
1417 * we have harvard caches and no way to combine instruction and data
1418 * accesses/misses in hardware.
1419 */
1420 static const unsigned armv7_a8_perf_map[PERF_COUNT_HW_MAX] = {
1421 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
1422 [PERF_COUNT_HW_INSTRUCTIONS] = ARMV7_PERFCTR_INSTR_EXECUTED,
1423 [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED,
1424 [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED,
1425 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
1426 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
1427 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES,
1428 };
1429
1430 static const unsigned armv7_a8_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
1431 [PERF_COUNT_HW_CACHE_OP_MAX]
1432 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1433 [C(L1D)] = {
1434 /*
1435 * The performance counters don't differentiate between read
1436 * and write accesses/misses so this isn't strictly correct,
1437 * but it's the best we can do. Writes and reads get
1438 * combined.
1439 */
1440 [C(OP_READ)] = {
1441 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS,
1442 [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL,
1443 },
1444 [C(OP_WRITE)] = {
1445 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS,
1446 [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL,
1447 },
1448 [C(OP_PREFETCH)] = {
1449 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1450 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1451 },
1452 },
1453 [C(L1I)] = {
1454 [C(OP_READ)] = {
1455 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_INST,
1456 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_INST_MISS,
1457 },
1458 [C(OP_WRITE)] = {
1459 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L1_INST,
1460 [C(RESULT_MISS)] = ARMV7_PERFCTR_L1_INST_MISS,
1461 },
1462 [C(OP_PREFETCH)] = {
1463 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1464 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1465 },
1466 },
1467 [C(LL)] = {
1468 [C(OP_READ)] = {
1469 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_ACCESS,
1470 [C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACH_MISS,
1471 },
1472 [C(OP_WRITE)] = {
1473 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_L2_ACCESS,
1474 [C(RESULT_MISS)] = ARMV7_PERFCTR_L2_CACH_MISS,
1475 },
1476 [C(OP_PREFETCH)] = {
1477 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1478 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1479 },
1480 },
1481 [C(DTLB)] = {
1482 /*
1483 * Only ITLB misses and DTLB refills are supported.
1484 * If users want the DTLB refills misses a raw counter
1485 * must be used.
1486 */
1487 [C(OP_READ)] = {
1488 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1489 [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
1490 },
1491 [C(OP_WRITE)] = {
1492 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1493 [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
1494 },
1495 [C(OP_PREFETCH)] = {
1496 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1497 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1498 },
1499 },
1500 [C(ITLB)] = {
1501 [C(OP_READ)] = {
1502 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1503 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS,
1504 },
1505 [C(OP_WRITE)] = {
1506 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1507 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS,
1508 },
1509 [C(OP_PREFETCH)] = {
1510 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1511 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1512 },
1513 },
1514 [C(BPU)] = {
1515 [C(OP_READ)] = {
1516 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_WRITE,
1517 [C(RESULT_MISS)]
1518 = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
1519 },
1520 [C(OP_WRITE)] = {
1521 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_WRITE,
1522 [C(RESULT_MISS)]
1523 = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
1524 },
1525 [C(OP_PREFETCH)] = {
1526 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1527 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1528 },
1529 },
1530 };
1531
1532 /*
1533 * Cortex-A9 HW events mapping
1534 */
1535 static const unsigned armv7_a9_perf_map[PERF_COUNT_HW_MAX] = {
1536 [PERF_COUNT_HW_CPU_CYCLES] = ARMV7_PERFCTR_CPU_CYCLES,
1537 [PERF_COUNT_HW_INSTRUCTIONS] =
1538 ARMV7_PERFCTR_INST_OUT_OF_RENAME_STAGE,
1539 [PERF_COUNT_HW_CACHE_REFERENCES] = ARMV7_PERFCTR_COHERENT_LINE_HIT,
1540 [PERF_COUNT_HW_CACHE_MISSES] = ARMV7_PERFCTR_COHERENT_LINE_MISS,
1541 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = ARMV7_PERFCTR_PC_WRITE,
1542 [PERF_COUNT_HW_BRANCH_MISSES] = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
1543 [PERF_COUNT_HW_BUS_CYCLES] = ARMV7_PERFCTR_CLOCK_CYCLES,
1544 };
1545
1546 static const unsigned armv7_a9_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
1547 [PERF_COUNT_HW_CACHE_OP_MAX]
1548 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1549 [C(L1D)] = {
1550 /*
1551 * The performance counters don't differentiate between read
1552 * and write accesses/misses so this isn't strictly correct,
1553 * but it's the best we can do. Writes and reads get
1554 * combined.
1555 */
1556 [C(OP_READ)] = {
1557 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS,
1558 [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL,
1559 },
1560 [C(OP_WRITE)] = {
1561 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_DCACHE_ACCESS,
1562 [C(RESULT_MISS)] = ARMV7_PERFCTR_DCACHE_REFILL,
1563 },
1564 [C(OP_PREFETCH)] = {
1565 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1566 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1567 },
1568 },
1569 [C(L1I)] = {
1570 [C(OP_READ)] = {
1571 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1572 [C(RESULT_MISS)] = ARMV7_PERFCTR_IFETCH_MISS,
1573 },
1574 [C(OP_WRITE)] = {
1575 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1576 [C(RESULT_MISS)] = ARMV7_PERFCTR_IFETCH_MISS,
1577 },
1578 [C(OP_PREFETCH)] = {
1579 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1580 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1581 },
1582 },
1583 [C(LL)] = {
1584 [C(OP_READ)] = {
1585 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1586 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1587 },
1588 [C(OP_WRITE)] = {
1589 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1590 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1591 },
1592 [C(OP_PREFETCH)] = {
1593 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1594 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1595 },
1596 },
1597 [C(DTLB)] = {
1598 /*
1599 * Only ITLB misses and DTLB refills are supported.
1600 * If users want the DTLB refills misses a raw counter
1601 * must be used.
1602 */
1603 [C(OP_READ)] = {
1604 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1605 [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
1606 },
1607 [C(OP_WRITE)] = {
1608 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1609 [C(RESULT_MISS)] = ARMV7_PERFCTR_DTLB_REFILL,
1610 },
1611 [C(OP_PREFETCH)] = {
1612 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1613 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1614 },
1615 },
1616 [C(ITLB)] = {
1617 [C(OP_READ)] = {
1618 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1619 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS,
1620 },
1621 [C(OP_WRITE)] = {
1622 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1623 [C(RESULT_MISS)] = ARMV7_PERFCTR_ITLB_MISS,
1624 },
1625 [C(OP_PREFETCH)] = {
1626 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1627 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1628 },
1629 },
1630 [C(BPU)] = {
1631 [C(OP_READ)] = {
1632 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_WRITE,
1633 [C(RESULT_MISS)]
1634 = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
1635 },
1636 [C(OP_WRITE)] = {
1637 [C(RESULT_ACCESS)] = ARMV7_PERFCTR_PC_WRITE,
1638 [C(RESULT_MISS)]
1639 = ARMV7_PERFCTR_PC_BRANCH_MIS_PRED,
1640 },
1641 [C(OP_PREFETCH)] = {
1642 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
1643 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
1644 },
1645 },
1646 };
1647
1648 /*
1649 * Perf Events counters
1650 */
1651 enum armv7_counters {
1652 ARMV7_CYCLE_COUNTER = 1, /* Cycle counter */
1653 ARMV7_COUNTER0 = 2, /* First event counter */
1654 };
1655
1656 /*
1657 * The cycle counter is ARMV7_CYCLE_COUNTER.
1658 * The first event counter is ARMV7_COUNTER0.
1659 * The last event counter is (ARMV7_COUNTER0 + armpmu->num_events - 1).
1660 */
1661 #define ARMV7_COUNTER_LAST (ARMV7_COUNTER0 + armpmu->num_events - 1)
1662
1663 /*
1664 * ARMv7 low level PMNC access
1665 */
1666
1667 /*
1668 * Per-CPU PMNC: config reg
1669 */
1670 #define ARMV7_PMNC_E (1 << 0) /* Enable all counters */
1671 #define ARMV7_PMNC_P (1 << 1) /* Reset all counters */
1672 #define ARMV7_PMNC_C (1 << 2) /* Cycle counter reset */
1673 #define ARMV7_PMNC_D (1 << 3) /* CCNT counts every 64th cpu cycle */
1674 #define ARMV7_PMNC_X (1 << 4) /* Export to ETM */
1675 #define ARMV7_PMNC_DP (1 << 5) /* Disable CCNT if non-invasive debug*/
1676 #define ARMV7_PMNC_N_SHIFT 11 /* Number of counters supported */
1677 #define ARMV7_PMNC_N_MASK 0x1f
1678 #define ARMV7_PMNC_MASK 0x3f /* Mask for writable bits */
1679
1680 /*
1681 * Available counters
1682 */
1683 #define ARMV7_CNT0 0 /* First event counter */
1684 #define ARMV7_CCNT 31 /* Cycle counter */
1685
1686 /* Perf Event to low level counters mapping */
1687 #define ARMV7_EVENT_CNT_TO_CNTx (ARMV7_COUNTER0 - ARMV7_CNT0)
1688
1689 /*
1690 * CNTENS: counters enable reg
1691 */
1692 #define ARMV7_CNTENS_P(idx) (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
1693 #define ARMV7_CNTENS_C (1 << ARMV7_CCNT)
1694
1695 /*
1696 * CNTENC: counters disable reg
1697 */
1698 #define ARMV7_CNTENC_P(idx) (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
1699 #define ARMV7_CNTENC_C (1 << ARMV7_CCNT)
1700
1701 /*
1702 * INTENS: counters overflow interrupt enable reg
1703 */
1704 #define ARMV7_INTENS_P(idx) (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
1705 #define ARMV7_INTENS_C (1 << ARMV7_CCNT)
1706
1707 /*
1708 * INTENC: counters overflow interrupt disable reg
1709 */
1710 #define ARMV7_INTENC_P(idx) (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
1711 #define ARMV7_INTENC_C (1 << ARMV7_CCNT)
1712
1713 /*
1714 * EVTSEL: Event selection reg
1715 */
1716 #define ARMV7_EVTSEL_MASK 0xff /* Mask for writable bits */
1717
1718 /*
1719 * SELECT: Counter selection reg
1720 */
1721 #define ARMV7_SELECT_MASK 0x1f /* Mask for writable bits */
1722
1723 /*
1724 * FLAG: counters overflow flag status reg
1725 */
1726 #define ARMV7_FLAG_P(idx) (1 << (idx - ARMV7_EVENT_CNT_TO_CNTx))
1727 #define ARMV7_FLAG_C (1 << ARMV7_CCNT)
1728 #define ARMV7_FLAG_MASK 0xffffffff /* Mask for writable bits */
1729 #define ARMV7_OVERFLOWED_MASK ARMV7_FLAG_MASK
1730
1731 static inline unsigned long armv7_pmnc_read(void)
1732 {
1733 u32 val;
1734 asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r"(val));
1735 return val;
1736 }
1737
1738 static inline void armv7_pmnc_write(unsigned long val)
1739 {
1740 val &= ARMV7_PMNC_MASK;
1741 asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(val));
1742 }
1743
1744 static inline int armv7_pmnc_has_overflowed(unsigned long pmnc)
1745 {
1746 return pmnc & ARMV7_OVERFLOWED_MASK;
1747 }
1748
1749 static inline int armv7_pmnc_counter_has_overflowed(unsigned long pmnc,
1750 enum armv7_counters counter)
1751 {
1752 int ret = 0;
1753
1754 if (counter == ARMV7_CYCLE_COUNTER)
1755 ret = pmnc & ARMV7_FLAG_C;
1756 else if ((counter >= ARMV7_COUNTER0) && (counter <= ARMV7_COUNTER_LAST))
1757 ret = pmnc & ARMV7_FLAG_P(counter);
1758 else
1759 pr_err("CPU%u checking wrong counter %d overflow status\n",
1760 smp_processor_id(), counter);
1761
1762 return ret;
1763 }
1764
1765 static inline int armv7_pmnc_select_counter(unsigned int idx)
1766 {
1767 u32 val;
1768
1769 if ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST)) {
1770 pr_err("CPU%u selecting wrong PMNC counter"
1771 " %d\n", smp_processor_id(), idx);
1772 return -1;
1773 }
1774
1775 val = (idx - ARMV7_EVENT_CNT_TO_CNTx) & ARMV7_SELECT_MASK;
1776 asm volatile("mcr p15, 0, %0, c9, c12, 5" : : "r" (val));
1777
1778 return idx;
1779 }
1780
1781 static inline u32 armv7pmu_read_counter(int idx)
1782 {
1783 unsigned long value = 0;
1784
1785 if (idx == ARMV7_CYCLE_COUNTER)
1786 asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (value));
1787 else if ((idx >= ARMV7_COUNTER0) && (idx <= ARMV7_COUNTER_LAST)) {
1788 if (armv7_pmnc_select_counter(idx) == idx)
1789 asm volatile("mrc p15, 0, %0, c9, c13, 2"
1790 : "=r" (value));
1791 } else
1792 pr_err("CPU%u reading wrong counter %d\n",
1793 smp_processor_id(), idx);
1794
1795 return value;
1796 }
1797
1798 static inline void armv7pmu_write_counter(int idx, u32 value)
1799 {
1800 if (idx == ARMV7_CYCLE_COUNTER)
1801 asm volatile("mcr p15, 0, %0, c9, c13, 0" : : "r" (value));
1802 else if ((idx >= ARMV7_COUNTER0) && (idx <= ARMV7_COUNTER_LAST)) {
1803 if (armv7_pmnc_select_counter(idx) == idx)
1804 asm volatile("mcr p15, 0, %0, c9, c13, 2"
1805 : : "r" (value));
1806 } else
1807 pr_err("CPU%u writing wrong counter %d\n",
1808 smp_processor_id(), idx);
1809 }
1810
1811 static inline void armv7_pmnc_write_evtsel(unsigned int idx, u32 val)
1812 {
1813 if (armv7_pmnc_select_counter(idx) == idx) {
1814 val &= ARMV7_EVTSEL_MASK;
1815 asm volatile("mcr p15, 0, %0, c9, c13, 1" : : "r" (val));
1816 }
1817 }
1818
1819 static inline u32 armv7_pmnc_enable_counter(unsigned int idx)
1820 {
1821 u32 val;
1822
1823 if ((idx != ARMV7_CYCLE_COUNTER) &&
1824 ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
1825 pr_err("CPU%u enabling wrong PMNC counter"
1826 " %d\n", smp_processor_id(), idx);
1827 return -1;
1828 }
1829
1830 if (idx == ARMV7_CYCLE_COUNTER)
1831 val = ARMV7_CNTENS_C;
1832 else
1833 val = ARMV7_CNTENS_P(idx);
1834
1835 asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r" (val));
1836
1837 return idx;
1838 }
1839
1840 static inline u32 armv7_pmnc_disable_counter(unsigned int idx)
1841 {
1842 u32 val;
1843
1844
1845 if ((idx != ARMV7_CYCLE_COUNTER) &&
1846 ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
1847 pr_err("CPU%u disabling wrong PMNC counter"
1848 " %d\n", smp_processor_id(), idx);
1849 return -1;
1850 }
1851
1852 if (idx == ARMV7_CYCLE_COUNTER)
1853 val = ARMV7_CNTENC_C;
1854 else
1855 val = ARMV7_CNTENC_P(idx);
1856
1857 asm volatile("mcr p15, 0, %0, c9, c12, 2" : : "r" (val));
1858
1859 return idx;
1860 }
1861
1862 static inline u32 armv7_pmnc_enable_intens(unsigned int idx)
1863 {
1864 u32 val;
1865
1866 if ((idx != ARMV7_CYCLE_COUNTER) &&
1867 ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
1868 pr_err("CPU%u enabling wrong PMNC counter"
1869 " interrupt enable %d\n", smp_processor_id(), idx);
1870 return -1;
1871 }
1872
1873 if (idx == ARMV7_CYCLE_COUNTER)
1874 val = ARMV7_INTENS_C;
1875 else
1876 val = ARMV7_INTENS_P(idx);
1877
1878 asm volatile("mcr p15, 0, %0, c9, c14, 1" : : "r" (val));
1879
1880 return idx;
1881 }
1882
1883 static inline u32 armv7_pmnc_disable_intens(unsigned int idx)
1884 {
1885 u32 val;
1886
1887 if ((idx != ARMV7_CYCLE_COUNTER) &&
1888 ((idx < ARMV7_COUNTER0) || (idx > ARMV7_COUNTER_LAST))) {
1889 pr_err("CPU%u disabling wrong PMNC counter"
1890 " interrupt enable %d\n", smp_processor_id(), idx);
1891 return -1;
1892 }
1893
1894 if (idx == ARMV7_CYCLE_COUNTER)
1895 val = ARMV7_INTENC_C;
1896 else
1897 val = ARMV7_INTENC_P(idx);
1898
1899 asm volatile("mcr p15, 0, %0, c9, c14, 2" : : "r" (val));
1900
1901 return idx;
1902 }
1903
1904 static inline u32 armv7_pmnc_getreset_flags(void)
1905 {
1906 u32 val;
1907
1908 /* Read */
1909 asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));
1910
1911 /* Write to clear flags */
1912 val &= ARMV7_FLAG_MASK;
1913 asm volatile("mcr p15, 0, %0, c9, c12, 3" : : "r" (val));
1914
1915 return val;
1916 }
1917
1918 #ifdef DEBUG
1919 static void armv7_pmnc_dump_regs(void)
1920 {
1921 u32 val;
1922 unsigned int cnt;
1923
1924 printk(KERN_INFO "PMNC registers dump:\n");
1925
1926 asm volatile("mrc p15, 0, %0, c9, c12, 0" : "=r" (val));
1927 printk(KERN_INFO "PMNC =0x%08x\n", val);
1928
1929 asm volatile("mrc p15, 0, %0, c9, c12, 1" : "=r" (val));
1930 printk(KERN_INFO "CNTENS=0x%08x\n", val);
1931
1932 asm volatile("mrc p15, 0, %0, c9, c14, 1" : "=r" (val));
1933 printk(KERN_INFO "INTENS=0x%08x\n", val);
1934
1935 asm volatile("mrc p15, 0, %0, c9, c12, 3" : "=r" (val));
1936 printk(KERN_INFO "FLAGS =0x%08x\n", val);
1937
1938 asm volatile("mrc p15, 0, %0, c9, c12, 5" : "=r" (val));
1939 printk(KERN_INFO "SELECT=0x%08x\n", val);
1940
1941 asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r" (val));
1942 printk(KERN_INFO "CCNT =0x%08x\n", val);
1943
1944 for (cnt = ARMV7_COUNTER0; cnt < ARMV7_COUNTER_LAST; cnt++) {
1945 armv7_pmnc_select_counter(cnt);
1946 asm volatile("mrc p15, 0, %0, c9, c13, 2" : "=r" (val));
1947 printk(KERN_INFO "CNT[%d] count =0x%08x\n",
1948 cnt-ARMV7_EVENT_CNT_TO_CNTx, val);
1949 asm volatile("mrc p15, 0, %0, c9, c13, 1" : "=r" (val));
1950 printk(KERN_INFO "CNT[%d] evtsel=0x%08x\n",
1951 cnt-ARMV7_EVENT_CNT_TO_CNTx, val);
1952 }
1953 }
1954 #endif
1955
1956 void armv7pmu_enable_event(struct hw_perf_event *hwc, int idx)
1957 {
1958 unsigned long flags;
1959
1960 /*
1961 * Enable counter and interrupt, and set the counter to count
1962 * the event that we're interested in.
1963 */
1964 spin_lock_irqsave(&pmu_lock, flags);
1965
1966 /*
1967 * Disable counter
1968 */
1969 armv7_pmnc_disable_counter(idx);
1970
1971 /*
1972 * Set event (if destined for PMNx counters)
1973 * We don't need to set the event if it's a cycle count
1974 */
1975 if (idx != ARMV7_CYCLE_COUNTER)
1976 armv7_pmnc_write_evtsel(idx, hwc->config_base);
1977
1978 /*
1979 * Enable interrupt for this counter
1980 */
1981 armv7_pmnc_enable_intens(idx);
1982
1983 /*
1984 * Enable counter
1985 */
1986 armv7_pmnc_enable_counter(idx);
1987
1988 spin_unlock_irqrestore(&pmu_lock, flags);
1989 }
1990
1991 static void armv7pmu_disable_event(struct hw_perf_event *hwc, int idx)
1992 {
1993 unsigned long flags;
1994
1995 /*
1996 * Disable counter and interrupt
1997 */
1998 spin_lock_irqsave(&pmu_lock, flags);
1999
2000 /*
2001 * Disable counter
2002 */
2003 armv7_pmnc_disable_counter(idx);
2004
2005 /*
2006 * Disable interrupt for this counter
2007 */
2008 armv7_pmnc_disable_intens(idx);
2009
2010 spin_unlock_irqrestore(&pmu_lock, flags);
2011 }
2012
2013 static irqreturn_t armv7pmu_handle_irq(int irq_num, void *dev)
2014 {
2015 unsigned long pmnc;
2016 struct perf_sample_data data;
2017 struct cpu_hw_events *cpuc;
2018 struct pt_regs *regs;
2019 int idx;
2020
2021 /*
2022 * Get and reset the IRQ flags
2023 */
2024 pmnc = armv7_pmnc_getreset_flags();
2025
2026 /*
2027 * Did an overflow occur?
2028 */
2029 if (!armv7_pmnc_has_overflowed(pmnc))
2030 return IRQ_NONE;
2031
2032 /*
2033 * Handle the counter(s) overflow(s)
2034 */
2035 regs = get_irq_regs();
2036
2037 perf_sample_data_init(&data, 0);
2038
2039 cpuc = &__get_cpu_var(cpu_hw_events);
2040 for (idx = 0; idx <= armpmu->num_events; ++idx) {
2041 struct perf_event *event = cpuc->events[idx];
2042 struct hw_perf_event *hwc;
2043
2044 if (!test_bit(idx, cpuc->active_mask))
2045 continue;
2046
2047 /*
2048 * We have a single interrupt for all counters. Check that
2049 * each counter has overflowed before we process it.
2050 */
2051 if (!armv7_pmnc_counter_has_overflowed(pmnc, idx))
2052 continue;
2053
2054 hwc = &event->hw;
2055 armpmu_event_update(event, hwc, idx);
2056 data.period = event->hw.last_period;
2057 if (!armpmu_event_set_period(event, hwc, idx))
2058 continue;
2059
2060 if (perf_event_overflow(event, 0, &data, regs))
2061 armpmu->disable(hwc, idx);
2062 }
2063
2064 /*
2065 * Handle the pending perf events.
2066 *
2067 * Note: this call *must* be run with interrupts disabled. For
2068 * platforms that can have the PMU interrupts raised as an NMI, this
2069 * will not work.
2070 */
2071 irq_work_run();
2072
2073 return IRQ_HANDLED;
2074 }
2075
2076 static void armv7pmu_start(void)
2077 {
2078 unsigned long flags;
2079
2080 spin_lock_irqsave(&pmu_lock, flags);
2081 /* Enable all counters */
2082 armv7_pmnc_write(armv7_pmnc_read() | ARMV7_PMNC_E);
2083 spin_unlock_irqrestore(&pmu_lock, flags);
2084 }
2085
2086 static void armv7pmu_stop(void)
2087 {
2088 unsigned long flags;
2089
2090 spin_lock_irqsave(&pmu_lock, flags);
2091 /* Disable all counters */
2092 armv7_pmnc_write(armv7_pmnc_read() & ~ARMV7_PMNC_E);
2093 spin_unlock_irqrestore(&pmu_lock, flags);
2094 }
2095
2096 static int armv7pmu_get_event_idx(struct cpu_hw_events *cpuc,
2097 struct hw_perf_event *event)
2098 {
2099 int idx;
2100
2101 /* Always place a cycle counter into the cycle counter. */
2102 if (event->config_base == ARMV7_PERFCTR_CPU_CYCLES) {
2103 if (test_and_set_bit(ARMV7_CYCLE_COUNTER, cpuc->used_mask))
2104 return -EAGAIN;
2105
2106 return ARMV7_CYCLE_COUNTER;
2107 } else {
2108 /*
2109 * For anything other than a cycle counter, try and use
2110 * the events counters
2111 */
2112 for (idx = ARMV7_COUNTER0; idx <= armpmu->num_events; ++idx) {
2113 if (!test_and_set_bit(idx, cpuc->used_mask))
2114 return idx;
2115 }
2116
2117 /* The counters are all in use. */
2118 return -EAGAIN;
2119 }
2120 }
2121
2122 static struct arm_pmu armv7pmu = {
2123 .handle_irq = armv7pmu_handle_irq,
2124 .enable = armv7pmu_enable_event,
2125 .disable = armv7pmu_disable_event,
2126 .read_counter = armv7pmu_read_counter,
2127 .write_counter = armv7pmu_write_counter,
2128 .get_event_idx = armv7pmu_get_event_idx,
2129 .start = armv7pmu_start,
2130 .stop = armv7pmu_stop,
2131 .raw_event_mask = 0xFF,
2132 .max_period = (1LLU << 32) - 1,
2133 };
2134
2135 static u32 __init armv7_reset_read_pmnc(void)
2136 {
2137 u32 nb_cnt;
2138
2139 /* Initialize & Reset PMNC: C and P bits */
2140 armv7_pmnc_write(ARMV7_PMNC_P | ARMV7_PMNC_C);
2141
2142 /* Read the nb of CNTx counters supported from PMNC */
2143 nb_cnt = (armv7_pmnc_read() >> ARMV7_PMNC_N_SHIFT) & ARMV7_PMNC_N_MASK;
2144
2145 /* Add the CPU cycles counter and return */
2146 return nb_cnt + 1;
2147 }
2148
2149 const struct arm_pmu *__init armv7_a8_pmu_init(void)
2150 {
2151 armv7pmu.id = ARM_PERF_PMU_ID_CA8;
2152 armv7pmu.cache_map = &armv7_a8_perf_cache_map;
2153 armv7pmu.event_map = &armv7_a8_perf_map;
2154 armv7pmu.num_events = armv7_reset_read_pmnc();
2155 return &armv7pmu;
2156 }
2157
2158 const struct arm_pmu *__init armv7_a9_pmu_init(void)
2159 {
2160 armv7pmu.id = ARM_PERF_PMU_ID_CA9;
2161 armv7pmu.cache_map = &armv7_a9_perf_cache_map;
2162 armv7pmu.event_map = &armv7_a9_perf_map;
2163 armv7pmu.num_events = armv7_reset_read_pmnc();
2164 return &armv7pmu;
2165 }
2166
2167
2168 /*
2169 * ARMv5 [xscale] Performance counter handling code.
2170 *
2171 * Based on xscale OProfile code.
2172 *
2173 * There are two variants of the xscale PMU that we support:
2174 * - xscale1pmu: 2 event counters and a cycle counter
2175 * - xscale2pmu: 4 event counters and a cycle counter
2176 * The two variants share event definitions, but have different
2177 * PMU structures.
2178 */
2179
2180 enum xscale_perf_types {
2181 XSCALE_PERFCTR_ICACHE_MISS = 0x00,
2182 XSCALE_PERFCTR_ICACHE_NO_DELIVER = 0x01,
2183 XSCALE_PERFCTR_DATA_STALL = 0x02,
2184 XSCALE_PERFCTR_ITLB_MISS = 0x03,
2185 XSCALE_PERFCTR_DTLB_MISS = 0x04,
2186 XSCALE_PERFCTR_BRANCH = 0x05,
2187 XSCALE_PERFCTR_BRANCH_MISS = 0x06,
2188 XSCALE_PERFCTR_INSTRUCTION = 0x07,
2189 XSCALE_PERFCTR_DCACHE_FULL_STALL = 0x08,
2190 XSCALE_PERFCTR_DCACHE_FULL_STALL_CONTIG = 0x09,
2191 XSCALE_PERFCTR_DCACHE_ACCESS = 0x0A,
2192 XSCALE_PERFCTR_DCACHE_MISS = 0x0B,
2193 XSCALE_PERFCTR_DCACHE_WRITE_BACK = 0x0C,
2194 XSCALE_PERFCTR_PC_CHANGED = 0x0D,
2195 XSCALE_PERFCTR_BCU_REQUEST = 0x10,
2196 XSCALE_PERFCTR_BCU_FULL = 0x11,
2197 XSCALE_PERFCTR_BCU_DRAIN = 0x12,
2198 XSCALE_PERFCTR_BCU_ECC_NO_ELOG = 0x14,
2199 XSCALE_PERFCTR_BCU_1_BIT_ERR = 0x15,
2200 XSCALE_PERFCTR_RMW = 0x16,
2201 /* XSCALE_PERFCTR_CCNT is not hardware defined */
2202 XSCALE_PERFCTR_CCNT = 0xFE,
2203 XSCALE_PERFCTR_UNUSED = 0xFF,
2204 };
2205
2206 enum xscale_counters {
2207 XSCALE_CYCLE_COUNTER = 1,
2208 XSCALE_COUNTER0,
2209 XSCALE_COUNTER1,
2210 XSCALE_COUNTER2,
2211 XSCALE_COUNTER3,
2212 };
2213
2214 static const unsigned xscale_perf_map[PERF_COUNT_HW_MAX] = {
2215 [PERF_COUNT_HW_CPU_CYCLES] = XSCALE_PERFCTR_CCNT,
2216 [PERF_COUNT_HW_INSTRUCTIONS] = XSCALE_PERFCTR_INSTRUCTION,
2217 [PERF_COUNT_HW_CACHE_REFERENCES] = HW_OP_UNSUPPORTED,
2218 [PERF_COUNT_HW_CACHE_MISSES] = HW_OP_UNSUPPORTED,
2219 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = XSCALE_PERFCTR_BRANCH,
2220 [PERF_COUNT_HW_BRANCH_MISSES] = XSCALE_PERFCTR_BRANCH_MISS,
2221 [PERF_COUNT_HW_BUS_CYCLES] = HW_OP_UNSUPPORTED,
2222 };
2223
2224 static const unsigned xscale_perf_cache_map[PERF_COUNT_HW_CACHE_MAX]
2225 [PERF_COUNT_HW_CACHE_OP_MAX]
2226 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
2227 [C(L1D)] = {
2228 [C(OP_READ)] = {
2229 [C(RESULT_ACCESS)] = XSCALE_PERFCTR_DCACHE_ACCESS,
2230 [C(RESULT_MISS)] = XSCALE_PERFCTR_DCACHE_MISS,
2231 },
2232 [C(OP_WRITE)] = {
2233 [C(RESULT_ACCESS)] = XSCALE_PERFCTR_DCACHE_ACCESS,
2234 [C(RESULT_MISS)] = XSCALE_PERFCTR_DCACHE_MISS,
2235 },
2236 [C(OP_PREFETCH)] = {
2237 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2238 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
2239 },
2240 },
2241 [C(L1I)] = {
2242 [C(OP_READ)] = {
2243 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2244 [C(RESULT_MISS)] = XSCALE_PERFCTR_ICACHE_MISS,
2245 },
2246 [C(OP_WRITE)] = {
2247 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2248 [C(RESULT_MISS)] = XSCALE_PERFCTR_ICACHE_MISS,
2249 },
2250 [C(OP_PREFETCH)] = {
2251 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2252 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
2253 },
2254 },
2255 [C(LL)] = {
2256 [C(OP_READ)] = {
2257 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2258 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
2259 },
2260 [C(OP_WRITE)] = {
2261 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2262 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
2263 },
2264 [C(OP_PREFETCH)] = {
2265 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2266 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
2267 },
2268 },
2269 [C(DTLB)] = {
2270 [C(OP_READ)] = {
2271 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2272 [C(RESULT_MISS)] = XSCALE_PERFCTR_DTLB_MISS,
2273 },
2274 [C(OP_WRITE)] = {
2275 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2276 [C(RESULT_MISS)] = XSCALE_PERFCTR_DTLB_MISS,
2277 },
2278 [C(OP_PREFETCH)] = {
2279 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2280 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
2281 },
2282 },
2283 [C(ITLB)] = {
2284 [C(OP_READ)] = {
2285 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2286 [C(RESULT_MISS)] = XSCALE_PERFCTR_ITLB_MISS,
2287 },
2288 [C(OP_WRITE)] = {
2289 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2290 [C(RESULT_MISS)] = XSCALE_PERFCTR_ITLB_MISS,
2291 },
2292 [C(OP_PREFETCH)] = {
2293 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2294 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
2295 },
2296 },
2297 [C(BPU)] = {
2298 [C(OP_READ)] = {
2299 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2300 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
2301 },
2302 [C(OP_WRITE)] = {
2303 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2304 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
2305 },
2306 [C(OP_PREFETCH)] = {
2307 [C(RESULT_ACCESS)] = CACHE_OP_UNSUPPORTED,
2308 [C(RESULT_MISS)] = CACHE_OP_UNSUPPORTED,
2309 },
2310 },
2311 };
2312
2313 #define XSCALE_PMU_ENABLE 0x001
2314 #define XSCALE_PMN_RESET 0x002
2315 #define XSCALE_CCNT_RESET 0x004
2316 #define XSCALE_PMU_RESET (CCNT_RESET | PMN_RESET)
2317 #define XSCALE_PMU_CNT64 0x008
2318
2319 #define XSCALE1_OVERFLOWED_MASK 0x700
2320 #define XSCALE1_CCOUNT_OVERFLOW 0x400
2321 #define XSCALE1_COUNT0_OVERFLOW 0x100
2322 #define XSCALE1_COUNT1_OVERFLOW 0x200
2323 #define XSCALE1_CCOUNT_INT_EN 0x040
2324 #define XSCALE1_COUNT0_INT_EN 0x010
2325 #define XSCALE1_COUNT1_INT_EN 0x020
2326 #define XSCALE1_COUNT0_EVT_SHFT 12
2327 #define XSCALE1_COUNT0_EVT_MASK (0xff << XSCALE1_COUNT0_EVT_SHFT)
2328 #define XSCALE1_COUNT1_EVT_SHFT 20
2329 #define XSCALE1_COUNT1_EVT_MASK (0xff << XSCALE1_COUNT1_EVT_SHFT)
2330
2331 static inline u32
2332 xscale1pmu_read_pmnc(void)
2333 {
2334 u32 val;
2335 asm volatile("mrc p14, 0, %0, c0, c0, 0" : "=r" (val));
2336 return val;
2337 }
2338
2339 static inline void
2340 xscale1pmu_write_pmnc(u32 val)
2341 {
2342 /* upper 4bits and 7, 11 are write-as-0 */
2343 val &= 0xffff77f;
2344 asm volatile("mcr p14, 0, %0, c0, c0, 0" : : "r" (val));
2345 }
2346
2347 static inline int
2348 xscale1_pmnc_counter_has_overflowed(unsigned long pmnc,
2349 enum xscale_counters counter)
2350 {
2351 int ret = 0;
2352
2353 switch (counter) {
2354 case XSCALE_CYCLE_COUNTER:
2355 ret = pmnc & XSCALE1_CCOUNT_OVERFLOW;
2356 break;
2357 case XSCALE_COUNTER0:
2358 ret = pmnc & XSCALE1_COUNT0_OVERFLOW;
2359 break;
2360 case XSCALE_COUNTER1:
2361 ret = pmnc & XSCALE1_COUNT1_OVERFLOW;
2362 break;
2363 default:
2364 WARN_ONCE(1, "invalid counter number (%d)\n", counter);
2365 }
2366
2367 return ret;
2368 }
2369
2370 static irqreturn_t
2371 xscale1pmu_handle_irq(int irq_num, void *dev)
2372 {
2373 unsigned long pmnc;
2374 struct perf_sample_data data;
2375 struct cpu_hw_events *cpuc;
2376 struct pt_regs *regs;
2377 int idx;
2378
2379 /*
2380 * NOTE: there's an A stepping erratum that states if an overflow
2381 * bit already exists and another occurs, the previous
2382 * Overflow bit gets cleared. There's no workaround.
2383 * Fixed in B stepping or later.
2384 */
2385 pmnc = xscale1pmu_read_pmnc();
2386
2387 /*
2388 * Write the value back to clear the overflow flags. Overflow
2389 * flags remain in pmnc for use below. We also disable the PMU
2390 * while we process the interrupt.
2391 */
2392 xscale1pmu_write_pmnc(pmnc & ~XSCALE_PMU_ENABLE);
2393
2394 if (!(pmnc & XSCALE1_OVERFLOWED_MASK))
2395 return IRQ_NONE;
2396
2397 regs = get_irq_regs();
2398
2399 perf_sample_data_init(&data, 0);
2400
2401 cpuc = &__get_cpu_var(cpu_hw_events);
2402 for (idx = 0; idx <= armpmu->num_events; ++idx) {
2403 struct perf_event *event = cpuc->events[idx];
2404 struct hw_perf_event *hwc;
2405
2406 if (!test_bit(idx, cpuc->active_mask))
2407 continue;
2408
2409 if (!xscale1_pmnc_counter_has_overflowed(pmnc, idx))
2410 continue;
2411
2412 hwc = &event->hw;
2413 armpmu_event_update(event, hwc, idx);
2414 data.period = event->hw.last_period;
2415 if (!armpmu_event_set_period(event, hwc, idx))
2416 continue;
2417
2418 if (perf_event_overflow(event, 0, &data, regs))
2419 armpmu->disable(hwc, idx);
2420 }
2421
2422 irq_work_run();
2423
2424 /*
2425 * Re-enable the PMU.
2426 */
2427 pmnc = xscale1pmu_read_pmnc() | XSCALE_PMU_ENABLE;
2428 xscale1pmu_write_pmnc(pmnc);
2429
2430 return IRQ_HANDLED;
2431 }
2432
2433 static void
2434 xscale1pmu_enable_event(struct hw_perf_event *hwc, int idx)
2435 {
2436 unsigned long val, mask, evt, flags;
2437
2438 switch (idx) {
2439 case XSCALE_CYCLE_COUNTER:
2440 mask = 0;
2441 evt = XSCALE1_CCOUNT_INT_EN;
2442 break;
2443 case XSCALE_COUNTER0:
2444 mask = XSCALE1_COUNT0_EVT_MASK;
2445 evt = (hwc->config_base << XSCALE1_COUNT0_EVT_SHFT) |
2446 XSCALE1_COUNT0_INT_EN;
2447 break;
2448 case XSCALE_COUNTER1:
2449 mask = XSCALE1_COUNT1_EVT_MASK;
2450 evt = (hwc->config_base << XSCALE1_COUNT1_EVT_SHFT) |
2451 XSCALE1_COUNT1_INT_EN;
2452 break;
2453 default:
2454 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
2455 return;
2456 }
2457
2458 spin_lock_irqsave(&pmu_lock, flags);
2459 val = xscale1pmu_read_pmnc();
2460 val &= ~mask;
2461 val |= evt;
2462 xscale1pmu_write_pmnc(val);
2463 spin_unlock_irqrestore(&pmu_lock, flags);
2464 }
2465
2466 static void
2467 xscale1pmu_disable_event(struct hw_perf_event *hwc, int idx)
2468 {
2469 unsigned long val, mask, evt, flags;
2470
2471 switch (idx) {
2472 case XSCALE_CYCLE_COUNTER:
2473 mask = XSCALE1_CCOUNT_INT_EN;
2474 evt = 0;
2475 break;
2476 case XSCALE_COUNTER0:
2477 mask = XSCALE1_COUNT0_INT_EN | XSCALE1_COUNT0_EVT_MASK;
2478 evt = XSCALE_PERFCTR_UNUSED << XSCALE1_COUNT0_EVT_SHFT;
2479 break;
2480 case XSCALE_COUNTER1:
2481 mask = XSCALE1_COUNT1_INT_EN | XSCALE1_COUNT1_EVT_MASK;
2482 evt = XSCALE_PERFCTR_UNUSED << XSCALE1_COUNT1_EVT_SHFT;
2483 break;
2484 default:
2485 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
2486 return;
2487 }
2488
2489 spin_lock_irqsave(&pmu_lock, flags);
2490 val = xscale1pmu_read_pmnc();
2491 val &= ~mask;
2492 val |= evt;
2493 xscale1pmu_write_pmnc(val);
2494 spin_unlock_irqrestore(&pmu_lock, flags);
2495 }
2496
2497 static int
2498 xscale1pmu_get_event_idx(struct cpu_hw_events *cpuc,
2499 struct hw_perf_event *event)
2500 {
2501 if (XSCALE_PERFCTR_CCNT == event->config_base) {
2502 if (test_and_set_bit(XSCALE_CYCLE_COUNTER, cpuc->used_mask))
2503 return -EAGAIN;
2504
2505 return XSCALE_CYCLE_COUNTER;
2506 } else {
2507 if (!test_and_set_bit(XSCALE_COUNTER1, cpuc->used_mask)) {
2508 return XSCALE_COUNTER1;
2509 }
2510
2511 if (!test_and_set_bit(XSCALE_COUNTER0, cpuc->used_mask)) {
2512 return XSCALE_COUNTER0;
2513 }
2514
2515 return -EAGAIN;
2516 }
2517 }
2518
2519 static void
2520 xscale1pmu_start(void)
2521 {
2522 unsigned long flags, val;
2523
2524 spin_lock_irqsave(&pmu_lock, flags);
2525 val = xscale1pmu_read_pmnc();
2526 val |= XSCALE_PMU_ENABLE;
2527 xscale1pmu_write_pmnc(val);
2528 spin_unlock_irqrestore(&pmu_lock, flags);
2529 }
2530
2531 static void
2532 xscale1pmu_stop(void)
2533 {
2534 unsigned long flags, val;
2535
2536 spin_lock_irqsave(&pmu_lock, flags);
2537 val = xscale1pmu_read_pmnc();
2538 val &= ~XSCALE_PMU_ENABLE;
2539 xscale1pmu_write_pmnc(val);
2540 spin_unlock_irqrestore(&pmu_lock, flags);
2541 }
2542
2543 static inline u32
2544 xscale1pmu_read_counter(int counter)
2545 {
2546 u32 val = 0;
2547
2548 switch (counter) {
2549 case XSCALE_CYCLE_COUNTER:
2550 asm volatile("mrc p14, 0, %0, c1, c0, 0" : "=r" (val));
2551 break;
2552 case XSCALE_COUNTER0:
2553 asm volatile("mrc p14, 0, %0, c2, c0, 0" : "=r" (val));
2554 break;
2555 case XSCALE_COUNTER1:
2556 asm volatile("mrc p14, 0, %0, c3, c0, 0" : "=r" (val));
2557 break;
2558 }
2559
2560 return val;
2561 }
2562
2563 static inline void
2564 xscale1pmu_write_counter(int counter, u32 val)
2565 {
2566 switch (counter) {
2567 case XSCALE_CYCLE_COUNTER:
2568 asm volatile("mcr p14, 0, %0, c1, c0, 0" : : "r" (val));
2569 break;
2570 case XSCALE_COUNTER0:
2571 asm volatile("mcr p14, 0, %0, c2, c0, 0" : : "r" (val));
2572 break;
2573 case XSCALE_COUNTER1:
2574 asm volatile("mcr p14, 0, %0, c3, c0, 0" : : "r" (val));
2575 break;
2576 }
2577 }
2578
2579 static const struct arm_pmu xscale1pmu = {
2580 .id = ARM_PERF_PMU_ID_XSCALE1,
2581 .handle_irq = xscale1pmu_handle_irq,
2582 .enable = xscale1pmu_enable_event,
2583 .disable = xscale1pmu_disable_event,
2584 .read_counter = xscale1pmu_read_counter,
2585 .write_counter = xscale1pmu_write_counter,
2586 .get_event_idx = xscale1pmu_get_event_idx,
2587 .start = xscale1pmu_start,
2588 .stop = xscale1pmu_stop,
2589 .cache_map = &xscale_perf_cache_map,
2590 .event_map = &xscale_perf_map,
2591 .raw_event_mask = 0xFF,
2592 .num_events = 3,
2593 .max_period = (1LLU << 32) - 1,
2594 };
2595
2596 const struct arm_pmu *__init xscale1pmu_init(void)
2597 {
2598 return &xscale1pmu;
2599 }
2600
2601 #define XSCALE2_OVERFLOWED_MASK 0x01f
2602 #define XSCALE2_CCOUNT_OVERFLOW 0x001
2603 #define XSCALE2_COUNT0_OVERFLOW 0x002
2604 #define XSCALE2_COUNT1_OVERFLOW 0x004
2605 #define XSCALE2_COUNT2_OVERFLOW 0x008
2606 #define XSCALE2_COUNT3_OVERFLOW 0x010
2607 #define XSCALE2_CCOUNT_INT_EN 0x001
2608 #define XSCALE2_COUNT0_INT_EN 0x002
2609 #define XSCALE2_COUNT1_INT_EN 0x004
2610 #define XSCALE2_COUNT2_INT_EN 0x008
2611 #define XSCALE2_COUNT3_INT_EN 0x010
2612 #define XSCALE2_COUNT0_EVT_SHFT 0
2613 #define XSCALE2_COUNT0_EVT_MASK (0xff << XSCALE2_COUNT0_EVT_SHFT)
2614 #define XSCALE2_COUNT1_EVT_SHFT 8
2615 #define XSCALE2_COUNT1_EVT_MASK (0xff << XSCALE2_COUNT1_EVT_SHFT)
2616 #define XSCALE2_COUNT2_EVT_SHFT 16
2617 #define XSCALE2_COUNT2_EVT_MASK (0xff << XSCALE2_COUNT2_EVT_SHFT)
2618 #define XSCALE2_COUNT3_EVT_SHFT 24
2619 #define XSCALE2_COUNT3_EVT_MASK (0xff << XSCALE2_COUNT3_EVT_SHFT)
2620
2621 static inline u32
2622 xscale2pmu_read_pmnc(void)
2623 {
2624 u32 val;
2625 asm volatile("mrc p14, 0, %0, c0, c1, 0" : "=r" (val));
2626 /* bits 1-2 and 4-23 are read-unpredictable */
2627 return val & 0xff000009;
2628 }
2629
2630 static inline void
2631 xscale2pmu_write_pmnc(u32 val)
2632 {
2633 /* bits 4-23 are write-as-0, 24-31 are write ignored */
2634 val &= 0xf;
2635 asm volatile("mcr p14, 0, %0, c0, c1, 0" : : "r" (val));
2636 }
2637
2638 static inline u32
2639 xscale2pmu_read_overflow_flags(void)
2640 {
2641 u32 val;
2642 asm volatile("mrc p14, 0, %0, c5, c1, 0" : "=r" (val));
2643 return val;
2644 }
2645
2646 static inline void
2647 xscale2pmu_write_overflow_flags(u32 val)
2648 {
2649 asm volatile("mcr p14, 0, %0, c5, c1, 0" : : "r" (val));
2650 }
2651
2652 static inline u32
2653 xscale2pmu_read_event_select(void)
2654 {
2655 u32 val;
2656 asm volatile("mrc p14, 0, %0, c8, c1, 0" : "=r" (val));
2657 return val;
2658 }
2659
2660 static inline void
2661 xscale2pmu_write_event_select(u32 val)
2662 {
2663 asm volatile("mcr p14, 0, %0, c8, c1, 0" : : "r"(val));
2664 }
2665
2666 static inline u32
2667 xscale2pmu_read_int_enable(void)
2668 {
2669 u32 val;
2670 asm volatile("mrc p14, 0, %0, c4, c1, 0" : "=r" (val));
2671 return val;
2672 }
2673
2674 static void
2675 xscale2pmu_write_int_enable(u32 val)
2676 {
2677 asm volatile("mcr p14, 0, %0, c4, c1, 0" : : "r" (val));
2678 }
2679
2680 static inline int
2681 xscale2_pmnc_counter_has_overflowed(unsigned long of_flags,
2682 enum xscale_counters counter)
2683 {
2684 int ret = 0;
2685
2686 switch (counter) {
2687 case XSCALE_CYCLE_COUNTER:
2688 ret = of_flags & XSCALE2_CCOUNT_OVERFLOW;
2689 break;
2690 case XSCALE_COUNTER0:
2691 ret = of_flags & XSCALE2_COUNT0_OVERFLOW;
2692 break;
2693 case XSCALE_COUNTER1:
2694 ret = of_flags & XSCALE2_COUNT1_OVERFLOW;
2695 break;
2696 case XSCALE_COUNTER2:
2697 ret = of_flags & XSCALE2_COUNT2_OVERFLOW;
2698 break;
2699 case XSCALE_COUNTER3:
2700 ret = of_flags & XSCALE2_COUNT3_OVERFLOW;
2701 break;
2702 default:
2703 WARN_ONCE(1, "invalid counter number (%d)\n", counter);
2704 }
2705
2706 return ret;
2707 }
2708
2709 static irqreturn_t
2710 xscale2pmu_handle_irq(int irq_num, void *dev)
2711 {
2712 unsigned long pmnc, of_flags;
2713 struct perf_sample_data data;
2714 struct cpu_hw_events *cpuc;
2715 struct pt_regs *regs;
2716 int idx;
2717
2718 /* Disable the PMU. */
2719 pmnc = xscale2pmu_read_pmnc();
2720 xscale2pmu_write_pmnc(pmnc & ~XSCALE_PMU_ENABLE);
2721
2722 /* Check the overflow flag register. */
2723 of_flags = xscale2pmu_read_overflow_flags();
2724 if (!(of_flags & XSCALE2_OVERFLOWED_MASK))
2725 return IRQ_NONE;
2726
2727 /* Clear the overflow bits. */
2728 xscale2pmu_write_overflow_flags(of_flags);
2729
2730 regs = get_irq_regs();
2731
2732 perf_sample_data_init(&data, 0);
2733
2734 cpuc = &__get_cpu_var(cpu_hw_events);
2735 for (idx = 0; idx <= armpmu->num_events; ++idx) {
2736 struct perf_event *event = cpuc->events[idx];
2737 struct hw_perf_event *hwc;
2738
2739 if (!test_bit(idx, cpuc->active_mask))
2740 continue;
2741
2742 if (!xscale2_pmnc_counter_has_overflowed(pmnc, idx))
2743 continue;
2744
2745 hwc = &event->hw;
2746 armpmu_event_update(event, hwc, idx);
2747 data.period = event->hw.last_period;
2748 if (!armpmu_event_set_period(event, hwc, idx))
2749 continue;
2750
2751 if (perf_event_overflow(event, 0, &data, regs))
2752 armpmu->disable(hwc, idx);
2753 }
2754
2755 irq_work_run();
2756
2757 /*
2758 * Re-enable the PMU.
2759 */
2760 pmnc = xscale2pmu_read_pmnc() | XSCALE_PMU_ENABLE;
2761 xscale2pmu_write_pmnc(pmnc);
2762
2763 return IRQ_HANDLED;
2764 }
2765
2766 static void
2767 xscale2pmu_enable_event(struct hw_perf_event *hwc, int idx)
2768 {
2769 unsigned long flags, ien, evtsel;
2770
2771 ien = xscale2pmu_read_int_enable();
2772 evtsel = xscale2pmu_read_event_select();
2773
2774 switch (idx) {
2775 case XSCALE_CYCLE_COUNTER:
2776 ien |= XSCALE2_CCOUNT_INT_EN;
2777 break;
2778 case XSCALE_COUNTER0:
2779 ien |= XSCALE2_COUNT0_INT_EN;
2780 evtsel &= ~XSCALE2_COUNT0_EVT_MASK;
2781 evtsel |= hwc->config_base << XSCALE2_COUNT0_EVT_SHFT;
2782 break;
2783 case XSCALE_COUNTER1:
2784 ien |= XSCALE2_COUNT1_INT_EN;
2785 evtsel &= ~XSCALE2_COUNT1_EVT_MASK;
2786 evtsel |= hwc->config_base << XSCALE2_COUNT1_EVT_SHFT;
2787 break;
2788 case XSCALE_COUNTER2:
2789 ien |= XSCALE2_COUNT2_INT_EN;
2790 evtsel &= ~XSCALE2_COUNT2_EVT_MASK;
2791 evtsel |= hwc->config_base << XSCALE2_COUNT2_EVT_SHFT;
2792 break;
2793 case XSCALE_COUNTER3:
2794 ien |= XSCALE2_COUNT3_INT_EN;
2795 evtsel &= ~XSCALE2_COUNT3_EVT_MASK;
2796 evtsel |= hwc->config_base << XSCALE2_COUNT3_EVT_SHFT;
2797 break;
2798 default:
2799 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
2800 return;
2801 }
2802
2803 spin_lock_irqsave(&pmu_lock, flags);
2804 xscale2pmu_write_event_select(evtsel);
2805 xscale2pmu_write_int_enable(ien);
2806 spin_unlock_irqrestore(&pmu_lock, flags);
2807 }
2808
2809 static void
2810 xscale2pmu_disable_event(struct hw_perf_event *hwc, int idx)
2811 {
2812 unsigned long flags, ien, evtsel;
2813
2814 ien = xscale2pmu_read_int_enable();
2815 evtsel = xscale2pmu_read_event_select();
2816
2817 switch (idx) {
2818 case XSCALE_CYCLE_COUNTER:
2819 ien &= ~XSCALE2_CCOUNT_INT_EN;
2820 break;
2821 case XSCALE_COUNTER0:
2822 ien &= ~XSCALE2_COUNT0_INT_EN;
2823 evtsel &= ~XSCALE2_COUNT0_EVT_MASK;
2824 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT0_EVT_SHFT;
2825 break;
2826 case XSCALE_COUNTER1:
2827 ien &= ~XSCALE2_COUNT1_INT_EN;
2828 evtsel &= ~XSCALE2_COUNT1_EVT_MASK;
2829 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT1_EVT_SHFT;
2830 break;
2831 case XSCALE_COUNTER2:
2832 ien &= ~XSCALE2_COUNT2_INT_EN;
2833 evtsel &= ~XSCALE2_COUNT2_EVT_MASK;
2834 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT2_EVT_SHFT;
2835 break;
2836 case XSCALE_COUNTER3:
2837 ien &= ~XSCALE2_COUNT3_INT_EN;
2838 evtsel &= ~XSCALE2_COUNT3_EVT_MASK;
2839 evtsel |= XSCALE_PERFCTR_UNUSED << XSCALE2_COUNT3_EVT_SHFT;
2840 break;
2841 default:
2842 WARN_ONCE(1, "invalid counter number (%d)\n", idx);
2843 return;
2844 }
2845
2846 spin_lock_irqsave(&pmu_lock, flags);
2847 xscale2pmu_write_event_select(evtsel);
2848 xscale2pmu_write_int_enable(ien);
2849 spin_unlock_irqrestore(&pmu_lock, flags);
2850 }
2851
2852 static int
2853 xscale2pmu_get_event_idx(struct cpu_hw_events *cpuc,
2854 struct hw_perf_event *event)
2855 {
2856 int idx = xscale1pmu_get_event_idx(cpuc, event);
2857 if (idx >= 0)
2858 goto out;
2859
2860 if (!test_and_set_bit(XSCALE_COUNTER3, cpuc->used_mask))
2861 idx = XSCALE_COUNTER3;
2862 else if (!test_and_set_bit(XSCALE_COUNTER2, cpuc->used_mask))
2863 idx = XSCALE_COUNTER2;
2864 out:
2865 return idx;
2866 }
2867
2868 static void
2869 xscale2pmu_start(void)
2870 {
2871 unsigned long flags, val;
2872
2873 spin_lock_irqsave(&pmu_lock, flags);
2874 val = xscale2pmu_read_pmnc() & ~XSCALE_PMU_CNT64;
2875 val |= XSCALE_PMU_ENABLE;
2876 xscale2pmu_write_pmnc(val);
2877 spin_unlock_irqrestore(&pmu_lock, flags);
2878 }
2879
2880 static void
2881 xscale2pmu_stop(void)
2882 {
2883 unsigned long flags, val;
2884
2885 spin_lock_irqsave(&pmu_lock, flags);
2886 val = xscale2pmu_read_pmnc();
2887 val &= ~XSCALE_PMU_ENABLE;
2888 xscale2pmu_write_pmnc(val);
2889 spin_unlock_irqrestore(&pmu_lock, flags);
2890 }
2891
2892 static inline u32
2893 xscale2pmu_read_counter(int counter)
2894 {
2895 u32 val = 0;
2896
2897 switch (counter) {
2898 case XSCALE_CYCLE_COUNTER:
2899 asm volatile("mrc p14, 0, %0, c1, c1, 0" : "=r" (val));
2900 break;
2901 case XSCALE_COUNTER0:
2902 asm volatile("mrc p14, 0, %0, c0, c2, 0" : "=r" (val));
2903 break;
2904 case XSCALE_COUNTER1:
2905 asm volatile("mrc p14, 0, %0, c1, c2, 0" : "=r" (val));
2906 break;
2907 case XSCALE_COUNTER2:
2908 asm volatile("mrc p14, 0, %0, c2, c2, 0" : "=r" (val));
2909 break;
2910 case XSCALE_COUNTER3:
2911 asm volatile("mrc p14, 0, %0, c3, c2, 0" : "=r" (val));
2912 break;
2913 }
2914
2915 return val;
2916 }
2917
2918 static inline void
2919 xscale2pmu_write_counter(int counter, u32 val)
2920 {
2921 switch (counter) {
2922 case XSCALE_CYCLE_COUNTER:
2923 asm volatile("mcr p14, 0, %0, c1, c1, 0" : : "r" (val));
2924 break;
2925 case XSCALE_COUNTER0:
2926 asm volatile("mcr p14, 0, %0, c0, c2, 0" : : "r" (val));
2927 break;
2928 case XSCALE_COUNTER1:
2929 asm volatile("mcr p14, 0, %0, c1, c2, 0" : : "r" (val));
2930 break;
2931 case XSCALE_COUNTER2:
2932 asm volatile("mcr p14, 0, %0, c2, c2, 0" : : "r" (val));
2933 break;
2934 case XSCALE_COUNTER3:
2935 asm volatile("mcr p14, 0, %0, c3, c2, 0" : : "r" (val));
2936 break;
2937 }
2938 }
2939
2940 static const struct arm_pmu xscale2pmu = {
2941 .id = ARM_PERF_PMU_ID_XSCALE2,
2942 .handle_irq = xscale2pmu_handle_irq,
2943 .enable = xscale2pmu_enable_event,
2944 .disable = xscale2pmu_disable_event,
2945 .read_counter = xscale2pmu_read_counter,
2946 .write_counter = xscale2pmu_write_counter,
2947 .get_event_idx = xscale2pmu_get_event_idx,
2948 .start = xscale2pmu_start,
2949 .stop = xscale2pmu_stop,
2950 .cache_map = &xscale_perf_cache_map,
2951 .event_map = &xscale_perf_map,
2952 .raw_event_mask = 0xFF,
2953 .num_events = 5,
2954 .max_period = (1LLU << 32) - 1,
2955 };
2956
2957 const struct arm_pmu *__init xscale2pmu_init(void)
2958 {
2959 return &xscale2pmu;
2960 }
2961
2962 static int __init
2963 init_hw_perf_events(void)
2964 {
2965 unsigned long cpuid = read_cpuid_id();
2966 unsigned long implementor = (cpuid & 0xFF000000) >> 24;
2967 unsigned long part_number = (cpuid & 0xFFF0);
2968
2969 /* ARM Ltd CPUs. */
2970 if (0x41 == implementor) {
2971 switch (part_number) {
2972 case 0xB360: /* ARM1136 */
2973 case 0xB560: /* ARM1156 */
2974 case 0xB760: /* ARM1176 */
2975 armpmu = armv6pmu_init();
2976 break;
2977 case 0xB020: /* ARM11mpcore */
2978 armpmu = armv6mpcore_pmu_init();
2979 break;
2980 case 0xC080: /* Cortex-A8 */
2981 armpmu = armv7_a8_pmu_init();
2982 break;
2983 case 0xC090: /* Cortex-A9 */
2984 armpmu = armv7_a9_pmu_init();
2985 break;
2986 }
2987 /* Intel CPUs [xscale]. */
2988 } else if (0x69 == implementor) {
2989 part_number = (cpuid >> 13) & 0x7;
2990 switch (part_number) {
2991 case 1:
2992 armpmu = xscale1pmu_init();
2993 break;
2994 case 2:
2995 armpmu = xscale2pmu_init();
2996 break;
2997 }
2998 }
2999
3000 if (armpmu) {
3001 pr_info("enabled with %s PMU driver, %d counters available\n",
3002 arm_pmu_names[armpmu->id], armpmu->num_events);
3003 } else {
3004 pr_info("no hardware support available\n");
3005 }
3006
3007 perf_pmu_register(&pmu);
3008
3009 return 0;
3010 }
3011 arch_initcall(init_hw_perf_events);
3012
3013 /*
3014 * Callchain handling code.
3015 */
3016
3017 /*
3018 * The registers we're interested in are at the end of the variable
3019 * length saved register structure. The fp points at the end of this
3020 * structure so the address of this struct is:
3021 * (struct frame_tail *)(xxx->fp)-1
3022 *
3023 * This code has been adapted from the ARM OProfile support.
3024 */
3025 struct frame_tail {
3026 struct frame_tail *fp;
3027 unsigned long sp;
3028 unsigned long lr;
3029 } __attribute__((packed));
3030
3031 /*
3032 * Get the return address for a single stackframe and return a pointer to the
3033 * next frame tail.
3034 */
3035 static struct frame_tail *
3036 user_backtrace(struct frame_tail *tail,
3037 struct perf_callchain_entry *entry)
3038 {
3039 struct frame_tail buftail;
3040
3041 /* Also check accessibility of one struct frame_tail beyond */
3042 if (!access_ok(VERIFY_READ, tail, sizeof(buftail)))
3043 return NULL;
3044 if (__copy_from_user_inatomic(&buftail, tail, sizeof(buftail)))
3045 return NULL;
3046
3047 perf_callchain_store(entry, buftail.lr);
3048
3049 /*
3050 * Frame pointers should strictly progress back up the stack
3051 * (towards higher addresses).
3052 */
3053 if (tail >= buftail.fp)
3054 return NULL;
3055
3056 return buftail.fp - 1;
3057 }
3058
3059 void
3060 perf_callchain_user(struct perf_callchain_entry *entry, struct pt_regs *regs)
3061 {
3062 struct frame_tail *tail;
3063
3064
3065 tail = (struct frame_tail *)regs->ARM_fp - 1;
3066
3067 while (tail && !((unsigned long)tail & 0x3))
3068 tail = user_backtrace(tail, entry);
3069 }
3070
3071 /*
3072 * Gets called by walk_stackframe() for every stackframe. This will be called
3073 * whist unwinding the stackframe and is like a subroutine return so we use
3074 * the PC.
3075 */
3076 static int
3077 callchain_trace(struct stackframe *fr,
3078 void *data)
3079 {
3080 struct perf_callchain_entry *entry = data;
3081 perf_callchain_store(entry, fr->pc);
3082 return 0;
3083 }
3084
3085 void
3086 perf_callchain_kernel(struct perf_callchain_entry *entry, struct pt_regs *regs)
3087 {
3088 struct stackframe fr;
3089
3090 fr.fp = regs->ARM_fp;
3091 fr.sp = regs->ARM_sp;
3092 fr.lr = regs->ARM_lr;
3093 fr.pc = regs->ARM_pc;
3094 walk_stackframe(&fr, callchain_trace, entry);
3095 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree