2 * Copyright (c) 2010 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicensen
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Thomas Eaton <thomas.g.eaton@intel.com>
25 * Scott Rowe <scott.m.rowe@intel.com>
28 #include "mdfld_dsi_dbi.h"
29 #include "mdfld_dsi_dpi.h"
30 #include "mdfld_dsi_output.h"
31 #include "mdfld_output.h"
33 #include "mdfld_dsi_pkg_sender.h"
35 #include "displays/pyr_cmd.h"
37 static struct drm_display_mode
*pyr_cmd_get_config_mode(struct drm_device
*dev
)
39 struct drm_display_mode
*mode
;
41 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
43 dev_err(dev
->dev
, "Out of memory\n");
47 dev_dbg(dev
->dev
, "hdisplay is %d\n", mode
->hdisplay
);
48 dev_dbg(dev
->dev
, "vdisplay is %d\n", mode
->vdisplay
);
49 dev_dbg(dev
->dev
, "HSS is %d\n", mode
->hsync_start
);
50 dev_dbg(dev
->dev
, "HSE is %d\n", mode
->hsync_end
);
51 dev_dbg(dev
->dev
, "htotal is %d\n", mode
->htotal
);
52 dev_dbg(dev
->dev
, "VSS is %d\n", mode
->vsync_start
);
53 dev_dbg(dev
->dev
, "VSE is %d\n", mode
->vsync_end
);
54 dev_dbg(dev
->dev
, "vtotal is %d\n", mode
->vtotal
);
55 dev_dbg(dev
->dev
, "clock is %d\n", mode
->clock
);
59 mode
->hsync_start
= 487;
60 mode
->hsync_end
= 490;
62 mode
->vsync_start
= 874;
63 mode
->vsync_end
= 878;
67 drm_mode_set_name(mode
);
68 drm_mode_set_crtcinfo(mode
, 0);
70 mode
->type
|= DRM_MODE_TYPE_PREFERRED
;
75 static bool pyr_dsi_dbi_mode_fixup(struct drm_encoder
*encoder
,
76 struct drm_display_mode
*mode
,
77 struct drm_display_mode
*adjusted_mode
)
79 struct drm_device
*dev
= encoder
->dev
;
80 struct drm_display_mode
*fixed_mode
= pyr_cmd_get_config_mode(dev
);
83 adjusted_mode
->hdisplay
= fixed_mode
->hdisplay
;
84 adjusted_mode
->hsync_start
= fixed_mode
->hsync_start
;
85 adjusted_mode
->hsync_end
= fixed_mode
->hsync_end
;
86 adjusted_mode
->htotal
= fixed_mode
->htotal
;
87 adjusted_mode
->vdisplay
= fixed_mode
->vdisplay
;
88 adjusted_mode
->vsync_start
= fixed_mode
->vsync_start
;
89 adjusted_mode
->vsync_end
= fixed_mode
->vsync_end
;
90 adjusted_mode
->vtotal
= fixed_mode
->vtotal
;
91 adjusted_mode
->clock
= fixed_mode
->clock
;
92 drm_mode_set_crtcinfo(adjusted_mode
, CRTC_INTERLACE_HALVE_V
);
98 static void pyr_dsi_dbi_set_power(struct drm_encoder
*encoder
, bool on
)
101 struct mdfld_dsi_encoder
*dsi_encoder
= MDFLD_DSI_ENCODER(encoder
);
102 struct mdfld_dsi_dbi_output
*dbi_output
=
103 MDFLD_DSI_DBI_OUTPUT(dsi_encoder
);
104 struct drm_device
*dev
= encoder
->dev
;
105 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
107 int pipe
= (dbi_output
->channel_num
== 0) ? 0 : 2;
109 dev_dbg(dev
->dev
, "pipe %d : %s, panel on: %s\n", pipe
,
111 dbi_output
->dbi_panel_on
? "True" : "False");
115 dev_priv
->dual_mipi
= true;
117 dev_priv
->dual_mipi
= false;
119 reg_offset
= MIPIC_REG_OFFSET
;
122 dev_priv
->dual_mipi
= false;
125 if (!gma_power_begin(dev
, true)) {
126 dev_err(dev
->dev
, "hw begin failed\n");
132 if (dbi_output
->dbi_panel_on
)
135 ret
= mdfld_dsi_dbi_update_power(dbi_output
, DRM_MODE_DPMS_ON
);
137 dev_err(dev
->dev
, "power on error\n");
141 dbi_output
->dbi_panel_on
= true;
144 dev_priv
->dbi_panel_on2
= true;
146 dev_priv
->dbi_panel_on
= true;
147 mdfld_enable_te(dev
, 0);
150 if (!dbi_output
->dbi_panel_on
&& !dbi_output
->first_boot
)
153 dbi_output
->dbi_panel_on
= false;
154 dbi_output
->first_boot
= false;
157 dev_priv
->dbi_panel_on2
= false;
158 mdfld_disable_te(dev
, 2);
160 dev_priv
->dbi_panel_on
= false;
161 mdfld_disable_te(dev
, 0);
163 if (dev_priv
->dbi_panel_on2
)
164 mdfld_enable_te(dev
, 2);
167 ret
= mdfld_dsi_dbi_update_power(dbi_output
, DRM_MODE_DPMS_OFF
);
169 dev_err(dev
->dev
, "power on error\n");
178 dev_err(dev
->dev
, "failed\n");
181 static void pyr_dsi_controller_dbi_init(struct mdfld_dsi_config
*dsi_config
,
184 struct drm_device
*dev
= dsi_config
->dev
;
185 u32 reg_offset
= pipe
? MIPIC_REG_OFFSET
: 0;
186 int lane_count
= dsi_config
->lane_count
;
189 dev_dbg(dev
->dev
, "Init DBI interface on pipe %d...\n", pipe
);
191 /* Un-ready device */
192 REG_WRITE((MIPIA_DEVICE_READY_REG
+ reg_offset
), 0x00000000);
194 /* Init dsi adapter before kicking off */
195 REG_WRITE((MIPIA_CONTROL_REG
+ reg_offset
), 0x00000018);
197 /* TODO: figure out how to setup these registers */
198 REG_WRITE((MIPIA_DPHY_PARAM_REG
+ reg_offset
), 0x150c600F);
199 REG_WRITE((MIPIA_CLK_LANE_SWITCH_TIME_CNT_REG
+ reg_offset
),
201 REG_WRITE((MIPIA_DBI_BW_CTRL_REG
+ reg_offset
), 0x00000400);
202 REG_WRITE((MIPIA_HS_LS_DBI_ENABLE_REG
+ reg_offset
), 0x00000000);
204 /* Enable all interrupts */
205 REG_WRITE((MIPIA_INTR_EN_REG
+ reg_offset
), 0xffffffff);
206 /* Max value: 20 clock cycles of txclkesc */
207 REG_WRITE((MIPIA_TURN_AROUND_TIMEOUT_REG
+ reg_offset
), 0x0000001f);
208 /* Min 21 txclkesc, max: ffffh */
209 REG_WRITE((MIPIA_DEVICE_RESET_TIMER_REG
+ reg_offset
), 0x0000ffff);
210 /* Min: 7d0 max: 4e20 */
211 REG_WRITE((MIPIA_INIT_COUNT_REG
+ reg_offset
), 0x00000fa0);
213 /* Set up func_prg */
215 val
|= (dsi_config
->channel_num
<< DSI_DBI_VIRT_CHANNEL_OFFSET
);
216 val
|= DSI_DBI_COLOR_FORMAT_OPTION2
;
217 REG_WRITE((MIPIA_DSI_FUNC_PRG_REG
+ reg_offset
), val
);
219 REG_WRITE((MIPIA_HS_TX_TIMEOUT_REG
+ reg_offset
), 0x3fffff);
220 REG_WRITE((MIPIA_LP_RX_TIMEOUT_REG
+ reg_offset
), 0xffff);
222 /* De-assert dbi_stall when half of DBI FIFO is empty */
223 /* REG_WRITE((MIPIA_DBI_FIFO_THROTTLE_REG + reg_offset), 0x00000000); */
225 REG_WRITE((MIPIA_HIGH_LOW_SWITCH_COUNT_REG
+ reg_offset
), 0x46);
226 REG_WRITE((MIPIA_EOT_DISABLE_REG
+ reg_offset
), 0x00000002);
227 REG_WRITE((MIPIA_LP_BYTECLK_REG
+ reg_offset
), 0x00000004);
228 REG_WRITE((MIPIA_DEVICE_READY_REG
+ reg_offset
), 0x00000001);
231 static void pyr_dsi_dbi_mode_set(struct drm_encoder
*encoder
,
232 struct drm_display_mode
*mode
,
233 struct drm_display_mode
*adjusted_mode
)
236 struct drm_device
*dev
= encoder
->dev
;
237 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
238 struct mdfld_dsi_encoder
*dsi_encoder
= MDFLD_DSI_ENCODER(encoder
);
239 struct mdfld_dsi_dbi_output
*dsi_output
=
240 MDFLD_DSI_DBI_OUTPUT(dsi_encoder
);
241 struct mdfld_dsi_config
*dsi_config
=
242 mdfld_dsi_encoder_get_config(dsi_encoder
);
243 struct mdfld_dsi_connector
*dsi_connector
= dsi_config
->connector
;
244 int pipe
= dsi_connector
->pipe
;
249 u32 dspcntr_reg
= DSPACNTR
;
250 u32 pipeconf_reg
= PIPEACONF
;
254 u32 dspcntr_val
= dev_priv
->dspcntr
;
255 u32 pipeconf_val
= dev_priv
->pipeconf
;
256 u32 h_active_area
= mode
->hdisplay
;
257 u32 v_active_area
= mode
->vdisplay
;
258 u32 mipi_val
= (PASS_FROM_SPHY_TO_AFE
| SEL_FLOPPED_HSTX
|
259 TE_TRIGGER_GPIO_PIN
);
261 dev_dbg(dev
->dev
, "mipi_val =0x%x\n", mipi_val
);
263 dev_dbg(dev
->dev
, "type %s\n", (pipe
== 2) ? "MIPI2" : "MIPI");
264 dev_dbg(dev
->dev
, "h %d v %d\n", mode
->hdisplay
, mode
->vdisplay
);
268 dspcntr_reg
= DSPCCNTR
;
269 pipeconf_reg
= PIPECCONF
;
271 reg_offset
= MIPIC_REG_OFFSET
;
273 dspcntr_val
= dev_priv
->dspcntr2
;
274 pipeconf_val
= dev_priv
->pipeconf2
;
276 mipi_val
|= 0x2; /* Two lanes for port A and C respectively */
279 if (!gma_power_begin(dev
, true)) {
280 dev_err(dev
->dev
, "hw begin failed\n");
284 /* Set up pipe related registers */
285 REG_WRITE(mipi_reg
, mipi_val
);
288 pyr_dsi_controller_dbi_init(dsi_config
, pipe
);
292 REG_WRITE(dspcntr_reg
, dspcntr_val
);
293 REG_READ(dspcntr_reg
);
295 /* 20ms delay before sending exit_sleep_mode */
298 /* Send exit_sleep_mode DCS */
299 ret
= mdfld_dsi_dbi_send_dcs(dsi_output
, exit_sleep_mode
, NULL
,
300 0, CMD_DATA_SRC_SYSTEM_MEM
);
302 dev_err(dev
->dev
, "sent exit_sleep_mode faild\n");
306 /*send set_tear_on DCS*/
307 ret
= mdfld_dsi_dbi_send_dcs(dsi_output
, set_tear_on
,
308 ¶m
, 1, CMD_DATA_SRC_SYSTEM_MEM
);
310 dev_err(dev
->dev
, "%s - sent set_tear_on faild\n", __func__
);
314 /* Do some init stuff */
315 mdfld_dsi_brightness_init(dsi_config
, pipe
);
316 mdfld_dsi_gen_fifo_ready(dev
, (MIPIA_GEN_FIFO_STAT_REG
+ reg_offset
),
317 HS_CTRL_FIFO_EMPTY
| HS_DATA_FIFO_EMPTY
);
319 REG_WRITE(pipeconf_reg
, pipeconf_val
| PIPEACONF_DSR
);
320 REG_READ(pipeconf_reg
);
322 /* TODO: this looks ugly, try to move it to CRTC mode setting */
324 dev_priv
->pipeconf2
|= PIPEACONF_DSR
;
326 dev_priv
->pipeconf
|= PIPEACONF_DSR
;
328 dev_dbg(dev
->dev
, "pipeconf %x\n", REG_READ(pipeconf_reg
));
330 ret
= mdfld_dsi_dbi_update_area(dsi_output
, 0, 0,
331 h_active_area
- 1, v_active_area
- 1);
333 dev_err(dev
->dev
, "update area failed\n");
341 dev_err(dev
->dev
, "mode set failed\n");
343 dev_dbg(dev
->dev
, "mode set done successfully\n");
346 static void pyr_dsi_dbi_prepare(struct drm_encoder
*encoder
)
348 struct mdfld_dsi_encoder
*dsi_encoder
= MDFLD_DSI_ENCODER(encoder
);
349 struct mdfld_dsi_dbi_output
*dbi_output
=
350 MDFLD_DSI_DBI_OUTPUT(dsi_encoder
);
352 dbi_output
->mode_flags
|= MODE_SETTING_IN_ENCODER
;
353 dbi_output
->mode_flags
&= ~MODE_SETTING_ENCODER_DONE
;
355 pyr_dsi_dbi_set_power(encoder
, false);
358 static void pyr_dsi_dbi_commit(struct drm_encoder
*encoder
)
360 struct mdfld_dsi_encoder
*dsi_encoder
= MDFLD_DSI_ENCODER(encoder
);
361 struct mdfld_dsi_dbi_output
*dbi_output
=
362 MDFLD_DSI_DBI_OUTPUT(dsi_encoder
);
363 struct drm_device
*dev
= dbi_output
->dev
;
364 struct drm_psb_private
*dev_priv
= dev
->dev_private
;
365 struct psb_drm_dpu_rect rect
;
367 pyr_dsi_dbi_set_power(encoder
, true);
369 dbi_output
->mode_flags
&= ~MODE_SETTING_IN_ENCODER
;
375 if (dbi_output
->channel_num
== 1) {
376 dev_priv
->dsr_fb_update
|= MDFLD_DSR_2D_3D_2
;
377 #ifdef CONFIG_MDFLD_DSI_DPU
378 /* If DPU enabled report a fullscreen damage */
379 mdfld_dbi_dpu_report_damage(dev
, MDFLD_PLANEC
, &rect
);
382 dev_priv
->dsr_fb_update
|= MDFLD_DSR_2D_3D_0
;
384 #ifdef CONFIG_MDFLD_DSI_DPU
385 mdfld_dbi_dpu_report_damage(dev
, MDFLD_PLANEA
, &rect
);
388 dbi_output
->mode_flags
|= MODE_SETTING_ENCODER_DONE
;
391 static void pyr_dsi_dbi_dpms(struct drm_encoder
*encoder
, int mode
)
393 struct mdfld_dsi_encoder
*dsi_encoder
= MDFLD_DSI_ENCODER(encoder
);
394 struct mdfld_dsi_dbi_output
*dbi_output
=
395 MDFLD_DSI_DBI_OUTPUT(dsi_encoder
);
396 struct drm_device
*dev
= dbi_output
->dev
;
398 dev_dbg(dev
->dev
, "%s\n", (mode
== DRM_MODE_DPMS_ON
? "on" : "off"));
400 if (mode
== DRM_MODE_DPMS_ON
)
401 pyr_dsi_dbi_set_power(encoder
, true);
403 pyr_dsi_dbi_set_power(encoder
, false);
407 * Update the DBI MIPI Panel Frame Buffer.
409 static void pyr_dsi_dbi_update_fb(struct mdfld_dsi_dbi_output
*dbi_output
,
412 struct mdfld_dsi_pkg_sender
*sender
=
413 mdfld_dsi_encoder_get_pkg_sender(&dbi_output
->base
);
414 struct drm_device
*dev
= dbi_output
->dev
;
415 struct drm_crtc
*crtc
= dbi_output
->base
.base
.crtc
;
416 struct psb_intel_crtc
*psb_crtc
= (crtc
) ?
417 to_psb_intel_crtc(crtc
) : NULL
;
419 u32 dpll_reg
= MRST_DPLL_A
;
420 u32 dspcntr_reg
= DSPACNTR
;
421 u32 pipeconf_reg
= PIPEACONF
;
422 u32 dsplinoff_reg
= DSPALINOFF
;
423 u32 dspsurf_reg
= DSPASURF
;
424 u32 hs_gen_ctrl_reg
= HS_GEN_CTRL_REG
;
425 u32 gen_fifo_stat_reg
= GEN_FIFO_STAT_REG
;
429 u32 fifo_stat_reg_val
;
432 u32 pipeconf_reg_val
;
434 /* If mode setting on-going, back off */
435 if ((dbi_output
->mode_flags
& MODE_SETTING_ON_GOING
) ||
436 (psb_crtc
&& psb_crtc
->mode_flags
& MODE_SETTING_ON_GOING
) ||
437 !(dbi_output
->mode_flags
& MODE_SETTING_ENCODER_DONE
))
441 * Look for errors here. In particular we're checking for whatever
442 * error status might have appeared during the last frame transmit
445 * Normally, the bits we're testing here would be set infrequently,
446 * if at all. However, one panel (at least) returns at least one
447 * error bit on most frames. So we've disabled the kernel message
450 * Still clear whatever error bits are set, except don't clear the
451 * ones that would make the Penwell DSI controller reset if we
454 intr_status
= REG_READ(INTR_STAT_REG
);
455 if ((intr_status
& 0x26FFFFFF) != 0) {
456 /* dev_err(dev->dev, "DSI status: 0x%08X\n", intr_status); */
457 intr_status
&= 0x26F3FFFF;
458 REG_WRITE(INTR_STAT_REG
, intr_status
);
462 dspcntr_reg
= DSPCCNTR
;
463 pipeconf_reg
= PIPECCONF
;
464 dsplinoff_reg
= DSPCLINOFF
;
465 dspsurf_reg
= DSPCSURF
;
467 hs_gen_ctrl_reg
= HS_GEN_CTRL_REG
+ MIPIC_REG_OFFSET
;
468 gen_fifo_stat_reg
= GEN_FIFO_STAT_REG
+ MIPIC_REG_OFFSET
,
470 reg_offset
= MIPIC_REG_OFFSET
;
473 if (!gma_power_begin(dev
, true)) {
474 dev_err(dev
->dev
, "hw begin failed\n");
478 fifo_stat_reg_val
= REG_READ(MIPIA_GEN_FIFO_STAT_REG
+ reg_offset
);
479 dpll_reg_val
= REG_READ(dpll_reg
);
480 dspcntr_reg_val
= REG_READ(dspcntr_reg
);
481 pipeconf_reg_val
= REG_READ(pipeconf_reg
);
483 if (!(fifo_stat_reg_val
& (1 << 27)) ||
484 (dpll_reg_val
& DPLL_VCO_ENABLE
) ||
485 !(dspcntr_reg_val
& DISPLAY_PLANE_ENABLE
) ||
486 !(pipeconf_reg_val
& DISPLAY_PLANE_ENABLE
)) {
490 /* Refresh plane changes */
491 REG_WRITE(dsplinoff_reg
, REG_READ(dsplinoff_reg
));
492 REG_WRITE(dspsurf_reg
, REG_READ(dspsurf_reg
));
493 REG_READ(dspsurf_reg
);
495 mdfld_dsi_send_dcs(sender
,
500 MDFLD_DSI_SEND_PACKAGE
);
503 * The idea here is to transmit a Generic Read command after the
504 * Write Memory Start/Continue commands finish. This asks for
505 * the panel to return an "ACK No Errors," or (if it has errors
506 * to report) an Error Report. This allows us to monitor the
507 * panel's perception of the health of the DSI.
509 mdfld_dsi_gen_fifo_ready(dev
, gen_fifo_stat_reg
,
510 HS_CTRL_FIFO_EMPTY
| HS_DATA_FIFO_EMPTY
);
511 REG_WRITE(hs_gen_ctrl_reg
, (1 << WORD_COUNTS_POS
) | GEN_READ_0
);
513 dbi_output
->dsr_fb_update_done
= true;
519 * TODO: will be removed later, should work out display interfaces for power
521 void pyr_dsi_adapter_init(struct mdfld_dsi_config
*dsi_config
, int pipe
)
523 if (!dsi_config
|| (pipe
!= 0 && pipe
!= 2)) {
527 pyr_dsi_controller_dbi_init(dsi_config
, pipe
);
530 static int pyr_cmd_get_panel_info(struct drm_device
*dev
, int pipe
,
531 struct panel_info
*pi
)
536 pi
->width_mm
= PYR_PANEL_WIDTH
;
537 pi
->height_mm
= PYR_PANEL_HEIGHT
;
542 /* PYR DBI encoder helper funcs */
543 static const struct drm_encoder_helper_funcs pyr_dsi_dbi_helper_funcs
= {
544 .dpms
= pyr_dsi_dbi_dpms
,
545 .mode_fixup
= pyr_dsi_dbi_mode_fixup
,
546 .prepare
= pyr_dsi_dbi_prepare
,
547 .mode_set
= pyr_dsi_dbi_mode_set
,
548 .commit
= pyr_dsi_dbi_commit
,
551 /* PYR DBI encoder funcs */
552 static const struct drm_encoder_funcs mdfld_dsi_dbi_encoder_funcs
= {
553 .destroy
= drm_encoder_cleanup
,
556 void pyr_cmd_init(struct drm_device
*dev
, struct panel_funcs
*p_funcs
)
558 p_funcs
->encoder_funcs
= &mdfld_dsi_dbi_encoder_funcs
;
559 p_funcs
->encoder_helper_funcs
= &pyr_dsi_dbi_helper_funcs
;
560 p_funcs
->get_config_mode
= &pyr_cmd_get_config_mode
;
561 p_funcs
->update_fb
= pyr_dsi_dbi_update_fb
;
562 p_funcs
->get_panel_info
= pyr_cmd_get_panel_info
;