1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include "intel_ringbuffer.h"
36 #include <linux/io-mapping.h>
38 /* General customization:
41 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
43 #define DRIVER_NAME "i915"
44 #define DRIVER_DESC "Intel Graphics"
45 #define DRIVER_DATE "20080730"
57 #define I915_NUM_PIPE 2
59 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
64 * 1.2: Add Power Management
65 * 1.3: Add vblank support
66 * 1.4: Fix cmdbuffer path, add heap destroy
67 * 1.5: Add vblank pipe configuration
68 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
69 * - Support vertical blank on secondary display pipe
71 #define DRIVER_MAJOR 1
72 #define DRIVER_MINOR 6
73 #define DRIVER_PATCHLEVEL 0
75 #define WATCH_COHERENCY 0
80 #define WATCH_INACTIVE 0
81 #define WATCH_PWRITE 0
83 #define I915_GEM_PHYS_CURSOR_0 1
84 #define I915_GEM_PHYS_CURSOR_1 2
85 #define I915_GEM_PHYS_OVERLAY_REGS 3
86 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
88 struct drm_i915_gem_phys_object
{
90 struct page
**page_list
;
91 drm_dma_handle_t
*handle
;
92 struct drm_gem_object
*cur_obj
;
96 struct mem_block
*next
;
97 struct mem_block
*prev
;
100 struct drm_file
*file_priv
; /* NULL: free, -1: heap, other: real files */
103 struct opregion_header
;
104 struct opregion_acpi
;
105 struct opregion_swsci
;
106 struct opregion_asle
;
108 struct intel_opregion
{
109 struct opregion_header
*header
;
110 struct opregion_acpi
*acpi
;
111 struct opregion_swsci
*swsci
;
112 struct opregion_asle
*asle
;
115 #define OPREGION_SIZE (8*1024)
117 struct intel_overlay
;
118 struct intel_overlay_error_state
;
120 struct drm_i915_master_private
{
121 drm_local_map_t
*sarea
;
122 struct _drm_i915_sarea
*sarea_priv
;
124 #define I915_FENCE_REG_NONE -1
126 struct drm_i915_fence_reg
{
127 struct drm_gem_object
*obj
;
128 struct list_head lru_list
;
131 struct sdvo_device_mapping
{
139 struct drm_i915_error_state
{
154 struct drm_i915_error_object
{
158 } *ringbuffer
, *batchbuffer
[2];
159 struct drm_i915_error_buffer
{
173 struct intel_overlay_error_state
*overlay
;
176 struct drm_i915_display_funcs
{
177 void (*dpms
)(struct drm_crtc
*crtc
, int mode
);
178 bool (*fbc_enabled
)(struct drm_device
*dev
);
179 void (*enable_fbc
)(struct drm_crtc
*crtc
, unsigned long interval
);
180 void (*disable_fbc
)(struct drm_device
*dev
);
181 int (*get_display_clock_speed
)(struct drm_device
*dev
);
182 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
183 void (*update_wm
)(struct drm_device
*dev
, int planea_clock
,
184 int planeb_clock
, int sr_hdisplay
, int sr_htotal
,
186 /* clock updates for mode set */
188 /* render clock increase/decrease */
189 /* display clock increase/decrease */
190 /* pll clock increase/decrease */
191 /* clock gating init */
194 struct intel_device_info
{
208 u8 is_broadwater
: 1;
213 u8 has_pipe_cxsr
: 1;
215 u8 cursor_needs_physical
: 1;
217 u8 overlay_needs_physical
: 1;
221 FBC_STOLEN_TOO_SMALL
, /* not enough space to hold compressed buffers */
222 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
223 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
224 FBC_BAD_PLANE
, /* fbc not supported on plane */
225 FBC_NOT_TILED
, /* buffer not tiled */
226 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
230 PCH_IBX
, /* Ibexpeak PCH */
231 PCH_CPT
, /* Cougarpoint PCH */
234 #define QUIRK_PIPEA_FORCE (1<<0)
238 typedef struct drm_i915_private
{
239 struct drm_device
*dev
;
241 const struct intel_device_info
*info
;
247 struct pci_dev
*bridge_dev
;
248 struct intel_ring_buffer render_ring
;
249 struct intel_ring_buffer bsd_ring
;
252 drm_dma_handle_t
*status_page_dmah
;
254 dma_addr_t dma_status_page
;
256 unsigned int seqno_gfx_addr
;
257 drm_local_map_t hws_map
;
258 struct drm_gem_object
*seqno_obj
;
259 struct drm_gem_object
*pwrctx
;
260 struct drm_gem_object
*renderctx
;
262 struct resource mch_res
;
269 #define I915_DEBUG_READ (1<<0)
270 #define I915_DEBUG_WRITE (1<<1)
271 unsigned long debug_flags
;
273 wait_queue_head_t irq_queue
;
274 atomic_t irq_received
;
275 /** Protects user_irq_refcount and irq_mask_reg */
276 spinlock_t user_irq_lock
;
278 /** Cached value of IMR to avoid reads in updating the bitfield */
281 /** splitted irq regs for graphics and display engine on Ironlake,
282 irq_mask_reg is still used for display irq. */
284 u32 gt_irq_enable_reg
;
285 u32 de_irq_enable_reg
;
286 u32 pch_irq_mask_reg
;
287 u32 pch_irq_enable_reg
;
289 u32 hotplug_supported_mask
;
290 struct work_struct hotplug_work
;
292 int tex_lru_log_granularity
;
293 int allow_batchbuffer
;
294 struct mem_block
*agp_heap
;
295 unsigned int sr01
, adpa
, ppcr
, dvob
, dvoc
, lvds
;
299 /* For hangcheck timer */
300 #define DRM_I915_HANGCHECK_PERIOD 75 /* in jiffies */
301 struct timer_list hangcheck_timer
;
304 uint32_t last_instdone
;
305 uint32_t last_instdone1
;
309 unsigned long cfb_size
;
310 unsigned long cfb_pitch
;
316 struct intel_opregion opregion
;
319 struct intel_overlay
*overlay
;
322 int backlight_duty_cycle
; /* restore backlight to this value */
323 bool panel_wants_dither
;
324 struct drm_display_mode
*panel_fixed_mode
;
325 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
326 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
328 /* Feature bits from the VBIOS */
329 unsigned int int_tv_support
:1;
330 unsigned int lvds_dither
:1;
331 unsigned int lvds_vbt
:1;
332 unsigned int int_crt_support
:1;
333 unsigned int lvds_use_ssc
:1;
334 unsigned int edp_support
:1;
338 struct notifier_block lid_notifier
;
340 int crt_ddc_bus
; /* 0 = unknown, else GPIO to use for CRT DDC */
341 struct drm_i915_fence_reg fence_regs
[16]; /* assume 965 */
342 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
343 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
345 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
347 spinlock_t error_lock
;
348 struct drm_i915_error_state
*first_error
;
349 struct work_struct error_work
;
350 struct workqueue_struct
*wq
;
352 /* Display functions */
353 struct drm_i915_display_funcs display
;
355 /* PCH chipset type */
356 enum intel_pch pch_type
;
358 unsigned long quirks
;
383 u32 saveTRANS_HTOTAL_A
;
384 u32 saveTRANS_HBLANK_A
;
385 u32 saveTRANS_HSYNC_A
;
386 u32 saveTRANS_VTOTAL_A
;
387 u32 saveTRANS_VBLANK_A
;
388 u32 saveTRANS_VSYNC_A
;
396 u32 savePFIT_PGM_RATIOS
;
397 u32 saveBLC_HIST_CTL
;
399 u32 saveBLC_PWM_CTL2
;
400 u32 saveBLC_CPU_PWM_CTL
;
401 u32 saveBLC_CPU_PWM_CTL2
;
414 u32 saveTRANS_HTOTAL_B
;
415 u32 saveTRANS_HBLANK_B
;
416 u32 saveTRANS_HSYNC_B
;
417 u32 saveTRANS_VTOTAL_B
;
418 u32 saveTRANS_VBLANK_B
;
419 u32 saveTRANS_VSYNC_B
;
433 u32 savePP_ON_DELAYS
;
434 u32 savePP_OFF_DELAYS
;
442 u32 savePFIT_CONTROL
;
443 u32 save_palette_a
[256];
444 u32 save_palette_b
[256];
445 u32 saveDPFC_CB_BASE
;
446 u32 saveFBC_CFB_BASE
;
449 u32 saveFBC_CONTROL2
;
459 u32 saveCACHE_MODE_0
;
460 u32 saveMI_ARB_STATE
;
471 uint64_t saveFENCE
[16];
482 u32 savePIPEA_GMCH_DATA_M
;
483 u32 savePIPEB_GMCH_DATA_M
;
484 u32 savePIPEA_GMCH_DATA_N
;
485 u32 savePIPEB_GMCH_DATA_N
;
486 u32 savePIPEA_DP_LINK_M
;
487 u32 savePIPEB_DP_LINK_M
;
488 u32 savePIPEA_DP_LINK_N
;
489 u32 savePIPEB_DP_LINK_N
;
500 u32 savePCH_DREF_CONTROL
;
501 u32 saveDISP_ARB_CTL
;
502 u32 savePIPEA_DATA_M1
;
503 u32 savePIPEA_DATA_N1
;
504 u32 savePIPEA_LINK_M1
;
505 u32 savePIPEA_LINK_N1
;
506 u32 savePIPEB_DATA_M1
;
507 u32 savePIPEB_DATA_N1
;
508 u32 savePIPEB_LINK_M1
;
509 u32 savePIPEB_LINK_N1
;
510 u32 saveMCHBAR_RENDER_STANDBY
;
513 struct drm_mm gtt_space
;
515 struct io_mapping
*gtt_mapping
;
519 * Membership on list of all loaded devices, used to evict
520 * inactive buffers under memory pressure.
522 * Modifications should only be done whilst holding the
523 * shrink_list_lock spinlock.
525 struct list_head shrink_list
;
527 spinlock_t active_list_lock
;
530 * List of objects which are not in the ringbuffer but which
531 * still have a write_domain which needs to be flushed before
534 * last_rendering_seqno is 0 while an object is in this list.
536 * A reference is held on the buffer while on this list.
538 struct list_head flushing_list
;
541 * List of objects currently pending a GPU write flush.
543 * All elements on this list will belong to either the
544 * active_list or flushing_list, last_rendering_seqno can
545 * be used to differentiate between the two elements.
547 struct list_head gpu_write_list
;
550 * LRU list of objects which are not in the ringbuffer and
551 * are ready to unbind, but are still in the GTT.
553 * last_rendering_seqno is 0 while an object is in this list.
555 * A reference is not held on the buffer while on this list,
556 * as merely being GTT-bound shouldn't prevent its being
557 * freed, and we'll pull it off the list in the free path.
559 struct list_head inactive_list
;
561 /** LRU list of objects with fence regs on them. */
562 struct list_head fence_list
;
565 * List of objects currently pending being freed.
567 * These objects are no longer in use, but due to a signal
568 * we were prevented from freeing them at the appointed time.
570 struct list_head deferred_free_list
;
573 * We leave the user IRQ off as much as possible,
574 * but this means that requests will finish and never
575 * be retired once the system goes idle. Set a timer to
576 * fire periodically while the ring is running. When it
577 * fires, go retire requests.
579 struct delayed_work retire_work
;
582 * Waiting sequence number, if any
584 uint32_t waiting_gem_seqno
;
587 * Last seq seen at irq time
589 uint32_t irq_gem_seqno
;
592 * Flag if the X Server, and thus DRM, is not currently in
593 * control of the device.
595 * This is set between LeaveVT and EnterVT. It needs to be
596 * replaced with a semaphore. It also needs to be
597 * transitioned away from for kernel modesetting.
602 * Flag if the hardware appears to be wedged.
604 * This is set when attempts to idle the device timeout.
605 * It prevents command submission from occuring and makes
606 * every pending request fail
610 /** Bit 6 swizzling required for X tiling */
611 uint32_t bit_6_swizzle_x
;
612 /** Bit 6 swizzling required for Y tiling */
613 uint32_t bit_6_swizzle_y
;
615 /* storage for physical objects */
616 struct drm_i915_gem_phys_object
*phys_objs
[I915_MAX_PHYS_OBJECT
];
618 struct sdvo_device_mapping sdvo_mappings
[2];
619 /* indicate whether the LVDS_BORDER should be enabled or not */
620 unsigned int lvds_border_bits
;
621 /* Panel fitter placement and size for Ironlake+ */
622 u32 pch_pf_pos
, pch_pf_size
;
624 struct drm_crtc
*plane_to_crtc_mapping
[2];
625 struct drm_crtc
*pipe_to_crtc_mapping
[2];
626 wait_queue_head_t pending_flip_queue
;
627 bool flip_pending_is_done
;
629 /* Reclocking support */
630 bool render_reclock_avail
;
631 bool lvds_downclock_avail
;
632 /* indicate whether the LVDS EDID is OK */
634 /* indicates the reduced downclock for LVDS*/
636 struct work_struct idle_work
;
637 struct timer_list idle_timer
;
641 struct child_device_config
*child_dev
;
642 struct drm_connector
*int_lvds_connector
;
644 bool mchbar_need_disable
;
653 unsigned long last_time1
;
655 struct timespec last_time2
;
656 unsigned long gfx_power
;
660 spinlock_t
*mchdev_lock
;
662 enum no_fbc_reason no_fbc_reason
;
664 struct drm_mm_node
*compressed_fb
;
665 struct drm_mm_node
*compressed_llb
;
667 /* list of fbdev register on this device */
668 struct intel_fbdev
*fbdev
;
669 } drm_i915_private_t
;
671 /** driver private structure attached to each drm_gem_object */
672 struct drm_i915_gem_object
{
673 struct drm_gem_object base
;
675 /** Current space allocated to this object in the GTT, if any. */
676 struct drm_mm_node
*gtt_space
;
678 /** This object's place on the active/flushing/inactive lists */
679 struct list_head list
;
680 /** This object's place on GPU write list */
681 struct list_head gpu_write_list
;
682 /** This object's place on eviction list */
683 struct list_head evict_list
;
686 * This is set if the object is on the active or flushing lists
687 * (has pending rendering), and is not set if it's on inactive (ready
690 unsigned int active
: 1;
693 * This is set if the object has been written to since last bound
696 unsigned int dirty
: 1;
699 * Fence register bits (if any) for this object. Will be set
700 * as needed when mapped into the GTT.
701 * Protected by dev->struct_mutex.
703 * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE)
705 signed int fence_reg
: 5;
708 * Used for checking the object doesn't appear more than once
709 * in an execbuffer object list.
711 unsigned int in_execbuffer
: 1;
714 * Advice: are the backing pages purgeable?
716 unsigned int madv
: 2;
719 * Refcount for the pages array. With the current locking scheme, there
720 * are at most two concurrent users: Binding a bo to the gtt and
721 * pwrite/pread using physical addresses. So two bits for a maximum
722 * of two users are enough.
724 unsigned int pages_refcount
: 2;
725 #define DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT 0x3
728 * Current tiling mode for the object.
730 unsigned int tiling_mode
: 2;
732 /** How many users have pinned this object in GTT space. The following
733 * users can each hold at most one reference: pwrite/pread, pin_ioctl
734 * (via user_pin_count), execbuffer (objects are not allowed multiple
735 * times for the same batchbuffer), and the framebuffer code. When
736 * switching/pageflipping, the framebuffer code has at most two buffers
739 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
740 * bits with absolutely no headroom. So use 4 bits. */
741 unsigned int pin_count
: 4;
742 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
744 /** AGP memory structure for our GTT binding. */
745 DRM_AGP_MEM
*agp_mem
;
750 * Current offset of the object in GTT space.
752 * This is the same as gtt_space->start
756 /* Which ring is refering to is this object */
757 struct intel_ring_buffer
*ring
;
760 * Fake offset for use by mmap(2)
762 uint64_t mmap_offset
;
764 /** Breadcrumb of last rendering to the buffer. */
765 uint32_t last_rendering_seqno
;
767 /** Current tiling stride for the object, if it's tiled. */
770 /** Record of address bit 17 of each page at last unbind. */
771 unsigned long *bit_17
;
773 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
777 * If present, while GEM_DOMAIN_CPU is in the read domain this array
778 * flags which individual pages are valid.
780 uint8_t *page_cpu_valid
;
782 /** User space pin count and filp owning the pin */
783 uint32_t user_pin_count
;
784 struct drm_file
*pin_filp
;
786 /** for phy allocated objects */
787 struct drm_i915_gem_phys_object
*phys_obj
;
790 * Number of crtcs where this object is currently the fb, but
791 * will be page flipped away on the next vblank. When it
792 * reaches 0, dev_priv->pending_flip_queue will be woken up.
794 atomic_t pending_flip
;
797 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
800 * Request queue structure.
802 * The request queue allows us to note sequence numbers that have been emitted
803 * and may be associated with active buffers to be retired.
805 * By keeping this list, we can avoid having to do questionable
806 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
807 * an emission time with seqnos for tracking how far ahead of the GPU we are.
809 struct drm_i915_gem_request
{
810 /** On Which ring this request was generated */
811 struct intel_ring_buffer
*ring
;
813 /** GEM sequence number associated with this request. */
816 /** Time at which this request was emitted, in jiffies. */
817 unsigned long emitted_jiffies
;
819 /** global list entry for this request */
820 struct list_head list
;
822 /** file_priv list entry for this request */
823 struct list_head client_list
;
826 struct drm_i915_file_private
{
828 struct list_head request_list
;
832 enum intel_chip_family
{
839 extern struct drm_ioctl_desc i915_ioctls
[];
840 extern int i915_max_ioctl
;
841 extern unsigned int i915_fbpercrtc
;
842 extern unsigned int i915_powersave
;
843 extern unsigned int i915_lvds_downclock
;
845 extern int i915_suspend(struct drm_device
*dev
, pm_message_t state
);
846 extern int i915_resume(struct drm_device
*dev
);
847 extern void i915_save_display(struct drm_device
*dev
);
848 extern void i915_restore_display(struct drm_device
*dev
);
849 extern int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
);
850 extern void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
);
853 extern void i915_kernel_lost_context(struct drm_device
* dev
);
854 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
855 extern int i915_driver_unload(struct drm_device
*);
856 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file_priv
);
857 extern void i915_driver_lastclose(struct drm_device
* dev
);
858 extern void i915_driver_preclose(struct drm_device
*dev
,
859 struct drm_file
*file_priv
);
860 extern void i915_driver_postclose(struct drm_device
*dev
,
861 struct drm_file
*file_priv
);
862 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
863 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
865 extern int i915_emit_box(struct drm_device
*dev
,
866 struct drm_clip_rect
*boxes
,
867 int i
, int DR1
, int DR4
);
868 extern int i965_reset(struct drm_device
*dev
, u8 flags
);
869 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
870 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
871 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
872 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
876 void i915_hangcheck_elapsed(unsigned long data
);
877 extern int i915_irq_emit(struct drm_device
*dev
, void *data
,
878 struct drm_file
*file_priv
);
879 extern int i915_irq_wait(struct drm_device
*dev
, void *data
,
880 struct drm_file
*file_priv
);
881 void i915_trace_irq_get(struct drm_device
*dev
, u32 seqno
);
882 extern void i915_enable_interrupt (struct drm_device
*dev
);
884 extern irqreturn_t
i915_driver_irq_handler(DRM_IRQ_ARGS
);
885 extern void i915_driver_irq_preinstall(struct drm_device
* dev
);
886 extern int i915_driver_irq_postinstall(struct drm_device
*dev
);
887 extern void i915_driver_irq_uninstall(struct drm_device
* dev
);
888 extern int i915_vblank_pipe_set(struct drm_device
*dev
, void *data
,
889 struct drm_file
*file_priv
);
890 extern int i915_vblank_pipe_get(struct drm_device
*dev
, void *data
,
891 struct drm_file
*file_priv
);
892 extern int i915_enable_vblank(struct drm_device
*dev
, int crtc
);
893 extern void i915_disable_vblank(struct drm_device
*dev
, int crtc
);
894 extern u32
i915_get_vblank_counter(struct drm_device
*dev
, int crtc
);
895 extern u32
gm45_get_vblank_counter(struct drm_device
*dev
, int crtc
);
896 extern int i915_vblank_swap(struct drm_device
*dev
, void *data
,
897 struct drm_file
*file_priv
);
898 extern void i915_enable_irq(drm_i915_private_t
*dev_priv
, u32 mask
);
899 extern void i915_disable_irq(drm_i915_private_t
*dev_priv
, u32 mask
);
900 extern void ironlake_enable_graphics_irq(drm_i915_private_t
*dev_priv
,
902 extern void ironlake_disable_graphics_irq(drm_i915_private_t
*dev_priv
,
906 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
909 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
911 void intel_enable_asle (struct drm_device
*dev
);
913 #ifdef CONFIG_DEBUG_FS
914 extern void i915_destroy_error_state(struct drm_device
*dev
);
916 #define i915_destroy_error_state(x)
921 extern int i915_mem_alloc(struct drm_device
*dev
, void *data
,
922 struct drm_file
*file_priv
);
923 extern int i915_mem_free(struct drm_device
*dev
, void *data
,
924 struct drm_file
*file_priv
);
925 extern int i915_mem_init_heap(struct drm_device
*dev
, void *data
,
926 struct drm_file
*file_priv
);
927 extern int i915_mem_destroy_heap(struct drm_device
*dev
, void *data
,
928 struct drm_file
*file_priv
);
929 extern void i915_mem_takedown(struct mem_block
**heap
);
930 extern void i915_mem_release(struct drm_device
* dev
,
931 struct drm_file
*file_priv
, struct mem_block
*heap
);
933 int i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
934 struct drm_file
*file_priv
);
935 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
936 struct drm_file
*file_priv
);
937 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
938 struct drm_file
*file_priv
);
939 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
940 struct drm_file
*file_priv
);
941 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
942 struct drm_file
*file_priv
);
943 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
944 struct drm_file
*file_priv
);
945 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
946 struct drm_file
*file_priv
);
947 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
948 struct drm_file
*file_priv
);
949 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
950 struct drm_file
*file_priv
);
951 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
952 struct drm_file
*file_priv
);
953 int i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
954 struct drm_file
*file_priv
);
955 int i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
956 struct drm_file
*file_priv
);
957 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
958 struct drm_file
*file_priv
);
959 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
960 struct drm_file
*file_priv
);
961 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
962 struct drm_file
*file_priv
);
963 int i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
964 struct drm_file
*file_priv
);
965 int i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
966 struct drm_file
*file_priv
);
967 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
968 struct drm_file
*file_priv
);
969 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
970 struct drm_file
*file_priv
);
971 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
972 struct drm_file
*file_priv
);
973 void i915_gem_load(struct drm_device
*dev
);
974 int i915_gem_init_object(struct drm_gem_object
*obj
);
975 struct drm_gem_object
* i915_gem_alloc_object(struct drm_device
*dev
,
977 void i915_gem_free_object(struct drm_gem_object
*obj
);
978 int i915_gem_object_pin(struct drm_gem_object
*obj
, uint32_t alignment
);
979 void i915_gem_object_unpin(struct drm_gem_object
*obj
);
980 int i915_gem_object_unbind(struct drm_gem_object
*obj
);
981 void i915_gem_release_mmap(struct drm_gem_object
*obj
);
982 void i915_gem_lastclose(struct drm_device
*dev
);
983 uint32_t i915_get_gem_seqno(struct drm_device
*dev
,
984 struct intel_ring_buffer
*ring
);
985 bool i915_seqno_passed(uint32_t seq1
, uint32_t seq2
);
986 int i915_gem_object_get_fence_reg(struct drm_gem_object
*obj
);
987 int i915_gem_object_put_fence_reg(struct drm_gem_object
*obj
);
988 void i915_gem_retire_requests(struct drm_device
*dev
);
989 void i915_gem_clflush_object(struct drm_gem_object
*obj
);
990 int i915_gem_object_set_domain(struct drm_gem_object
*obj
,
991 uint32_t read_domains
,
992 uint32_t write_domain
);
993 int i915_gem_init_ringbuffer(struct drm_device
*dev
);
994 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
995 int i915_gem_do_init(struct drm_device
*dev
, unsigned long start
,
997 int i915_gpu_idle(struct drm_device
*dev
);
998 int i915_gem_idle(struct drm_device
*dev
);
999 uint32_t i915_add_request(struct drm_device
*dev
,
1000 struct drm_file
*file_priv
,
1001 struct drm_i915_gem_request
*request
,
1002 struct intel_ring_buffer
*ring
);
1003 int i915_do_wait_request(struct drm_device
*dev
,
1006 struct intel_ring_buffer
*ring
);
1007 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
1008 void i915_gem_process_flushing_list(struct drm_device
*dev
,
1009 uint32_t flush_domains
,
1010 struct intel_ring_buffer
*ring
);
1011 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object
*obj
,
1013 int i915_gem_object_set_to_display_plane(struct drm_gem_object
*obj
);
1014 int i915_gem_attach_phys_object(struct drm_device
*dev
,
1015 struct drm_gem_object
*obj
,
1018 void i915_gem_detach_phys_object(struct drm_device
*dev
,
1019 struct drm_gem_object
*obj
);
1020 void i915_gem_free_all_phys_object(struct drm_device
*dev
);
1021 int i915_gem_object_get_pages(struct drm_gem_object
*obj
, gfp_t gfpmask
);
1022 void i915_gem_object_put_pages(struct drm_gem_object
*obj
);
1023 void i915_gem_release(struct drm_device
* dev
, struct drm_file
*file_priv
);
1024 int i915_gem_object_flush_write_domain(struct drm_gem_object
*obj
);
1026 void i915_gem_shrinker_init(void);
1027 void i915_gem_shrinker_exit(void);
1029 /* i915_gem_evict.c */
1030 int i915_gem_evict_something(struct drm_device
*dev
, int min_size
, unsigned alignment
);
1031 int i915_gem_evict_everything(struct drm_device
*dev
);
1032 int i915_gem_evict_inactive(struct drm_device
*dev
);
1034 /* i915_gem_tiling.c */
1035 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
1036 void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object
*obj
);
1037 void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object
*obj
);
1038 bool i915_tiling_ok(struct drm_device
*dev
, int stride
, int size
,
1040 bool i915_gem_object_fence_offset_ok(struct drm_gem_object
*obj
,
1043 /* i915_gem_debug.c */
1044 void i915_gem_dump_object(struct drm_gem_object
*obj
, int len
,
1045 const char *where
, uint32_t mark
);
1047 void i915_verify_inactive(struct drm_device
*dev
, char *file
, int line
);
1049 #define i915_verify_inactive(dev, file, line)
1051 void i915_gem_object_check_coherency(struct drm_gem_object
*obj
, int handle
);
1052 void i915_gem_dump_object(struct drm_gem_object
*obj
, int len
,
1053 const char *where
, uint32_t mark
);
1054 void i915_dump_lru(struct drm_device
*dev
, const char *where
);
1056 /* i915_debugfs.c */
1057 int i915_debugfs_init(struct drm_minor
*minor
);
1058 void i915_debugfs_cleanup(struct drm_minor
*minor
);
1060 /* i915_suspend.c */
1061 extern int i915_save_state(struct drm_device
*dev
);
1062 extern int i915_restore_state(struct drm_device
*dev
);
1064 /* i915_suspend.c */
1065 extern int i915_save_state(struct drm_device
*dev
);
1066 extern int i915_restore_state(struct drm_device
*dev
);
1068 /* intel_opregion.c */
1069 extern int intel_opregion_setup(struct drm_device
*dev
);
1071 extern void intel_opregion_init(struct drm_device
*dev
);
1072 extern void intel_opregion_fini(struct drm_device
*dev
);
1073 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
1074 extern void intel_opregion_gse_intr(struct drm_device
*dev
);
1075 extern void intel_opregion_enable_asle(struct drm_device
*dev
);
1077 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
1078 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
1079 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
1080 static inline void intel_opregion_gse_intr(struct drm_device
*dev
) { return; }
1081 static inline void intel_opregion_enable_asle(struct drm_device
*dev
) { return; }
1085 extern void intel_modeset_init(struct drm_device
*dev
);
1086 extern void intel_modeset_cleanup(struct drm_device
*dev
);
1087 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
1088 extern void i8xx_disable_fbc(struct drm_device
*dev
);
1089 extern void g4x_disable_fbc(struct drm_device
*dev
);
1090 extern void ironlake_disable_fbc(struct drm_device
*dev
);
1091 extern void intel_disable_fbc(struct drm_device
*dev
);
1092 extern void intel_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
);
1093 extern bool intel_fbc_enabled(struct drm_device
*dev
);
1094 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
1095 extern void intel_detect_pch (struct drm_device
*dev
);
1096 extern int intel_trans_dp_port_sel (struct drm_crtc
*crtc
);
1099 #ifdef CONFIG_DEBUG_FS
1100 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
1101 extern void intel_overlay_print_error_state(struct seq_file
*m
, struct intel_overlay_error_state
*error
);
1105 * Lock test for when it's just for synchronization of ring access.
1107 * In that case, we don't need to do it when GEM is initialized as nobody else
1108 * has access to the ring.
1110 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
1111 if (((drm_i915_private_t *)dev->dev_private)->render_ring.gem_object \
1113 LOCK_TEST_WITH_RETURN(dev, file_priv); \
1116 static inline u32
i915_read(struct drm_i915_private
*dev_priv
, u32 reg
)
1120 val
= readl(dev_priv
->regs
+ reg
);
1121 if (dev_priv
->debug_flags
& I915_DEBUG_READ
)
1122 printk(KERN_ERR
"read 0x%08x from 0x%08x\n", val
, reg
);
1126 static inline void i915_write(struct drm_i915_private
*dev_priv
, u32 reg
,
1129 writel(val
, dev_priv
->regs
+ reg
);
1130 if (dev_priv
->debug_flags
& I915_DEBUG_WRITE
)
1131 printk(KERN_ERR
"wrote 0x%08x to 0x%08x\n", val
, reg
);
1134 #define I915_READ(reg) i915_read(dev_priv, (reg))
1135 #define I915_WRITE(reg, val) i915_write(dev_priv, (reg), (val))
1136 #define I915_READ16(reg) readw(dev_priv->regs + (reg))
1137 #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
1138 #define I915_READ8(reg) readb(dev_priv->regs + (reg))
1139 #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
1140 #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
1141 #define I915_READ64(reg) readq(dev_priv->regs + (reg))
1142 #define POSTING_READ(reg) (void)I915_READ(reg)
1143 #define POSTING_READ16(reg) (void)I915_READ16(reg)
1145 #define I915_DEBUG_ENABLE_IO() (dev_priv->debug_flags |= I915_DEBUG_READ | \
1147 #define I915_DEBUG_DISABLE_IO() (dev_priv->debug_flags &= ~(I915_DEBUG_READ | \
1150 #define I915_VERBOSE 0
1152 #define BEGIN_LP_RING(n) do { \
1153 drm_i915_private_t *dev_priv__ = dev->dev_private; \
1155 DRM_DEBUG(" BEGIN_LP_RING %x\n", (int)(n)); \
1156 intel_ring_begin(dev, &dev_priv__->render_ring, (n)); \
1160 #define OUT_RING(x) do { \
1161 drm_i915_private_t *dev_priv__ = dev->dev_private; \
1163 DRM_DEBUG(" OUT_RING %x\n", (int)(x)); \
1164 intel_ring_emit(dev, &dev_priv__->render_ring, x); \
1167 #define ADVANCE_LP_RING() do { \
1168 drm_i915_private_t *dev_priv__ = dev->dev_private; \
1170 DRM_DEBUG("ADVANCE_LP_RING %x\n", \
1171 dev_priv__->render_ring.tail); \
1172 intel_ring_advance(dev, &dev_priv__->render_ring); \
1176 * Reads a dword out of the status page, which is written to from the command
1177 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
1178 * MI_STORE_DATA_IMM.
1180 * The following dwords have a reserved meaning:
1181 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
1182 * 0x04: ring 0 head pointer
1183 * 0x05: ring 1 head pointer (915-class)
1184 * 0x06: ring 2 head pointer (915-class)
1185 * 0x10-0x1b: Context status DWords (GM45)
1186 * 0x1f: Last written status offset. (GM45)
1188 * The area from dword 0x20 to 0x3ff is available for driver usage.
1190 #define READ_HWSP(dev_priv, reg) (((volatile u32 *)\
1191 (dev_priv->render_ring.status_page.page_addr))[reg])
1192 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
1193 #define I915_GEM_HWS_INDEX 0x20
1194 #define I915_BREADCRUMB_INDEX 0x21
1196 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1198 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1199 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1200 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1201 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1202 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1203 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1204 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1205 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1206 #define IS_I965G(dev) (INTEL_INFO(dev)->is_i965g)
1207 #define IS_I965GM(dev) (INTEL_INFO(dev)->is_i965gm)
1208 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1209 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1210 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1211 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1212 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1213 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1214 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1215 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1216 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1217 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1218 #define IS_IRONLAKE(dev) (INTEL_INFO(dev)->is_ironlake)
1219 #define IS_I9XX(dev) (INTEL_INFO(dev)->is_i9xx)
1220 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1222 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1223 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1224 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1225 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1226 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1228 #define HAS_BSD(dev) (IS_IRONLAKE(dev) || IS_G4X(dev))
1229 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1231 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1232 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1234 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1235 * rows, which changed the alignment requirements and fence programming.
1237 #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
1239 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (IS_I9XX(dev) && !IS_PINEVIEW(dev))
1240 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1241 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1242 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1243 #define SUPPORTS_TV(dev) (IS_I9XX(dev) && IS_MOBILE(dev) && \
1244 !IS_IRONLAKE(dev) && !IS_PINEVIEW(dev) && \
1246 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1247 /* dsparb controlled by hw only */
1248 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1250 #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IRONLAKE(dev))
1251 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1252 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1253 #define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
1255 #define HAS_PCH_SPLIT(dev) (IS_IRONLAKE(dev) || \
1257 #define HAS_PIPE_CONTROL(dev) (IS_IRONLAKE(dev) || IS_GEN6(dev))
1259 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1260 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1262 #define PRIMARY_RINGBUFFER_SIZE (128*1024)