arch/arm/mach-pnx4008/clock.c

   1 /*
   2  * arch/arm/mach-pnx4008/clock.c
   3  *
   4  * Clock control driver for PNX4008
   5  *
   6  * Authors: Vitaly Wool, Dmitry Chigirev <source@mvista.com>
   7  * Generic clock management functions are partially based on:
   8  *  linux/arch/arm/mach-omap/clock.c
   9  *
  10  * 2005-2006 (c) MontaVista Software, Inc. This file is licensed under
  11  * the terms of the GNU General Public License version 2. This program
  12  * is licensed "as is" without any warranty of any kind, whether express
  13  * or implied.
  14  */
  15
  16 #include <linux/module.h>
  17 #include <linux/kernel.h>
  18 #include <linux/list.h>
  19 #include <linux/errno.h>
  20 #include <linux/device.h>
  21 #include <linux/err.h>
  22 #include <linux/delay.h>
  23 #include <linux/io.h>
  24
  25 #include <asm/clkdev.h>
  26
  27 #include <mach/hardware.h>
  28 #include <mach/clock.h>
  29 #include "clock.h"
  30
  31 /*forward declaration*/
  32 static struct clk per_ck;
  33 static struct clk hclk_ck;
  34 static struct clk ck_1MHz;
  35 static struct clk ck_13MHz;
  36 static struct clk ck_pll1;
  37 static int local_set_rate(struct clk *clk, u32 rate);
  38
  39 static inline void clock_lock(void)
  40 {
  41         local_irq_disable();
  42 }
  43
  44 static inline void clock_unlock(void)
  45 {
  46         local_irq_enable();
  47 }
  48
  49 static void propagate_rate(struct clk *clk)
  50 {
  51         struct clk *tmp_clk;
  52
  53         tmp_clk = clk;
  54         while (tmp_clk->propagate_next) {
  55                 tmp_clk = tmp_clk->propagate_next;
  56                 local_set_rate(tmp_clk, tmp_clk->user_rate);
  57         }
  58 }
  59
  60 static void clk_reg_disable(struct clk *clk)
  61 {
  62         if (clk->enable_reg)
  63                 __raw_writel(__raw_readl(clk->enable_reg) &
  64                              ~(1 << clk->enable_shift), clk->enable_reg);
  65 }
  66
  67 static int clk_reg_enable(struct clk *clk)
  68 {
  69         if (clk->enable_reg)
  70                 __raw_writel(__raw_readl(clk->enable_reg) |
  71                              (1 << clk->enable_shift), clk->enable_reg);
  72         return 0;
  73 }
  74
  75 static inline void clk_reg_disable1(struct clk *clk)
  76 {
  77         if (clk->enable_reg1)
  78                 __raw_writel(__raw_readl(clk->enable_reg1) &
  79                              ~(1 << clk->enable_shift1), clk->enable_reg1);
  80 }
  81
  82 static inline void clk_reg_enable1(struct clk *clk)
  83 {
  84         if (clk->enable_reg1)
  85                 __raw_writel(__raw_readl(clk->enable_reg1) |
  86                              (1 << clk->enable_shift1), clk->enable_reg1);
  87 }
  88
  89 static int clk_wait_for_pll_lock(struct clk *clk)
  90 {
  91         int i;
  92         i = 0;
  93         while (i++ < 0xFFF && !(__raw_readl(clk->scale_reg) & 1)) ;     /*wait for PLL to lock */
  94
  95         if (!(__raw_readl(clk->scale_reg) & 1)) {
  96                 printk(KERN_ERR
  97                        "%s ERROR: failed to lock, scale reg data: %x\n",
  98                        clk->name, __raw_readl(clk->scale_reg));
  99                 return -1;
 100         }
 101         return 0;
 102 }
 103
 104 static int switch_to_dirty_13mhz(struct clk *clk)
 105 {
 106         int i;
 107         int ret;
 108         u32 tmp_reg;
 109
 110         ret = 0;
 111
 112         if (!clk->rate)
 113                 clk_reg_enable1(clk);
 114
 115         tmp_reg = __raw_readl(clk->parent_switch_reg);
 116         /*if 13Mhz clock selected, select 13'MHz (dirty) source from OSC */
 117         if (!(tmp_reg & 1)) {
 118                 tmp_reg |= (1 << 1);    /* Trigger switch to 13'MHz (dirty) clock */
 119                 __raw_writel(tmp_reg, clk->parent_switch_reg);
 120                 i = 0;
 121                 while (i++ < 0xFFF && !(__raw_readl(clk->parent_switch_reg) & 1)) ;     /*wait for 13'MHz selection status */
 122
 123                 if (!(__raw_readl(clk->parent_switch_reg) & 1)) {
 124                         printk(KERN_ERR
 125                                "%s ERROR: failed to select 13'MHz, parent sw reg data: %x\n",
 126                                clk->name, __raw_readl(clk->parent_switch_reg));
 127                         ret = -1;
 128                 }
 129         }
 130
 131         if (!clk->rate)
 132                 clk_reg_disable1(clk);
 133
 134         return ret;
 135 }
 136
 137 static int switch_to_clean_13mhz(struct clk *clk)
 138 {
 139         int i;
 140         int ret;
 141         u32 tmp_reg;
 142
 143         ret = 0;
 144
 145         if (!clk->rate)
 146                 clk_reg_enable1(clk);
 147
 148         tmp_reg = __raw_readl(clk->parent_switch_reg);
 149         /*if 13'Mhz clock selected, select 13MHz (clean) source from OSC */
 150         if (tmp_reg & 1) {
 151                 tmp_reg &= ~(1 << 1);   /* Trigger switch to 13MHz (clean) clock */
 152                 __raw_writel(tmp_reg, clk->parent_switch_reg);
 153                 i = 0;
 154                 while (i++ < 0xFFF && (__raw_readl(clk->parent_switch_reg) & 1)) ;      /*wait for 13MHz selection status */
 155
 156                 if (__raw_readl(clk->parent_switch_reg) & 1) {
 157                         printk(KERN_ERR
 158                                "%s ERROR: failed to select 13MHz, parent sw reg data: %x\n",
 159                                clk->name, __raw_readl(clk->parent_switch_reg));
 160                         ret = -1;
 161                 }
 162         }
 163
 164         if (!clk->rate)
 165                 clk_reg_disable1(clk);
 166
 167         return ret;
 168 }
 169
 170 static int set_13MHz_parent(struct clk *clk, struct clk *parent)
 171 {
 172         int ret = -EINVAL;
 173
 174         if (parent == &ck_13MHz)
 175                 ret = switch_to_clean_13mhz(clk);
 176         else if (parent == &ck_pll1)
 177                 ret = switch_to_dirty_13mhz(clk);
 178
 179         return ret;
 180 }
 181
 182 #define PLL160_MIN_FCCO 156000
 183 #define PLL160_MAX_FCCO 320000
 184
 185 /*
 186  * Calculate pll160 settings.
 187  * Possible input: up to 320MHz with step of clk->parent->rate.
 188  * In PNX4008 parent rate for pll160s may be either 1 or 13MHz.
 189  * Ignored paths: "feedback" (bit 13 set), "div-by-N".
 190  * Setting ARM PLL4 rate to 0 will put CPU into direct run mode.
 191  * Setting PLL5 and PLL3 rate to 0 will disable USB and DSP clock input.
 192  * Please refer to PNX4008 IC manual for details.
 193  */
 194
 195 static int pll160_set_rate(struct clk *clk, u32 rate)
 196 {
 197         u32 tmp_reg, tmp_m, tmp_2p, i;
 198         u32 parent_rate;
 199         int ret = -EINVAL;
 200
 201         parent_rate = clk->parent->rate;
 202
 203         if (!parent_rate)
 204                 goto out;
 205
 206         /* set direct run for ARM or disable output for others  */
 207         clk_reg_disable(clk);
 208
 209         /* disable source input as well (ignored for ARM) */
 210         clk_reg_disable1(clk);
 211
 212         tmp_reg = __raw_readl(clk->scale_reg);
 213         tmp_reg &= ~0x1ffff;    /*clear all settings, power down */
 214         __raw_writel(tmp_reg, clk->scale_reg);
 215
 216         rate -= rate % parent_rate;     /*round down the input */
 217
 218         if (rate > PLL160_MAX_FCCO)
 219                 rate = PLL160_MAX_FCCO;
 220
 221         if (!rate) {
 222                 clk->rate = 0;
 223                 ret = 0;
 224                 goto out;
 225         }
 226
 227         clk_reg_enable1(clk);
 228         tmp_reg = __raw_readl(clk->scale_reg);
 229
 230         if (rate == parent_rate) {
 231                 /*enter direct bypass mode */
 232                 tmp_reg |= ((1 << 14) | (1 << 15));
 233                 __raw_writel(tmp_reg, clk->scale_reg);
 234                 clk->rate = parent_rate;
 235                 clk_reg_enable(clk);
 236                 ret = 0;
 237                 goto out;
 238         }
 239
 240         i = 0;
 241         for (tmp_2p = 1; tmp_2p < 16; tmp_2p <<= 1) {
 242                 if (rate * tmp_2p >= PLL160_MIN_FCCO)
 243                         break;
 244                 i++;
 245         }
 246
 247         if (tmp_2p > 1)
 248                 tmp_reg |= ((i - 1) << 11);
 249         else
 250                 tmp_reg |= (1 << 14);   /*direct mode, no divide */
 251
 252         tmp_m = rate * tmp_2p;
 253         tmp_m /= parent_rate;
 254
 255         tmp_reg |= (tmp_m - 1) << 1;    /*calculate M */
 256         tmp_reg |= (1 << 16);   /*power up PLL */
 257         __raw_writel(tmp_reg, clk->scale_reg);
 258
 259         if (clk_wait_for_pll_lock(clk) < 0) {
 260                 clk_reg_disable(clk);
 261                 clk_reg_disable1(clk);
 262
 263                 tmp_reg = __raw_readl(clk->scale_reg);
 264                 tmp_reg &= ~0x1ffff;    /*clear all settings, power down */
 265                 __raw_writel(tmp_reg, clk->scale_reg);
 266                 clk->rate = 0;
 267                 ret = -EFAULT;
 268                 goto out;
 269         }
 270
 271         clk->rate = (tmp_m * parent_rate) / tmp_2p;
 272
 273         if (clk->flags & RATE_PROPAGATES)
 274                 propagate_rate(clk);
 275
 276         clk_reg_enable(clk);
 277         ret = 0;
 278
 279 out:
 280         return ret;
 281 }
 282
 283 /*configure PER_CLK*/
 284 static int per_clk_set_rate(struct clk *clk, u32 rate)
 285 {
 286         u32 tmp;
 287
 288         tmp = __raw_readl(clk->scale_reg);
 289         tmp &= ~(0x1f << 2);
 290         tmp |= ((clk->parent->rate / clk->rate) - 1) << 2;
 291         __raw_writel(tmp, clk->scale_reg);
 292         clk->rate = rate;
 293         return 0;
 294 }
 295
 296 /*configure HCLK*/
 297 static int hclk_set_rate(struct clk *clk, u32 rate)
 298 {
 299         u32 tmp;
 300         tmp = __raw_readl(clk->scale_reg);
 301         tmp = tmp & ~0x3;
 302         switch (rate) {
 303         case 1:
 304                 break;
 305         case 2:
 306                 tmp |= 1;
 307                 break;
 308         case 4:
 309                 tmp |= 2;
 310                 break;
 311         }
 312
 313         __raw_writel(tmp, clk->scale_reg);
 314         clk->rate = rate;
 315         return 0;
 316 }
 317
 318 static u32 hclk_round_rate(struct clk *clk, u32 rate)
 319 {
 320         switch (rate) {
 321         case 1:
 322         case 4:
 323                 return rate;
 324         }
 325         return 2;
 326 }
 327
 328 static u32 per_clk_round_rate(struct clk *clk, u32 rate)
 329 {
 330         return CLK_RATE_13MHZ;
 331 }
 332
 333 static int on_off_set_rate(struct clk *clk, u32 rate)
 334 {
 335         if (rate) {
 336                 clk_reg_enable(clk);
 337                 clk->rate = 1;
 338         } else {
 339                 clk_reg_disable(clk);
 340                 clk->rate = 0;
 341         }
 342         return 0;
 343 }
 344
 345 static int on_off_inv_set_rate(struct clk *clk, u32 rate)
 346 {
 347         if (rate) {
 348                 clk_reg_disable(clk);   /*enable bit is inverted */
 349                 clk->rate = 1;
 350         } else {
 351                 clk_reg_enable(clk);
 352                 clk->rate = 0;
 353         }
 354         return 0;
 355 }
 356
 357 static u32 on_off_round_rate(struct clk *clk, u32 rate)
 358 {
 359         return (rate ? 1 : 0);
 360 }
 361
 362 static u32 pll4_round_rate(struct clk *clk, u32 rate)
 363 {
 364         if (rate > CLK_RATE_208MHZ)
 365                 rate = CLK_RATE_208MHZ;
 366         if (rate == CLK_RATE_208MHZ && hclk_ck.user_rate == 1)
 367                 rate = CLK_RATE_208MHZ - CLK_RATE_13MHZ;
 368         return (rate - (rate % (hclk_ck.user_rate * CLK_RATE_13MHZ)));
 369 }
 370
 371 static u32 pll3_round_rate(struct clk *clk, u32 rate)
 372 {
 373         if (rate > CLK_RATE_208MHZ)
 374                 rate = CLK_RATE_208MHZ;
 375         return (rate - rate % CLK_RATE_13MHZ);
 376 }
 377
 378 static u32 pll5_round_rate(struct clk *clk, u32 rate)
 379 {
 380         return (rate ? CLK_RATE_48MHZ : 0);
 381 }
 382
 383 static u32 ck_13MHz_round_rate(struct clk *clk, u32 rate)
 384 {
 385         return (rate ? CLK_RATE_13MHZ : 0);
 386 }
 387
 388 static int ck_13MHz_set_rate(struct clk *clk, u32 rate)
 389 {
 390         if (rate) {
 391                 clk_reg_disable(clk);   /*enable bit is inverted */
 392                 udelay(500);
 393                 clk->rate = CLK_RATE_13MHZ;
 394                 ck_1MHz.rate = CLK_RATE_1MHZ;
 395         } else {
 396                 clk_reg_enable(clk);
 397                 clk->rate = 0;
 398                 ck_1MHz.rate = 0;
 399         }
 400         return 0;
 401 }
 402
 403 static int pll1_set_rate(struct clk *clk, u32 rate)
 404 {
 405 #if 0 /* doesn't work on some boards, probably a HW BUG */
 406         if (rate) {
 407                 clk_reg_disable(clk);   /*enable bit is inverted */
 408                 if (!clk_wait_for_pll_lock(clk)) {
 409                         clk->rate = CLK_RATE_13MHZ;
 410                 } else {
 411                         clk_reg_enable(clk);
 412                         clk->rate = 0;
 413                 }
 414
 415         } else {
 416                 clk_reg_enable(clk);
 417                 clk->rate = 0;
 418         }
 419 #endif
 420         return 0;
 421 }
 422
 423 /* Clock sources */
 424
 425 static struct clk osc_13MHz = {
 426         .name = "osc_13MHz",
 427         .flags = FIXED_RATE,
 428         .rate = CLK_RATE_13MHZ,
 429 };
 430
 431 static struct clk ck_13MHz = {
 432         .name = "ck_13MHz",
 433         .parent = &osc_13MHz,
 434         .flags = NEEDS_INITIALIZATION,
 435         .round_rate = &ck_13MHz_round_rate,
 436         .set_rate = &ck_13MHz_set_rate,
 437         .enable_reg = OSC13CTRL_REG,
 438         .enable_shift = 0,
 439         .rate = CLK_RATE_13MHZ,
 440 };
 441
 442 static struct clk osc_32KHz = {
 443         .name = "osc_32KHz",
 444         .flags = FIXED_RATE,
 445         .rate = CLK_RATE_32KHZ,
 446 };
 447
 448 /*attached to PLL5*/
 449 static struct clk ck_1MHz = {
 450         .name = "ck_1MHz",
 451         .flags = FIXED_RATE | PARENT_SET_RATE,
 452         .parent = &ck_13MHz,
 453 };
 454
 455 /* PLL1 (397) - provides 13' MHz clock */
 456 static struct clk ck_pll1 = {
 457         .name = "ck_pll1",
 458         .parent = &osc_32KHz,
 459         .flags = NEEDS_INITIALIZATION,
 460         .round_rate = &ck_13MHz_round_rate,
 461         .set_rate = &pll1_set_rate,
 462         .enable_reg = PLLCTRL_REG,
 463         .enable_shift = 1,
 464         .scale_reg = PLLCTRL_REG,
 465         .rate = CLK_RATE_13MHZ,
 466 };
 467
 468 /* CPU/Bus PLL */
 469 static struct clk ck_pll4 = {
 470         .name = "ck_pll4",
 471         .parent = &ck_pll1,
 472         .flags = RATE_PROPAGATES | NEEDS_INITIALIZATION,
 473         .propagate_next = &per_ck,
 474         .round_rate = &pll4_round_rate,
 475         .set_rate = &pll160_set_rate,
 476         .rate = CLK_RATE_208MHZ,
 477         .scale_reg = HCLKPLLCTRL_REG,
 478         .enable_reg = PWRCTRL_REG,
 479         .enable_shift = 2,
 480         .parent_switch_reg = SYSCLKCTRL_REG,
 481         .set_parent = &set_13MHz_parent,
 482 };
 483
 484 /* USB PLL */
 485 static struct clk ck_pll5 = {
 486         .name = "ck_pll5",
 487         .parent = &ck_1MHz,
 488         .flags = NEEDS_INITIALIZATION,
 489         .round_rate = &pll5_round_rate,
 490         .set_rate = &pll160_set_rate,
 491         .scale_reg = USBCTRL_REG,
 492         .enable_reg = USBCTRL_REG,
 493         .enable_shift = 18,
 494         .enable_reg1 = USBCTRL_REG,
 495         .enable_shift1 = 17,
 496 };
 497
 498 /* XPERTTeak DSP PLL */
 499 static struct clk ck_pll3 = {
 500         .name = "ck_pll3",
 501         .parent = &ck_pll1,
 502         .flags = NEEDS_INITIALIZATION,
 503         .round_rate = &pll3_round_rate,
 504         .set_rate = &pll160_set_rate,
 505         .scale_reg = DSPPLLCTRL_REG,
 506         .enable_reg = DSPCLKCTRL_REG,
 507         .enable_shift = 3,
 508         .enable_reg1 = DSPCLKCTRL_REG,
 509         .enable_shift1 = 2,
 510         .parent_switch_reg = DSPCLKCTRL_REG,
 511         .set_parent = &set_13MHz_parent,
 512 };
 513
 514 static struct clk hclk_ck = {
 515         .name = "hclk_ck",
 516         .parent = &ck_pll4,
 517         .flags = PARENT_SET_RATE,
 518         .set_rate = &hclk_set_rate,
 519         .round_rate = &hclk_round_rate,
 520         .scale_reg = HCLKDIVCTRL_REG,
 521         .rate = 2,
 522         .user_rate = 2,
 523 };
 524
 525 static struct clk per_ck = {
 526         .name = "per_ck",
 527         .parent = &ck_pll4,
 528         .flags = FIXED_RATE,
 529         .propagate_next = &hclk_ck,
 530         .set_rate = &per_clk_set_rate,
 531         .round_rate = &per_clk_round_rate,
 532         .scale_reg = HCLKDIVCTRL_REG,
 533         .rate = CLK_RATE_13MHZ,
 534         .user_rate = CLK_RATE_13MHZ,
 535 };
 536
 537 static struct clk m2hclk_ck = {
 538         .name = "m2hclk_ck",
 539         .parent = &hclk_ck,
 540         .flags = NEEDS_INITIALIZATION,
 541         .round_rate = &on_off_round_rate,
 542         .set_rate = &on_off_inv_set_rate,
 543         .rate = 1,
 544         .enable_shift = 6,
 545         .enable_reg = PWRCTRL_REG,
 546 };
 547
 548 static struct clk vfp9_ck = {
 549         .name = "vfp9_ck",
 550         .parent = &ck_pll4,
 551         .flags = NEEDS_INITIALIZATION,
 552         .round_rate = &on_off_round_rate,
 553         .set_rate = &on_off_set_rate,
 554         .rate = 1,
 555         .enable_shift = 4,
 556         .enable_reg = VFP9CLKCTRL_REG,
 557 };
 558
 559 static struct clk keyscan_ck = {
 560         .name = "keyscan_ck",
 561         .parent = &osc_32KHz,
 562         .flags = NEEDS_INITIALIZATION,
 563         .round_rate = &on_off_round_rate,
 564         .set_rate = &on_off_set_rate,
 565         .enable_shift = 0,
 566         .enable_reg = KEYCLKCTRL_REG,
 567 };
 568
 569 static struct clk touch_ck = {
 570         .name = "touch_ck",
 571         .parent = &osc_32KHz,
 572         .flags = NEEDS_INITIALIZATION,
 573         .round_rate = &on_off_round_rate,
 574         .set_rate = &on_off_set_rate,
 575         .enable_shift = 0,
 576         .enable_reg = TSCLKCTRL_REG,
 577 };
 578
 579 static struct clk pwm1_ck = {
 580         .name = "pwm1_ck",
 581         .parent = &osc_32KHz,
 582         .flags = NEEDS_INITIALIZATION,
 583         .round_rate = &on_off_round_rate,
 584         .set_rate = &on_off_set_rate,
 585         .enable_shift = 0,
 586         .enable_reg = PWMCLKCTRL_REG,
 587 };
 588
 589 static struct clk pwm2_ck = {
 590         .name = "pwm2_ck",
 591         .parent = &osc_32KHz,
 592         .flags = NEEDS_INITIALIZATION,
 593         .round_rate = &on_off_round_rate,
 594         .set_rate = &on_off_set_rate,
 595         .enable_shift = 2,
 596         .enable_reg = PWMCLKCTRL_REG,
 597 };
 598
 599 static struct clk jpeg_ck = {
 600         .name = "jpeg_ck",
 601         .parent = &hclk_ck,
 602         .flags = NEEDS_INITIALIZATION,
 603         .round_rate = &on_off_round_rate,
 604         .set_rate = &on_off_set_rate,
 605         .enable_shift = 0,
 606         .enable_reg = JPEGCLKCTRL_REG,
 607 };
 608
 609 static struct clk ms_ck = {
 610         .name = "ms_ck",
 611         .parent = &ck_pll4,
 612         .flags = NEEDS_INITIALIZATION,
 613         .round_rate = &on_off_round_rate,
 614         .set_rate = &on_off_set_rate,
 615         .enable_shift = 5,
 616         .enable_reg = MSCTRL_REG,
 617 };
 618
 619 static struct clk dum_ck = {
 620         .name = "dum_ck",
 621         .parent = &hclk_ck,
 622         .flags = NEEDS_INITIALIZATION,
 623         .round_rate = &on_off_round_rate,
 624         .set_rate = &on_off_set_rate,
 625         .enable_shift = 0,
 626         .enable_reg = DUMCLKCTRL_REG,
 627 };
 628
 629 static struct clk flash_ck = {
 630         .name = "flash_ck",
 631         .parent = &hclk_ck,
 632         .round_rate = &on_off_round_rate,
 633         .set_rate = &on_off_set_rate,
 634         .enable_shift = 1,      /* Only MLC clock supported */
 635         .enable_reg = FLASHCLKCTRL_REG,
 636 };
 637
 638 static struct clk i2c0_ck = {
 639         .name = "i2c0_ck",
 640         .parent = &per_ck,
 641         .flags = NEEDS_INITIALIZATION | FIXED_RATE,
 642         .enable_shift = 0,
 643         .enable_reg = I2CCLKCTRL_REG,
 644         .rate = 13000000,
 645         .enable = clk_reg_enable,
 646         .disable = clk_reg_disable,
 647 };
 648
 649 static struct clk i2c1_ck = {
 650         .name = "i2c1_ck",
 651         .parent = &per_ck,
 652         .flags = NEEDS_INITIALIZATION | FIXED_RATE,
 653         .enable_shift = 1,
 654         .enable_reg = I2CCLKCTRL_REG,
 655         .rate = 13000000,
 656         .enable = clk_reg_enable,
 657         .disable = clk_reg_disable,
 658 };
 659
 660 static struct clk i2c2_ck = {
 661         .name = "i2c2_ck",
 662         .parent = &per_ck,
 663         .flags = NEEDS_INITIALIZATION | FIXED_RATE,
 664         .enable_shift = 2,
 665         .enable_reg = USB_OTG_CLKCTRL_REG,
 666         .rate = 13000000,
 667         .enable = clk_reg_enable,
 668         .disable = clk_reg_disable,
 669 };
 670
 671 static struct clk spi0_ck = {
 672         .name = "spi0_ck",
 673         .parent = &hclk_ck,
 674         .flags = NEEDS_INITIALIZATION,
 675         .round_rate = &on_off_round_rate,
 676         .set_rate = &on_off_set_rate,
 677         .enable_shift = 0,
 678         .enable_reg = SPICTRL_REG,
 679 };
 680
 681 static struct clk spi1_ck = {
 682         .name = "spi1_ck",
 683         .parent = &hclk_ck,
 684         .flags = NEEDS_INITIALIZATION,
 685         .round_rate = &on_off_round_rate,
 686         .set_rate = &on_off_set_rate,
 687         .enable_shift = 4,
 688         .enable_reg = SPICTRL_REG,
 689 };
 690
 691 static struct clk dma_ck = {
 692         .name = "dma_ck",
 693         .parent = &hclk_ck,
 694         .round_rate = &on_off_round_rate,
 695         .set_rate = &on_off_set_rate,
 696         .enable_shift = 0,
 697         .enable_reg = DMACLKCTRL_REG,
 698 };
 699
 700 static struct clk uart3_ck = {
 701         .name = "uart3_ck",
 702         .parent = &per_ck,
 703         .flags = NEEDS_INITIALIZATION,
 704         .round_rate = &on_off_round_rate,
 705         .set_rate = &on_off_set_rate,
 706         .rate = 1,
 707         .enable_shift = 0,
 708         .enable_reg = UARTCLKCTRL_REG,
 709 };
 710
 711 static struct clk uart4_ck = {
 712         .name = "uart4_ck",
 713         .parent = &per_ck,
 714         .flags = NEEDS_INITIALIZATION,
 715         .round_rate = &on_off_round_rate,
 716         .set_rate = &on_off_set_rate,
 717         .enable_shift = 1,
 718         .enable_reg = UARTCLKCTRL_REG,
 719 };
 720
 721 static struct clk uart5_ck = {
 722         .name = "uart5_ck",
 723         .parent = &per_ck,
 724         .flags = NEEDS_INITIALIZATION,
 725         .round_rate = &on_off_round_rate,
 726         .set_rate = &on_off_set_rate,
 727         .rate = 1,
 728         .enable_shift = 2,
 729         .enable_reg = UARTCLKCTRL_REG,
 730 };
 731
 732 static struct clk uart6_ck = {
 733         .name = "uart6_ck",
 734         .parent = &per_ck,
 735         .flags = NEEDS_INITIALIZATION,
 736         .round_rate = &on_off_round_rate,
 737         .set_rate = &on_off_set_rate,
 738         .enable_shift = 3,
 739         .enable_reg = UARTCLKCTRL_REG,
 740 };
 741
 742 static struct clk wdt_ck = {
 743         .name = "wdt_ck",
 744         .parent = &per_ck,
 745         .flags = NEEDS_INITIALIZATION,
 746         .enable_shift = 0,
 747         .enable_reg = TIMCLKCTRL_REG,
 748         .enable = clk_reg_enable,
 749         .disable = clk_reg_disable,
 750 };
 751
 752 /* These clocks are visible outside this module
 753  * and can be initialized
 754  */
 755 static struct clk *onchip_clks[] __initdata = {
 756         &ck_13MHz,
 757         &ck_pll1,
 758         &ck_pll4,
 759         &ck_pll5,
 760         &ck_pll3,
 761         &vfp9_ck,
 762         &m2hclk_ck,
 763         &hclk_ck,
 764         &dma_ck,
 765         &flash_ck,
 766         &dum_ck,
 767         &keyscan_ck,
 768         &pwm1_ck,
 769         &pwm2_ck,
 770         &jpeg_ck,
 771         &ms_ck,
 772         &touch_ck,
 773         &i2c0_ck,
 774         &i2c1_ck,
 775         &i2c2_ck,
 776         &spi0_ck,
 777         &spi1_ck,
 778         &uart3_ck,
 779         &uart4_ck,
 780         &uart5_ck,
 781         &uart6_ck,
 782         &wdt_ck,
 783 };
 784
 785 static struct clk_lookup onchip_clkreg[] = {
 786         { .clk = &ck_13MHz,     .con_id = "ck_13MHz"    },
 787         { .clk = &ck_pll1,      .con_id = "ck_pll1"     },
 788         { .clk = &ck_pll4,      .con_id = "ck_pll4"     },
 789         { .clk = &ck_pll5,      .con_id = "ck_pll5"     },
 790         { .clk = &ck_pll3,      .con_id = "ck_pll3"     },
 791         { .clk = &vfp9_ck,      .con_id = "vfp9_ck"     },
 792         { .clk = &m2hclk_ck,    .con_id = "m2hclk_ck"   },
 793         { .clk = &hclk_ck,      .con_id = "hclk_ck"     },
 794         { .clk = &dma_ck,       .con_id = "dma_ck"      },
 795         { .clk = &flash_ck,     .con_id = "flash_ck"    },
 796         { .clk = &dum_ck,       .con_id = "dum_ck"      },
 797         { .clk = &keyscan_ck,   .con_id = "keyscan_ck"  },
 798         { .clk = &pwm1_ck,      .con_id = "pwm1_ck"     },
 799         { .clk = &pwm2_ck,      .con_id = "pwm2_ck"     },
 800         { .clk = &jpeg_ck,      .con_id = "jpeg_ck"     },
 801         { .clk = &ms_ck,        .con_id = "ms_ck"       },
 802         { .clk = &touch_ck,     .con_id = "touch_ck"    },
 803         { .clk = &i2c0_ck,      .dev_id = "pnx-i2c.0"   },
 804         { .clk = &i2c1_ck,      .dev_id = "pnx-i2c.1"   },
 805         { .clk = &i2c2_ck,      .dev_id = "pnx-i2c.2"   },
 806         { .clk = &spi0_ck,      .con_id = "spi0_ck"     },
 807         { .clk = &spi1_ck,      .con_id = "spi1_ck"     },
 808         { .clk = &uart3_ck,     .con_id = "uart3_ck"    },
 809         { .clk = &uart4_ck,     .con_id = "uart4_ck"    },
 810         { .clk = &uart5_ck,     .con_id = "uart5_ck"    },
 811         { .clk = &uart6_ck,     .con_id = "uart6_ck"    },
 812         { .clk = &wdt_ck,       .dev_id = "pnx4008-watchdog" },
 813 };
 814
 815 static void local_clk_disable(struct clk *clk)
 816 {
 817         if (WARN_ON(clk->usecount == 0))
 818                 return;
 819
 820         if (!(--clk->usecount)) {
 821                 if (clk->disable)
 822                         clk->disable(clk);
 823                 else if (!(clk->flags & FIXED_RATE) && clk->rate && clk->set_rate)
 824                         clk->set_rate(clk, 0);
 825                 if (clk->parent)
 826                         local_clk_disable(clk->parent);
 827         }
 828 }
 829
 830 static int local_clk_enable(struct clk *clk)
 831 {
 832         int ret = 0;
 833
 834         if (clk->usecount == 0) {
 835                 if (clk->parent) {
 836                         ret = local_clk_enable(clk->parent);
 837                         if (ret != 0)
 838                                 goto out;
 839                 }
 840
 841                 if (clk->enable)
 842                         ret = clk->enable(clk);
 843                 else if (!(clk->flags & FIXED_RATE) && !clk->rate && clk->set_rate
 844                             && clk->user_rate)
 845                         ret = clk->set_rate(clk, clk->user_rate);
 846
 847                 if (ret != 0 && clk->parent) {
 848                         local_clk_disable(clk->parent);
 849                         goto out;
 850                 }
 851
 852                 clk->usecount++;
 853         }
 854 out:
 855         return ret;
 856 }
 857
 858 static int local_set_rate(struct clk *clk, u32 rate)
 859 {
 860         int ret = -EINVAL;
 861         if (clk->set_rate) {
 862
 863                 if (clk->user_rate == clk->rate && clk->parent->rate) {
 864                         /* if clock enabled or rate not set */
 865                         clk->user_rate = clk->round_rate(clk, rate);
 866                         ret = clk->set_rate(clk, clk->user_rate);
 867                 } else
 868                         clk->user_rate = clk->round_rate(clk, rate);
 869                 ret = 0;
 870         }
 871         return ret;
 872 }
 873
 874 int clk_set_rate(struct clk *clk, unsigned long rate)
 875 {
 876         int ret = -EINVAL;
 877
 878         if (clk->flags & FIXED_RATE)
 879                 goto out;
 880
 881         clock_lock();
 882         if ((clk->flags & PARENT_SET_RATE) && clk->parent) {
 883
 884                 clk->user_rate = clk->round_rate(clk, rate);
 885                 /* parent clock needs to be refreshed
 886                    for the setting to take effect */
 887         } else {
 888                 ret = local_set_rate(clk, rate);
 889         }
 890         ret = 0;
 891         clock_unlock();
 892
 893 out:
 894         return ret;
 895 }
 896
 897 EXPORT_SYMBOL(clk_set_rate);
 898
 899 unsigned long clk_get_rate(struct clk *clk)
 900 {
 901         unsigned long ret;
 902         clock_lock();
 903         ret = clk->rate;
 904         clock_unlock();
 905         return ret;
 906 }
 907 EXPORT_SYMBOL(clk_get_rate);
 908
 909 int clk_enable(struct clk *clk)
 910 {
 911         int ret;
 912
 913         clock_lock();
 914         ret = local_clk_enable(clk);
 915         clock_unlock();
 916         return ret;
 917 }
 918
 919 EXPORT_SYMBOL(clk_enable);
 920
 921 void clk_disable(struct clk *clk)
 922 {
 923         clock_lock();
 924         local_clk_disable(clk);
 925         clock_unlock();
 926 }
 927
 928 EXPORT_SYMBOL(clk_disable);
 929
 930 long clk_round_rate(struct clk *clk, unsigned long rate)
 931 {
 932         long ret;
 933         clock_lock();
 934         if (clk->round_rate)
 935                 ret = clk->round_rate(clk, rate);
 936         else
 937                 ret = clk->rate;
 938         clock_unlock();
 939         return ret;
 940 }
 941
 942 EXPORT_SYMBOL(clk_round_rate);
 943
 944 int clk_set_parent(struct clk *clk, struct clk *parent)
 945 {
 946         int ret = -ENODEV;
 947         if (!clk->set_parent)
 948                 goto out;
 949
 950         clock_lock();
 951         ret = clk->set_parent(clk, parent);
 952         if (!ret)
 953                 clk->parent = parent;
 954         clock_unlock();
 955
 956 out:
 957         return ret;
 958 }
 959
 960 EXPORT_SYMBOL(clk_set_parent);
 961
 962 static int __init clk_init(void)
 963 {
 964         struct clk **clkp;
 965
 966         /* Disable autoclocking, as it doesn't seem to work */
 967         __raw_writel(0xff, AUTOCLK_CTRL);
 968
 969         for (clkp = onchip_clks; clkp < onchip_clks + ARRAY_SIZE(onchip_clks);
 970              clkp++) {
 971                 struct clk *clk = *clkp;
 972                 if (clk->flags & NEEDS_INITIALIZATION) {
 973                         if (clk->set_rate) {
 974                                 clk->user_rate = clk->rate;
 975                                 local_set_rate(clk, clk->user_rate);
 976                                 if (clk->set_parent)
 977                                         clk->set_parent(clk, clk->parent);
 978                         }
 979                         if (clk->enable && clk->usecount)
 980                                 clk->enable(clk);
 981                         if (clk->disable && !clk->usecount)
 982                                 clk->disable(clk);
 983                 }
 984                 pr_debug("%s: clock %s, rate %ld\n",
 985                         __func__, clk->name, clk->rate);
 986         }
 987
 988         local_clk_enable(&ck_pll4);
 989
 990         /* if ck_13MHz is not used, disable it. */
 991         if (ck_13MHz.usecount == 0)
 992                 local_clk_disable(&ck_13MHz);
 993
 994         /* Disable autoclocking */
 995         __raw_writeb(0xff, AUTOCLK_CTRL);
 996
 997         clkdev_add_table(onchip_clkreg, ARRAY_SIZE(onchip_clkreg));
 998
 999         return 0;
1000 }
1001
1002 arch_initcall(clk_init);