2 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
3 * Copyright (C) 2009-2010 Amit Kucheria <amit.kucheria@canonical.com>
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
14 #include <linux/delay.h>
15 #include <linux/clk.h>
18 #include <asm/clkdev.h>
20 #include <mach/hardware.h>
21 #include <mach/common.h>
22 #include <mach/clock.h>
26 /* External clock values passed-in by the board code */
27 static unsigned long external_high_reference
, external_low_reference
;
28 static unsigned long oscillator_reference
, ckih2_reference
;
30 static struct clk osc_clk
;
31 static struct clk pll1_main_clk
;
32 static struct clk pll1_sw_clk
;
33 static struct clk pll2_sw_clk
;
34 static struct clk pll3_sw_clk
;
35 static struct clk lp_apm_clk
;
36 static struct clk periph_apm_clk
;
37 static struct clk ahb_clk
;
38 static struct clk ipg_clk
;
40 #define MAX_DPLL_WAIT_TRIES 1000 /* 1000 * udelay(1) = 1ms */
42 static int _clk_ccgr_enable(struct clk
*clk
)
46 reg
= __raw_readl(clk
->enable_reg
);
47 reg
|= MXC_CCM_CCGRx_MOD_ON
<< clk
->enable_shift
;
48 __raw_writel(reg
, clk
->enable_reg
);
53 static void _clk_ccgr_disable(struct clk
*clk
)
56 reg
= __raw_readl(clk
->enable_reg
);
57 reg
&= ~(MXC_CCM_CCGRx_MOD_OFF
<< clk
->enable_shift
);
58 __raw_writel(reg
, clk
->enable_reg
);
62 static void _clk_ccgr_disable_inwait(struct clk
*clk
)
66 reg
= __raw_readl(clk
->enable_reg
);
67 reg
&= ~(MXC_CCM_CCGRx_CG_MASK
<< clk
->enable_shift
);
68 reg
|= MXC_CCM_CCGRx_MOD_IDLE
<< clk
->enable_shift
;
69 __raw_writel(reg
, clk
->enable_reg
);
73 * For the 4-to-1 muxed input clock
75 static inline u32
_get_mux(struct clk
*parent
, struct clk
*m0
,
76 struct clk
*m1
, struct clk
*m2
, struct clk
*m3
)
80 else if (parent
== m1
)
82 else if (parent
== m2
)
84 else if (parent
== m3
)
92 static inline void __iomem
*_get_pll_base(struct clk
*pll
)
94 if (pll
== &pll1_main_clk
)
95 return MX51_DPLL1_BASE
;
96 else if (pll
== &pll2_sw_clk
)
97 return MX51_DPLL2_BASE
;
98 else if (pll
== &pll3_sw_clk
)
99 return MX51_DPLL3_BASE
;
106 static unsigned long clk_pll_get_rate(struct clk
*clk
)
108 long mfi
, mfn
, mfd
, pdf
, ref_clk
, mfn_abs
;
109 unsigned long dp_op
, dp_mfd
, dp_mfn
, dp_ctl
, pll_hfsm
, dbl
;
110 void __iomem
*pllbase
;
112 unsigned long parent_rate
;
114 parent_rate
= clk_get_rate(clk
->parent
);
116 pllbase
= _get_pll_base(clk
);
118 dp_ctl
= __raw_readl(pllbase
+ MXC_PLL_DP_CTL
);
119 pll_hfsm
= dp_ctl
& MXC_PLL_DP_CTL_HFSM
;
120 dbl
= dp_ctl
& MXC_PLL_DP_CTL_DPDCK0_2_EN
;
123 dp_op
= __raw_readl(pllbase
+ MXC_PLL_DP_OP
);
124 dp_mfd
= __raw_readl(pllbase
+ MXC_PLL_DP_MFD
);
125 dp_mfn
= __raw_readl(pllbase
+ MXC_PLL_DP_MFN
);
127 dp_op
= __raw_readl(pllbase
+ MXC_PLL_DP_HFS_OP
);
128 dp_mfd
= __raw_readl(pllbase
+ MXC_PLL_DP_HFS_MFD
);
129 dp_mfn
= __raw_readl(pllbase
+ MXC_PLL_DP_HFS_MFN
);
131 pdf
= dp_op
& MXC_PLL_DP_OP_PDF_MASK
;
132 mfi
= (dp_op
& MXC_PLL_DP_OP_MFI_MASK
) >> MXC_PLL_DP_OP_MFI_OFFSET
;
133 mfi
= (mfi
<= 5) ? 5 : mfi
;
134 mfd
= dp_mfd
& MXC_PLL_DP_MFD_MASK
;
135 mfn
= mfn_abs
= dp_mfn
& MXC_PLL_DP_MFN_MASK
;
136 /* Sign extend to 32-bits */
137 if (mfn
>= 0x04000000) {
142 ref_clk
= 2 * parent_rate
;
146 ref_clk
/= (pdf
+ 1);
147 temp
= (u64
) ref_clk
* mfn_abs
;
148 do_div(temp
, mfd
+ 1);
151 temp
= (ref_clk
* mfi
) + temp
;
156 static int _clk_pll_set_rate(struct clk
*clk
, unsigned long rate
)
159 void __iomem
*pllbase
;
161 long mfi
, pdf
, mfn
, mfd
= 999999;
163 unsigned long quad_parent_rate
;
164 unsigned long pll_hfsm
, dp_ctl
;
165 unsigned long parent_rate
;
167 parent_rate
= clk_get_rate(clk
->parent
);
169 pllbase
= _get_pll_base(clk
);
171 quad_parent_rate
= 4 * parent_rate
;
173 while (++pdf
< 16 && mfi
< 5)
174 mfi
= rate
* (pdf
+1) / quad_parent_rate
;
179 temp64
= rate
* (pdf
+1) - quad_parent_rate
* mfi
;
180 do_div(temp64
, quad_parent_rate
/1000000);
183 dp_ctl
= __raw_readl(pllbase
+ MXC_PLL_DP_CTL
);
185 __raw_writel(dp_ctl
| 0x1000L
, pllbase
+ MXC_PLL_DP_CTL
);
186 pll_hfsm
= dp_ctl
& MXC_PLL_DP_CTL_HFSM
;
188 reg
= mfi
<< 4 | pdf
;
189 __raw_writel(reg
, pllbase
+ MXC_PLL_DP_OP
);
190 __raw_writel(mfd
, pllbase
+ MXC_PLL_DP_MFD
);
191 __raw_writel(mfn
, pllbase
+ MXC_PLL_DP_MFN
);
193 reg
= mfi
<< 4 | pdf
;
194 __raw_writel(reg
, pllbase
+ MXC_PLL_DP_HFS_OP
);
195 __raw_writel(mfd
, pllbase
+ MXC_PLL_DP_HFS_MFD
);
196 __raw_writel(mfn
, pllbase
+ MXC_PLL_DP_HFS_MFN
);
202 static int _clk_pll_enable(struct clk
*clk
)
205 void __iomem
*pllbase
;
208 pllbase
= _get_pll_base(clk
);
209 reg
= __raw_readl(pllbase
+ MXC_PLL_DP_CTL
) | MXC_PLL_DP_CTL_UPEN
;
210 __raw_writel(reg
, pllbase
+ MXC_PLL_DP_CTL
);
214 reg
= __raw_readl(pllbase
+ MXC_PLL_DP_CTL
);
215 if (reg
& MXC_PLL_DP_CTL_LRF
)
219 } while (++i
< MAX_DPLL_WAIT_TRIES
);
221 if (i
== MAX_DPLL_WAIT_TRIES
) {
222 pr_err("MX5: pll locking failed\n");
229 static void _clk_pll_disable(struct clk
*clk
)
232 void __iomem
*pllbase
;
234 pllbase
= _get_pll_base(clk
);
235 reg
= __raw_readl(pllbase
+ MXC_PLL_DP_CTL
) & ~MXC_PLL_DP_CTL_UPEN
;
236 __raw_writel(reg
, pllbase
+ MXC_PLL_DP_CTL
);
239 static int _clk_pll1_sw_set_parent(struct clk
*clk
, struct clk
*parent
)
243 reg
= __raw_readl(MXC_CCM_CCSR
);
245 /* When switching from pll_main_clk to a bypass clock, first select a
246 * multiplexed clock in 'step_sel', then shift the glitchless mux
249 * When switching back, do it in reverse order
251 if (parent
== &pll1_main_clk
) {
252 /* Switch to pll1_main_clk */
253 reg
&= ~MXC_CCM_CCSR_PLL1_SW_CLK_SEL
;
254 __raw_writel(reg
, MXC_CCM_CCSR
);
255 /* step_clk mux switched to lp_apm, to save power. */
256 reg
= __raw_readl(MXC_CCM_CCSR
);
257 reg
&= ~MXC_CCM_CCSR_STEP_SEL_MASK
;
258 reg
|= (MXC_CCM_CCSR_STEP_SEL_LP_APM
<<
259 MXC_CCM_CCSR_STEP_SEL_OFFSET
);
261 if (parent
== &lp_apm_clk
) {
262 step
= MXC_CCM_CCSR_STEP_SEL_LP_APM
;
263 } else if (parent
== &pll2_sw_clk
) {
264 step
= MXC_CCM_CCSR_STEP_SEL_PLL2_DIVIDED
;
265 } else if (parent
== &pll3_sw_clk
) {
266 step
= MXC_CCM_CCSR_STEP_SEL_PLL3_DIVIDED
;
270 reg
&= ~MXC_CCM_CCSR_STEP_SEL_MASK
;
271 reg
|= (step
<< MXC_CCM_CCSR_STEP_SEL_OFFSET
);
273 __raw_writel(reg
, MXC_CCM_CCSR
);
274 /* Switch to step_clk */
275 reg
= __raw_readl(MXC_CCM_CCSR
);
276 reg
|= MXC_CCM_CCSR_PLL1_SW_CLK_SEL
;
278 __raw_writel(reg
, MXC_CCM_CCSR
);
282 static unsigned long clk_pll1_sw_get_rate(struct clk
*clk
)
285 unsigned long parent_rate
;
287 parent_rate
= clk_get_rate(clk
->parent
);
289 reg
= __raw_readl(MXC_CCM_CCSR
);
291 if (clk
->parent
== &pll2_sw_clk
) {
292 div
= ((reg
& MXC_CCM_CCSR_PLL2_PODF_MASK
) >>
293 MXC_CCM_CCSR_PLL2_PODF_OFFSET
) + 1;
294 } else if (clk
->parent
== &pll3_sw_clk
) {
295 div
= ((reg
& MXC_CCM_CCSR_PLL3_PODF_MASK
) >>
296 MXC_CCM_CCSR_PLL3_PODF_OFFSET
) + 1;
299 return parent_rate
/ div
;
302 static int _clk_pll2_sw_set_parent(struct clk
*clk
, struct clk
*parent
)
306 reg
= __raw_readl(MXC_CCM_CCSR
);
308 if (parent
== &pll2_sw_clk
)
309 reg
&= ~MXC_CCM_CCSR_PLL2_SW_CLK_SEL
;
311 reg
|= MXC_CCM_CCSR_PLL2_SW_CLK_SEL
;
313 __raw_writel(reg
, MXC_CCM_CCSR
);
317 static int _clk_lp_apm_set_parent(struct clk
*clk
, struct clk
*parent
)
321 if (parent
== &osc_clk
)
322 reg
= __raw_readl(MXC_CCM_CCSR
) & ~MXC_CCM_CCSR_LP_APM_SEL
;
326 __raw_writel(reg
, MXC_CCM_CCSR
);
331 static unsigned long clk_arm_get_rate(struct clk
*clk
)
334 unsigned long parent_rate
;
336 parent_rate
= clk_get_rate(clk
->parent
);
337 cacrr
= __raw_readl(MXC_CCM_CACRR
);
338 div
= (cacrr
& MXC_CCM_CACRR_ARM_PODF_MASK
) + 1;
340 return parent_rate
/ div
;
343 static int _clk_periph_apm_set_parent(struct clk
*clk
, struct clk
*parent
)
348 mux
= _get_mux(parent
, &pll1_sw_clk
, &pll3_sw_clk
, &lp_apm_clk
, NULL
);
350 reg
= __raw_readl(MXC_CCM_CBCMR
) & ~MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK
;
351 reg
|= mux
<< MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET
;
352 __raw_writel(reg
, MXC_CCM_CBCMR
);
356 reg
= __raw_readl(MXC_CCM_CDHIPR
);
357 if (!(reg
& MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY
))
361 } while (++i
< MAX_DPLL_WAIT_TRIES
);
363 if (i
== MAX_DPLL_WAIT_TRIES
) {
364 pr_err("MX5: Set parent for periph_apm clock failed\n");
371 static int _clk_main_bus_set_parent(struct clk
*clk
, struct clk
*parent
)
375 reg
= __raw_readl(MXC_CCM_CBCDR
);
377 if (parent
== &pll2_sw_clk
)
378 reg
&= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL
;
379 else if (parent
== &periph_apm_clk
)
380 reg
|= MXC_CCM_CBCDR_PERIPH_CLK_SEL
;
384 __raw_writel(reg
, MXC_CCM_CBCDR
);
389 static struct clk main_bus_clk
= {
390 .parent
= &pll2_sw_clk
,
391 .set_parent
= _clk_main_bus_set_parent
,
394 static unsigned long clk_ahb_get_rate(struct clk
*clk
)
397 unsigned long parent_rate
;
399 parent_rate
= clk_get_rate(clk
->parent
);
401 reg
= __raw_readl(MXC_CCM_CBCDR
);
402 div
= ((reg
& MXC_CCM_CBCDR_AHB_PODF_MASK
) >>
403 MXC_CCM_CBCDR_AHB_PODF_OFFSET
) + 1;
404 return parent_rate
/ div
;
408 static int _clk_ahb_set_rate(struct clk
*clk
, unsigned long rate
)
411 unsigned long parent_rate
;
414 parent_rate
= clk_get_rate(clk
->parent
);
416 div
= parent_rate
/ rate
;
417 if (div
> 8 || div
< 1 || ((parent_rate
/ div
) != rate
))
420 reg
= __raw_readl(MXC_CCM_CBCDR
);
421 reg
&= ~MXC_CCM_CBCDR_AHB_PODF_MASK
;
422 reg
|= (div
- 1) << MXC_CCM_CBCDR_AHB_PODF_OFFSET
;
423 __raw_writel(reg
, MXC_CCM_CBCDR
);
427 reg
= __raw_readl(MXC_CCM_CDHIPR
);
428 if (!(reg
& MXC_CCM_CDHIPR_AHB_PODF_BUSY
))
432 } while (++i
< MAX_DPLL_WAIT_TRIES
);
434 if (i
== MAX_DPLL_WAIT_TRIES
) {
435 pr_err("MX5: clk_ahb_set_rate failed\n");
442 static unsigned long _clk_ahb_round_rate(struct clk
*clk
,
446 unsigned long parent_rate
;
448 parent_rate
= clk_get_rate(clk
->parent
);
450 div
= parent_rate
/ rate
;
455 return parent_rate
/ div
;
459 static int _clk_max_enable(struct clk
*clk
)
463 _clk_ccgr_enable(clk
);
465 /* Handshake with MAX when LPM is entered. */
466 reg
= __raw_readl(MXC_CCM_CLPCR
);
467 reg
&= ~MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS
;
468 __raw_writel(reg
, MXC_CCM_CLPCR
);
473 static void _clk_max_disable(struct clk
*clk
)
477 _clk_ccgr_disable_inwait(clk
);
479 /* No Handshake with MAX when LPM is entered as its disabled. */
480 reg
= __raw_readl(MXC_CCM_CLPCR
);
481 reg
|= MXC_CCM_CLPCR_BYPASS_MAX_LPM_HS
;
482 __raw_writel(reg
, MXC_CCM_CLPCR
);
485 static unsigned long clk_ipg_get_rate(struct clk
*clk
)
488 unsigned long parent_rate
;
490 parent_rate
= clk_get_rate(clk
->parent
);
492 reg
= __raw_readl(MXC_CCM_CBCDR
);
493 div
= ((reg
& MXC_CCM_CBCDR_IPG_PODF_MASK
) >>
494 MXC_CCM_CBCDR_IPG_PODF_OFFSET
) + 1;
496 return parent_rate
/ div
;
499 static unsigned long clk_ipg_per_get_rate(struct clk
*clk
)
501 u32 reg
, prediv1
, prediv2
, podf
;
502 unsigned long parent_rate
;
504 parent_rate
= clk_get_rate(clk
->parent
);
506 if (clk
->parent
== &main_bus_clk
|| clk
->parent
== &lp_apm_clk
) {
507 /* the main_bus_clk is the one before the DVFS engine */
508 reg
= __raw_readl(MXC_CCM_CBCDR
);
509 prediv1
= ((reg
& MXC_CCM_CBCDR_PERCLK_PRED1_MASK
) >>
510 MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET
) + 1;
511 prediv2
= ((reg
& MXC_CCM_CBCDR_PERCLK_PRED2_MASK
) >>
512 MXC_CCM_CBCDR_PERCLK_PRED2_OFFSET
) + 1;
513 podf
= ((reg
& MXC_CCM_CBCDR_PERCLK_PODF_MASK
) >>
514 MXC_CCM_CBCDR_PERCLK_PODF_OFFSET
) + 1;
515 return parent_rate
/ (prediv1
* prediv2
* podf
);
516 } else if (clk
->parent
== &ipg_clk
)
522 static int _clk_ipg_per_set_parent(struct clk
*clk
, struct clk
*parent
)
526 reg
= __raw_readl(MXC_CCM_CBCMR
);
528 reg
&= ~MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL
;
529 reg
&= ~MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL
;
531 if (parent
== &ipg_clk
)
532 reg
|= MXC_CCM_CBCMR_PERCLK_IPG_CLK_SEL
;
533 else if (parent
== &lp_apm_clk
)
534 reg
|= MXC_CCM_CBCMR_PERCLK_LP_APM_CLK_SEL
;
535 else if (parent
!= &main_bus_clk
)
538 __raw_writel(reg
, MXC_CCM_CBCMR
);
543 static unsigned long clk_uart_get_rate(struct clk
*clk
)
545 u32 reg
, prediv
, podf
;
546 unsigned long parent_rate
;
548 parent_rate
= clk_get_rate(clk
->parent
);
550 reg
= __raw_readl(MXC_CCM_CSCDR1
);
551 prediv
= ((reg
& MXC_CCM_CSCDR1_UART_CLK_PRED_MASK
) >>
552 MXC_CCM_CSCDR1_UART_CLK_PRED_OFFSET
) + 1;
553 podf
= ((reg
& MXC_CCM_CSCDR1_UART_CLK_PODF_MASK
) >>
554 MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET
) + 1;
556 return parent_rate
/ (prediv
* podf
);
559 static int _clk_uart_set_parent(struct clk
*clk
, struct clk
*parent
)
563 mux
= _get_mux(parent
, &pll1_sw_clk
, &pll2_sw_clk
, &pll3_sw_clk
,
565 reg
= __raw_readl(MXC_CCM_CSCMR1
) & ~MXC_CCM_CSCMR1_UART_CLK_SEL_MASK
;
566 reg
|= mux
<< MXC_CCM_CSCMR1_UART_CLK_SEL_OFFSET
;
567 __raw_writel(reg
, MXC_CCM_CSCMR1
);
572 static unsigned long get_high_reference_clock_rate(struct clk
*clk
)
574 return external_high_reference
;
577 static unsigned long get_low_reference_clock_rate(struct clk
*clk
)
579 return external_low_reference
;
582 static unsigned long get_oscillator_reference_clock_rate(struct clk
*clk
)
584 return oscillator_reference
;
587 static unsigned long get_ckih2_reference_clock_rate(struct clk
*clk
)
589 return ckih2_reference
;
592 /* External high frequency clock */
593 static struct clk ckih_clk
= {
594 .get_rate
= get_high_reference_clock_rate
,
597 static struct clk ckih2_clk
= {
598 .get_rate
= get_ckih2_reference_clock_rate
,
601 static struct clk osc_clk
= {
602 .get_rate
= get_oscillator_reference_clock_rate
,
605 /* External low frequency (32kHz) clock */
606 static struct clk ckil_clk
= {
607 .get_rate
= get_low_reference_clock_rate
,
610 static struct clk pll1_main_clk
= {
612 .get_rate
= clk_pll_get_rate
,
613 .enable
= _clk_pll_enable
,
614 .disable
= _clk_pll_disable
,
617 /* Clock tree block diagram (WIP):
618 * CCM: Clock Controller Module
621 * | CCM Switcher -> CCM_CLK_ROOT_GEN ->
626 /* PLL1 SW supplies to ARM core */
627 static struct clk pll1_sw_clk
= {
628 .parent
= &pll1_main_clk
,
629 .set_parent
= _clk_pll1_sw_set_parent
,
630 .get_rate
= clk_pll1_sw_get_rate
,
633 /* PLL2 SW supplies to AXI/AHB/IP buses */
634 static struct clk pll2_sw_clk
= {
636 .get_rate
= clk_pll_get_rate
,
637 .set_rate
= _clk_pll_set_rate
,
638 .set_parent
= _clk_pll2_sw_set_parent
,
639 .enable
= _clk_pll_enable
,
640 .disable
= _clk_pll_disable
,
643 /* PLL3 SW supplies to serial clocks like USB, SSI, etc. */
644 static struct clk pll3_sw_clk
= {
646 .set_rate
= _clk_pll_set_rate
,
647 .get_rate
= clk_pll_get_rate
,
648 .enable
= _clk_pll_enable
,
649 .disable
= _clk_pll_disable
,
652 /* Low-power Audio Playback Mode clock */
653 static struct clk lp_apm_clk
= {
655 .set_parent
= _clk_lp_apm_set_parent
,
658 static struct clk periph_apm_clk
= {
659 .parent
= &pll1_sw_clk
,
660 .set_parent
= _clk_periph_apm_set_parent
,
663 static struct clk cpu_clk
= {
664 .parent
= &pll1_sw_clk
,
665 .get_rate
= clk_arm_get_rate
,
668 static struct clk ahb_clk
= {
669 .parent
= &main_bus_clk
,
670 .get_rate
= clk_ahb_get_rate
,
671 .set_rate
= _clk_ahb_set_rate
,
672 .round_rate
= _clk_ahb_round_rate
,
675 /* Main IP interface clock for access to registers */
676 static struct clk ipg_clk
= {
678 .get_rate
= clk_ipg_get_rate
,
681 static struct clk ipg_perclk
= {
682 .parent
= &lp_apm_clk
,
683 .get_rate
= clk_ipg_per_get_rate
,
684 .set_parent
= _clk_ipg_per_set_parent
,
687 static struct clk uart_root_clk
= {
688 .parent
= &pll2_sw_clk
,
689 .get_rate
= clk_uart_get_rate
,
690 .set_parent
= _clk_uart_set_parent
,
693 static struct clk ahb_max_clk
= {
695 .enable_reg
= MXC_CCM_CCGR0
,
696 .enable_shift
= MXC_CCM_CCGRx_CG14_OFFSET
,
697 .enable
= _clk_max_enable
,
698 .disable
= _clk_max_disable
,
701 static struct clk aips_tz1_clk
= {
703 .secondary
= &ahb_max_clk
,
704 .enable_reg
= MXC_CCM_CCGR0
,
705 .enable_shift
= MXC_CCM_CCGRx_CG12_OFFSET
,
706 .enable
= _clk_ccgr_enable
,
707 .disable
= _clk_ccgr_disable_inwait
,
710 static struct clk aips_tz2_clk
= {
712 .secondary
= &ahb_max_clk
,
713 .enable_reg
= MXC_CCM_CCGR0
,
714 .enable_shift
= MXC_CCM_CCGRx_CG13_OFFSET
,
715 .enable
= _clk_ccgr_enable
,
716 .disable
= _clk_ccgr_disable_inwait
,
719 static struct clk gpt_32k_clk
= {
724 #define DEFINE_CLOCK(name, i, er, es, gr, sr, p, s) \
725 static struct clk name = { \
728 .enable_shift = es, \
731 .enable = _clk_ccgr_enable, \
732 .disable = _clk_ccgr_disable, \
737 /* DEFINE_CLOCK(name, id, enable_reg, enable_shift,
738 get_rate, set_rate, parent, secondary); */
740 /* Shared peripheral bus arbiter */
741 DEFINE_CLOCK(spba_clk
, 0, MXC_CCM_CCGR5
, MXC_CCM_CCGRx_CG0_OFFSET
,
742 NULL
, NULL
, &ipg_clk
, NULL
);
745 DEFINE_CLOCK(uart1_clk
, 0, MXC_CCM_CCGR1
, MXC_CCM_CCGRx_CG4_OFFSET
,
746 NULL
, NULL
, &uart_root_clk
, NULL
);
747 DEFINE_CLOCK(uart2_clk
, 1, MXC_CCM_CCGR1
, MXC_CCM_CCGRx_CG6_OFFSET
,
748 NULL
, NULL
, &uart_root_clk
, NULL
);
749 DEFINE_CLOCK(uart3_clk
, 2, MXC_CCM_CCGR1
, MXC_CCM_CCGRx_CG8_OFFSET
,
750 NULL
, NULL
, &uart_root_clk
, NULL
);
751 DEFINE_CLOCK(uart1_ipg_clk
, 0, MXC_CCM_CCGR1
, MXC_CCM_CCGRx_CG3_OFFSET
,
752 NULL
, NULL
, &ipg_clk
, &aips_tz1_clk
);
753 DEFINE_CLOCK(uart2_ipg_clk
, 1, MXC_CCM_CCGR1
, MXC_CCM_CCGRx_CG5_OFFSET
,
754 NULL
, NULL
, &ipg_clk
, &aips_tz1_clk
);
755 DEFINE_CLOCK(uart3_ipg_clk
, 2, MXC_CCM_CCGR1
, MXC_CCM_CCGRx_CG7_OFFSET
,
756 NULL
, NULL
, &ipg_clk
, &spba_clk
);
759 DEFINE_CLOCK(gpt_clk
, 0, MXC_CCM_CCGR2
, MXC_CCM_CCGRx_CG9_OFFSET
,
760 NULL
, NULL
, &ipg_clk
, NULL
);
761 DEFINE_CLOCK(gpt_ipg_clk
, 0, MXC_CCM_CCGR2
, MXC_CCM_CCGRx_CG10_OFFSET
,
762 NULL
, NULL
, &ipg_clk
, NULL
);
765 DEFINE_CLOCK(fec_clk
, 0, MXC_CCM_CCGR2
, MXC_CCM_CCGRx_CG12_OFFSET
,
766 NULL
, NULL
, &ipg_clk
, NULL
);
768 #define _REGISTER_CLOCK(d, n, c) \
775 static struct clk_lookup lookups
[] = {
776 _REGISTER_CLOCK("imx-uart.0", NULL
, uart1_clk
)
777 _REGISTER_CLOCK("imx-uart.1", NULL
, uart2_clk
)
778 _REGISTER_CLOCK("imx-uart.2", NULL
, uart3_clk
)
779 _REGISTER_CLOCK(NULL
, "gpt", gpt_clk
)
780 _REGISTER_CLOCK("fec.0", NULL
, fec_clk
)
783 static void clk_tree_init(void)
787 ipg_perclk
.set_parent(&ipg_perclk
, &lp_apm_clk
);
790 * Initialise the IPG PER CLK dividers to 3. IPG_PER_CLK should be at
791 * 8MHz, its derived from lp_apm.
793 * FIXME: Verify if true for all boards
795 reg
= __raw_readl(MXC_CCM_CBCDR
);
796 reg
&= ~MXC_CCM_CBCDR_PERCLK_PRED1_MASK
;
797 reg
&= ~MXC_CCM_CBCDR_PERCLK_PRED2_MASK
;
798 reg
&= ~MXC_CCM_CBCDR_PERCLK_PODF_MASK
;
799 reg
|= (2 << MXC_CCM_CBCDR_PERCLK_PRED1_OFFSET
);
800 __raw_writel(reg
, MXC_CCM_CBCDR
);
803 int __init
mx51_clocks_init(unsigned long ckil
, unsigned long osc
,
804 unsigned long ckih1
, unsigned long ckih2
)
808 external_low_reference
= ckil
;
809 external_high_reference
= ckih1
;
810 ckih2_reference
= ckih2
;
811 oscillator_reference
= osc
;
813 for (i
= 0; i
< ARRAY_SIZE(lookups
); i
++)
814 clkdev_add(&lookups
[i
]);
818 clk_enable(&cpu_clk
);
819 clk_enable(&main_bus_clk
);
822 mxc_timer_init(&gpt_clk
, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR
),