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drm/radeon/kms: fix sideport detection on newer rs880 boards
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / gpu / drm / radeon / radeon_atombios.c
blob05ef0c43a1abb0a12b7337c8b739953ef77ee5f0
1 /*
2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors: Dave Airlie
24 * Alex Deucher
25 */
26 #include "drmP.h"
27 #include "radeon_drm.h"
28 #include "radeon.h"
29
30 #include "atom.h"
31 #include "atom-bits.h"
32
33 /* from radeon_encoder.c */
34 extern uint32_t
35 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device,
36 uint8_t dac);
37 extern void radeon_link_encoder_connector(struct drm_device *dev);
38 extern void
39 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id,
40 uint32_t supported_device);
41
42 /* from radeon_connector.c */
43 extern void
44 radeon_add_atom_connector(struct drm_device *dev,
45 uint32_t connector_id,
46 uint32_t supported_device,
47 int connector_type,
48 struct radeon_i2c_bus_rec *i2c_bus,
49 bool linkb, uint32_t igp_lane_info,
50 uint16_t connector_object_id,
51 struct radeon_hpd *hpd);
52
53 /* from radeon_legacy_encoder.c */
54 extern void
55 radeon_add_legacy_encoder(struct drm_device *dev, uint32_t encoder_id,
56 uint32_t supported_device);
57
58 union atom_supported_devices {
59 struct _ATOM_SUPPORTED_DEVICES_INFO info;
60 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
61 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
62 };
63
64 static inline struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
65 uint8_t id)
66 {
67 struct atom_context *ctx = rdev->mode_info.atom_context;
68 ATOM_GPIO_I2C_ASSIGMENT *gpio;
69 struct radeon_i2c_bus_rec i2c;
70 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
71 struct _ATOM_GPIO_I2C_INFO *i2c_info;
72 uint16_t data_offset, size;
73 int i, num_indices;
74
75 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
76 i2c.valid = false;
77
78 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
79 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
80
81 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
82 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
83
84 for (i = 0; i < num_indices; i++) {
85 gpio = &i2c_info->asGPIO_Info[i];
86
87 if (gpio->sucI2cId.ucAccess == id) {
88 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
89 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
90 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
91 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
92 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
93 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
94 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
95 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
96 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
97 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
98 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
99 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
100 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
101 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
102 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
103 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
104
105 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
106 i2c.hw_capable = true;
107 else
108 i2c.hw_capable = false;
109
110 if (gpio->sucI2cId.ucAccess == 0xa0)
111 i2c.mm_i2c = true;
112 else
113 i2c.mm_i2c = false;
114
115 i2c.i2c_id = gpio->sucI2cId.ucAccess;
116
117 i2c.valid = true;
118 break;
119 }
120 }
121 }
122
123 return i2c;
124 }
125
126 static inline struct radeon_gpio_rec radeon_lookup_gpio(struct radeon_device *rdev,
127 u8 id)
128 {
129 struct atom_context *ctx = rdev->mode_info.atom_context;
130 struct radeon_gpio_rec gpio;
131 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
132 struct _ATOM_GPIO_PIN_LUT *gpio_info;
133 ATOM_GPIO_PIN_ASSIGNMENT *pin;
134 u16 data_offset, size;
135 int i, num_indices;
136
137 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
138 gpio.valid = false;
139
140 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
141 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
142
143 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
144 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
145
146 for (i = 0; i < num_indices; i++) {
147 pin = &gpio_info->asGPIO_Pin[i];
148 if (id == pin->ucGPIO_ID) {
149 gpio.id = pin->ucGPIO_ID;
150 gpio.reg = pin->usGpioPin_AIndex * 4;
151 gpio.mask = (1 << pin->ucGpioPinBitShift);
152 gpio.valid = true;
153 break;
154 }
155 }
156 }
157
158 return gpio;
159 }
160
161 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
162 struct radeon_gpio_rec *gpio)
163 {
164 struct radeon_hpd hpd;
165 u32 reg;
166
167 if (ASIC_IS_DCE4(rdev))
168 reg = EVERGREEN_DC_GPIO_HPD_A;
169 else
170 reg = AVIVO_DC_GPIO_HPD_A;
171
172 hpd.gpio = *gpio;
173 if (gpio->reg == reg) {
174 switch(gpio->mask) {
175 case (1 << 0):
176 hpd.hpd = RADEON_HPD_1;
177 break;
178 case (1 << 8):
179 hpd.hpd = RADEON_HPD_2;
180 break;
181 case (1 << 16):
182 hpd.hpd = RADEON_HPD_3;
183 break;
184 case (1 << 24):
185 hpd.hpd = RADEON_HPD_4;
186 break;
187 case (1 << 26):
188 hpd.hpd = RADEON_HPD_5;
189 break;
190 case (1 << 28):
191 hpd.hpd = RADEON_HPD_6;
192 break;
193 default:
194 hpd.hpd = RADEON_HPD_NONE;
195 break;
196 }
197 } else
198 hpd.hpd = RADEON_HPD_NONE;
199 return hpd;
200 }
201
202 static bool radeon_atom_apply_quirks(struct drm_device *dev,
203 uint32_t supported_device,
204 int *connector_type,
205 struct radeon_i2c_bus_rec *i2c_bus,
206 uint16_t *line_mux,
207 struct radeon_hpd *hpd)
208 {
209 struct radeon_device *rdev = dev->dev_private;
210
211 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
212 if ((dev->pdev->device == 0x791e) &&
213 (dev->pdev->subsystem_vendor == 0x1043) &&
214 (dev->pdev->subsystem_device == 0x826d)) {
215 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
216 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
217 *connector_type = DRM_MODE_CONNECTOR_DVID;
218 }
219
220 /* Asrock RS600 board lists the DVI port as HDMI */
221 if ((dev->pdev->device == 0x7941) &&
222 (dev->pdev->subsystem_vendor == 0x1849) &&
223 (dev->pdev->subsystem_device == 0x7941)) {
224 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
225 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
226 *connector_type = DRM_MODE_CONNECTOR_DVID;
227 }
228
229 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
230 if ((dev->pdev->device == 0x7941) &&
231 (dev->pdev->subsystem_vendor == 0x147b) &&
232 (dev->pdev->subsystem_device == 0x2412)) {
233 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
234 return false;
235 }
236
237 /* Falcon NW laptop lists vga ddc line for LVDS */
238 if ((dev->pdev->device == 0x5653) &&
239 (dev->pdev->subsystem_vendor == 0x1462) &&
240 (dev->pdev->subsystem_device == 0x0291)) {
241 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
242 i2c_bus->valid = false;
243 *line_mux = 53;
244 }
245 }
246
247 /* HIS X1300 is DVI+VGA, not DVI+DVI */
248 if ((dev->pdev->device == 0x7146) &&
249 (dev->pdev->subsystem_vendor == 0x17af) &&
250 (dev->pdev->subsystem_device == 0x2058)) {
251 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
252 return false;
253 }
254
255 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
256 if ((dev->pdev->device == 0x7142) &&
257 (dev->pdev->subsystem_vendor == 0x1458) &&
258 (dev->pdev->subsystem_device == 0x2134)) {
259 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
260 return false;
261 }
262
263
264 /* Funky macbooks */
265 if ((dev->pdev->device == 0x71C5) &&
266 (dev->pdev->subsystem_vendor == 0x106b) &&
267 (dev->pdev->subsystem_device == 0x0080)) {
268 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
269 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
270 return false;
271 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
272 *line_mux = 0x90;
273 }
274
275 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
276 if ((dev->pdev->device == 0x9598) &&
277 (dev->pdev->subsystem_vendor == 0x1043) &&
278 (dev->pdev->subsystem_device == 0x01da)) {
279 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
280 *connector_type = DRM_MODE_CONNECTOR_DVII;
281 }
282 }
283
284 /* ASUS HD 3600 board lists the DVI port as HDMI */
285 if ((dev->pdev->device == 0x9598) &&
286 (dev->pdev->subsystem_vendor == 0x1043) &&
287 (dev->pdev->subsystem_device == 0x01e4)) {
288 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
289 *connector_type = DRM_MODE_CONNECTOR_DVII;
290 }
291 }
292
293 /* ASUS HD 3450 board lists the DVI port as HDMI */
294 if ((dev->pdev->device == 0x95C5) &&
295 (dev->pdev->subsystem_vendor == 0x1043) &&
296 (dev->pdev->subsystem_device == 0x01e2)) {
297 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
298 *connector_type = DRM_MODE_CONNECTOR_DVII;
299 }
300 }
301
302 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
303 * HDMI + VGA reporting as HDMI
304 */
305 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
306 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
307 *connector_type = DRM_MODE_CONNECTOR_VGA;
308 *line_mux = 0;
309 }
310 }
311
312 /* Acer laptop reports DVI-D as DVI-I and hpd pins reversed */
313 if ((dev->pdev->device == 0x95c4) &&
314 (dev->pdev->subsystem_vendor == 0x1025) &&
315 (dev->pdev->subsystem_device == 0x013c)) {
316 struct radeon_gpio_rec gpio;
317
318 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
319 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
320 gpio = radeon_lookup_gpio(rdev, 6);
321 *hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
322 *connector_type = DRM_MODE_CONNECTOR_DVID;
323 } else if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
324 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
325 gpio = radeon_lookup_gpio(rdev, 7);
326 *hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
327 }
328 }
329
330 /* XFX Pine Group device rv730 reports no VGA DDC lines
331 * even though they are wired up to record 0x93
332 */
333 if ((dev->pdev->device == 0x9498) &&
334 (dev->pdev->subsystem_vendor == 0x1682) &&
335 (dev->pdev->subsystem_device == 0x2452)) {
336 struct radeon_device *rdev = dev->dev_private;
337 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
338 }
339 return true;
340 }
341
342 const int supported_devices_connector_convert[] = {
343 DRM_MODE_CONNECTOR_Unknown,
344 DRM_MODE_CONNECTOR_VGA,
345 DRM_MODE_CONNECTOR_DVII,
346 DRM_MODE_CONNECTOR_DVID,
347 DRM_MODE_CONNECTOR_DVIA,
348 DRM_MODE_CONNECTOR_SVIDEO,
349 DRM_MODE_CONNECTOR_Composite,
350 DRM_MODE_CONNECTOR_LVDS,
351 DRM_MODE_CONNECTOR_Unknown,
352 DRM_MODE_CONNECTOR_Unknown,
353 DRM_MODE_CONNECTOR_HDMIA,
354 DRM_MODE_CONNECTOR_HDMIB,
355 DRM_MODE_CONNECTOR_Unknown,
356 DRM_MODE_CONNECTOR_Unknown,
357 DRM_MODE_CONNECTOR_9PinDIN,
358 DRM_MODE_CONNECTOR_DisplayPort
359 };
360
361 const uint16_t supported_devices_connector_object_id_convert[] = {
362 CONNECTOR_OBJECT_ID_NONE,
363 CONNECTOR_OBJECT_ID_VGA,
364 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
365 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
366 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
367 CONNECTOR_OBJECT_ID_COMPOSITE,
368 CONNECTOR_OBJECT_ID_SVIDEO,
369 CONNECTOR_OBJECT_ID_LVDS,
370 CONNECTOR_OBJECT_ID_9PIN_DIN,
371 CONNECTOR_OBJECT_ID_9PIN_DIN,
372 CONNECTOR_OBJECT_ID_DISPLAYPORT,
373 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
374 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
375 CONNECTOR_OBJECT_ID_SVIDEO
376 };
377
378 const int object_connector_convert[] = {
379 DRM_MODE_CONNECTOR_Unknown,
380 DRM_MODE_CONNECTOR_DVII,
381 DRM_MODE_CONNECTOR_DVII,
382 DRM_MODE_CONNECTOR_DVID,
383 DRM_MODE_CONNECTOR_DVID,
384 DRM_MODE_CONNECTOR_VGA,
385 DRM_MODE_CONNECTOR_Composite,
386 DRM_MODE_CONNECTOR_SVIDEO,
387 DRM_MODE_CONNECTOR_Unknown,
388 DRM_MODE_CONNECTOR_Unknown,
389 DRM_MODE_CONNECTOR_9PinDIN,
390 DRM_MODE_CONNECTOR_Unknown,
391 DRM_MODE_CONNECTOR_HDMIA,
392 DRM_MODE_CONNECTOR_HDMIB,
393 DRM_MODE_CONNECTOR_LVDS,
394 DRM_MODE_CONNECTOR_9PinDIN,
395 DRM_MODE_CONNECTOR_Unknown,
396 DRM_MODE_CONNECTOR_Unknown,
397 DRM_MODE_CONNECTOR_Unknown,
398 DRM_MODE_CONNECTOR_DisplayPort,
399 DRM_MODE_CONNECTOR_eDP,
400 DRM_MODE_CONNECTOR_Unknown
401 };
402
403 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
404 {
405 struct radeon_device *rdev = dev->dev_private;
406 struct radeon_mode_info *mode_info = &rdev->mode_info;
407 struct atom_context *ctx = mode_info->atom_context;
408 int index = GetIndexIntoMasterTable(DATA, Object_Header);
409 u16 size, data_offset;
410 u8 frev, crev;
411 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
412 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
413 ATOM_OBJECT_HEADER *obj_header;
414 int i, j, path_size, device_support;
415 int connector_type;
416 u16 igp_lane_info, conn_id, connector_object_id;
417 bool linkb;
418 struct radeon_i2c_bus_rec ddc_bus;
419 struct radeon_gpio_rec gpio;
420 struct radeon_hpd hpd;
421
422 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
423 return false;
424
425 if (crev < 2)
426 return false;
427
428 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
429 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
430 (ctx->bios + data_offset +
431 le16_to_cpu(obj_header->usDisplayPathTableOffset));
432 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
433 (ctx->bios + data_offset +
434 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
435 device_support = le16_to_cpu(obj_header->usDeviceSupport);
436
437 path_size = 0;
438 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
439 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
440 ATOM_DISPLAY_OBJECT_PATH *path;
441 addr += path_size;
442 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
443 path_size += le16_to_cpu(path->usSize);
444 linkb = false;
445 if (device_support & le16_to_cpu(path->usDeviceTag)) {
446 uint8_t con_obj_id, con_obj_num, con_obj_type;
447
448 con_obj_id =
449 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
450 >> OBJECT_ID_SHIFT;
451 con_obj_num =
452 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
453 >> ENUM_ID_SHIFT;
454 con_obj_type =
455 (le16_to_cpu(path->usConnObjectId) &
456 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
457
458 /* TODO CV support */
459 if (le16_to_cpu(path->usDeviceTag) ==
460 ATOM_DEVICE_CV_SUPPORT)
461 continue;
462
463 /* IGP chips */
464 if ((rdev->flags & RADEON_IS_IGP) &&
465 (con_obj_id ==
466 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
467 uint16_t igp_offset = 0;
468 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
469
470 index =
471 GetIndexIntoMasterTable(DATA,
472 IntegratedSystemInfo);
473
474 if (atom_parse_data_header(ctx, index, &size, &frev,
475 &crev, &igp_offset)) {
476
477 if (crev >= 2) {
478 igp_obj =
479 (ATOM_INTEGRATED_SYSTEM_INFO_V2
480 *) (ctx->bios + igp_offset);
481
482 if (igp_obj) {
483 uint32_t slot_config, ct;
484
485 if (con_obj_num == 1)
486 slot_config =
487 igp_obj->
488 ulDDISlot1Config;
489 else
490 slot_config =
491 igp_obj->
492 ulDDISlot2Config;
493
494 ct = (slot_config >> 16) & 0xff;
495 connector_type =
496 object_connector_convert
497 [ct];
498 connector_object_id = ct;
499 igp_lane_info =
500 slot_config & 0xffff;
501 } else
502 continue;
503 } else
504 continue;
505 } else {
506 igp_lane_info = 0;
507 connector_type =
508 object_connector_convert[con_obj_id];
509 connector_object_id = con_obj_id;
510 }
511 } else {
512 igp_lane_info = 0;
513 connector_type =
514 object_connector_convert[con_obj_id];
515 connector_object_id = con_obj_id;
516 }
517
518 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
519 continue;
520
521 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2);
522 j++) {
523 uint8_t enc_obj_id, enc_obj_num, enc_obj_type;
524
525 enc_obj_id =
526 (le16_to_cpu(path->usGraphicObjIds[j]) &
527 OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
528 enc_obj_num =
529 (le16_to_cpu(path->usGraphicObjIds[j]) &
530 ENUM_ID_MASK) >> ENUM_ID_SHIFT;
531 enc_obj_type =
532 (le16_to_cpu(path->usGraphicObjIds[j]) &
533 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
534
535 /* FIXME: add support for router objects */
536 if (enc_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
537 if (enc_obj_num == 2)
538 linkb = true;
539 else
540 linkb = false;
541
542 radeon_add_atom_encoder(dev,
543 enc_obj_id,
544 le16_to_cpu
545 (path->
546 usDeviceTag));
547
548 }
549 }
550
551 /* look up gpio for ddc, hpd */
552 ddc_bus.valid = false;
553 hpd.hpd = RADEON_HPD_NONE;
554 if ((le16_to_cpu(path->usDeviceTag) &
555 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
556 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
557 if (le16_to_cpu(path->usConnObjectId) ==
558 le16_to_cpu(con_obj->asObjects[j].
559 usObjectID)) {
560 ATOM_COMMON_RECORD_HEADER
561 *record =
562 (ATOM_COMMON_RECORD_HEADER
563 *)
564 (ctx->bios + data_offset +
565 le16_to_cpu(con_obj->
566 asObjects[j].
567 usRecordOffset));
568 ATOM_I2C_RECORD *i2c_record;
569 ATOM_HPD_INT_RECORD *hpd_record;
570 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
571 hpd.hpd = RADEON_HPD_NONE;
572
573 while (record->ucRecordType > 0
574 && record->
575 ucRecordType <=
576 ATOM_MAX_OBJECT_RECORD_NUMBER) {
577 switch (record->ucRecordType) {
578 case ATOM_I2C_RECORD_TYPE:
579 i2c_record =
580 (ATOM_I2C_RECORD *)
581 record;
582 i2c_config =
583 (ATOM_I2C_ID_CONFIG_ACCESS *)
584 &i2c_record->sucI2cId;
585 ddc_bus = radeon_lookup_i2c_gpio(rdev,
586 i2c_config->
587 ucAccess);
588 break;
589 case ATOM_HPD_INT_RECORD_TYPE:
590 hpd_record =
591 (ATOM_HPD_INT_RECORD *)
592 record;
593 gpio = radeon_lookup_gpio(rdev,
594 hpd_record->ucHPDIntGPIOID);
595 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
596 hpd.plugged_state = hpd_record->ucPlugged_PinState;
597 break;
598 }
599 record =
600 (ATOM_COMMON_RECORD_HEADER
601 *) ((char *)record
602 +
603 record->
604 ucRecordSize);
605 }
606 break;
607 }
608 }
609 }
610
611 /* needed for aux chan transactions */
612 ddc_bus.hpd_id = hpd.hpd ? (hpd.hpd - 1) : 0;
613
614 conn_id = le16_to_cpu(path->usConnObjectId);
615
616 if (!radeon_atom_apply_quirks
617 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
618 &ddc_bus, &conn_id, &hpd))
619 continue;
620
621 radeon_add_atom_connector(dev,
622 conn_id,
623 le16_to_cpu(path->
624 usDeviceTag),
625 connector_type, &ddc_bus,
626 linkb, igp_lane_info,
627 connector_object_id,
628 &hpd);
629
630 }
631 }
632
633 radeon_link_encoder_connector(dev);
634
635 return true;
636 }
637
638 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
639 int connector_type,
640 uint16_t devices)
641 {
642 struct radeon_device *rdev = dev->dev_private;
643
644 if (rdev->flags & RADEON_IS_IGP) {
645 return supported_devices_connector_object_id_convert
646 [connector_type];
647 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
648 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
649 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
650 struct radeon_mode_info *mode_info = &rdev->mode_info;
651 struct atom_context *ctx = mode_info->atom_context;
652 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
653 uint16_t size, data_offset;
654 uint8_t frev, crev;
655 ATOM_XTMDS_INFO *xtmds;
656
657 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
658 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
659
660 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
661 if (connector_type == DRM_MODE_CONNECTOR_DVII)
662 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
663 else
664 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
665 } else {
666 if (connector_type == DRM_MODE_CONNECTOR_DVII)
667 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
668 else
669 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
670 }
671 } else
672 return supported_devices_connector_object_id_convert
673 [connector_type];
674 } else {
675 return supported_devices_connector_object_id_convert
676 [connector_type];
677 }
678 }
679
680 struct bios_connector {
681 bool valid;
682 uint16_t line_mux;
683 uint16_t devices;
684 int connector_type;
685 struct radeon_i2c_bus_rec ddc_bus;
686 struct radeon_hpd hpd;
687 };
688
689 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
690 drm_device
691 *dev)
692 {
693 struct radeon_device *rdev = dev->dev_private;
694 struct radeon_mode_info *mode_info = &rdev->mode_info;
695 struct atom_context *ctx = mode_info->atom_context;
696 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
697 uint16_t size, data_offset;
698 uint8_t frev, crev;
699 uint16_t device_support;
700 uint8_t dac;
701 union atom_supported_devices *supported_devices;
702 int i, j, max_device;
703 struct bios_connector bios_connectors[ATOM_MAX_SUPPORTED_DEVICE];
704
705 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
706 return false;
707
708 supported_devices =
709 (union atom_supported_devices *)(ctx->bios + data_offset);
710
711 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
712
713 if (frev > 1)
714 max_device = ATOM_MAX_SUPPORTED_DEVICE;
715 else
716 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
717
718 for (i = 0; i < max_device; i++) {
719 ATOM_CONNECTOR_INFO_I2C ci =
720 supported_devices->info.asConnInfo[i];
721
722 bios_connectors[i].valid = false;
723
724 if (!(device_support & (1 << i))) {
725 continue;
726 }
727
728 if (i == ATOM_DEVICE_CV_INDEX) {
729 DRM_DEBUG("Skipping Component Video\n");
730 continue;
731 }
732
733 bios_connectors[i].connector_type =
734 supported_devices_connector_convert[ci.sucConnectorInfo.
735 sbfAccess.
736 bfConnectorType];
737
738 if (bios_connectors[i].connector_type ==
739 DRM_MODE_CONNECTOR_Unknown)
740 continue;
741
742 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
743
744 bios_connectors[i].line_mux =
745 ci.sucI2cId.ucAccess;
746
747 /* give tv unique connector ids */
748 if (i == ATOM_DEVICE_TV1_INDEX) {
749 bios_connectors[i].ddc_bus.valid = false;
750 bios_connectors[i].line_mux = 50;
751 } else if (i == ATOM_DEVICE_TV2_INDEX) {
752 bios_connectors[i].ddc_bus.valid = false;
753 bios_connectors[i].line_mux = 51;
754 } else if (i == ATOM_DEVICE_CV_INDEX) {
755 bios_connectors[i].ddc_bus.valid = false;
756 bios_connectors[i].line_mux = 52;
757 } else
758 bios_connectors[i].ddc_bus =
759 radeon_lookup_i2c_gpio(rdev,
760 bios_connectors[i].line_mux);
761
762 if ((crev > 1) && (frev > 1)) {
763 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
764 switch (isb) {
765 case 0x4:
766 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
767 break;
768 case 0xa:
769 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
770 break;
771 default:
772 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
773 break;
774 }
775 } else {
776 if (i == ATOM_DEVICE_DFP1_INDEX)
777 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
778 else if (i == ATOM_DEVICE_DFP2_INDEX)
779 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
780 else
781 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
782 }
783
784 /* Always set the connector type to VGA for CRT1/CRT2. if they are
785 * shared with a DVI port, we'll pick up the DVI connector when we
786 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
787 */
788 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
789 bios_connectors[i].connector_type =
790 DRM_MODE_CONNECTOR_VGA;
791
792 if (!radeon_atom_apply_quirks
793 (dev, (1 << i), &bios_connectors[i].connector_type,
794 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
795 &bios_connectors[i].hpd))
796 continue;
797
798 bios_connectors[i].valid = true;
799 bios_connectors[i].devices = (1 << i);
800
801 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
802 radeon_add_atom_encoder(dev,
803 radeon_get_encoder_id(dev,
804 (1 << i),
805 dac),
806 (1 << i));
807 else
808 radeon_add_legacy_encoder(dev,
809 radeon_get_encoder_id(dev,
810 (1 << i),
811 dac),
812 (1 << i));
813 }
814
815 /* combine shared connectors */
816 for (i = 0; i < max_device; i++) {
817 if (bios_connectors[i].valid) {
818 for (j = 0; j < max_device; j++) {
819 if (bios_connectors[j].valid && (i != j)) {
820 if (bios_connectors[i].line_mux ==
821 bios_connectors[j].line_mux) {
822 /* make sure not to combine LVDS */
823 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
824 bios_connectors[i].line_mux = 53;
825 bios_connectors[i].ddc_bus.valid = false;
826 continue;
827 }
828 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
829 bios_connectors[j].line_mux = 53;
830 bios_connectors[j].ddc_bus.valid = false;
831 continue;
832 }
833 /* combine analog and digital for DVI-I */
834 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
835 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
836 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
837 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
838 bios_connectors[i].devices |=
839 bios_connectors[j].devices;
840 bios_connectors[i].connector_type =
841 DRM_MODE_CONNECTOR_DVII;
842 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
843 bios_connectors[i].hpd =
844 bios_connectors[j].hpd;
845 bios_connectors[j].valid = false;
846 }
847 }
848 }
849 }
850 }
851 }
852
853 /* add the connectors */
854 for (i = 0; i < max_device; i++) {
855 if (bios_connectors[i].valid) {
856 uint16_t connector_object_id =
857 atombios_get_connector_object_id(dev,
858 bios_connectors[i].connector_type,
859 bios_connectors[i].devices);
860 radeon_add_atom_connector(dev,
861 bios_connectors[i].line_mux,
862 bios_connectors[i].devices,
863 bios_connectors[i].
864 connector_type,
865 &bios_connectors[i].ddc_bus,
866 false, 0,
867 connector_object_id,
868 &bios_connectors[i].hpd);
869 }
870 }
871
872 radeon_link_encoder_connector(dev);
873
874 return true;
875 }
876
877 union firmware_info {
878 ATOM_FIRMWARE_INFO info;
879 ATOM_FIRMWARE_INFO_V1_2 info_12;
880 ATOM_FIRMWARE_INFO_V1_3 info_13;
881 ATOM_FIRMWARE_INFO_V1_4 info_14;
882 ATOM_FIRMWARE_INFO_V2_1 info_21;
883 };
884
885 bool radeon_atom_get_clock_info(struct drm_device *dev)
886 {
887 struct radeon_device *rdev = dev->dev_private;
888 struct radeon_mode_info *mode_info = &rdev->mode_info;
889 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
890 union firmware_info *firmware_info;
891 uint8_t frev, crev;
892 struct radeon_pll *p1pll = &rdev->clock.p1pll;
893 struct radeon_pll *p2pll = &rdev->clock.p2pll;
894 struct radeon_pll *dcpll = &rdev->clock.dcpll;
895 struct radeon_pll *spll = &rdev->clock.spll;
896 struct radeon_pll *mpll = &rdev->clock.mpll;
897 uint16_t data_offset;
898
899 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
900 &frev, &crev, &data_offset)) {
901 firmware_info =
902 (union firmware_info *)(mode_info->atom_context->bios +
903 data_offset);
904 /* pixel clocks */
905 p1pll->reference_freq =
906 le16_to_cpu(firmware_info->info.usReferenceClock);
907 p1pll->reference_div = 0;
908
909 if (crev < 2)
910 p1pll->pll_out_min =
911 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
912 else
913 p1pll->pll_out_min =
914 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
915 p1pll->pll_out_max =
916 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
917
918 if (crev >= 4) {
919 p1pll->lcd_pll_out_min =
920 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
921 if (p1pll->lcd_pll_out_min == 0)
922 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
923 p1pll->lcd_pll_out_max =
924 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
925 if (p1pll->lcd_pll_out_max == 0)
926 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
927 } else {
928 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
929 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
930 }
931
932 if (p1pll->pll_out_min == 0) {
933 if (ASIC_IS_AVIVO(rdev))
934 p1pll->pll_out_min = 64800;
935 else
936 p1pll->pll_out_min = 20000;
937 } else if (p1pll->pll_out_min > 64800) {
938 /* Limiting the pll output range is a good thing generally as
939 * it limits the number of possible pll combinations for a given
940 * frequency presumably to the ones that work best on each card.
941 * However, certain duallink DVI monitors seem to like
942 * pll combinations that would be limited by this at least on
943 * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per
944 * family.
945 */
946 if (!radeon_new_pll)
947 p1pll->pll_out_min = 64800;
948 }
949
950 p1pll->pll_in_min =
951 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
952 p1pll->pll_in_max =
953 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
954
955 *p2pll = *p1pll;
956
957 /* system clock */
958 spll->reference_freq =
959 le16_to_cpu(firmware_info->info.usReferenceClock);
960 spll->reference_div = 0;
961
962 spll->pll_out_min =
963 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
964 spll->pll_out_max =
965 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
966
967 /* ??? */
968 if (spll->pll_out_min == 0) {
969 if (ASIC_IS_AVIVO(rdev))
970 spll->pll_out_min = 64800;
971 else
972 spll->pll_out_min = 20000;
973 }
974
975 spll->pll_in_min =
976 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
977 spll->pll_in_max =
978 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
979
980 /* memory clock */
981 mpll->reference_freq =
982 le16_to_cpu(firmware_info->info.usReferenceClock);
983 mpll->reference_div = 0;
984
985 mpll->pll_out_min =
986 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
987 mpll->pll_out_max =
988 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
989
990 /* ??? */
991 if (mpll->pll_out_min == 0) {
992 if (ASIC_IS_AVIVO(rdev))
993 mpll->pll_out_min = 64800;
994 else
995 mpll->pll_out_min = 20000;
996 }
997
998 mpll->pll_in_min =
999 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1000 mpll->pll_in_max =
1001 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1002
1003 rdev->clock.default_sclk =
1004 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1005 rdev->clock.default_mclk =
1006 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1007
1008 if (ASIC_IS_DCE4(rdev)) {
1009 rdev->clock.default_dispclk =
1010 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1011 if (rdev->clock.default_dispclk == 0)
1012 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1013 rdev->clock.dp_extclk =
1014 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1015 }
1016 *dcpll = *p1pll;
1017
1018 return true;
1019 }
1020
1021 return false;
1022 }
1023
1024 union igp_info {
1025 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1026 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1027 };
1028
1029 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1030 {
1031 struct radeon_mode_info *mode_info = &rdev->mode_info;
1032 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1033 union igp_info *igp_info;
1034 u8 frev, crev;
1035 u16 data_offset;
1036
1037 /* sideport is AMD only */
1038 if (rdev->family == CHIP_RS600)
1039 return false;
1040
1041 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1042 &frev, &crev, &data_offset)) {
1043 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1044 data_offset);
1045 switch (crev) {
1046 case 1:
1047 if (igp_info->info.ulBootUpMemoryClock)
1048 return true;
1049 break;
1050 case 2:
1051 if (igp_info->info_2.ulBootUpSidePortClock)
1052 return true;
1053 break;
1054 default:
1055 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1056 break;
1057 }
1058 }
1059 return false;
1060 }
1061
1062 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1063 struct radeon_encoder_int_tmds *tmds)
1064 {
1065 struct drm_device *dev = encoder->base.dev;
1066 struct radeon_device *rdev = dev->dev_private;
1067 struct radeon_mode_info *mode_info = &rdev->mode_info;
1068 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1069 uint16_t data_offset;
1070 struct _ATOM_TMDS_INFO *tmds_info;
1071 uint8_t frev, crev;
1072 uint16_t maxfreq;
1073 int i;
1074
1075 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1076 &frev, &crev, &data_offset)) {
1077 tmds_info =
1078 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1079 data_offset);
1080
1081 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1082 for (i = 0; i < 4; i++) {
1083 tmds->tmds_pll[i].freq =
1084 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1085 tmds->tmds_pll[i].value =
1086 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1087 tmds->tmds_pll[i].value |=
1088 (tmds_info->asMiscInfo[i].
1089 ucPLL_VCO_Gain & 0x3f) << 6;
1090 tmds->tmds_pll[i].value |=
1091 (tmds_info->asMiscInfo[i].
1092 ucPLL_DutyCycle & 0xf) << 12;
1093 tmds->tmds_pll[i].value |=
1094 (tmds_info->asMiscInfo[i].
1095 ucPLL_VoltageSwing & 0xf) << 16;
1096
1097 DRM_DEBUG("TMDS PLL From ATOMBIOS %u %x\n",
1098 tmds->tmds_pll[i].freq,
1099 tmds->tmds_pll[i].value);
1100
1101 if (maxfreq == tmds->tmds_pll[i].freq) {
1102 tmds->tmds_pll[i].freq = 0xffffffff;
1103 break;
1104 }
1105 }
1106 return true;
1107 }
1108 return false;
1109 }
1110
1111 static struct radeon_atom_ss *radeon_atombios_get_ss_info(struct
1112 radeon_encoder
1113 *encoder,
1114 int id)
1115 {
1116 struct drm_device *dev = encoder->base.dev;
1117 struct radeon_device *rdev = dev->dev_private;
1118 struct radeon_mode_info *mode_info = &rdev->mode_info;
1119 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1120 uint16_t data_offset;
1121 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1122 uint8_t frev, crev;
1123 struct radeon_atom_ss *ss = NULL;
1124 int i;
1125
1126 if (id > ATOM_MAX_SS_ENTRY)
1127 return NULL;
1128
1129 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1130 &frev, &crev, &data_offset)) {
1131 ss_info =
1132 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1133
1134 ss =
1135 kzalloc(sizeof(struct radeon_atom_ss), GFP_KERNEL);
1136
1137 if (!ss)
1138 return NULL;
1139
1140 for (i = 0; i < ATOM_MAX_SS_ENTRY; i++) {
1141 if (ss_info->asSS_Info[i].ucSS_Id == id) {
1142 ss->percentage =
1143 le16_to_cpu(ss_info->asSS_Info[i].usSpreadSpectrumPercentage);
1144 ss->type = ss_info->asSS_Info[i].ucSpreadSpectrumType;
1145 ss->step = ss_info->asSS_Info[i].ucSS_Step;
1146 ss->delay = ss_info->asSS_Info[i].ucSS_Delay;
1147 ss->range = ss_info->asSS_Info[i].ucSS_Range;
1148 ss->refdiv = ss_info->asSS_Info[i].ucRecommendedRef_Div;
1149 break;
1150 }
1151 }
1152 }
1153 return ss;
1154 }
1155
1156 union lvds_info {
1157 struct _ATOM_LVDS_INFO info;
1158 struct _ATOM_LVDS_INFO_V12 info_12;
1159 };
1160
1161 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1162 radeon_encoder
1163 *encoder)
1164 {
1165 struct drm_device *dev = encoder->base.dev;
1166 struct radeon_device *rdev = dev->dev_private;
1167 struct radeon_mode_info *mode_info = &rdev->mode_info;
1168 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1169 uint16_t data_offset, misc;
1170 union lvds_info *lvds_info;
1171 uint8_t frev, crev;
1172 struct radeon_encoder_atom_dig *lvds = NULL;
1173
1174 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1175 &frev, &crev, &data_offset)) {
1176 lvds_info =
1177 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1178 lvds =
1179 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1180
1181 if (!lvds)
1182 return NULL;
1183
1184 lvds->native_mode.clock =
1185 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1186 lvds->native_mode.hdisplay =
1187 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1188 lvds->native_mode.vdisplay =
1189 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1190 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1191 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1192 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1193 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1194 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1195 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1196 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1197 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1198 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1199 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1200 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1201 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1202 lvds->panel_pwr_delay =
1203 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1204 lvds->lvds_misc = lvds_info->info.ucLVDS_Misc;
1205
1206 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1207 if (misc & ATOM_VSYNC_POLARITY)
1208 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1209 if (misc & ATOM_HSYNC_POLARITY)
1210 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1211 if (misc & ATOM_COMPOSITESYNC)
1212 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1213 if (misc & ATOM_INTERLACE)
1214 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1215 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1216 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1217
1218 /* set crtc values */
1219 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1220
1221 lvds->ss = radeon_atombios_get_ss_info(encoder, lvds_info->info.ucSS_Id);
1222
1223 if (ASIC_IS_AVIVO(rdev)) {
1224 if (radeon_new_pll == 0)
1225 lvds->pll_algo = PLL_ALGO_LEGACY;
1226 else
1227 lvds->pll_algo = PLL_ALGO_NEW;
1228 } else {
1229 if (radeon_new_pll == 1)
1230 lvds->pll_algo = PLL_ALGO_NEW;
1231 else
1232 lvds->pll_algo = PLL_ALGO_LEGACY;
1233 }
1234
1235 encoder->native_mode = lvds->native_mode;
1236 }
1237 return lvds;
1238 }
1239
1240 struct radeon_encoder_primary_dac *
1241 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1242 {
1243 struct drm_device *dev = encoder->base.dev;
1244 struct radeon_device *rdev = dev->dev_private;
1245 struct radeon_mode_info *mode_info = &rdev->mode_info;
1246 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1247 uint16_t data_offset;
1248 struct _COMPASSIONATE_DATA *dac_info;
1249 uint8_t frev, crev;
1250 uint8_t bg, dac;
1251 struct radeon_encoder_primary_dac *p_dac = NULL;
1252
1253 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1254 &frev, &crev, &data_offset)) {
1255 dac_info = (struct _COMPASSIONATE_DATA *)
1256 (mode_info->atom_context->bios + data_offset);
1257
1258 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1259
1260 if (!p_dac)
1261 return NULL;
1262
1263 bg = dac_info->ucDAC1_BG_Adjustment;
1264 dac = dac_info->ucDAC1_DAC_Adjustment;
1265 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1266
1267 }
1268 return p_dac;
1269 }
1270
1271 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1272 struct drm_display_mode *mode)
1273 {
1274 struct radeon_mode_info *mode_info = &rdev->mode_info;
1275 ATOM_ANALOG_TV_INFO *tv_info;
1276 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1277 ATOM_DTD_FORMAT *dtd_timings;
1278 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1279 u8 frev, crev;
1280 u16 data_offset, misc;
1281
1282 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1283 &frev, &crev, &data_offset))
1284 return false;
1285
1286 switch (crev) {
1287 case 1:
1288 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1289 if (index >= MAX_SUPPORTED_TV_TIMING)
1290 return false;
1291
1292 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1293 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1294 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1295 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1296 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1297
1298 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1299 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1300 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1301 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1302 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1303
1304 mode->flags = 0;
1305 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1306 if (misc & ATOM_VSYNC_POLARITY)
1307 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1308 if (misc & ATOM_HSYNC_POLARITY)
1309 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1310 if (misc & ATOM_COMPOSITESYNC)
1311 mode->flags |= DRM_MODE_FLAG_CSYNC;
1312 if (misc & ATOM_INTERLACE)
1313 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1314 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1315 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1316
1317 mode->clock = le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1318
1319 if (index == 1) {
1320 /* PAL timings appear to have wrong values for totals */
1321 mode->crtc_htotal -= 1;
1322 mode->crtc_vtotal -= 1;
1323 }
1324 break;
1325 case 2:
1326 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1327 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1328 return false;
1329
1330 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1331 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1332 le16_to_cpu(dtd_timings->usHBlanking_Time);
1333 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1334 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1335 le16_to_cpu(dtd_timings->usHSyncOffset);
1336 mode->crtc_hsync_end = mode->crtc_hsync_start +
1337 le16_to_cpu(dtd_timings->usHSyncWidth);
1338
1339 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1340 le16_to_cpu(dtd_timings->usVBlanking_Time);
1341 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1342 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1343 le16_to_cpu(dtd_timings->usVSyncOffset);
1344 mode->crtc_vsync_end = mode->crtc_vsync_start +
1345 le16_to_cpu(dtd_timings->usVSyncWidth);
1346
1347 mode->flags = 0;
1348 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1349 if (misc & ATOM_VSYNC_POLARITY)
1350 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1351 if (misc & ATOM_HSYNC_POLARITY)
1352 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1353 if (misc & ATOM_COMPOSITESYNC)
1354 mode->flags |= DRM_MODE_FLAG_CSYNC;
1355 if (misc & ATOM_INTERLACE)
1356 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1357 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1358 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1359
1360 mode->clock = le16_to_cpu(dtd_timings->usPixClk) * 10;
1361 break;
1362 }
1363 return true;
1364 }
1365
1366 enum radeon_tv_std
1367 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1368 {
1369 struct radeon_mode_info *mode_info = &rdev->mode_info;
1370 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1371 uint16_t data_offset;
1372 uint8_t frev, crev;
1373 struct _ATOM_ANALOG_TV_INFO *tv_info;
1374 enum radeon_tv_std tv_std = TV_STD_NTSC;
1375
1376 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1377 &frev, &crev, &data_offset)) {
1378
1379 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1380 (mode_info->atom_context->bios + data_offset);
1381
1382 switch (tv_info->ucTV_BootUpDefaultStandard) {
1383 case ATOM_TV_NTSC:
1384 tv_std = TV_STD_NTSC;
1385 DRM_INFO("Default TV standard: NTSC\n");
1386 break;
1387 case ATOM_TV_NTSCJ:
1388 tv_std = TV_STD_NTSC_J;
1389 DRM_INFO("Default TV standard: NTSC-J\n");
1390 break;
1391 case ATOM_TV_PAL:
1392 tv_std = TV_STD_PAL;
1393 DRM_INFO("Default TV standard: PAL\n");
1394 break;
1395 case ATOM_TV_PALM:
1396 tv_std = TV_STD_PAL_M;
1397 DRM_INFO("Default TV standard: PAL-M\n");
1398 break;
1399 case ATOM_TV_PALN:
1400 tv_std = TV_STD_PAL_N;
1401 DRM_INFO("Default TV standard: PAL-N\n");
1402 break;
1403 case ATOM_TV_PALCN:
1404 tv_std = TV_STD_PAL_CN;
1405 DRM_INFO("Default TV standard: PAL-CN\n");
1406 break;
1407 case ATOM_TV_PAL60:
1408 tv_std = TV_STD_PAL_60;
1409 DRM_INFO("Default TV standard: PAL-60\n");
1410 break;
1411 case ATOM_TV_SECAM:
1412 tv_std = TV_STD_SECAM;
1413 DRM_INFO("Default TV standard: SECAM\n");
1414 break;
1415 default:
1416 tv_std = TV_STD_NTSC;
1417 DRM_INFO("Unknown TV standard; defaulting to NTSC\n");
1418 break;
1419 }
1420 }
1421 return tv_std;
1422 }
1423
1424 struct radeon_encoder_tv_dac *
1425 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1426 {
1427 struct drm_device *dev = encoder->base.dev;
1428 struct radeon_device *rdev = dev->dev_private;
1429 struct radeon_mode_info *mode_info = &rdev->mode_info;
1430 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1431 uint16_t data_offset;
1432 struct _COMPASSIONATE_DATA *dac_info;
1433 uint8_t frev, crev;
1434 uint8_t bg, dac;
1435 struct radeon_encoder_tv_dac *tv_dac = NULL;
1436
1437 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1438 &frev, &crev, &data_offset)) {
1439
1440 dac_info = (struct _COMPASSIONATE_DATA *)
1441 (mode_info->atom_context->bios + data_offset);
1442
1443 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1444
1445 if (!tv_dac)
1446 return NULL;
1447
1448 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1449 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1450 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1451
1452 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1453 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1454 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1455
1456 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1457 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1458 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1459
1460 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1461 }
1462 return tv_dac;
1463 }
1464
1465 static const char *thermal_controller_names[] = {
1466 "NONE",
1467 "LM63",
1468 "ADM1032",
1469 "ADM1030",
1470 "MUA6649",
1471 "LM64",
1472 "F75375",
1473 "ASC7512",
1474 };
1475
1476 static const char *pp_lib_thermal_controller_names[] = {
1477 "NONE",
1478 "LM63",
1479 "ADM1032",
1480 "ADM1030",
1481 "MUA6649",
1482 "LM64",
1483 "F75375",
1484 "RV6xx",
1485 "RV770",
1486 "ADT7473",
1487 };
1488
1489 union power_info {
1490 struct _ATOM_POWERPLAY_INFO info;
1491 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1492 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1493 struct _ATOM_PPLIB_POWERPLAYTABLE info_4;
1494 };
1495
1496 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
1497 {
1498 struct radeon_mode_info *mode_info = &rdev->mode_info;
1499 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1500 u16 data_offset;
1501 u8 frev, crev;
1502 u32 misc, misc2 = 0, sclk, mclk;
1503 union power_info *power_info;
1504 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1505 struct _ATOM_PPLIB_STATE *power_state;
1506 int num_modes = 0, i, j;
1507 int state_index = 0, mode_index = 0;
1508 struct radeon_i2c_bus_rec i2c_bus;
1509
1510 rdev->pm.default_power_state = NULL;
1511
1512 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1513 &frev, &crev, &data_offset)) {
1514 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1515 if (frev < 4) {
1516 /* add the i2c bus for thermal/fan chip */
1517 if (power_info->info.ucOverdriveThermalController > 0) {
1518 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
1519 thermal_controller_names[power_info->info.ucOverdriveThermalController],
1520 power_info->info.ucOverdriveControllerAddress >> 1);
1521 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
1522 rdev->pm.i2c_bus = radeon_i2c_create(rdev->ddev, &i2c_bus, "Thermal");
1523 }
1524 num_modes = power_info->info.ucNumOfPowerModeEntries;
1525 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
1526 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
1527 for (i = 0; i < num_modes; i++) {
1528 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1529 switch (frev) {
1530 case 1:
1531 rdev->pm.power_state[state_index].num_clock_modes = 1;
1532 rdev->pm.power_state[state_index].clock_info[0].mclk =
1533 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
1534 rdev->pm.power_state[state_index].clock_info[0].sclk =
1535 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
1536 /* skip invalid modes */
1537 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1538 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1539 continue;
1540 /* skip overclock modes for now */
1541 if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
1542 rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1543 (rdev->pm.power_state[state_index].clock_info[0].sclk >
1544 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1545 continue;
1546 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1547 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
1548 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
1549 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1550 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1551 VOLTAGE_GPIO;
1552 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1553 radeon_lookup_gpio(rdev,
1554 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
1555 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1556 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1557 true;
1558 else
1559 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1560 false;
1561 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1562 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1563 VOLTAGE_VDDC;
1564 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1565 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
1566 }
1567 /* order matters! */
1568 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1569 rdev->pm.power_state[state_index].type =
1570 POWER_STATE_TYPE_POWERSAVE;
1571 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1572 rdev->pm.power_state[state_index].type =
1573 POWER_STATE_TYPE_BATTERY;
1574 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1575 rdev->pm.power_state[state_index].type =
1576 POWER_STATE_TYPE_BATTERY;
1577 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1578 rdev->pm.power_state[state_index].type =
1579 POWER_STATE_TYPE_BALANCED;
1580 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN)
1581 rdev->pm.power_state[state_index].type =
1582 POWER_STATE_TYPE_PERFORMANCE;
1583 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1584 rdev->pm.power_state[state_index].type =
1585 POWER_STATE_TYPE_DEFAULT;
1586 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1587 rdev->pm.power_state[state_index].default_clock_mode =
1588 &rdev->pm.power_state[state_index].clock_info[0];
1589 }
1590 state_index++;
1591 break;
1592 case 2:
1593 rdev->pm.power_state[state_index].num_clock_modes = 1;
1594 rdev->pm.power_state[state_index].clock_info[0].mclk =
1595 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
1596 rdev->pm.power_state[state_index].clock_info[0].sclk =
1597 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
1598 /* skip invalid modes */
1599 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1600 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1601 continue;
1602 /* skip overclock modes for now */
1603 if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
1604 rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1605 (rdev->pm.power_state[state_index].clock_info[0].sclk >
1606 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1607 continue;
1608 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1609 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
1610 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
1611 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
1612 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1613 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1614 VOLTAGE_GPIO;
1615 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1616 radeon_lookup_gpio(rdev,
1617 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
1618 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1619 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1620 true;
1621 else
1622 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1623 false;
1624 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1625 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1626 VOLTAGE_VDDC;
1627 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1628 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
1629 }
1630 /* order matters! */
1631 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1632 rdev->pm.power_state[state_index].type =
1633 POWER_STATE_TYPE_POWERSAVE;
1634 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1635 rdev->pm.power_state[state_index].type =
1636 POWER_STATE_TYPE_BATTERY;
1637 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1638 rdev->pm.power_state[state_index].type =
1639 POWER_STATE_TYPE_BATTERY;
1640 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1641 rdev->pm.power_state[state_index].type =
1642 POWER_STATE_TYPE_BALANCED;
1643 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN)
1644 rdev->pm.power_state[state_index].type =
1645 POWER_STATE_TYPE_PERFORMANCE;
1646 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1647 rdev->pm.power_state[state_index].type =
1648 POWER_STATE_TYPE_BALANCED;
1649 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1650 rdev->pm.power_state[state_index].type =
1651 POWER_STATE_TYPE_DEFAULT;
1652 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1653 rdev->pm.power_state[state_index].default_clock_mode =
1654 &rdev->pm.power_state[state_index].clock_info[0];
1655 }
1656 state_index++;
1657 break;
1658 case 3:
1659 rdev->pm.power_state[state_index].num_clock_modes = 1;
1660 rdev->pm.power_state[state_index].clock_info[0].mclk =
1661 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
1662 rdev->pm.power_state[state_index].clock_info[0].sclk =
1663 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
1664 /* skip invalid modes */
1665 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
1666 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
1667 continue;
1668 /* skip overclock modes for now */
1669 if ((rdev->pm.power_state[state_index].clock_info[0].mclk >
1670 rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1671 (rdev->pm.power_state[state_index].clock_info[0].sclk >
1672 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1673 continue;
1674 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1675 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
1676 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
1677 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
1678 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
1679 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1680 VOLTAGE_GPIO;
1681 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
1682 radeon_lookup_gpio(rdev,
1683 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
1684 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
1685 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1686 true;
1687 else
1688 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
1689 false;
1690 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
1691 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
1692 VOLTAGE_VDDC;
1693 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
1694 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
1695 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
1696 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
1697 true;
1698 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
1699 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
1700 }
1701 }
1702 /* order matters! */
1703 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
1704 rdev->pm.power_state[state_index].type =
1705 POWER_STATE_TYPE_POWERSAVE;
1706 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
1707 rdev->pm.power_state[state_index].type =
1708 POWER_STATE_TYPE_BATTERY;
1709 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
1710 rdev->pm.power_state[state_index].type =
1711 POWER_STATE_TYPE_BATTERY;
1712 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
1713 rdev->pm.power_state[state_index].type =
1714 POWER_STATE_TYPE_BALANCED;
1715 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN)
1716 rdev->pm.power_state[state_index].type =
1717 POWER_STATE_TYPE_PERFORMANCE;
1718 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
1719 rdev->pm.power_state[state_index].type =
1720 POWER_STATE_TYPE_BALANCED;
1721 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
1722 rdev->pm.power_state[state_index].type =
1723 POWER_STATE_TYPE_DEFAULT;
1724 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1725 rdev->pm.power_state[state_index].default_clock_mode =
1726 &rdev->pm.power_state[state_index].clock_info[0];
1727 }
1728 state_index++;
1729 break;
1730 }
1731 }
1732 } else if (frev == 4) {
1733 /* add the i2c bus for thermal/fan chip */
1734 /* no support for internal controller yet */
1735 if (power_info->info_4.sThermalController.ucType > 0) {
1736 if ((power_info->info_4.sThermalController.ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) ||
1737 (power_info->info_4.sThermalController.ucType == ATOM_PP_THERMALCONTROLLER_RV770)) {
1738 DRM_INFO("Internal thermal controller %s fan control\n",
1739 (power_info->info_4.sThermalController.ucFanParameters &
1740 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1741 } else {
1742 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
1743 pp_lib_thermal_controller_names[power_info->info_4.sThermalController.ucType],
1744 power_info->info_4.sThermalController.ucI2cAddress >> 1,
1745 (power_info->info_4.sThermalController.ucFanParameters &
1746 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
1747 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info_4.sThermalController.ucI2cLine);
1748 rdev->pm.i2c_bus = radeon_i2c_create(rdev->ddev, &i2c_bus, "Thermal");
1749 }
1750 }
1751 for (i = 0; i < power_info->info_4.ucNumStates; i++) {
1752 mode_index = 0;
1753 power_state = (struct _ATOM_PPLIB_STATE *)
1754 (mode_info->atom_context->bios +
1755 data_offset +
1756 le16_to_cpu(power_info->info_4.usStateArrayOffset) +
1757 i * power_info->info_4.ucStateEntrySize);
1758 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
1759 (mode_info->atom_context->bios +
1760 data_offset +
1761 le16_to_cpu(power_info->info_4.usNonClockInfoArrayOffset) +
1762 (power_state->ucNonClockStateIndex *
1763 power_info->info_4.ucNonClockSize));
1764 for (j = 0; j < (power_info->info_4.ucStateEntrySize - 1); j++) {
1765 if (rdev->flags & RADEON_IS_IGP) {
1766 struct _ATOM_PPLIB_RS780_CLOCK_INFO *clock_info =
1767 (struct _ATOM_PPLIB_RS780_CLOCK_INFO *)
1768 (mode_info->atom_context->bios +
1769 data_offset +
1770 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1771 (power_state->ucClockStateIndices[j] *
1772 power_info->info_4.ucClockInfoSize));
1773 sclk = le16_to_cpu(clock_info->usLowEngineClockLow);
1774 sclk |= clock_info->ucLowEngineClockHigh << 16;
1775 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1776 /* skip invalid modes */
1777 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
1778 continue;
1779 /* skip overclock modes for now */
1780 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk >
1781 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN)
1782 continue;
1783 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1784 VOLTAGE_SW;
1785 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
1786 clock_info->usVDDC;
1787 mode_index++;
1788 } else {
1789 struct _ATOM_PPLIB_R600_CLOCK_INFO *clock_info =
1790 (struct _ATOM_PPLIB_R600_CLOCK_INFO *)
1791 (mode_info->atom_context->bios +
1792 data_offset +
1793 le16_to_cpu(power_info->info_4.usClockInfoArrayOffset) +
1794 (power_state->ucClockStateIndices[j] *
1795 power_info->info_4.ucClockInfoSize));
1796 sclk = le16_to_cpu(clock_info->usEngineClockLow);
1797 sclk |= clock_info->ucEngineClockHigh << 16;
1798 mclk = le16_to_cpu(clock_info->usMemoryClockLow);
1799 mclk |= clock_info->ucMemoryClockHigh << 16;
1800 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
1801 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
1802 /* skip invalid modes */
1803 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
1804 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
1805 continue;
1806 /* skip overclock modes for now */
1807 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk >
1808 rdev->clock.default_mclk + RADEON_MODE_OVERCLOCK_MARGIN) ||
1809 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk >
1810 rdev->clock.default_sclk + RADEON_MODE_OVERCLOCK_MARGIN))
1811 continue;
1812 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
1813 VOLTAGE_SW;
1814 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
1815 clock_info->usVDDC;
1816 mode_index++;
1817 }
1818 }
1819 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
1820 if (mode_index) {
1821 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
1822 misc2 = le16_to_cpu(non_clock_info->usClassification);
1823 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes =
1824 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
1825 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
1826 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
1827 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
1828 rdev->pm.power_state[state_index].type =
1829 POWER_STATE_TYPE_BATTERY;
1830 break;
1831 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
1832 rdev->pm.power_state[state_index].type =
1833 POWER_STATE_TYPE_BALANCED;
1834 break;
1835 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
1836 rdev->pm.power_state[state_index].type =
1837 POWER_STATE_TYPE_PERFORMANCE;
1838 break;
1839 }
1840 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
1841 rdev->pm.power_state[state_index].type =
1842 POWER_STATE_TYPE_DEFAULT;
1843 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1844 rdev->pm.power_state[state_index].default_clock_mode =
1845 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
1846 }
1847 state_index++;
1848 }
1849 }
1850 }
1851 } else {
1852 /* XXX figure out some good default low power mode for cards w/out power tables */
1853 }
1854
1855 if (rdev->pm.default_power_state == NULL) {
1856 /* add the default mode */
1857 rdev->pm.power_state[state_index].type =
1858 POWER_STATE_TYPE_DEFAULT;
1859 rdev->pm.power_state[state_index].num_clock_modes = 1;
1860 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
1861 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
1862 rdev->pm.power_state[state_index].default_clock_mode =
1863 &rdev->pm.power_state[state_index].clock_info[0];
1864 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
1865 if (rdev->asic->get_pcie_lanes)
1866 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = radeon_get_pcie_lanes(rdev);
1867 else
1868 rdev->pm.power_state[state_index].non_clock_info.pcie_lanes = 16;
1869 rdev->pm.default_power_state = &rdev->pm.power_state[state_index];
1870 state_index++;
1871 }
1872 rdev->pm.num_power_states = state_index;
1873
1874 rdev->pm.current_power_state = rdev->pm.default_power_state;
1875 rdev->pm.current_clock_mode =
1876 rdev->pm.default_power_state->default_clock_mode;
1877 }
1878
1879 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
1880 {
1881 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
1882 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
1883
1884 args.ucEnable = enable;
1885
1886 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1887 }
1888
1889 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
1890 {
1891 GET_ENGINE_CLOCK_PS_ALLOCATION args;
1892 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
1893
1894 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1895 return args.ulReturnEngineClock;
1896 }
1897
1898 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
1899 {
1900 GET_MEMORY_CLOCK_PS_ALLOCATION args;
1901 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
1902
1903 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1904 return args.ulReturnMemoryClock;
1905 }
1906
1907 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
1908 uint32_t eng_clock)
1909 {
1910 SET_ENGINE_CLOCK_PS_ALLOCATION args;
1911 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
1912
1913 args.ulTargetEngineClock = eng_clock; /* 10 khz */
1914
1915 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1916 }
1917
1918 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
1919 uint32_t mem_clock)
1920 {
1921 SET_MEMORY_CLOCK_PS_ALLOCATION args;
1922 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
1923
1924 if (rdev->flags & RADEON_IS_IGP)
1925 return;
1926
1927 args.ulTargetMemoryClock = mem_clock; /* 10 khz */
1928
1929 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1930 }
1931
1932 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
1933 {
1934 struct radeon_device *rdev = dev->dev_private;
1935 uint32_t bios_2_scratch, bios_6_scratch;
1936
1937 if (rdev->family >= CHIP_R600) {
1938 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
1939 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1940 } else {
1941 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
1942 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1943 }
1944
1945 /* let the bios control the backlight */
1946 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
1947
1948 /* tell the bios not to handle mode switching */
1949 bios_6_scratch |= (ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH | ATOM_S6_ACC_MODE);
1950
1951 if (rdev->family >= CHIP_R600) {
1952 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
1953 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
1954 } else {
1955 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
1956 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
1957 }
1958
1959 }
1960
1961 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
1962 {
1963 uint32_t scratch_reg;
1964 int i;
1965
1966 if (rdev->family >= CHIP_R600)
1967 scratch_reg = R600_BIOS_0_SCRATCH;
1968 else
1969 scratch_reg = RADEON_BIOS_0_SCRATCH;
1970
1971 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1972 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
1973 }
1974
1975 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
1976 {
1977 uint32_t scratch_reg;
1978 int i;
1979
1980 if (rdev->family >= CHIP_R600)
1981 scratch_reg = R600_BIOS_0_SCRATCH;
1982 else
1983 scratch_reg = RADEON_BIOS_0_SCRATCH;
1984
1985 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
1986 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
1987 }
1988
1989 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
1990 {
1991 struct drm_device *dev = encoder->dev;
1992 struct radeon_device *rdev = dev->dev_private;
1993 uint32_t bios_6_scratch;
1994
1995 if (rdev->family >= CHIP_R600)
1996 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
1997 else
1998 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
1999
2000 if (lock)
2001 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
2002 else
2003 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
2004
2005 if (rdev->family >= CHIP_R600)
2006 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2007 else
2008 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2009 }
2010
2011 /* at some point we may want to break this out into individual functions */
2012 void
2013 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
2014 struct drm_encoder *encoder,
2015 bool connected)
2016 {
2017 struct drm_device *dev = connector->dev;
2018 struct radeon_device *rdev = dev->dev_private;
2019 struct radeon_connector *radeon_connector =
2020 to_radeon_connector(connector);
2021 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2022 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
2023
2024 if (rdev->family >= CHIP_R600) {
2025 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2026 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2027 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
2028 } else {
2029 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2030 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2031 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
2032 }
2033
2034 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
2035 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
2036 if (connected) {
2037 DRM_DEBUG("TV1 connected\n");
2038 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
2039 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
2040 } else {
2041 DRM_DEBUG("TV1 disconnected\n");
2042 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
2043 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
2044 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
2045 }
2046 }
2047 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
2048 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
2049 if (connected) {
2050 DRM_DEBUG("CV connected\n");
2051 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
2052 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
2053 } else {
2054 DRM_DEBUG("CV disconnected\n");
2055 bios_0_scratch &= ~ATOM_S0_CV_MASK;
2056 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
2057 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
2058 }
2059 }
2060 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
2061 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
2062 if (connected) {
2063 DRM_DEBUG("LCD1 connected\n");
2064 bios_0_scratch |= ATOM_S0_LCD1;
2065 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
2066 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
2067 } else {
2068 DRM_DEBUG("LCD1 disconnected\n");
2069 bios_0_scratch &= ~ATOM_S0_LCD1;
2070 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
2071 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
2072 }
2073 }
2074 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
2075 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
2076 if (connected) {
2077 DRM_DEBUG("CRT1 connected\n");
2078 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
2079 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
2080 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
2081 } else {
2082 DRM_DEBUG("CRT1 disconnected\n");
2083 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
2084 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
2085 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
2086 }
2087 }
2088 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
2089 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
2090 if (connected) {
2091 DRM_DEBUG("CRT2 connected\n");
2092 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
2093 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
2094 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
2095 } else {
2096 DRM_DEBUG("CRT2 disconnected\n");
2097 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
2098 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
2099 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
2100 }
2101 }
2102 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
2103 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
2104 if (connected) {
2105 DRM_DEBUG("DFP1 connected\n");
2106 bios_0_scratch |= ATOM_S0_DFP1;
2107 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
2108 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
2109 } else {
2110 DRM_DEBUG("DFP1 disconnected\n");
2111 bios_0_scratch &= ~ATOM_S0_DFP1;
2112 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
2113 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
2114 }
2115 }
2116 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
2117 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
2118 if (connected) {
2119 DRM_DEBUG("DFP2 connected\n");
2120 bios_0_scratch |= ATOM_S0_DFP2;
2121 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
2122 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
2123 } else {
2124 DRM_DEBUG("DFP2 disconnected\n");
2125 bios_0_scratch &= ~ATOM_S0_DFP2;
2126 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
2127 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
2128 }
2129 }
2130 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
2131 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
2132 if (connected) {
2133 DRM_DEBUG("DFP3 connected\n");
2134 bios_0_scratch |= ATOM_S0_DFP3;
2135 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
2136 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
2137 } else {
2138 DRM_DEBUG("DFP3 disconnected\n");
2139 bios_0_scratch &= ~ATOM_S0_DFP3;
2140 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
2141 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
2142 }
2143 }
2144 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
2145 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
2146 if (connected) {
2147 DRM_DEBUG("DFP4 connected\n");
2148 bios_0_scratch |= ATOM_S0_DFP4;
2149 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
2150 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
2151 } else {
2152 DRM_DEBUG("DFP4 disconnected\n");
2153 bios_0_scratch &= ~ATOM_S0_DFP4;
2154 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
2155 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
2156 }
2157 }
2158 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
2159 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
2160 if (connected) {
2161 DRM_DEBUG("DFP5 connected\n");
2162 bios_0_scratch |= ATOM_S0_DFP5;
2163 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
2164 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
2165 } else {
2166 DRM_DEBUG("DFP5 disconnected\n");
2167 bios_0_scratch &= ~ATOM_S0_DFP5;
2168 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
2169 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
2170 }
2171 }
2172
2173 if (rdev->family >= CHIP_R600) {
2174 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
2175 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2176 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
2177 } else {
2178 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
2179 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2180 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
2181 }
2182 }
2183
2184 void
2185 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
2186 {
2187 struct drm_device *dev = encoder->dev;
2188 struct radeon_device *rdev = dev->dev_private;
2189 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2190 uint32_t bios_3_scratch;
2191
2192 if (rdev->family >= CHIP_R600)
2193 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
2194 else
2195 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
2196
2197 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2198 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
2199 bios_3_scratch |= (crtc << 18);
2200 }
2201 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2202 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
2203 bios_3_scratch |= (crtc << 24);
2204 }
2205 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2206 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
2207 bios_3_scratch |= (crtc << 16);
2208 }
2209 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2210 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
2211 bios_3_scratch |= (crtc << 20);
2212 }
2213 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2214 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
2215 bios_3_scratch |= (crtc << 17);
2216 }
2217 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2218 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
2219 bios_3_scratch |= (crtc << 19);
2220 }
2221 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2222 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
2223 bios_3_scratch |= (crtc << 23);
2224 }
2225 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2226 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
2227 bios_3_scratch |= (crtc << 25);
2228 }
2229
2230 if (rdev->family >= CHIP_R600)
2231 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
2232 else
2233 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
2234 }
2235
2236 void
2237 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
2238 {
2239 struct drm_device *dev = encoder->dev;
2240 struct radeon_device *rdev = dev->dev_private;
2241 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2242 uint32_t bios_2_scratch;
2243
2244 if (rdev->family >= CHIP_R600)
2245 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
2246 else
2247 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
2248
2249 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
2250 if (on)
2251 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
2252 else
2253 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
2254 }
2255 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
2256 if (on)
2257 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
2258 else
2259 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
2260 }
2261 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2262 if (on)
2263 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
2264 else
2265 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
2266 }
2267 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2268 if (on)
2269 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
2270 else
2271 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
2272 }
2273 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2274 if (on)
2275 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
2276 else
2277 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
2278 }
2279 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
2280 if (on)
2281 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
2282 else
2283 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
2284 }
2285 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
2286 if (on)
2287 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
2288 else
2289 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
2290 }
2291 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
2292 if (on)
2293 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
2294 else
2295 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
2296 }
2297 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
2298 if (on)
2299 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
2300 else
2301 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
2302 }
2303 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
2304 if (on)
2305 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
2306 else
2307 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
2308 }
2309
2310 if (rdev->family >= CHIP_R600)
2311 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
2312 else
2313 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
2314 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree