arch/powerpc/include/asm/ptrace.h

   1 #ifndef _ASM_POWERPC_PTRACE_H
   2 #define _ASM_POWERPC_PTRACE_H
   3
   4 /*
   5  * Copyright (C) 2001 PPC64 Team, IBM Corp
   6  *
   7  * This struct defines the way the registers are stored on the
   8  * kernel stack during a system call or other kernel entry.
   9  *
  10  * this should only contain volatile regs
  11  * since we can keep non-volatile in the thread_struct
  12  * should set this up when only volatiles are saved
  13  * by intr code.
  14  *
  15  * Since this is going on the stack, *CARE MUST BE TAKEN* to insure
  16  * that the overall structure is a multiple of 16 bytes in length.
  17  *
  18  * Note that the offsets of the fields in this struct correspond with
  19  * the PT_* values below.  This simplifies arch/powerpc/kernel/ptrace.c.
  20  *
  21  * This program is free software; you can redistribute it and/or
  22  * modify it under the terms of the GNU General Public License
  23  * as published by the Free Software Foundation; either version
  24  * 2 of the License, or (at your option) any later version.
  25  */
  26
  27 #ifdef __KERNEL__
  28 #include <linux/types.h>
  29 #else
  30 #include <stdint.h>
  31 #endif
  32
  33 #ifndef __ASSEMBLY__
  34
  35 struct pt_regs {
  36         unsigned long gpr[32];
  37         unsigned long nip;
  38         unsigned long msr;
  39         unsigned long orig_gpr3;        /* Used for restarting system calls */
  40         unsigned long ctr;
  41         unsigned long link;
  42         unsigned long xer;
  43         unsigned long ccr;
  44 #ifdef __powerpc64__
  45         unsigned long softe;            /* Soft enabled/disabled */
  46 #else
  47         unsigned long mq;               /* 601 only (not used at present) */
  48                                         /* Used on APUS to hold IPL value. */
  49 #endif
  50         unsigned long trap;             /* Reason for being here */
  51         /* N.B. for critical exceptions on 4xx, the dar and dsisr
  52            fields are overloaded to hold srr0 and srr1. */
  53         unsigned long dar;              /* Fault registers */
  54         unsigned long dsisr;            /* on 4xx/Book-E used for ESR */
  55         unsigned long result;           /* Result of a system call */
  56 };
  57
  58 #endif /* __ASSEMBLY__ */
  59
  60 #ifdef __KERNEL__
  61
  62 #ifdef __powerpc64__
  63
  64 #define STACK_FRAME_OVERHEAD    112     /* size of minimum stack frame */
  65 #define STACK_FRAME_LR_SAVE     2       /* Location of LR in stack frame */
  66 #define STACK_FRAME_REGS_MARKER ASM_CONST(0x7265677368657265)
  67 #define STACK_INT_FRAME_SIZE    (sizeof(struct pt_regs) + \
  68                                         STACK_FRAME_OVERHEAD + 288)
  69 #define STACK_FRAME_MARKER      12
  70
  71 /* Size of dummy stack frame allocated when calling signal handler. */
  72 #define __SIGNAL_FRAMESIZE      128
  73 #define __SIGNAL_FRAMESIZE32    64
  74
  75 #else /* __powerpc64__ */
  76
  77 #define STACK_FRAME_OVERHEAD    16      /* size of minimum stack frame */
  78 #define STACK_FRAME_LR_SAVE     1       /* Location of LR in stack frame */
  79 #define STACK_FRAME_REGS_MARKER ASM_CONST(0x72656773)
  80 #define STACK_INT_FRAME_SIZE    (sizeof(struct pt_regs) + STACK_FRAME_OVERHEAD)
  81 #define STACK_FRAME_MARKER      2
  82
  83 /* Size of stack frame allocated when calling signal handler. */
  84 #define __SIGNAL_FRAMESIZE      64
  85
  86 #endif /* __powerpc64__ */
  87
  88 #ifndef __ASSEMBLY__
  89
  90 #define instruction_pointer(regs) ((regs)->nip)
  91 #define user_stack_pointer(regs) ((regs)->gpr[1])
  92 #define regs_return_value(regs) ((regs)->gpr[3])
  93
  94 #ifdef CONFIG_SMP
  95 extern unsigned long profile_pc(struct pt_regs *regs);
  96 #else
  97 #define profile_pc(regs) instruction_pointer(regs)
  98 #endif
  99
 100 #ifdef __powerpc64__
 101 #define user_mode(regs) ((((regs)->msr) >> MSR_PR_LG) & 0x1)
 102 #else
 103 #define user_mode(regs) (((regs)->msr & MSR_PR) != 0)
 104 #endif
 105
 106 #define force_successful_syscall_return()   \
 107         do { \
 108                 set_thread_flag(TIF_NOERROR); \
 109         } while(0)
 110
 111 struct task_struct;
 112 extern unsigned long ptrace_get_reg(struct task_struct *task, int regno);
 113 extern int ptrace_put_reg(struct task_struct *task, int regno,
 114                           unsigned long data);
 115
 116 /*
 117  * We use the least-significant bit of the trap field to indicate
 118  * whether we have saved the full set of registers, or only a
 119  * partial set.  A 1 there means the partial set.
 120  * On 4xx we use the next bit to indicate whether the exception
 121  * is a critical exception (1 means it is).
 122  */
 123 #define FULL_REGS(regs)         (((regs)->trap & 1) == 0)
 124 #ifndef __powerpc64__
 125 #define IS_CRITICAL_EXC(regs)   (((regs)->trap & 2) != 0)
 126 #define IS_MCHECK_EXC(regs)     (((regs)->trap & 4) != 0)
 127 #define IS_DEBUG_EXC(regs)      (((regs)->trap & 8) != 0)
 128 #endif /* ! __powerpc64__ */
 129 #define TRAP(regs)              ((regs)->trap & ~0xF)
 130 #ifdef __powerpc64__
 131 #define CHECK_FULL_REGS(regs)   BUG_ON(regs->trap & 1)
 132 #else
 133 #define CHECK_FULL_REGS(regs)                                                 \
 134 do {                                                                          \
 135         if ((regs)->trap & 1)                                                 \
 136                 printk(KERN_CRIT "%s: partial register set\n", __func__); \
 137 } while (0)
 138 #endif /* __powerpc64__ */
 139
 140 #define arch_has_single_step()  (1)
 141 #define arch_has_block_step()   (!cpu_has_feature(CPU_FTR_601))
 142 #define ARCH_HAS_USER_SINGLE_STEP_INFO
 143
 144 #endif /* __ASSEMBLY__ */
 145
 146 #endif /* __KERNEL__ */
 147
 148 /*
 149  * Offsets used by 'ptrace' system call interface.
 150  * These can't be changed without breaking binary compatibility
 151  * with MkLinux, etc.
 152  */
 153 #define PT_R0   0
 154 #define PT_R1   1
 155 #define PT_R2   2
 156 #define PT_R3   3
 157 #define PT_R4   4
 158 #define PT_R5   5
 159 #define PT_R6   6
 160 #define PT_R7   7
 161 #define PT_R8   8
 162 #define PT_R9   9
 163 #define PT_R10  10
 164 #define PT_R11  11
 165 #define PT_R12  12
 166 #define PT_R13  13
 167 #define PT_R14  14
 168 #define PT_R15  15
 169 #define PT_R16  16
 170 #define PT_R17  17
 171 #define PT_R18  18
 172 #define PT_R19  19
 173 #define PT_R20  20
 174 #define PT_R21  21
 175 #define PT_R22  22
 176 #define PT_R23  23
 177 #define PT_R24  24
 178 #define PT_R25  25
 179 #define PT_R26  26
 180 #define PT_R27  27
 181 #define PT_R28  28
 182 #define PT_R29  29
 183 #define PT_R30  30
 184 #define PT_R31  31
 185
 186 #define PT_NIP  32
 187 #define PT_MSR  33
 188 #define PT_ORIG_R3 34
 189 #define PT_CTR  35
 190 #define PT_LNK  36
 191 #define PT_XER  37
 192 #define PT_CCR  38
 193 #ifndef __powerpc64__
 194 #define PT_MQ   39
 195 #else
 196 #define PT_SOFTE 39
 197 #endif
 198 #define PT_TRAP 40
 199 #define PT_DAR  41
 200 #define PT_DSISR 42
 201 #define PT_RESULT 43
 202 #define PT_REGS_COUNT 44
 203
 204 #define PT_FPR0 48      /* each FP reg occupies 2 slots in this space */
 205
 206 #ifndef __powerpc64__
 207
 208 #define PT_FPR31 (PT_FPR0 + 2*31)
 209 #define PT_FPSCR (PT_FPR0 + 2*32 + 1)
 210
 211 #else /* __powerpc64__ */
 212
 213 #define PT_FPSCR (PT_FPR0 + 32) /* each FP reg occupies 1 slot in 64-bit space */
 214
 215 #ifdef __KERNEL__
 216 #define PT_FPSCR32 (PT_FPR0 + 2*32 + 1) /* each FP reg occupies 2 32-bit userspace slots */
 217 #endif
 218
 219 #define PT_VR0 82       /* each Vector reg occupies 2 slots in 64-bit */
 220 #define PT_VSCR (PT_VR0 + 32*2 + 1)
 221 #define PT_VRSAVE (PT_VR0 + 33*2)
 222
 223 #ifdef __KERNEL__
 224 #define PT_VR0_32 164   /* each Vector reg occupies 4 slots in 32-bit */
 225 #define PT_VSCR_32 (PT_VR0 + 32*4 + 3)
 226 #define PT_VRSAVE_32 (PT_VR0 + 33*4)
 227 #endif
 228
 229 /*
 230  * Only store first 32 VSRs here. The second 32 VSRs in VR0-31
 231  */
 232 #define PT_VSR0 150     /* each VSR reg occupies 2 slots in 64-bit */
 233 #define PT_VSR31 (PT_VSR0 + 2*31)
 234 #ifdef __KERNEL__
 235 #define PT_VSR0_32 300  /* each VSR reg occupies 4 slots in 32-bit */
 236 #endif
 237 #endif /* __powerpc64__ */
 238
 239 /*
 240  * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go.
 241  * The transfer totals 34 quadword.  Quadwords 0-31 contain the
 242  * corresponding vector registers.  Quadword 32 contains the vscr as the
 243  * last word (offset 12) within that quadword.  Quadword 33 contains the
 244  * vrsave as the first word (offset 0) within the quadword.
 245  *
 246  * This definition of the VMX state is compatible with the current PPC32
 247  * ptrace interface.  This allows signal handling and ptrace to use the same
 248  * structures.  This also simplifies the implementation of a bi-arch
 249  * (combined (32- and 64-bit) gdb.
 250  */
 251 #define PTRACE_GETVRREGS        18
 252 #define PTRACE_SETVRREGS        19
 253
 254 /* Get/set all the upper 32-bits of the SPE registers, accumulator, and
 255  * spefscr, in one go */
 256 #define PTRACE_GETEVRREGS       20
 257 #define PTRACE_SETEVRREGS       21
 258
 259 /* Get the first 32 128bit VSX registers */
 260 #define PTRACE_GETVSRREGS       27
 261 #define PTRACE_SETVSRREGS       28
 262
 263 /*
 264  * Get or set a debug register. The first 16 are DABR registers and the
 265  * second 16 are IABR registers.
 266  */
 267 #define PTRACE_GET_DEBUGREG     25
 268 #define PTRACE_SET_DEBUGREG     26
 269
 270 /* (new) PTRACE requests using the same numbers as x86 and the same
 271  * argument ordering. Additionally, they support more registers too
 272  */
 273 #define PTRACE_GETREGS            12
 274 #define PTRACE_SETREGS            13
 275 #define PTRACE_GETFPREGS          14
 276 #define PTRACE_SETFPREGS          15
 277 #define PTRACE_GETREGS64          22
 278 #define PTRACE_SETREGS64          23
 279
 280 /* (old) PTRACE requests with inverted arguments */
 281 #define PPC_PTRACE_GETREGS      0x99    /* Get GPRs 0 - 31 */
 282 #define PPC_PTRACE_SETREGS      0x98    /* Set GPRs 0 - 31 */
 283 #define PPC_PTRACE_GETFPREGS    0x97    /* Get FPRs 0 - 31 */
 284 #define PPC_PTRACE_SETFPREGS    0x96    /* Set FPRs 0 - 31 */
 285
 286 /* Calls to trace a 64bit program from a 32bit program */
 287 #define PPC_PTRACE_PEEKTEXT_3264 0x95
 288 #define PPC_PTRACE_PEEKDATA_3264 0x94
 289 #define PPC_PTRACE_POKETEXT_3264 0x93
 290 #define PPC_PTRACE_POKEDATA_3264 0x92
 291 #define PPC_PTRACE_PEEKUSR_3264  0x91
 292 #define PPC_PTRACE_POKEUSR_3264  0x90
 293
 294 #define PTRACE_SINGLEBLOCK      0x100   /* resume execution until next branch */
 295
 296 #define PPC_PTRACE_GETHWDBGINFO 0x89
 297 #define PPC_PTRACE_SETHWDEBUG   0x88
 298 #define PPC_PTRACE_DELHWDEBUG   0x87
 299
 300 #ifndef __ASSEMBLY__
 301
 302 struct ppc_debug_info {
 303         uint32_t version;               /* Only version 1 exists to date */
 304         uint32_t num_instruction_bps;
 305         uint32_t num_data_bps;
 306         uint32_t num_condition_regs;
 307         uint32_t data_bp_alignment;
 308         uint32_t sizeof_condition;      /* size of the DVC register */
 309         uint64_t features;
 310 };
 311
 312 #endif /* __ASSEMBLY__ */
 313
 314 /*
 315  * features will have bits indication whether there is support for:
 316  */
 317 #define PPC_DEBUG_FEATURE_INSN_BP_RANGE         0x0000000000000001
 318 #define PPC_DEBUG_FEATURE_INSN_BP_MASK          0x0000000000000002
 319 #define PPC_DEBUG_FEATURE_DATA_BP_RANGE         0x0000000000000004
 320 #define PPC_DEBUG_FEATURE_DATA_BP_MASK          0x0000000000000008
 321
 322 #ifndef __ASSEMBLY__
 323
 324 struct ppc_hw_breakpoint {
 325         uint32_t version;               /* currently, version must be 1 */
 326         uint32_t trigger_type;          /* only some combinations allowed */
 327         uint32_t addr_mode;             /* address match mode */
 328         uint32_t condition_mode;        /* break/watchpoint condition flags */
 329         uint64_t addr;                  /* break/watchpoint address */
 330         uint64_t addr2;                 /* range end or mask */
 331         uint64_t condition_value;       /* contents of the DVC register */
 332 };
 333
 334 #endif /* __ASSEMBLY__ */
 335
 336 /*
 337  * Trigger Type
 338  */
 339 #define PPC_BREAKPOINT_TRIGGER_EXECUTE  0x00000001
 340 #define PPC_BREAKPOINT_TRIGGER_READ     0x00000002
 341 #define PPC_BREAKPOINT_TRIGGER_WRITE    0x00000004
 342 #define PPC_BREAKPOINT_TRIGGER_RW       \
 343         (PPC_BREAKPOINT_TRIGGER_READ | PPC_BREAKPOINT_TRIGGER_WRITE)
 344
 345 /*
 346  * Address Mode
 347  */
 348 #define PPC_BREAKPOINT_MODE_EXACT               0x00000000
 349 #define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE     0x00000001
 350 #define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE     0x00000002
 351 #define PPC_BREAKPOINT_MODE_MASK                0x00000003
 352
 353 /*
 354  * Condition Mode
 355  */
 356 #define PPC_BREAKPOINT_CONDITION_MODE   0x00000003
 357 #define PPC_BREAKPOINT_CONDITION_NONE   0x00000000
 358 #define PPC_BREAKPOINT_CONDITION_AND    0x00000001
 359 #define PPC_BREAKPOINT_CONDITION_EXACT  PPC_BREAKPOINT_CONDITION_AND
 360 #define PPC_BREAKPOINT_CONDITION_OR     0x00000002
 361 #define PPC_BREAKPOINT_CONDITION_AND_OR 0x00000003
 362 #define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000
 363 #define PPC_BREAKPOINT_CONDITION_BE_SHIFT       16
 364 #define PPC_BREAKPOINT_CONDITION_BE(n)  \
 365         (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT))
 366
 367 #endif /* _ASM_POWERPC_PTRACE_H */