arch/arm/plat-iop/time.c

   1 /*
   2  * arch/arm/plat-iop/time.c
   3  *
   4  * Timer code for IOP32x and IOP33x based systems
   5  *
   6  * Author: Deepak Saxena <dsaxena@mvista.com>
   7  *
   8  * Copyright 2002-2003 MontaVista Software Inc.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License as published by the
  12  * Free Software Foundation; either version 2 of the License, or (at your
  13  * option) any later version.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/time.h>
  19 #include <linux/init.h>
  20 #include <linux/timex.h>
  21 #include <linux/io.h>
  22 #include <linux/clocksource.h>
  23 #include <linux/clockchips.h>
  24 #include <mach/hardware.h>
  25 #include <asm/irq.h>
  26 #include <asm/uaccess.h>
  27 #include <asm/mach/irq.h>
  28 #include <asm/mach/time.h>
  29 #include <mach/time.h>
  30
  31 /*
  32  * IOP clocksource (free-running timer 1).
  33  */
  34 static cycle_t iop_clocksource_read(struct clocksource *unused)
  35 {
  36         return 0xffffffffu - read_tcr1();
  37 }
  38
  39 static struct clocksource iop_clocksource = {
  40         .name           = "iop_timer1",
  41         .rating         = 300,
  42         .read           = iop_clocksource_read,
  43         .mask           = CLOCKSOURCE_MASK(32),
  44         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
  45 };
  46
  47 static void __init iop_clocksource_set_hz(struct clocksource *cs, unsigned int hz)
  48 {
  49         u64 temp;
  50         u32 shift;
  51
  52         /* Find shift and mult values for hz. */
  53         shift = 32;
  54         do {
  55                 temp = (u64) NSEC_PER_SEC << shift;
  56                 do_div(temp, hz);
  57                 if ((temp >> 32) == 0)
  58                         break;
  59         } while (--shift != 0);
  60
  61         cs->shift = shift;
  62         cs->mult = (u32) temp;
  63
  64         printk(KERN_INFO "clocksource: %s uses shift %u mult %#x\n",
  65                cs->name, cs->shift, cs->mult);
  66 }
  67
  68 /*
  69  * IOP sched_clock() implementation via its clocksource.
  70  */
  71 unsigned long long sched_clock(void)
  72 {
  73         cycle_t cyc = iop_clocksource_read(NULL);
  74         struct clocksource *cs = &iop_clocksource;
  75
  76         return clocksource_cyc2ns(cyc, cs->mult, cs->shift);
  77 }
  78
  79 /*
  80  * IOP clockevents (interrupting timer 0).
  81  */
  82 static int iop_set_next_event(unsigned long delta,
  83                               struct clock_event_device *unused)
  84 {
  85         u32 tmr = IOP_TMR_PRIVILEGED | IOP_TMR_RATIO_1_1;
  86
  87         BUG_ON(delta == 0);
  88         write_tmr0(tmr & ~(IOP_TMR_EN | IOP_TMR_RELOAD));
  89         write_tcr0(delta);
  90         write_tmr0((tmr & ~IOP_TMR_RELOAD) | IOP_TMR_EN);
  91
  92         return 0;
  93 }
  94
  95 static unsigned long ticks_per_jiffy;
  96
  97 static void iop_set_mode(enum clock_event_mode mode,
  98                          struct clock_event_device *unused)
  99 {
 100         u32 tmr = read_tmr0();
 101
 102         switch (mode) {
 103         case CLOCK_EVT_MODE_PERIODIC:
 104                 write_tmr0(tmr & ~IOP_TMR_EN);
 105                 write_tcr0(ticks_per_jiffy - 1);
 106                 tmr |= (IOP_TMR_RELOAD | IOP_TMR_EN);
 107                 break;
 108         case CLOCK_EVT_MODE_ONESHOT:
 109                 /* ->set_next_event sets period and enables timer */
 110                 tmr &= ~(IOP_TMR_RELOAD | IOP_TMR_EN);
 111                 break;
 112         case CLOCK_EVT_MODE_RESUME:
 113                 tmr |= IOP_TMR_EN;
 114                 break;
 115         case CLOCK_EVT_MODE_SHUTDOWN:
 116         case CLOCK_EVT_MODE_UNUSED:
 117         default:
 118                 tmr &= ~IOP_TMR_EN;
 119                 break;
 120         }
 121
 122         write_tmr0(tmr);
 123 }
 124
 125 static struct clock_event_device iop_clockevent = {
 126         .name           = "iop_timer0",
 127         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 128         .rating         = 300,
 129         .set_next_event = iop_set_next_event,
 130         .set_mode       = iop_set_mode,
 131 };
 132
 133 static void __init iop_clockevent_set_hz(struct clock_event_device *ce, unsigned int hz)
 134 {
 135         u64 temp;
 136         u32 shift;
 137
 138         /* Find shift and mult values for hz. */
 139         shift = 32;
 140         do {
 141                 temp = (u64) hz << shift;
 142                 do_div(temp, NSEC_PER_SEC);
 143                 if ((temp >> 32) == 0)
 144                         break;
 145         } while (--shift != 0);
 146
 147         ce->shift = shift;
 148         ce->mult = (u32) temp;
 149
 150         printk(KERN_INFO "clockevent: %s uses shift %u mult %#lx\n",
 151                ce->name, ce->shift, ce->mult);
 152 }
 153
 154 static irqreturn_t
 155 iop_timer_interrupt(int irq, void *dev_id)
 156 {
 157         struct clock_event_device *evt = dev_id;
 158
 159         write_tisr(1);
 160         evt->event_handler(evt);
 161         return IRQ_HANDLED;
 162 }
 163
 164 static struct irqaction iop_timer_irq = {
 165         .name           = "IOP Timer Tick",
 166         .handler        = iop_timer_interrupt,
 167         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 168         .dev_id         = &iop_clockevent,
 169 };
 170
 171 static unsigned long iop_tick_rate;
 172 unsigned long get_iop_tick_rate(void)
 173 {
 174         return iop_tick_rate;
 175 }
 176 EXPORT_SYMBOL(get_iop_tick_rate);
 177
 178 void __init iop_init_time(unsigned long tick_rate)
 179 {
 180         u32 timer_ctl;
 181
 182         ticks_per_jiffy = DIV_ROUND_CLOSEST(tick_rate, HZ);
 183         iop_tick_rate = tick_rate;
 184
 185         timer_ctl = IOP_TMR_EN | IOP_TMR_PRIVILEGED |
 186                         IOP_TMR_RELOAD | IOP_TMR_RATIO_1_1;
 187
 188         /*
 189          * Set up interrupting clockevent timer 0.
 190          */
 191         write_tmr0(timer_ctl & ~IOP_TMR_EN);
 192         setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq);
 193         iop_clockevent_set_hz(&iop_clockevent, tick_rate);
 194         iop_clockevent.max_delta_ns =
 195                 clockevent_delta2ns(0xfffffffe, &iop_clockevent);
 196         iop_clockevent.min_delta_ns =
 197                 clockevent_delta2ns(0xf, &iop_clockevent);
 198         iop_clockevent.cpumask = cpumask_of(0);
 199         clockevents_register_device(&iop_clockevent);
 200         write_trr0(ticks_per_jiffy - 1);
 201         write_tcr0(ticks_per_jiffy - 1);
 202         write_tmr0(timer_ctl);
 203
 204         /*
 205          * Set up free-running clocksource timer 1.
 206          */
 207         write_trr1(0xffffffff);
 208         write_tcr1(0xffffffff);
 209         write_tmr1(timer_ctl);
 210         iop_clocksource_set_hz(&iop_clocksource, tick_rate);
 211         clocksource_register(&iop_clocksource);
 212 }