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ath9k: port to cfg80211 rfkill
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / wireless / ath / ath9k / hw.c
blob34935a8ee59de1c443a1a3fc7a2cfe7ece086a92
1 /*
2 * Copyright (c) 2008-2009 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18 #include <asm/unaligned.h>
19
20 #include "ath9k.h"
21 #include "initvals.h"
22
23 static int btcoex_enable;
24 module_param(btcoex_enable, bool, 0);
25 MODULE_PARM_DESC(btcoex_enable, "Enable Bluetooth coexistence support");
26
27 #define ATH9K_CLOCK_RATE_CCK 22
28 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
29 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
30
31 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
32 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
33 enum ath9k_ht_macmode macmode);
34 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
35 struct ar5416_eeprom_def *pEepData,
36 u32 reg, u32 value);
37 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
38 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan);
39
40 /********************/
41 /* Helper Functions */
42 /********************/
43
44 static u32 ath9k_hw_mac_usec(struct ath_hw *ah, u32 clks)
45 {
46 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
47
48 if (!ah->curchan) /* should really check for CCK instead */
49 return clks / ATH9K_CLOCK_RATE_CCK;
50 if (conf->channel->band == IEEE80211_BAND_2GHZ)
51 return clks / ATH9K_CLOCK_RATE_2GHZ_OFDM;
52
53 return clks / ATH9K_CLOCK_RATE_5GHZ_OFDM;
54 }
55
56 static u32 ath9k_hw_mac_to_usec(struct ath_hw *ah, u32 clks)
57 {
58 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
59
60 if (conf_is_ht40(conf))
61 return ath9k_hw_mac_usec(ah, clks) / 2;
62 else
63 return ath9k_hw_mac_usec(ah, clks);
64 }
65
66 static u32 ath9k_hw_mac_clks(struct ath_hw *ah, u32 usecs)
67 {
68 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
69
70 if (!ah->curchan) /* should really check for CCK instead */
71 return usecs *ATH9K_CLOCK_RATE_CCK;
72 if (conf->channel->band == IEEE80211_BAND_2GHZ)
73 return usecs *ATH9K_CLOCK_RATE_2GHZ_OFDM;
74 return usecs *ATH9K_CLOCK_RATE_5GHZ_OFDM;
75 }
76
77 static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
78 {
79 struct ieee80211_conf *conf = &ah->ah_sc->hw->conf;
80
81 if (conf_is_ht40(conf))
82 return ath9k_hw_mac_clks(ah, usecs) * 2;
83 else
84 return ath9k_hw_mac_clks(ah, usecs);
85 }
86
87 /*
88 * Read and write, they both share the same lock. We do this to serialize
89 * reads and writes on Atheros 802.11n PCI devices only. This is required
90 * as the FIFO on these devices can only accept sanely 2 requests. After
91 * that the device goes bananas. Serializing the reads/writes prevents this
92 * from happening.
93 */
94
95 void ath9k_iowrite32(struct ath_hw *ah, u32 reg_offset, u32 val)
96 {
97 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
98 unsigned long flags;
99 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
100 iowrite32(val, ah->ah_sc->mem + reg_offset);
101 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
102 } else
103 iowrite32(val, ah->ah_sc->mem + reg_offset);
104 }
105
106 unsigned int ath9k_ioread32(struct ath_hw *ah, u32 reg_offset)
107 {
108 u32 val;
109 if (ah->config.serialize_regmode == SER_REG_MODE_ON) {
110 unsigned long flags;
111 spin_lock_irqsave(&ah->ah_sc->sc_serial_rw, flags);
112 val = ioread32(ah->ah_sc->mem + reg_offset);
113 spin_unlock_irqrestore(&ah->ah_sc->sc_serial_rw, flags);
114 } else
115 val = ioread32(ah->ah_sc->mem + reg_offset);
116 return val;
117 }
118
119 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
120 {
121 int i;
122
123 BUG_ON(timeout < AH_TIME_QUANTUM);
124
125 for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
126 if ((REG_READ(ah, reg) & mask) == val)
127 return true;
128
129 udelay(AH_TIME_QUANTUM);
130 }
131
132 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
133 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
134 timeout, reg, REG_READ(ah, reg), mask, val);
135
136 return false;
137 }
138
139 u32 ath9k_hw_reverse_bits(u32 val, u32 n)
140 {
141 u32 retval;
142 int i;
143
144 for (i = 0, retval = 0; i < n; i++) {
145 retval = (retval << 1) | (val & 1);
146 val >>= 1;
147 }
148 return retval;
149 }
150
151 bool ath9k_get_channel_edges(struct ath_hw *ah,
152 u16 flags, u16 *low,
153 u16 *high)
154 {
155 struct ath9k_hw_capabilities *pCap = &ah->caps;
156
157 if (flags & CHANNEL_5GHZ) {
158 *low = pCap->low_5ghz_chan;
159 *high = pCap->high_5ghz_chan;
160 return true;
161 }
162 if ((flags & CHANNEL_2GHZ)) {
163 *low = pCap->low_2ghz_chan;
164 *high = pCap->high_2ghz_chan;
165 return true;
166 }
167 return false;
168 }
169
170 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
171 const struct ath_rate_table *rates,
172 u32 frameLen, u16 rateix,
173 bool shortPreamble)
174 {
175 u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
176 u32 kbps;
177
178 kbps = rates->info[rateix].ratekbps;
179
180 if (kbps == 0)
181 return 0;
182
183 switch (rates->info[rateix].phy) {
184 case WLAN_RC_PHY_CCK:
185 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
186 if (shortPreamble && rates->info[rateix].short_preamble)
187 phyTime >>= 1;
188 numBits = frameLen << 3;
189 txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
190 break;
191 case WLAN_RC_PHY_OFDM:
192 if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
193 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
194 numBits = OFDM_PLCP_BITS + (frameLen << 3);
195 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
196 txTime = OFDM_SIFS_TIME_QUARTER
197 + OFDM_PREAMBLE_TIME_QUARTER
198 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
199 } else if (ah->curchan &&
200 IS_CHAN_HALF_RATE(ah->curchan)) {
201 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
202 numBits = OFDM_PLCP_BITS + (frameLen << 3);
203 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
204 txTime = OFDM_SIFS_TIME_HALF +
205 OFDM_PREAMBLE_TIME_HALF
206 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
207 } else {
208 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
209 numBits = OFDM_PLCP_BITS + (frameLen << 3);
210 numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
211 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
212 + (numSymbols * OFDM_SYMBOL_TIME);
213 }
214 break;
215 default:
216 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
217 "Unknown phy %u (rate ix %u)\n",
218 rates->info[rateix].phy, rateix);
219 txTime = 0;
220 break;
221 }
222
223 return txTime;
224 }
225
226 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
227 struct ath9k_channel *chan,
228 struct chan_centers *centers)
229 {
230 int8_t extoff;
231
232 if (!IS_CHAN_HT40(chan)) {
233 centers->ctl_center = centers->ext_center =
234 centers->synth_center = chan->channel;
235 return;
236 }
237
238 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
239 (chan->chanmode == CHANNEL_G_HT40PLUS)) {
240 centers->synth_center =
241 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
242 extoff = 1;
243 } else {
244 centers->synth_center =
245 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
246 extoff = -1;
247 }
248
249 centers->ctl_center =
250 centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
251 centers->ext_center =
252 centers->synth_center + (extoff *
253 ((ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_20) ?
254 HT40_CHANNEL_CENTER_SHIFT : 15));
255 }
256
257 /******************/
258 /* Chip Revisions */
259 /******************/
260
261 static void ath9k_hw_read_revisions(struct ath_hw *ah)
262 {
263 u32 val;
264
265 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
266
267 if (val == 0xFF) {
268 val = REG_READ(ah, AR_SREV);
269 ah->hw_version.macVersion =
270 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
271 ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
272 ah->is_pciexpress = (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
273 } else {
274 if (!AR_SREV_9100(ah))
275 ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
276
277 ah->hw_version.macRev = val & AR_SREV_REVISION;
278
279 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
280 ah->is_pciexpress = true;
281 }
282 }
283
284 static int ath9k_hw_get_radiorev(struct ath_hw *ah)
285 {
286 u32 val;
287 int i;
288
289 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
290
291 for (i = 0; i < 8; i++)
292 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
293 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
294 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
295
296 return ath9k_hw_reverse_bits(val, 8);
297 }
298
299 /************************************/
300 /* HW Attach, Detach, Init Routines */
301 /************************************/
302
303 static void ath9k_hw_disablepcie(struct ath_hw *ah)
304 {
305 if (AR_SREV_9100(ah))
306 return;
307
308 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
309 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
310 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
311 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
312 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
313 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
314 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
315 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
316 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
317
318 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
319 }
320
321 static bool ath9k_hw_chip_test(struct ath_hw *ah)
322 {
323 u32 regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
324 u32 regHold[2];
325 u32 patternData[4] = { 0x55555555,
326 0xaaaaaaaa,
327 0x66666666,
328 0x99999999 };
329 int i, j;
330
331 for (i = 0; i < 2; i++) {
332 u32 addr = regAddr[i];
333 u32 wrData, rdData;
334
335 regHold[i] = REG_READ(ah, addr);
336 for (j = 0; j < 0x100; j++) {
337 wrData = (j << 16) | j;
338 REG_WRITE(ah, addr, wrData);
339 rdData = REG_READ(ah, addr);
340 if (rdData != wrData) {
341 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
342 "address test failed "
343 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
344 addr, wrData, rdData);
345 return false;
346 }
347 }
348 for (j = 0; j < 4; j++) {
349 wrData = patternData[j];
350 REG_WRITE(ah, addr, wrData);
351 rdData = REG_READ(ah, addr);
352 if (wrData != rdData) {
353 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
354 "address test failed "
355 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
356 addr, wrData, rdData);
357 return false;
358 }
359 }
360 REG_WRITE(ah, regAddr[i], regHold[i]);
361 }
362 udelay(100);
363
364 return true;
365 }
366
367 static const char *ath9k_hw_devname(u16 devid)
368 {
369 switch (devid) {
370 case AR5416_DEVID_PCI:
371 return "Atheros 5416";
372 case AR5416_DEVID_PCIE:
373 return "Atheros 5418";
374 case AR9160_DEVID_PCI:
375 return "Atheros 9160";
376 case AR5416_AR9100_DEVID:
377 return "Atheros 9100";
378 case AR9280_DEVID_PCI:
379 case AR9280_DEVID_PCIE:
380 return "Atheros 9280";
381 case AR9285_DEVID_PCIE:
382 return "Atheros 9285";
383 }
384
385 return NULL;
386 }
387
388 static void ath9k_hw_set_defaults(struct ath_hw *ah)
389 {
390 int i;
391
392 ah->config.dma_beacon_response_time = 2;
393 ah->config.sw_beacon_response_time = 10;
394 ah->config.additional_swba_backoff = 0;
395 ah->config.ack_6mb = 0x0;
396 ah->config.cwm_ignore_extcca = 0;
397 ah->config.pcie_powersave_enable = 0;
398 ah->config.pcie_clock_req = 0;
399 ah->config.pcie_waen = 0;
400 ah->config.analog_shiftreg = 1;
401 ah->config.ht_enable = 1;
402 ah->config.ofdm_trig_low = 200;
403 ah->config.ofdm_trig_high = 500;
404 ah->config.cck_trig_high = 200;
405 ah->config.cck_trig_low = 100;
406 ah->config.enable_ani = 1;
407 ah->config.diversity_control = 0;
408 ah->config.antenna_switch_swap = 0;
409
410 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
411 ah->config.spurchans[i][0] = AR_NO_SPUR;
412 ah->config.spurchans[i][1] = AR_NO_SPUR;
413 }
414
415 ah->config.intr_mitigation = true;
416
417 /*
418 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
419 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
420 * This means we use it for all AR5416 devices, and the few
421 * minor PCI AR9280 devices out there.
422 *
423 * Serialization is required because these devices do not handle
424 * well the case of two concurrent reads/writes due to the latency
425 * involved. During one read/write another read/write can be issued
426 * on another CPU while the previous read/write may still be working
427 * on our hardware, if we hit this case the hardware poops in a loop.
428 * We prevent this by serializing reads and writes.
429 *
430 * This issue is not present on PCI-Express devices or pre-AR5416
431 * devices (legacy, 802.11abg).
432 */
433 if (num_possible_cpus() > 1)
434 ah->config.serialize_regmode = SER_REG_MODE_AUTO;
435 }
436
437 static struct ath_hw *ath9k_hw_newstate(u16 devid, struct ath_softc *sc,
438 int *status)
439 {
440 struct ath_hw *ah;
441
442 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL);
443 if (ah == NULL) {
444 DPRINTF(sc, ATH_DBG_FATAL,
445 "Cannot allocate memory for state block\n");
446 *status = -ENOMEM;
447 return NULL;
448 }
449
450 ah->ah_sc = sc;
451 ah->hw_version.magic = AR5416_MAGIC;
452 ah->regulatory.country_code = CTRY_DEFAULT;
453 ah->hw_version.devid = devid;
454 ah->hw_version.subvendorid = 0;
455
456 ah->ah_flags = 0;
457 if ((devid == AR5416_AR9100_DEVID))
458 ah->hw_version.macVersion = AR_SREV_VERSION_9100;
459 if (!AR_SREV_9100(ah))
460 ah->ah_flags = AH_USE_EEPROM;
461
462 ah->regulatory.power_limit = MAX_RATE_POWER;
463 ah->regulatory.tp_scale = ATH9K_TP_SCALE_MAX;
464 ah->atim_window = 0;
465 ah->diversity_control = ah->config.diversity_control;
466 ah->antenna_switch_swap =
467 ah->config.antenna_switch_swap;
468 ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
469 ah->beacon_interval = 100;
470 ah->enable_32kHz_clock = DONT_USE_32KHZ;
471 ah->slottime = (u32) -1;
472 ah->acktimeout = (u32) -1;
473 ah->ctstimeout = (u32) -1;
474 ah->globaltxtimeout = (u32) -1;
475
476 ah->gbeacon_rate = 0;
477
478 return ah;
479 }
480
481 static int ath9k_hw_rfattach(struct ath_hw *ah)
482 {
483 bool rfStatus = false;
484 int ecode = 0;
485
486 rfStatus = ath9k_hw_init_rf(ah, &ecode);
487 if (!rfStatus) {
488 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
489 "RF setup failed, status: %u\n", ecode);
490 return ecode;
491 }
492
493 return 0;
494 }
495
496 static int ath9k_hw_rf_claim(struct ath_hw *ah)
497 {
498 u32 val;
499
500 REG_WRITE(ah, AR_PHY(0), 0x00000007);
501
502 val = ath9k_hw_get_radiorev(ah);
503 switch (val & AR_RADIO_SREV_MAJOR) {
504 case 0:
505 val = AR_RAD5133_SREV_MAJOR;
506 break;
507 case AR_RAD5133_SREV_MAJOR:
508 case AR_RAD5122_SREV_MAJOR:
509 case AR_RAD2133_SREV_MAJOR:
510 case AR_RAD2122_SREV_MAJOR:
511 break;
512 default:
513 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
514 "Radio Chip Rev 0x%02X not supported\n",
515 val & AR_RADIO_SREV_MAJOR);
516 return -EOPNOTSUPP;
517 }
518
519 ah->hw_version.analog5GhzRev = val;
520
521 return 0;
522 }
523
524 static int ath9k_hw_init_macaddr(struct ath_hw *ah)
525 {
526 u32 sum;
527 int i;
528 u16 eeval;
529
530 sum = 0;
531 for (i = 0; i < 3; i++) {
532 eeval = ah->eep_ops->get_eeprom(ah, AR_EEPROM_MAC(i));
533 sum += eeval;
534 ah->macaddr[2 * i] = eeval >> 8;
535 ah->macaddr[2 * i + 1] = eeval & 0xff;
536 }
537 if (sum == 0 || sum == 0xffff * 3)
538 return -EADDRNOTAVAIL;
539
540 return 0;
541 }
542
543 static void ath9k_hw_init_rxgain_ini(struct ath_hw *ah)
544 {
545 u32 rxgain_type;
546
547 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_17) {
548 rxgain_type = ah->eep_ops->get_eeprom(ah, EEP_RXGAIN_TYPE);
549
550 if (rxgain_type == AR5416_EEP_RXGAIN_13DB_BACKOFF)
551 INIT_INI_ARRAY(&ah->iniModesRxGain,
552 ar9280Modes_backoff_13db_rxgain_9280_2,
553 ARRAY_SIZE(ar9280Modes_backoff_13db_rxgain_9280_2), 6);
554 else if (rxgain_type == AR5416_EEP_RXGAIN_23DB_BACKOFF)
555 INIT_INI_ARRAY(&ah->iniModesRxGain,
556 ar9280Modes_backoff_23db_rxgain_9280_2,
557 ARRAY_SIZE(ar9280Modes_backoff_23db_rxgain_9280_2), 6);
558 else
559 INIT_INI_ARRAY(&ah->iniModesRxGain,
560 ar9280Modes_original_rxgain_9280_2,
561 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
562 } else {
563 INIT_INI_ARRAY(&ah->iniModesRxGain,
564 ar9280Modes_original_rxgain_9280_2,
565 ARRAY_SIZE(ar9280Modes_original_rxgain_9280_2), 6);
566 }
567 }
568
569 static void ath9k_hw_init_txgain_ini(struct ath_hw *ah)
570 {
571 u32 txgain_type;
572
573 if (ah->eep_ops->get_eeprom(ah, EEP_MINOR_REV) >= AR5416_EEP_MINOR_VER_19) {
574 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
575
576 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER)
577 INIT_INI_ARRAY(&ah->iniModesTxGain,
578 ar9280Modes_high_power_tx_gain_9280_2,
579 ARRAY_SIZE(ar9280Modes_high_power_tx_gain_9280_2), 6);
580 else
581 INIT_INI_ARRAY(&ah->iniModesTxGain,
582 ar9280Modes_original_tx_gain_9280_2,
583 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
584 } else {
585 INIT_INI_ARRAY(&ah->iniModesTxGain,
586 ar9280Modes_original_tx_gain_9280_2,
587 ARRAY_SIZE(ar9280Modes_original_tx_gain_9280_2), 6);
588 }
589 }
590
591 static int ath9k_hw_post_attach(struct ath_hw *ah)
592 {
593 int ecode;
594
595 if (!ath9k_hw_chip_test(ah))
596 return -ENODEV;
597
598 ecode = ath9k_hw_rf_claim(ah);
599 if (ecode != 0)
600 return ecode;
601
602 ecode = ath9k_hw_eeprom_attach(ah);
603 if (ecode != 0)
604 return ecode;
605
606 DPRINTF(ah->ah_sc, ATH_DBG_CONFIG, "Eeprom VER: %d, REV: %d\n",
607 ah->eep_ops->get_eeprom_ver(ah), ah->eep_ops->get_eeprom_rev(ah));
608
609 ecode = ath9k_hw_rfattach(ah);
610 if (ecode != 0)
611 return ecode;
612
613 if (!AR_SREV_9100(ah)) {
614 ath9k_hw_ani_setup(ah);
615 ath9k_hw_ani_attach(ah);
616 }
617
618 return 0;
619 }
620
621 static struct ath_hw *ath9k_hw_do_attach(u16 devid, struct ath_softc *sc,
622 int *status)
623 {
624 struct ath_hw *ah;
625 int ecode;
626 u32 i, j;
627
628 ah = ath9k_hw_newstate(devid, sc, status);
629 if (ah == NULL)
630 return NULL;
631
632 ath9k_hw_set_defaults(ah);
633
634 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
635 DPRINTF(sc, ATH_DBG_FATAL, "Couldn't reset chip\n");
636 ecode = -EIO;
637 goto bad;
638 }
639
640 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
641 DPRINTF(sc, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
642 ecode = -EIO;
643 goto bad;
644 }
645
646 if (ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
647 if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
648 (AR_SREV_9280(ah) && !ah->is_pciexpress)) {
649 ah->config.serialize_regmode =
650 SER_REG_MODE_ON;
651 } else {
652 ah->config.serialize_regmode =
653 SER_REG_MODE_OFF;
654 }
655 }
656
657 DPRINTF(sc, ATH_DBG_RESET, "serialize_regmode is %d\n",
658 ah->config.serialize_regmode);
659
660 if ((ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCI) &&
661 (ah->hw_version.macVersion != AR_SREV_VERSION_5416_PCIE) &&
662 (ah->hw_version.macVersion != AR_SREV_VERSION_9160) &&
663 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah)) && (!AR_SREV_9285(ah))) {
664 DPRINTF(sc, ATH_DBG_FATAL,
665 "Mac Chip Rev 0x%02x.%x is not supported by "
666 "this driver\n", ah->hw_version.macVersion,
667 ah->hw_version.macRev);
668 ecode = -EOPNOTSUPP;
669 goto bad;
670 }
671
672 if (AR_SREV_9100(ah)) {
673 ah->iq_caldata.calData = &iq_cal_multi_sample;
674 ah->supp_cals = IQ_MISMATCH_CAL;
675 ah->is_pciexpress = false;
676 }
677 ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
678
679 if (AR_SREV_9160_10_OR_LATER(ah)) {
680 if (AR_SREV_9280_10_OR_LATER(ah)) {
681 ah->iq_caldata.calData = &iq_cal_single_sample;
682 ah->adcgain_caldata.calData =
683 &adc_gain_cal_single_sample;
684 ah->adcdc_caldata.calData =
685 &adc_dc_cal_single_sample;
686 ah->adcdc_calinitdata.calData =
687 &adc_init_dc_cal;
688 } else {
689 ah->iq_caldata.calData = &iq_cal_multi_sample;
690 ah->adcgain_caldata.calData =
691 &adc_gain_cal_multi_sample;
692 ah->adcdc_caldata.calData =
693 &adc_dc_cal_multi_sample;
694 ah->adcdc_calinitdata.calData =
695 &adc_init_dc_cal;
696 }
697 ah->supp_cals = ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
698 }
699
700 ah->ani_function = ATH9K_ANI_ALL;
701 if (AR_SREV_9280_10_OR_LATER(ah))
702 ah->ani_function &= ~ATH9K_ANI_NOISE_IMMUNITY_LEVEL;
703
704 if (AR_SREV_9285_12_OR_LATER(ah)) {
705
706 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285_1_2,
707 ARRAY_SIZE(ar9285Modes_9285_1_2), 6);
708 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285_1_2,
709 ARRAY_SIZE(ar9285Common_9285_1_2), 2);
710
711 if (ah->config.pcie_clock_req) {
712 INIT_INI_ARRAY(&ah->iniPcieSerdes,
713 ar9285PciePhy_clkreq_off_L1_9285_1_2,
714 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285_1_2), 2);
715 } else {
716 INIT_INI_ARRAY(&ah->iniPcieSerdes,
717 ar9285PciePhy_clkreq_always_on_L1_9285_1_2,
718 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285_1_2),
719 2);
720 }
721 } else if (AR_SREV_9285_10_OR_LATER(ah)) {
722 INIT_INI_ARRAY(&ah->iniModes, ar9285Modes_9285,
723 ARRAY_SIZE(ar9285Modes_9285), 6);
724 INIT_INI_ARRAY(&ah->iniCommon, ar9285Common_9285,
725 ARRAY_SIZE(ar9285Common_9285), 2);
726
727 if (ah->config.pcie_clock_req) {
728 INIT_INI_ARRAY(&ah->iniPcieSerdes,
729 ar9285PciePhy_clkreq_off_L1_9285,
730 ARRAY_SIZE(ar9285PciePhy_clkreq_off_L1_9285), 2);
731 } else {
732 INIT_INI_ARRAY(&ah->iniPcieSerdes,
733 ar9285PciePhy_clkreq_always_on_L1_9285,
734 ARRAY_SIZE(ar9285PciePhy_clkreq_always_on_L1_9285), 2);
735 }
736 } else if (AR_SREV_9280_20_OR_LATER(ah)) {
737 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280_2,
738 ARRAY_SIZE(ar9280Modes_9280_2), 6);
739 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280_2,
740 ARRAY_SIZE(ar9280Common_9280_2), 2);
741
742 if (ah->config.pcie_clock_req) {
743 INIT_INI_ARRAY(&ah->iniPcieSerdes,
744 ar9280PciePhy_clkreq_off_L1_9280,
745 ARRAY_SIZE(ar9280PciePhy_clkreq_off_L1_9280),2);
746 } else {
747 INIT_INI_ARRAY(&ah->iniPcieSerdes,
748 ar9280PciePhy_clkreq_always_on_L1_9280,
749 ARRAY_SIZE(ar9280PciePhy_clkreq_always_on_L1_9280), 2);
750 }
751 INIT_INI_ARRAY(&ah->iniModesAdditional,
752 ar9280Modes_fast_clock_9280_2,
753 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2), 3);
754 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
755 INIT_INI_ARRAY(&ah->iniModes, ar9280Modes_9280,
756 ARRAY_SIZE(ar9280Modes_9280), 6);
757 INIT_INI_ARRAY(&ah->iniCommon, ar9280Common_9280,
758 ARRAY_SIZE(ar9280Common_9280), 2);
759 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
760 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9160,
761 ARRAY_SIZE(ar5416Modes_9160), 6);
762 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9160,
763 ARRAY_SIZE(ar5416Common_9160), 2);
764 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9160,
765 ARRAY_SIZE(ar5416Bank0_9160), 2);
766 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9160,
767 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
768 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9160,
769 ARRAY_SIZE(ar5416Bank1_9160), 2);
770 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9160,
771 ARRAY_SIZE(ar5416Bank2_9160), 2);
772 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9160,
773 ARRAY_SIZE(ar5416Bank3_9160), 3);
774 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9160,
775 ARRAY_SIZE(ar5416Bank6_9160), 3);
776 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9160,
777 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
778 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9160,
779 ARRAY_SIZE(ar5416Bank7_9160), 2);
780 if (AR_SREV_9160_11(ah)) {
781 INIT_INI_ARRAY(&ah->iniAddac,
782 ar5416Addac_91601_1,
783 ARRAY_SIZE(ar5416Addac_91601_1), 2);
784 } else {
785 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9160,
786 ARRAY_SIZE(ar5416Addac_9160), 2);
787 }
788 } else if (AR_SREV_9100_OR_LATER(ah)) {
789 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes_9100,
790 ARRAY_SIZE(ar5416Modes_9100), 6);
791 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common_9100,
792 ARRAY_SIZE(ar5416Common_9100), 2);
793 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0_9100,
794 ARRAY_SIZE(ar5416Bank0_9100), 2);
795 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain_9100,
796 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
797 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1_9100,
798 ARRAY_SIZE(ar5416Bank1_9100), 2);
799 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2_9100,
800 ARRAY_SIZE(ar5416Bank2_9100), 2);
801 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3_9100,
802 ARRAY_SIZE(ar5416Bank3_9100), 3);
803 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6_9100,
804 ARRAY_SIZE(ar5416Bank6_9100), 3);
805 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC_9100,
806 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
807 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7_9100,
808 ARRAY_SIZE(ar5416Bank7_9100), 2);
809 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac_9100,
810 ARRAY_SIZE(ar5416Addac_9100), 2);
811 } else {
812 INIT_INI_ARRAY(&ah->iniModes, ar5416Modes,
813 ARRAY_SIZE(ar5416Modes), 6);
814 INIT_INI_ARRAY(&ah->iniCommon, ar5416Common,
815 ARRAY_SIZE(ar5416Common), 2);
816 INIT_INI_ARRAY(&ah->iniBank0, ar5416Bank0,
817 ARRAY_SIZE(ar5416Bank0), 2);
818 INIT_INI_ARRAY(&ah->iniBB_RfGain, ar5416BB_RfGain,
819 ARRAY_SIZE(ar5416BB_RfGain), 3);
820 INIT_INI_ARRAY(&ah->iniBank1, ar5416Bank1,
821 ARRAY_SIZE(ar5416Bank1), 2);
822 INIT_INI_ARRAY(&ah->iniBank2, ar5416Bank2,
823 ARRAY_SIZE(ar5416Bank2), 2);
824 INIT_INI_ARRAY(&ah->iniBank3, ar5416Bank3,
825 ARRAY_SIZE(ar5416Bank3), 3);
826 INIT_INI_ARRAY(&ah->iniBank6, ar5416Bank6,
827 ARRAY_SIZE(ar5416Bank6), 3);
828 INIT_INI_ARRAY(&ah->iniBank6TPC, ar5416Bank6TPC,
829 ARRAY_SIZE(ar5416Bank6TPC), 3);
830 INIT_INI_ARRAY(&ah->iniBank7, ar5416Bank7,
831 ARRAY_SIZE(ar5416Bank7), 2);
832 INIT_INI_ARRAY(&ah->iniAddac, ar5416Addac,
833 ARRAY_SIZE(ar5416Addac), 2);
834 }
835
836 if (ah->is_pciexpress)
837 ath9k_hw_configpcipowersave(ah, 0);
838 else
839 ath9k_hw_disablepcie(ah);
840
841 ecode = ath9k_hw_post_attach(ah);
842 if (ecode != 0)
843 goto bad;
844
845 if (AR_SREV_9285_12_OR_LATER(ah)) {
846 u32 txgain_type = ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE);
847
848 /* txgain table */
849 if (txgain_type == AR5416_EEP_TXGAIN_HIGH_POWER) {
850 INIT_INI_ARRAY(&ah->iniModesTxGain,
851 ar9285Modes_high_power_tx_gain_9285_1_2,
852 ARRAY_SIZE(ar9285Modes_high_power_tx_gain_9285_1_2), 6);
853 } else {
854 INIT_INI_ARRAY(&ah->iniModesTxGain,
855 ar9285Modes_original_tx_gain_9285_1_2,
856 ARRAY_SIZE(ar9285Modes_original_tx_gain_9285_1_2), 6);
857 }
858
859 }
860
861 /* rxgain table */
862 if (AR_SREV_9280_20(ah))
863 ath9k_hw_init_rxgain_ini(ah);
864
865 /* txgain table */
866 if (AR_SREV_9280_20(ah))
867 ath9k_hw_init_txgain_ini(ah);
868
869 ath9k_hw_fill_cap_info(ah);
870
871 if ((ah->hw_version.devid == AR9280_DEVID_PCI) &&
872 test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes)) {
873
874 /* EEPROM Fixup */
875 for (i = 0; i < ah->iniModes.ia_rows; i++) {
876 u32 reg = INI_RA(&ah->iniModes, i, 0);
877
878 for (j = 1; j < ah->iniModes.ia_columns; j++) {
879 u32 val = INI_RA(&ah->iniModes, i, j);
880
881 INI_RA(&ah->iniModes, i, j) =
882 ath9k_hw_ini_fixup(ah,
883 &ah->eeprom.def,
884 reg, val);
885 }
886 }
887 }
888
889 ecode = ath9k_hw_init_macaddr(ah);
890 if (ecode != 0) {
891 DPRINTF(sc, ATH_DBG_FATAL,
892 "Failed to initialize MAC address\n");
893 goto bad;
894 }
895
896 if (AR_SREV_9285(ah))
897 ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
898 else
899 ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
900
901 ath9k_init_nfcal_hist_buffer(ah);
902
903 return ah;
904 bad:
905 if (ah)
906 ath9k_hw_detach(ah);
907 if (status)
908 *status = ecode;
909
910 return NULL;
911 }
912
913 static void ath9k_hw_init_bb(struct ath_hw *ah,
914 struct ath9k_channel *chan)
915 {
916 u32 synthDelay;
917
918 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
919 if (IS_CHAN_B(chan))
920 synthDelay = (4 * synthDelay) / 22;
921 else
922 synthDelay /= 10;
923
924 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
925
926 udelay(synthDelay + BASE_ACTIVATE_DELAY);
927 }
928
929 static void ath9k_hw_init_qos(struct ath_hw *ah)
930 {
931 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
932 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
933
934 REG_WRITE(ah, AR_QOS_NO_ACK,
935 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
936 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
937 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
938
939 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
940 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
941 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
942 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
943 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
944 }
945
946 static void ath9k_hw_init_pll(struct ath_hw *ah,
947 struct ath9k_channel *chan)
948 {
949 u32 pll;
950
951 if (AR_SREV_9100(ah)) {
952 if (chan && IS_CHAN_5GHZ(chan))
953 pll = 0x1450;
954 else
955 pll = 0x1458;
956 } else {
957 if (AR_SREV_9280_10_OR_LATER(ah)) {
958 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
959
960 if (chan && IS_CHAN_HALF_RATE(chan))
961 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
962 else if (chan && IS_CHAN_QUARTER_RATE(chan))
963 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
964
965 if (chan && IS_CHAN_5GHZ(chan)) {
966 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
967
968
969 if (AR_SREV_9280_20(ah)) {
970 if (((chan->channel % 20) == 0)
971 || ((chan->channel % 10) == 0))
972 pll = 0x2850;
973 else
974 pll = 0x142c;
975 }
976 } else {
977 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
978 }
979
980 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
981
982 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
983
984 if (chan && IS_CHAN_HALF_RATE(chan))
985 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
986 else if (chan && IS_CHAN_QUARTER_RATE(chan))
987 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
988
989 if (chan && IS_CHAN_5GHZ(chan))
990 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
991 else
992 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
993 } else {
994 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
995
996 if (chan && IS_CHAN_HALF_RATE(chan))
997 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
998 else if (chan && IS_CHAN_QUARTER_RATE(chan))
999 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1000
1001 if (chan && IS_CHAN_5GHZ(chan))
1002 pll |= SM(0xa, AR_RTC_PLL_DIV);
1003 else
1004 pll |= SM(0xb, AR_RTC_PLL_DIV);
1005 }
1006 }
1007 REG_WRITE(ah, AR_RTC_PLL_CONTROL, pll);
1008
1009 udelay(RTC_PLL_SETTLE_DELAY);
1010
1011 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1012 }
1013
1014 static void ath9k_hw_init_chain_masks(struct ath_hw *ah)
1015 {
1016 int rx_chainmask, tx_chainmask;
1017
1018 rx_chainmask = ah->rxchainmask;
1019 tx_chainmask = ah->txchainmask;
1020
1021 switch (rx_chainmask) {
1022 case 0x5:
1023 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1024 AR_PHY_SWAP_ALT_CHAIN);
1025 case 0x3:
1026 if (((ah)->hw_version.macVersion <= AR_SREV_VERSION_9160)) {
1027 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
1028 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
1029 break;
1030 }
1031 case 0x1:
1032 case 0x2:
1033 case 0x7:
1034 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
1035 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
1036 break;
1037 default:
1038 break;
1039 }
1040
1041 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
1042 if (tx_chainmask == 0x5) {
1043 REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
1044 AR_PHY_SWAP_ALT_CHAIN);
1045 }
1046 if (AR_SREV_9100(ah))
1047 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
1048 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
1049 }
1050
1051 static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1052 enum nl80211_iftype opmode)
1053 {
1054 ah->mask_reg = AR_IMR_TXERR |
1055 AR_IMR_TXURN |
1056 AR_IMR_RXERR |
1057 AR_IMR_RXORN |
1058 AR_IMR_BCNMISC;
1059
1060 if (ah->config.intr_mitigation)
1061 ah->mask_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
1062 else
1063 ah->mask_reg |= AR_IMR_RXOK;
1064
1065 ah->mask_reg |= AR_IMR_TXOK;
1066
1067 if (opmode == NL80211_IFTYPE_AP)
1068 ah->mask_reg |= AR_IMR_MIB;
1069
1070 REG_WRITE(ah, AR_IMR, ah->mask_reg);
1071 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
1072
1073 if (!AR_SREV_9100(ah)) {
1074 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
1075 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
1076 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
1077 }
1078 }
1079
1080 static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1081 {
1082 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1083 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1084 ah->acktimeout = (u32) -1;
1085 return false;
1086 } else {
1087 REG_RMW_FIELD(ah, AR_TIME_OUT,
1088 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
1089 ah->acktimeout = us;
1090 return true;
1091 }
1092 }
1093
1094 static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1095 {
1096 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1097 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1098 ah->ctstimeout = (u32) -1;
1099 return false;
1100 } else {
1101 REG_RMW_FIELD(ah, AR_TIME_OUT,
1102 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
1103 ah->ctstimeout = us;
1104 return true;
1105 }
1106 }
1107
1108 static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1109 {
1110 if (tu > 0xFFFF) {
1111 DPRINTF(ah->ah_sc, ATH_DBG_XMIT,
1112 "bad global tx timeout %u\n", tu);
1113 ah->globaltxtimeout = (u32) -1;
1114 return false;
1115 } else {
1116 REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1117 ah->globaltxtimeout = tu;
1118 return true;
1119 }
1120 }
1121
1122 static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1123 {
1124 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1125 ah->misc_mode);
1126
1127 if (ah->misc_mode != 0)
1128 REG_WRITE(ah, AR_PCU_MISC,
1129 REG_READ(ah, AR_PCU_MISC) | ah->misc_mode);
1130 if (ah->slottime != (u32) -1)
1131 ath9k_hw_setslottime(ah, ah->slottime);
1132 if (ah->acktimeout != (u32) -1)
1133 ath9k_hw_set_ack_timeout(ah, ah->acktimeout);
1134 if (ah->ctstimeout != (u32) -1)
1135 ath9k_hw_set_cts_timeout(ah, ah->ctstimeout);
1136 if (ah->globaltxtimeout != (u32) -1)
1137 ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1138 }
1139
1140 const char *ath9k_hw_probe(u16 vendorid, u16 devid)
1141 {
1142 return vendorid == ATHEROS_VENDOR_ID ?
1143 ath9k_hw_devname(devid) : NULL;
1144 }
1145
1146 void ath9k_hw_detach(struct ath_hw *ah)
1147 {
1148 if (!AR_SREV_9100(ah))
1149 ath9k_hw_ani_detach(ah);
1150
1151 ath9k_hw_rfdetach(ah);
1152 ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1153 kfree(ah);
1154 }
1155
1156 struct ath_hw *ath9k_hw_attach(u16 devid, struct ath_softc *sc, int *error)
1157 {
1158 struct ath_hw *ah = NULL;
1159
1160 switch (devid) {
1161 case AR5416_DEVID_PCI:
1162 case AR5416_DEVID_PCIE:
1163 case AR5416_AR9100_DEVID:
1164 case AR9160_DEVID_PCI:
1165 case AR9280_DEVID_PCI:
1166 case AR9280_DEVID_PCIE:
1167 case AR9285_DEVID_PCIE:
1168 ah = ath9k_hw_do_attach(devid, sc, error);
1169 break;
1170 default:
1171 *error = -ENXIO;
1172 break;
1173 }
1174
1175 return ah;
1176 }
1177
1178 /*******/
1179 /* INI */
1180 /*******/
1181
1182 static void ath9k_hw_override_ini(struct ath_hw *ah,
1183 struct ath9k_channel *chan)
1184 {
1185 /*
1186 * Set the RX_ABORT and RX_DIS and clear if off only after
1187 * RXE is set for MAC. This prevents frames with corrupted
1188 * descriptor status.
1189 */
1190 REG_SET_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
1191
1192
1193 if (!AR_SREV_5416_20_OR_LATER(ah) ||
1194 AR_SREV_9280_10_OR_LATER(ah))
1195 return;
1196
1197 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
1198 }
1199
1200 static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1201 struct ar5416_eeprom_def *pEepData,
1202 u32 reg, u32 value)
1203 {
1204 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
1205
1206 switch (ah->hw_version.devid) {
1207 case AR9280_DEVID_PCI:
1208 if (reg == 0x7894) {
1209 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1210 "ini VAL: %x EEPROM: %x\n", value,
1211 (pBase->version & 0xff));
1212
1213 if ((pBase->version & 0xff) > 0x0a) {
1214 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1215 "PWDCLKIND: %d\n",
1216 pBase->pwdclkind);
1217 value &= ~AR_AN_TOP2_PWDCLKIND;
1218 value |= AR_AN_TOP2_PWDCLKIND &
1219 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1220 } else {
1221 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1222 "PWDCLKIND Earlier Rev\n");
1223 }
1224
1225 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM,
1226 "final ini VAL: %x\n", value);
1227 }
1228 break;
1229 }
1230
1231 return value;
1232 }
1233
1234 static u32 ath9k_hw_ini_fixup(struct ath_hw *ah,
1235 struct ar5416_eeprom_def *pEepData,
1236 u32 reg, u32 value)
1237 {
1238 if (ah->eep_map == EEP_MAP_4KBITS)
1239 return value;
1240 else
1241 return ath9k_hw_def_ini_fixup(ah, pEepData, reg, value);
1242 }
1243
1244 static void ath9k_olc_init(struct ath_hw *ah)
1245 {
1246 u32 i;
1247
1248 for (i = 0; i < AR9280_TX_GAIN_TABLE_SIZE; i++)
1249 ah->originalGain[i] =
1250 MS(REG_READ(ah, AR_PHY_TX_GAIN_TBL1 + i * 4),
1251 AR_PHY_TX_GAIN);
1252 ah->PDADCdelta = 0;
1253 }
1254
1255 static u32 ath9k_regd_get_ctl(struct ath_regulatory *reg,
1256 struct ath9k_channel *chan)
1257 {
1258 u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1259
1260 if (IS_CHAN_B(chan))
1261 ctl |= CTL_11B;
1262 else if (IS_CHAN_G(chan))
1263 ctl |= CTL_11G;
1264 else
1265 ctl |= CTL_11A;
1266
1267 return ctl;
1268 }
1269
1270 static int ath9k_hw_process_ini(struct ath_hw *ah,
1271 struct ath9k_channel *chan,
1272 enum ath9k_ht_macmode macmode)
1273 {
1274 int i, regWrites = 0;
1275 struct ieee80211_channel *channel = chan->chan;
1276 u32 modesIndex, freqIndex;
1277
1278 switch (chan->chanmode) {
1279 case CHANNEL_A:
1280 case CHANNEL_A_HT20:
1281 modesIndex = 1;
1282 freqIndex = 1;
1283 break;
1284 case CHANNEL_A_HT40PLUS:
1285 case CHANNEL_A_HT40MINUS:
1286 modesIndex = 2;
1287 freqIndex = 1;
1288 break;
1289 case CHANNEL_G:
1290 case CHANNEL_G_HT20:
1291 case CHANNEL_B:
1292 modesIndex = 4;
1293 freqIndex = 2;
1294 break;
1295 case CHANNEL_G_HT40PLUS:
1296 case CHANNEL_G_HT40MINUS:
1297 modesIndex = 3;
1298 freqIndex = 2;
1299 break;
1300
1301 default:
1302 return -EINVAL;
1303 }
1304
1305 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1306 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
1307 ah->eep_ops->set_addac(ah, chan);
1308
1309 if (AR_SREV_5416_22_OR_LATER(ah)) {
1310 REG_WRITE_ARRAY(&ah->iniAddac, 1, regWrites);
1311 } else {
1312 struct ar5416IniArray temp;
1313 u32 addacSize =
1314 sizeof(u32) * ah->iniAddac.ia_rows *
1315 ah->iniAddac.ia_columns;
1316
1317 memcpy(ah->addac5416_21,
1318 ah->iniAddac.ia_array, addacSize);
1319
1320 (ah->addac5416_21)[31 * ah->iniAddac.ia_columns + 1] = 0;
1321
1322 temp.ia_array = ah->addac5416_21;
1323 temp.ia_columns = ah->iniAddac.ia_columns;
1324 temp.ia_rows = ah->iniAddac.ia_rows;
1325 REG_WRITE_ARRAY(&temp, 1, regWrites);
1326 }
1327
1328 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
1329
1330 for (i = 0; i < ah->iniModes.ia_rows; i++) {
1331 u32 reg = INI_RA(&ah->iniModes, i, 0);
1332 u32 val = INI_RA(&ah->iniModes, i, modesIndex);
1333
1334 REG_WRITE(ah, reg, val);
1335
1336 if (reg >= 0x7800 && reg < 0x78a0
1337 && ah->config.analog_shiftreg) {
1338 udelay(100);
1339 }
1340
1341 DO_DELAY(regWrites);
1342 }
1343
1344 if (AR_SREV_9280(ah))
1345 REG_WRITE_ARRAY(&ah->iniModesRxGain, modesIndex, regWrites);
1346
1347 if (AR_SREV_9280(ah) || AR_SREV_9285_12_OR_LATER(ah))
1348 REG_WRITE_ARRAY(&ah->iniModesTxGain, modesIndex, regWrites);
1349
1350 for (i = 0; i < ah->iniCommon.ia_rows; i++) {
1351 u32 reg = INI_RA(&ah->iniCommon, i, 0);
1352 u32 val = INI_RA(&ah->iniCommon, i, 1);
1353
1354 REG_WRITE(ah, reg, val);
1355
1356 if (reg >= 0x7800 && reg < 0x78a0
1357 && ah->config.analog_shiftreg) {
1358 udelay(100);
1359 }
1360
1361 DO_DELAY(regWrites);
1362 }
1363
1364 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
1365
1366 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
1367 REG_WRITE_ARRAY(&ah->iniModesAdditional, modesIndex,
1368 regWrites);
1369 }
1370
1371 ath9k_hw_override_ini(ah, chan);
1372 ath9k_hw_set_regs(ah, chan, macmode);
1373 ath9k_hw_init_chain_masks(ah);
1374
1375 if (OLC_FOR_AR9280_20_LATER)
1376 ath9k_olc_init(ah);
1377
1378 ah->eep_ops->set_txpower(ah, chan,
1379 ath9k_regd_get_ctl(&ah->regulatory, chan),
1380 channel->max_antenna_gain * 2,
1381 channel->max_power * 2,
1382 min((u32) MAX_RATE_POWER,
1383 (u32) ah->regulatory.power_limit));
1384
1385 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1386 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1387 "ar5416SetRfRegs failed\n");
1388 return -EIO;
1389 }
1390
1391 return 0;
1392 }
1393
1394 /****************************************/
1395 /* Reset and Channel Switching Routines */
1396 /****************************************/
1397
1398 static void ath9k_hw_set_rfmode(struct ath_hw *ah, struct ath9k_channel *chan)
1399 {
1400 u32 rfMode = 0;
1401
1402 if (chan == NULL)
1403 return;
1404
1405 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1406 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1407
1408 if (!AR_SREV_9280_10_OR_LATER(ah))
1409 rfMode |= (IS_CHAN_5GHZ(chan)) ?
1410 AR_PHY_MODE_RF5GHZ : AR_PHY_MODE_RF2GHZ;
1411
1412 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1413 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1414
1415 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1416 }
1417
1418 static void ath9k_hw_mark_phy_inactive(struct ath_hw *ah)
1419 {
1420 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1421 }
1422
1423 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1424 {
1425 u32 regval;
1426
1427 regval = REG_READ(ah, AR_AHB_MODE);
1428 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
1429
1430 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
1431 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
1432
1433 REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1434
1435 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
1436 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
1437
1438 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1439
1440 if (AR_SREV_9285(ah)) {
1441 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1442 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
1443 } else {
1444 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
1445 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
1446 }
1447 }
1448
1449 static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1450 {
1451 u32 val;
1452
1453 val = REG_READ(ah, AR_STA_ID1);
1454 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1455 switch (opmode) {
1456 case NL80211_IFTYPE_AP:
1457 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1458 | AR_STA_ID1_KSRCH_MODE);
1459 REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1460 break;
1461 case NL80211_IFTYPE_ADHOC:
1462 case NL80211_IFTYPE_MESH_POINT:
1463 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1464 | AR_STA_ID1_KSRCH_MODE);
1465 REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1466 break;
1467 case NL80211_IFTYPE_STATION:
1468 case NL80211_IFTYPE_MONITOR:
1469 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1470 break;
1471 }
1472 }
1473
1474 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah,
1475 u32 coef_scaled,
1476 u32 *coef_mantissa,
1477 u32 *coef_exponent)
1478 {
1479 u32 coef_exp, coef_man;
1480
1481 for (coef_exp = 31; coef_exp > 0; coef_exp--)
1482 if ((coef_scaled >> coef_exp) & 0x1)
1483 break;
1484
1485 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1486
1487 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1488
1489 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1490 *coef_exponent = coef_exp - 16;
1491 }
1492
1493 static void ath9k_hw_set_delta_slope(struct ath_hw *ah,
1494 struct ath9k_channel *chan)
1495 {
1496 u32 coef_scaled, ds_coef_exp, ds_coef_man;
1497 u32 clockMhzScaled = 0x64000000;
1498 struct chan_centers centers;
1499
1500 if (IS_CHAN_HALF_RATE(chan))
1501 clockMhzScaled = clockMhzScaled >> 1;
1502 else if (IS_CHAN_QUARTER_RATE(chan))
1503 clockMhzScaled = clockMhzScaled >> 2;
1504
1505 ath9k_hw_get_channel_centers(ah, chan, &centers);
1506 coef_scaled = clockMhzScaled / centers.synth_center;
1507
1508 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1509 &ds_coef_exp);
1510
1511 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1512 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
1513 REG_RMW_FIELD(ah, AR_PHY_TIMING3,
1514 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
1515
1516 coef_scaled = (9 * coef_scaled) / 10;
1517
1518 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
1519 &ds_coef_exp);
1520
1521 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1522 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
1523 REG_RMW_FIELD(ah, AR_PHY_HALFGI,
1524 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
1525 }
1526
1527 static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1528 {
1529 u32 rst_flags;
1530 u32 tmpReg;
1531
1532 if (AR_SREV_9100(ah)) {
1533 u32 val = REG_READ(ah, AR_RTC_DERIVED_CLK);
1534 val &= ~AR_RTC_DERIVED_CLK_PERIOD;
1535 val |= SM(1, AR_RTC_DERIVED_CLK_PERIOD);
1536 REG_WRITE(ah, AR_RTC_DERIVED_CLK, val);
1537 (void)REG_READ(ah, AR_RTC_DERIVED_CLK);
1538 }
1539
1540 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1541 AR_RTC_FORCE_WAKE_ON_INT);
1542
1543 if (AR_SREV_9100(ah)) {
1544 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1545 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1546 } else {
1547 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1548 if (tmpReg &
1549 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1550 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1551 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1552 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1553 } else {
1554 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1555 }
1556
1557 rst_flags = AR_RTC_RC_MAC_WARM;
1558 if (type == ATH9K_RESET_COLD)
1559 rst_flags |= AR_RTC_RC_MAC_COLD;
1560 }
1561
1562 REG_WRITE(ah, AR_RTC_RC, rst_flags);
1563 udelay(50);
1564
1565 REG_WRITE(ah, AR_RTC_RC, 0);
1566 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1567 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
1568 "RTC stuck in MAC reset\n");
1569 return false;
1570 }
1571
1572 if (!AR_SREV_9100(ah))
1573 REG_WRITE(ah, AR_RC, 0);
1574
1575 ath9k_hw_init_pll(ah, NULL);
1576
1577 if (AR_SREV_9100(ah))
1578 udelay(50);
1579
1580 return true;
1581 }
1582
1583 static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1584 {
1585 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1586 AR_RTC_FORCE_WAKE_ON_INT);
1587
1588 REG_WRITE(ah, AR_RTC_RESET, 0);
1589 udelay(2);
1590 REG_WRITE(ah, AR_RTC_RESET, 1);
1591
1592 if (!ath9k_hw_wait(ah,
1593 AR_RTC_STATUS,
1594 AR_RTC_STATUS_M,
1595 AR_RTC_STATUS_ON,
1596 AH_WAIT_TIMEOUT)) {
1597 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n");
1598 return false;
1599 }
1600
1601 ath9k_hw_read_revisions(ah);
1602
1603 return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1604 }
1605
1606 static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1607 {
1608 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1609 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1610
1611 switch (type) {
1612 case ATH9K_RESET_POWER_ON:
1613 return ath9k_hw_set_reset_power_on(ah);
1614 case ATH9K_RESET_WARM:
1615 case ATH9K_RESET_COLD:
1616 return ath9k_hw_set_reset(ah, type);
1617 default:
1618 return false;
1619 }
1620 }
1621
1622 static void ath9k_hw_set_regs(struct ath_hw *ah, struct ath9k_channel *chan,
1623 enum ath9k_ht_macmode macmode)
1624 {
1625 u32 phymode;
1626 u32 enableDacFifo = 0;
1627
1628 if (AR_SREV_9285_10_OR_LATER(ah))
1629 enableDacFifo = (REG_READ(ah, AR_PHY_TURBO) &
1630 AR_PHY_FC_ENABLE_DAC_FIFO);
1631
1632 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1633 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | enableDacFifo;
1634
1635 if (IS_CHAN_HT40(chan)) {
1636 phymode |= AR_PHY_FC_DYN2040_EN;
1637
1638 if ((chan->chanmode == CHANNEL_A_HT40PLUS) ||
1639 (chan->chanmode == CHANNEL_G_HT40PLUS))
1640 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1641
1642 if (ah->extprotspacing == ATH9K_HT_EXTPROTSPACING_25)
1643 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1644 }
1645 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1646
1647 ath9k_hw_set11nmac2040(ah, macmode);
1648
1649 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1650 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1651 }
1652
1653 static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1654 struct ath9k_channel *chan)
1655 {
1656 if (OLC_FOR_AR9280_20_LATER) {
1657 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON))
1658 return false;
1659 } else if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
1660 return false;
1661
1662 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1663 return false;
1664
1665 ah->chip_fullsleep = false;
1666 ath9k_hw_init_pll(ah, chan);
1667 ath9k_hw_set_rfmode(ah, chan);
1668
1669 return true;
1670 }
1671
1672 static bool ath9k_hw_channel_change(struct ath_hw *ah,
1673 struct ath9k_channel *chan,
1674 enum ath9k_ht_macmode macmode)
1675 {
1676 struct ieee80211_channel *channel = chan->chan;
1677 u32 synthDelay, qnum;
1678
1679 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1680 if (ath9k_hw_numtxpending(ah, qnum)) {
1681 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE,
1682 "Transmit frames pending on queue %d\n", qnum);
1683 return false;
1684 }
1685 }
1686
1687 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1688 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1689 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1690 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1691 "Could not kill baseband RX\n");
1692 return false;
1693 }
1694
1695 ath9k_hw_set_regs(ah, chan, macmode);
1696
1697 if (AR_SREV_9280_10_OR_LATER(ah)) {
1698 ath9k_hw_ar9280_set_channel(ah, chan);
1699 } else {
1700 if (!(ath9k_hw_set_channel(ah, chan))) {
1701 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
1702 "Failed to set channel\n");
1703 return false;
1704 }
1705 }
1706
1707 ah->eep_ops->set_txpower(ah, chan,
1708 ath9k_regd_get_ctl(&ah->regulatory, chan),
1709 channel->max_antenna_gain * 2,
1710 channel->max_power * 2,
1711 min((u32) MAX_RATE_POWER,
1712 (u32) ah->regulatory.power_limit));
1713
1714 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
1715 if (IS_CHAN_B(chan))
1716 synthDelay = (4 * synthDelay) / 22;
1717 else
1718 synthDelay /= 10;
1719
1720 udelay(synthDelay + BASE_ACTIVATE_DELAY);
1721
1722 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
1723
1724 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
1725 ath9k_hw_set_delta_slope(ah, chan);
1726
1727 if (AR_SREV_9280_10_OR_LATER(ah))
1728 ath9k_hw_9280_spur_mitigate(ah, chan);
1729 else
1730 ath9k_hw_spur_mitigate(ah, chan);
1731
1732 if (!chan->oneTimeCalsDone)
1733 chan->oneTimeCalsDone = true;
1734
1735 return true;
1736 }
1737
1738 static void ath9k_hw_9280_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1739 {
1740 int bb_spur = AR_NO_SPUR;
1741 int freq;
1742 int bin, cur_bin;
1743 int bb_spur_off, spur_subchannel_sd;
1744 int spur_freq_sd;
1745 int spur_delta_phase;
1746 int denominator;
1747 int upper, lower, cur_vit_mask;
1748 int tmp, newVal;
1749 int i;
1750 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1751 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
1752 };
1753 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
1754 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
1755 };
1756 int inc[4] = { 0, 100, 0, 0 };
1757 struct chan_centers centers;
1758
1759 int8_t mask_m[123];
1760 int8_t mask_p[123];
1761 int8_t mask_amt;
1762 int tmp_mask;
1763 int cur_bb_spur;
1764 bool is2GHz = IS_CHAN_2GHZ(chan);
1765
1766 memset(&mask_m, 0, sizeof(int8_t) * 123);
1767 memset(&mask_p, 0, sizeof(int8_t) * 123);
1768
1769 ath9k_hw_get_channel_centers(ah, chan, &centers);
1770 freq = centers.synth_center;
1771
1772 ah->config.spurmode = SPUR_ENABLE_EEPROM;
1773 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
1774 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
1775
1776 if (is2GHz)
1777 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
1778 else
1779 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
1780
1781 if (AR_NO_SPUR == cur_bb_spur)
1782 break;
1783 cur_bb_spur = cur_bb_spur - freq;
1784
1785 if (IS_CHAN_HT40(chan)) {
1786 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
1787 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
1788 bb_spur = cur_bb_spur;
1789 break;
1790 }
1791 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
1792 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
1793 bb_spur = cur_bb_spur;
1794 break;
1795 }
1796 }
1797
1798 if (AR_NO_SPUR == bb_spur) {
1799 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1800 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1801 return;
1802 } else {
1803 REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
1804 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
1805 }
1806
1807 bin = bb_spur * 320;
1808
1809 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
1810
1811 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
1812 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
1813 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
1814 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
1815 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
1816
1817 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
1818 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
1819 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
1820 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
1821 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
1822 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
1823
1824 if (IS_CHAN_HT40(chan)) {
1825 if (bb_spur < 0) {
1826 spur_subchannel_sd = 1;
1827 bb_spur_off = bb_spur + 10;
1828 } else {
1829 spur_subchannel_sd = 0;
1830 bb_spur_off = bb_spur - 10;
1831 }
1832 } else {
1833 spur_subchannel_sd = 0;
1834 bb_spur_off = bb_spur;
1835 }
1836
1837 if (IS_CHAN_HT40(chan))
1838 spur_delta_phase =
1839 ((bb_spur * 262144) /
1840 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1841 else
1842 spur_delta_phase =
1843 ((bb_spur * 524288) /
1844 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
1845
1846 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
1847 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
1848
1849 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
1850 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
1851 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
1852 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
1853
1854 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
1855 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
1856
1857 cur_bin = -6000;
1858 upper = bin + 100;
1859 lower = bin - 100;
1860
1861 for (i = 0; i < 4; i++) {
1862 int pilot_mask = 0;
1863 int chan_mask = 0;
1864 int bp = 0;
1865 for (bp = 0; bp < 30; bp++) {
1866 if ((cur_bin > lower) && (cur_bin < upper)) {
1867 pilot_mask = pilot_mask | 0x1 << bp;
1868 chan_mask = chan_mask | 0x1 << bp;
1869 }
1870 cur_bin += 100;
1871 }
1872 cur_bin += inc[i];
1873 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
1874 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
1875 }
1876
1877 cur_vit_mask = 6100;
1878 upper = bin + 120;
1879 lower = bin - 120;
1880
1881 for (i = 0; i < 123; i++) {
1882 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
1883
1884 /* workaround for gcc bug #37014 */
1885 volatile int tmp_v = abs(cur_vit_mask - bin);
1886
1887 if (tmp_v < 75)
1888 mask_amt = 1;
1889 else
1890 mask_amt = 0;
1891 if (cur_vit_mask < 0)
1892 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
1893 else
1894 mask_p[cur_vit_mask / 100] = mask_amt;
1895 }
1896 cur_vit_mask -= 100;
1897 }
1898
1899 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
1900 | (mask_m[48] << 26) | (mask_m[49] << 24)
1901 | (mask_m[50] << 22) | (mask_m[51] << 20)
1902 | (mask_m[52] << 18) | (mask_m[53] << 16)
1903 | (mask_m[54] << 14) | (mask_m[55] << 12)
1904 | (mask_m[56] << 10) | (mask_m[57] << 8)
1905 | (mask_m[58] << 6) | (mask_m[59] << 4)
1906 | (mask_m[60] << 2) | (mask_m[61] << 0);
1907 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
1908 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
1909
1910 tmp_mask = (mask_m[31] << 28)
1911 | (mask_m[32] << 26) | (mask_m[33] << 24)
1912 | (mask_m[34] << 22) | (mask_m[35] << 20)
1913 | (mask_m[36] << 18) | (mask_m[37] << 16)
1914 | (mask_m[48] << 14) | (mask_m[39] << 12)
1915 | (mask_m[40] << 10) | (mask_m[41] << 8)
1916 | (mask_m[42] << 6) | (mask_m[43] << 4)
1917 | (mask_m[44] << 2) | (mask_m[45] << 0);
1918 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
1919 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
1920
1921 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
1922 | (mask_m[18] << 26) | (mask_m[18] << 24)
1923 | (mask_m[20] << 22) | (mask_m[20] << 20)
1924 | (mask_m[22] << 18) | (mask_m[22] << 16)
1925 | (mask_m[24] << 14) | (mask_m[24] << 12)
1926 | (mask_m[25] << 10) | (mask_m[26] << 8)
1927 | (mask_m[27] << 6) | (mask_m[28] << 4)
1928 | (mask_m[29] << 2) | (mask_m[30] << 0);
1929 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
1930 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
1931
1932 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
1933 | (mask_m[2] << 26) | (mask_m[3] << 24)
1934 | (mask_m[4] << 22) | (mask_m[5] << 20)
1935 | (mask_m[6] << 18) | (mask_m[7] << 16)
1936 | (mask_m[8] << 14) | (mask_m[9] << 12)
1937 | (mask_m[10] << 10) | (mask_m[11] << 8)
1938 | (mask_m[12] << 6) | (mask_m[13] << 4)
1939 | (mask_m[14] << 2) | (mask_m[15] << 0);
1940 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
1941 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
1942
1943 tmp_mask = (mask_p[15] << 28)
1944 | (mask_p[14] << 26) | (mask_p[13] << 24)
1945 | (mask_p[12] << 22) | (mask_p[11] << 20)
1946 | (mask_p[10] << 18) | (mask_p[9] << 16)
1947 | (mask_p[8] << 14) | (mask_p[7] << 12)
1948 | (mask_p[6] << 10) | (mask_p[5] << 8)
1949 | (mask_p[4] << 6) | (mask_p[3] << 4)
1950 | (mask_p[2] << 2) | (mask_p[1] << 0);
1951 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
1952 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
1953
1954 tmp_mask = (mask_p[30] << 28)
1955 | (mask_p[29] << 26) | (mask_p[28] << 24)
1956 | (mask_p[27] << 22) | (mask_p[26] << 20)
1957 | (mask_p[25] << 18) | (mask_p[24] << 16)
1958 | (mask_p[23] << 14) | (mask_p[22] << 12)
1959 | (mask_p[21] << 10) | (mask_p[20] << 8)
1960 | (mask_p[19] << 6) | (mask_p[18] << 4)
1961 | (mask_p[17] << 2) | (mask_p[16] << 0);
1962 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
1963 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
1964
1965 tmp_mask = (mask_p[45] << 28)
1966 | (mask_p[44] << 26) | (mask_p[43] << 24)
1967 | (mask_p[42] << 22) | (mask_p[41] << 20)
1968 | (mask_p[40] << 18) | (mask_p[39] << 16)
1969 | (mask_p[38] << 14) | (mask_p[37] << 12)
1970 | (mask_p[36] << 10) | (mask_p[35] << 8)
1971 | (mask_p[34] << 6) | (mask_p[33] << 4)
1972 | (mask_p[32] << 2) | (mask_p[31] << 0);
1973 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
1974 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
1975
1976 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
1977 | (mask_p[59] << 26) | (mask_p[58] << 24)
1978 | (mask_p[57] << 22) | (mask_p[56] << 20)
1979 | (mask_p[55] << 18) | (mask_p[54] << 16)
1980 | (mask_p[53] << 14) | (mask_p[52] << 12)
1981 | (mask_p[51] << 10) | (mask_p[50] << 8)
1982 | (mask_p[49] << 6) | (mask_p[48] << 4)
1983 | (mask_p[47] << 2) | (mask_p[46] << 0);
1984 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
1985 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
1986 }
1987
1988 static void ath9k_hw_spur_mitigate(struct ath_hw *ah, struct ath9k_channel *chan)
1989 {
1990 int bb_spur = AR_NO_SPUR;
1991 int bin, cur_bin;
1992 int spur_freq_sd;
1993 int spur_delta_phase;
1994 int denominator;
1995 int upper, lower, cur_vit_mask;
1996 int tmp, new;
1997 int i;
1998 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
1999 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
2000 };
2001 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
2002 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
2003 };
2004 int inc[4] = { 0, 100, 0, 0 };
2005
2006 int8_t mask_m[123];
2007 int8_t mask_p[123];
2008 int8_t mask_amt;
2009 int tmp_mask;
2010 int cur_bb_spur;
2011 bool is2GHz = IS_CHAN_2GHZ(chan);
2012
2013 memset(&mask_m, 0, sizeof(int8_t) * 123);
2014 memset(&mask_p, 0, sizeof(int8_t) * 123);
2015
2016 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
2017 cur_bb_spur = ah->eep_ops->get_spur_channel(ah, i, is2GHz);
2018 if (AR_NO_SPUR == cur_bb_spur)
2019 break;
2020 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
2021 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
2022 bb_spur = cur_bb_spur;
2023 break;
2024 }
2025 }
2026
2027 if (AR_NO_SPUR == bb_spur)
2028 return;
2029
2030 bin = bb_spur * 32;
2031
2032 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
2033 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
2034 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
2035 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
2036 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
2037
2038 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
2039
2040 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
2041 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
2042 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
2043 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
2044 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
2045 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
2046
2047 spur_delta_phase = ((bb_spur * 524288) / 100) &
2048 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
2049
2050 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
2051 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
2052
2053 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
2054 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
2055 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
2056 REG_WRITE(ah, AR_PHY_TIMING11, new);
2057
2058 cur_bin = -6000;
2059 upper = bin + 100;
2060 lower = bin - 100;
2061
2062 for (i = 0; i < 4; i++) {
2063 int pilot_mask = 0;
2064 int chan_mask = 0;
2065 int bp = 0;
2066 for (bp = 0; bp < 30; bp++) {
2067 if ((cur_bin > lower) && (cur_bin < upper)) {
2068 pilot_mask = pilot_mask | 0x1 << bp;
2069 chan_mask = chan_mask | 0x1 << bp;
2070 }
2071 cur_bin += 100;
2072 }
2073 cur_bin += inc[i];
2074 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
2075 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
2076 }
2077
2078 cur_vit_mask = 6100;
2079 upper = bin + 120;
2080 lower = bin - 120;
2081
2082 for (i = 0; i < 123; i++) {
2083 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
2084
2085 /* workaround for gcc bug #37014 */
2086 volatile int tmp_v = abs(cur_vit_mask - bin);
2087
2088 if (tmp_v < 75)
2089 mask_amt = 1;
2090 else
2091 mask_amt = 0;
2092 if (cur_vit_mask < 0)
2093 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
2094 else
2095 mask_p[cur_vit_mask / 100] = mask_amt;
2096 }
2097 cur_vit_mask -= 100;
2098 }
2099
2100 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
2101 | (mask_m[48] << 26) | (mask_m[49] << 24)
2102 | (mask_m[50] << 22) | (mask_m[51] << 20)
2103 | (mask_m[52] << 18) | (mask_m[53] << 16)
2104 | (mask_m[54] << 14) | (mask_m[55] << 12)
2105 | (mask_m[56] << 10) | (mask_m[57] << 8)
2106 | (mask_m[58] << 6) | (mask_m[59] << 4)
2107 | (mask_m[60] << 2) | (mask_m[61] << 0);
2108 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
2109 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
2110
2111 tmp_mask = (mask_m[31] << 28)
2112 | (mask_m[32] << 26) | (mask_m[33] << 24)
2113 | (mask_m[34] << 22) | (mask_m[35] << 20)
2114 | (mask_m[36] << 18) | (mask_m[37] << 16)
2115 | (mask_m[48] << 14) | (mask_m[39] << 12)
2116 | (mask_m[40] << 10) | (mask_m[41] << 8)
2117 | (mask_m[42] << 6) | (mask_m[43] << 4)
2118 | (mask_m[44] << 2) | (mask_m[45] << 0);
2119 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
2120 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
2121
2122 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
2123 | (mask_m[18] << 26) | (mask_m[18] << 24)
2124 | (mask_m[20] << 22) | (mask_m[20] << 20)
2125 | (mask_m[22] << 18) | (mask_m[22] << 16)
2126 | (mask_m[24] << 14) | (mask_m[24] << 12)
2127 | (mask_m[25] << 10) | (mask_m[26] << 8)
2128 | (mask_m[27] << 6) | (mask_m[28] << 4)
2129 | (mask_m[29] << 2) | (mask_m[30] << 0);
2130 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
2131 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
2132
2133 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
2134 | (mask_m[2] << 26) | (mask_m[3] << 24)
2135 | (mask_m[4] << 22) | (mask_m[5] << 20)
2136 | (mask_m[6] << 18) | (mask_m[7] << 16)
2137 | (mask_m[8] << 14) | (mask_m[9] << 12)
2138 | (mask_m[10] << 10) | (mask_m[11] << 8)
2139 | (mask_m[12] << 6) | (mask_m[13] << 4)
2140 | (mask_m[14] << 2) | (mask_m[15] << 0);
2141 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
2142 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
2143
2144 tmp_mask = (mask_p[15] << 28)
2145 | (mask_p[14] << 26) | (mask_p[13] << 24)
2146 | (mask_p[12] << 22) | (mask_p[11] << 20)
2147 | (mask_p[10] << 18) | (mask_p[9] << 16)
2148 | (mask_p[8] << 14) | (mask_p[7] << 12)
2149 | (mask_p[6] << 10) | (mask_p[5] << 8)
2150 | (mask_p[4] << 6) | (mask_p[3] << 4)
2151 | (mask_p[2] << 2) | (mask_p[1] << 0);
2152 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
2153 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
2154
2155 tmp_mask = (mask_p[30] << 28)
2156 | (mask_p[29] << 26) | (mask_p[28] << 24)
2157 | (mask_p[27] << 22) | (mask_p[26] << 20)
2158 | (mask_p[25] << 18) | (mask_p[24] << 16)
2159 | (mask_p[23] << 14) | (mask_p[22] << 12)
2160 | (mask_p[21] << 10) | (mask_p[20] << 8)
2161 | (mask_p[19] << 6) | (mask_p[18] << 4)
2162 | (mask_p[17] << 2) | (mask_p[16] << 0);
2163 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
2164 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
2165
2166 tmp_mask = (mask_p[45] << 28)
2167 | (mask_p[44] << 26) | (mask_p[43] << 24)
2168 | (mask_p[42] << 22) | (mask_p[41] << 20)
2169 | (mask_p[40] << 18) | (mask_p[39] << 16)
2170 | (mask_p[38] << 14) | (mask_p[37] << 12)
2171 | (mask_p[36] << 10) | (mask_p[35] << 8)
2172 | (mask_p[34] << 6) | (mask_p[33] << 4)
2173 | (mask_p[32] << 2) | (mask_p[31] << 0);
2174 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
2175 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
2176
2177 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
2178 | (mask_p[59] << 26) | (mask_p[58] << 24)
2179 | (mask_p[57] << 22) | (mask_p[56] << 20)
2180 | (mask_p[55] << 18) | (mask_p[54] << 16)
2181 | (mask_p[53] << 14) | (mask_p[52] << 12)
2182 | (mask_p[51] << 10) | (mask_p[50] << 8)
2183 | (mask_p[49] << 6) | (mask_p[48] << 4)
2184 | (mask_p[47] << 2) | (mask_p[46] << 0);
2185 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
2186 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
2187 }
2188
2189 static void ath9k_enable_rfkill(struct ath_hw *ah)
2190 {
2191 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
2192 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
2193
2194 REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
2195 AR_GPIO_INPUT_MUX2_RFSILENT);
2196
2197 ath9k_hw_cfg_gpio_input(ah, ah->rfkill_gpio);
2198 REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
2199 }
2200
2201 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2202 bool bChannelChange)
2203 {
2204 u32 saveLedState;
2205 struct ath_softc *sc = ah->ah_sc;
2206 struct ath9k_channel *curchan = ah->curchan;
2207 u32 saveDefAntenna;
2208 u32 macStaId1;
2209 int i, rx_chainmask, r;
2210
2211 ah->extprotspacing = sc->ht_extprotspacing;
2212 ah->txchainmask = sc->tx_chainmask;
2213 ah->rxchainmask = sc->rx_chainmask;
2214
2215 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2216 return -EIO;
2217
2218 if (curchan)
2219 ath9k_hw_getnf(ah, curchan);
2220
2221 if (bChannelChange &&
2222 (ah->chip_fullsleep != true) &&
2223 (ah->curchan != NULL) &&
2224 (chan->channel != ah->curchan->channel) &&
2225 ((chan->channelFlags & CHANNEL_ALL) ==
2226 (ah->curchan->channelFlags & CHANNEL_ALL)) &&
2227 (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
2228 !IS_CHAN_A_5MHZ_SPACED(ah->curchan)))) {
2229
2230 if (ath9k_hw_channel_change(ah, chan, sc->tx_chan_width)) {
2231 ath9k_hw_loadnf(ah, ah->curchan);
2232 ath9k_hw_start_nfcal(ah);
2233 return 0;
2234 }
2235 }
2236
2237 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
2238 if (saveDefAntenna == 0)
2239 saveDefAntenna = 1;
2240
2241 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
2242
2243 saveLedState = REG_READ(ah, AR_CFG_LED) &
2244 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
2245 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
2246
2247 ath9k_hw_mark_phy_inactive(ah);
2248
2249 if (!ath9k_hw_chip_reset(ah, chan)) {
2250 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Chip reset failed\n");
2251 return -EINVAL;
2252 }
2253
2254 if (AR_SREV_9280_10_OR_LATER(ah))
2255 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, AR_GPIO_JTAG_DISABLE);
2256
2257 r = ath9k_hw_process_ini(ah, chan, sc->tx_chan_width);
2258 if (r)
2259 return r;
2260
2261 /* Setup MFP options for CCMP */
2262 if (AR_SREV_9280_20_OR_LATER(ah)) {
2263 /* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
2264 * frames when constructing CCMP AAD. */
2265 REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
2266 0xc7ff);
2267 ah->sw_mgmt_crypto = false;
2268 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
2269 /* Disable hardware crypto for management frames */
2270 REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
2271 AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
2272 REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2273 AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
2274 ah->sw_mgmt_crypto = true;
2275 } else
2276 ah->sw_mgmt_crypto = true;
2277
2278 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
2279 ath9k_hw_set_delta_slope(ah, chan);
2280
2281 if (AR_SREV_9280_10_OR_LATER(ah))
2282 ath9k_hw_9280_spur_mitigate(ah, chan);
2283 else
2284 ath9k_hw_spur_mitigate(ah, chan);
2285
2286 ah->eep_ops->set_board_values(ah, chan);
2287
2288 ath9k_hw_decrease_chain_power(ah, chan);
2289
2290 REG_WRITE(ah, AR_STA_ID0, get_unaligned_le32(ah->macaddr));
2291 REG_WRITE(ah, AR_STA_ID1, get_unaligned_le16(ah->macaddr + 4)
2292 | macStaId1
2293 | AR_STA_ID1_RTS_USE_DEF
2294 | (ah->config.
2295 ack_6mb ? AR_STA_ID1_ACKCTS_6MB : 0)
2296 | ah->sta_id1_defaults);
2297 ath9k_hw_set_operating_mode(ah, ah->opmode);
2298
2299 REG_WRITE(ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
2300 REG_WRITE(ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
2301
2302 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
2303
2304 REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
2305 REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
2306 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
2307
2308 REG_WRITE(ah, AR_ISR, ~0);
2309
2310 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
2311
2312 if (AR_SREV_9280_10_OR_LATER(ah))
2313 ath9k_hw_ar9280_set_channel(ah, chan);
2314 else
2315 if (!(ath9k_hw_set_channel(ah, chan)))
2316 return -EIO;
2317
2318 for (i = 0; i < AR_NUM_DCU; i++)
2319 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
2320
2321 ah->intr_txqs = 0;
2322 for (i = 0; i < ah->caps.total_queues; i++)
2323 ath9k_hw_resettxqueue(ah, i);
2324
2325 ath9k_hw_init_interrupt_masks(ah, ah->opmode);
2326 ath9k_hw_init_qos(ah);
2327
2328 if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
2329 ath9k_enable_rfkill(ah);
2330
2331 ath9k_hw_init_user_settings(ah);
2332
2333 REG_WRITE(ah, AR_STA_ID1,
2334 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
2335
2336 ath9k_hw_set_dma(ah);
2337
2338 REG_WRITE(ah, AR_OBS, 8);
2339
2340 if (ah->config.intr_mitigation) {
2341 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
2342 REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
2343 }
2344
2345 ath9k_hw_init_bb(ah, chan);
2346
2347 if (!ath9k_hw_init_cal(ah, chan))
2348 return -EIO;;
2349
2350 rx_chainmask = ah->rxchainmask;
2351 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
2352 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
2353 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
2354 }
2355
2356 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2357
2358 if (AR_SREV_9100(ah)) {
2359 u32 mask;
2360 mask = REG_READ(ah, AR_CFG);
2361 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2362 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2363 "CFG Byte Swap Set 0x%x\n", mask);
2364 } else {
2365 mask =
2366 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2367 REG_WRITE(ah, AR_CFG, mask);
2368 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
2369 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2370 }
2371 } else {
2372 #ifdef __BIG_ENDIAN
2373 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
2374 #endif
2375 }
2376
2377 return 0;
2378 }
2379
2380 /************************/
2381 /* Key Cache Management */
2382 /************************/
2383
2384 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2385 {
2386 u32 keyType;
2387
2388 if (entry >= ah->caps.keycache_size) {
2389 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2390 "keychache entry %u out of range\n", entry);
2391 return false;
2392 }
2393
2394 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
2395
2396 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
2397 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
2398 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
2399 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
2400 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
2401 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
2402 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
2403 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
2404
2405 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2406 u16 micentry = entry + 64;
2407
2408 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
2409 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2410 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
2411 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2412
2413 }
2414
2415 if (ah->curchan == NULL)
2416 return true;
2417
2418 return true;
2419 }
2420
2421 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2422 {
2423 u32 macHi, macLo;
2424
2425 if (entry >= ah->caps.keycache_size) {
2426 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2427 "keychache entry %u out of range\n", entry);
2428 return false;
2429 }
2430
2431 if (mac != NULL) {
2432 macHi = (mac[5] << 8) | mac[4];
2433 macLo = (mac[3] << 24) |
2434 (mac[2] << 16) |
2435 (mac[1] << 8) |
2436 mac[0];
2437 macLo >>= 1;
2438 macLo |= (macHi & 1) << 31;
2439 macHi >>= 1;
2440 } else {
2441 macLo = macHi = 0;
2442 }
2443 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
2444 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
2445
2446 return true;
2447 }
2448
2449 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2450 const struct ath9k_keyval *k,
2451 const u8 *mac)
2452 {
2453 const struct ath9k_hw_capabilities *pCap = &ah->caps;
2454 u32 key0, key1, key2, key3, key4;
2455 u32 keyType;
2456
2457 if (entry >= pCap->keycache_size) {
2458 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2459 "keycache entry %u out of range\n", entry);
2460 return false;
2461 }
2462
2463 switch (k->kv_type) {
2464 case ATH9K_CIPHER_AES_OCB:
2465 keyType = AR_KEYTABLE_TYPE_AES;
2466 break;
2467 case ATH9K_CIPHER_AES_CCM:
2468 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2469 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2470 "AES-CCM not supported by mac rev 0x%x\n",
2471 ah->hw_version.macRev);
2472 return false;
2473 }
2474 keyType = AR_KEYTABLE_TYPE_CCM;
2475 break;
2476 case ATH9K_CIPHER_TKIP:
2477 keyType = AR_KEYTABLE_TYPE_TKIP;
2478 if (ATH9K_IS_MIC_ENABLED(ah)
2479 && entry + 64 >= pCap->keycache_size) {
2480 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2481 "entry %u inappropriate for TKIP\n", entry);
2482 return false;
2483 }
2484 break;
2485 case ATH9K_CIPHER_WEP:
2486 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2487 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2488 "WEP key length %u too small\n", k->kv_len);
2489 return false;
2490 }
2491 if (k->kv_len <= WLAN_KEY_LEN_WEP40)
2492 keyType = AR_KEYTABLE_TYPE_40;
2493 else if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2494 keyType = AR_KEYTABLE_TYPE_104;
2495 else
2496 keyType = AR_KEYTABLE_TYPE_128;
2497 break;
2498 case ATH9K_CIPHER_CLR:
2499 keyType = AR_KEYTABLE_TYPE_CLR;
2500 break;
2501 default:
2502 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2503 "cipher %u not supported\n", k->kv_type);
2504 return false;
2505 }
2506
2507 key0 = get_unaligned_le32(k->kv_val + 0);
2508 key1 = get_unaligned_le16(k->kv_val + 4);
2509 key2 = get_unaligned_le32(k->kv_val + 6);
2510 key3 = get_unaligned_le16(k->kv_val + 10);
2511 key4 = get_unaligned_le32(k->kv_val + 12);
2512 if (k->kv_len <= WLAN_KEY_LEN_WEP104)
2513 key4 &= 0xff;
2514
2515 /*
2516 * Note: Key cache registers access special memory area that requires
2517 * two 32-bit writes to actually update the values in the internal
2518 * memory. Consequently, the exact order and pairs used here must be
2519 * maintained.
2520 */
2521
2522 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
2523 u16 micentry = entry + 64;
2524
2525 /*
2526 * Write inverted key[47:0] first to avoid Michael MIC errors
2527 * on frames that could be sent or received at the same time.
2528 * The correct key will be written in the end once everything
2529 * else is ready.
2530 */
2531 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
2532 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
2533
2534 /* Write key[95:48] */
2535 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2536 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2537
2538 /* Write key[127:96] and key type */
2539 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2540 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2541
2542 /* Write MAC address for the entry */
2543 (void) ath9k_hw_keysetmac(ah, entry, mac);
2544
2545 if (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) {
2546 /*
2547 * TKIP uses two key cache entries:
2548 * Michael MIC TX/RX keys in the same key cache entry
2549 * (idx = main index + 64):
2550 * key0 [31:0] = RX key [31:0]
2551 * key1 [15:0] = TX key [31:16]
2552 * key1 [31:16] = reserved
2553 * key2 [31:0] = RX key [63:32]
2554 * key3 [15:0] = TX key [15:0]
2555 * key3 [31:16] = reserved
2556 * key4 [31:0] = TX key [63:32]
2557 */
2558 u32 mic0, mic1, mic2, mic3, mic4;
2559
2560 mic0 = get_unaligned_le32(k->kv_mic + 0);
2561 mic2 = get_unaligned_le32(k->kv_mic + 4);
2562 mic1 = get_unaligned_le16(k->kv_txmic + 2) & 0xffff;
2563 mic3 = get_unaligned_le16(k->kv_txmic + 0) & 0xffff;
2564 mic4 = get_unaligned_le32(k->kv_txmic + 4);
2565
2566 /* Write RX[31:0] and TX[31:16] */
2567 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2568 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
2569
2570 /* Write RX[63:32] and TX[15:0] */
2571 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2572 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
2573
2574 /* Write TX[63:32] and keyType(reserved) */
2575 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
2576 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2577 AR_KEYTABLE_TYPE_CLR);
2578
2579 } else {
2580 /*
2581 * TKIP uses four key cache entries (two for group
2582 * keys):
2583 * Michael MIC TX/RX keys are in different key cache
2584 * entries (idx = main index + 64 for TX and
2585 * main index + 32 + 96 for RX):
2586 * key0 [31:0] = TX/RX MIC key [31:0]
2587 * key1 [31:0] = reserved
2588 * key2 [31:0] = TX/RX MIC key [63:32]
2589 * key3 [31:0] = reserved
2590 * key4 [31:0] = reserved
2591 *
2592 * Upper layer code will call this function separately
2593 * for TX and RX keys when these registers offsets are
2594 * used.
2595 */
2596 u32 mic0, mic2;
2597
2598 mic0 = get_unaligned_le32(k->kv_mic + 0);
2599 mic2 = get_unaligned_le32(k->kv_mic + 4);
2600
2601 /* Write MIC key[31:0] */
2602 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
2603 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
2604
2605 /* Write MIC key[63:32] */
2606 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
2607 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
2608
2609 /* Write TX[63:32] and keyType(reserved) */
2610 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
2611 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
2612 AR_KEYTABLE_TYPE_CLR);
2613 }
2614
2615 /* MAC address registers are reserved for the MIC entry */
2616 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
2617 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
2618
2619 /*
2620 * Write the correct (un-inverted) key[47:0] last to enable
2621 * TKIP now that all other registers are set with correct
2622 * values.
2623 */
2624 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2625 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2626 } else {
2627 /* Write key[47:0] */
2628 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
2629 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
2630
2631 /* Write key[95:48] */
2632 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
2633 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
2634
2635 /* Write key[127:96] and key type */
2636 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
2637 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
2638
2639 /* Write MAC address for the entry */
2640 (void) ath9k_hw_keysetmac(ah, entry, mac);
2641 }
2642
2643 return true;
2644 }
2645
2646 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry)
2647 {
2648 if (entry < ah->caps.keycache_size) {
2649 u32 val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
2650 if (val & AR_KEYTABLE_VALID)
2651 return true;
2652 }
2653 return false;
2654 }
2655
2656 /******************************/
2657 /* Power Management (Chipset) */
2658 /******************************/
2659
2660 static void ath9k_set_power_sleep(struct ath_hw *ah, int setChip)
2661 {
2662 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2663 if (setChip) {
2664 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2665 AR_RTC_FORCE_WAKE_EN);
2666 if (!AR_SREV_9100(ah))
2667 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2668
2669 REG_CLR_BIT(ah, (AR_RTC_RESET),
2670 AR_RTC_RESET_EN);
2671 }
2672 }
2673
2674 static void ath9k_set_power_network_sleep(struct ath_hw *ah, int setChip)
2675 {
2676 REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2677 if (setChip) {
2678 struct ath9k_hw_capabilities *pCap = &ah->caps;
2679
2680 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2681 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
2682 AR_RTC_FORCE_WAKE_ON_INT);
2683 } else {
2684 REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
2685 AR_RTC_FORCE_WAKE_EN);
2686 }
2687 }
2688 }
2689
2690 static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2691 {
2692 u32 val;
2693 int i;
2694
2695 if (setChip) {
2696 if ((REG_READ(ah, AR_RTC_STATUS) &
2697 AR_RTC_STATUS_M) == AR_RTC_STATUS_SHUTDOWN) {
2698 if (ath9k_hw_set_reset_reg(ah,
2699 ATH9K_RESET_POWER_ON) != true) {
2700 return false;
2701 }
2702 }
2703 if (AR_SREV_9100(ah))
2704 REG_SET_BIT(ah, AR_RTC_RESET,
2705 AR_RTC_RESET_EN);
2706
2707 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2708 AR_RTC_FORCE_WAKE_EN);
2709 udelay(50);
2710
2711 for (i = POWER_UP_TIME / 50; i > 0; i--) {
2712 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
2713 if (val == AR_RTC_STATUS_ON)
2714 break;
2715 udelay(50);
2716 REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
2717 AR_RTC_FORCE_WAKE_EN);
2718 }
2719 if (i == 0) {
2720 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2721 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2722 return false;
2723 }
2724 }
2725
2726 REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2727
2728 return true;
2729 }
2730
2731 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2732 {
2733 int status = true, setChip = true;
2734 static const char *modes[] = {
2735 "AWAKE",
2736 "FULL-SLEEP",
2737 "NETWORK SLEEP",
2738 "UNDEFINED"
2739 };
2740
2741 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s -> %s\n",
2742 modes[ah->power_mode], modes[mode]);
2743
2744 switch (mode) {
2745 case ATH9K_PM_AWAKE:
2746 status = ath9k_hw_set_power_awake(ah, setChip);
2747 break;
2748 case ATH9K_PM_FULL_SLEEP:
2749 ath9k_set_power_sleep(ah, setChip);
2750 ah->chip_fullsleep = true;
2751 break;
2752 case ATH9K_PM_NETWORK_SLEEP:
2753 ath9k_set_power_network_sleep(ah, setChip);
2754 break;
2755 default:
2756 DPRINTF(ah->ah_sc, ATH_DBG_FATAL,
2757 "Unknown power mode %u\n", mode);
2758 return false;
2759 }
2760 ah->power_mode = mode;
2761
2762 return status;
2763 }
2764
2765 /*
2766 * Helper for ASPM support.
2767 *
2768 * Disable PLL when in L0s as well as receiver clock when in L1.
2769 * This power saving option must be enabled through the SerDes.
2770 *
2771 * Programming the SerDes must go through the same 288 bit serial shift
2772 * register as the other analog registers. Hence the 9 writes.
2773 */
2774 void ath9k_hw_configpcipowersave(struct ath_hw *ah, int restore)
2775 {
2776 u8 i;
2777
2778 if (ah->is_pciexpress != true)
2779 return;
2780
2781 /* Do not touch SerDes registers */
2782 if (ah->config.pcie_powersave_enable == 2)
2783 return;
2784
2785 /* Nothing to do on restore for 11N */
2786 if (restore)
2787 return;
2788
2789 if (AR_SREV_9280_20_OR_LATER(ah)) {
2790 /*
2791 * AR9280 2.0 or later chips use SerDes values from the
2792 * initvals.h initialized depending on chipset during
2793 * ath9k_hw_do_attach()
2794 */
2795 for (i = 0; i < ah->iniPcieSerdes.ia_rows; i++) {
2796 REG_WRITE(ah, INI_RA(&ah->iniPcieSerdes, i, 0),
2797 INI_RA(&ah->iniPcieSerdes, i, 1));
2798 }
2799 } else if (AR_SREV_9280(ah) &&
2800 (ah->hw_version.macRev == AR_SREV_REVISION_9280_10)) {
2801 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
2802 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2803
2804 /* RX shut off when elecidle is asserted */
2805 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
2806 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
2807 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
2808
2809 /* Shut off CLKREQ active in L1 */
2810 if (ah->config.pcie_clock_req)
2811 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
2812 else
2813 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
2814
2815 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2816 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2817 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
2818
2819 /* Load the new settings */
2820 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2821
2822 } else {
2823 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
2824 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
2825
2826 /* RX shut off when elecidle is asserted */
2827 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
2828 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
2829 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
2830
2831 /*
2832 * Ignore ah->ah_config.pcie_clock_req setting for
2833 * pre-AR9280 11n
2834 */
2835 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
2836
2837 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
2838 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
2839 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
2840
2841 /* Load the new settings */
2842 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
2843 }
2844
2845 udelay(1000);
2846
2847 /* set bit 19 to allow forcing of pcie core into L1 state */
2848 REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
2849
2850 /* Several PCIe massages to ensure proper behaviour */
2851 if (ah->config.pcie_waen) {
2852 REG_WRITE(ah, AR_WA, ah->config.pcie_waen);
2853 } else {
2854 if (AR_SREV_9285(ah))
2855 REG_WRITE(ah, AR_WA, AR9285_WA_DEFAULT);
2856 /*
2857 * On AR9280 chips bit 22 of 0x4004 needs to be set to
2858 * otherwise card may disappear.
2859 */
2860 else if (AR_SREV_9280(ah))
2861 REG_WRITE(ah, AR_WA, AR9280_WA_DEFAULT);
2862 else
2863 REG_WRITE(ah, AR_WA, AR_WA_DEFAULT);
2864 }
2865 }
2866
2867 /**********************/
2868 /* Interrupt Handling */
2869 /**********************/
2870
2871 bool ath9k_hw_intrpend(struct ath_hw *ah)
2872 {
2873 u32 host_isr;
2874
2875 if (AR_SREV_9100(ah))
2876 return true;
2877
2878 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
2879 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
2880 return true;
2881
2882 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
2883 if ((host_isr & AR_INTR_SYNC_DEFAULT)
2884 && (host_isr != AR_INTR_SPURIOUS))
2885 return true;
2886
2887 return false;
2888 }
2889
2890 bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
2891 {
2892 u32 isr = 0;
2893 u32 mask2 = 0;
2894 struct ath9k_hw_capabilities *pCap = &ah->caps;
2895 u32 sync_cause = 0;
2896 bool fatal_int = false;
2897
2898 if (!AR_SREV_9100(ah)) {
2899 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
2900 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
2901 == AR_RTC_STATUS_ON) {
2902 isr = REG_READ(ah, AR_ISR);
2903 }
2904 }
2905
2906 sync_cause = REG_READ(ah, AR_INTR_SYNC_CAUSE) &
2907 AR_INTR_SYNC_DEFAULT;
2908
2909 *masked = 0;
2910
2911 if (!isr && !sync_cause)
2912 return false;
2913 } else {
2914 *masked = 0;
2915 isr = REG_READ(ah, AR_ISR);
2916 }
2917
2918 if (isr) {
2919 if (isr & AR_ISR_BCNMISC) {
2920 u32 isr2;
2921 isr2 = REG_READ(ah, AR_ISR_S2);
2922 if (isr2 & AR_ISR_S2_TIM)
2923 mask2 |= ATH9K_INT_TIM;
2924 if (isr2 & AR_ISR_S2_DTIM)
2925 mask2 |= ATH9K_INT_DTIM;
2926 if (isr2 & AR_ISR_S2_DTIMSYNC)
2927 mask2 |= ATH9K_INT_DTIMSYNC;
2928 if (isr2 & (AR_ISR_S2_CABEND))
2929 mask2 |= ATH9K_INT_CABEND;
2930 if (isr2 & AR_ISR_S2_GTT)
2931 mask2 |= ATH9K_INT_GTT;
2932 if (isr2 & AR_ISR_S2_CST)
2933 mask2 |= ATH9K_INT_CST;
2934 if (isr2 & AR_ISR_S2_TSFOOR)
2935 mask2 |= ATH9K_INT_TSFOOR;
2936 }
2937
2938 isr = REG_READ(ah, AR_ISR_RAC);
2939 if (isr == 0xffffffff) {
2940 *masked = 0;
2941 return false;
2942 }
2943
2944 *masked = isr & ATH9K_INT_COMMON;
2945
2946 if (ah->config.intr_mitigation) {
2947 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
2948 *masked |= ATH9K_INT_RX;
2949 }
2950
2951 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
2952 *masked |= ATH9K_INT_RX;
2953 if (isr &
2954 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
2955 AR_ISR_TXEOL)) {
2956 u32 s0_s, s1_s;
2957
2958 *masked |= ATH9K_INT_TX;
2959
2960 s0_s = REG_READ(ah, AR_ISR_S0_S);
2961 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
2962 ah->intr_txqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
2963
2964 s1_s = REG_READ(ah, AR_ISR_S1_S);
2965 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
2966 ah->intr_txqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
2967 }
2968
2969 if (isr & AR_ISR_RXORN) {
2970 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
2971 "receive FIFO overrun interrupt\n");
2972 }
2973
2974 if (!AR_SREV_9100(ah)) {
2975 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2976 u32 isr5 = REG_READ(ah, AR_ISR_S5_S);
2977 if (isr5 & AR_ISR_S5_TIM_TIMER)
2978 *masked |= ATH9K_INT_TIM_TIMER;
2979 }
2980 }
2981
2982 *masked |= mask2;
2983 }
2984
2985 if (AR_SREV_9100(ah))
2986 return true;
2987
2988 if (sync_cause) {
2989 fatal_int =
2990 (sync_cause &
2991 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
2992 ? true : false;
2993
2994 if (fatal_int) {
2995 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
2996 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
2997 "received PCI FATAL interrupt\n");
2998 }
2999 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
3000 DPRINTF(ah->ah_sc, ATH_DBG_ANY,
3001 "received PCI PERR interrupt\n");
3002 }
3003 *masked |= ATH9K_INT_FATAL;
3004 }
3005 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
3006 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3007 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
3008 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
3009 REG_WRITE(ah, AR_RC, 0);
3010 *masked |= ATH9K_INT_FATAL;
3011 }
3012 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
3013 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT,
3014 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
3015 }
3016
3017 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
3018 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
3019 }
3020
3021 return true;
3022 }
3023
3024 enum ath9k_int ath9k_hw_intrget(struct ath_hw *ah)
3025 {
3026 return ah->mask_reg;
3027 }
3028
3029 enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3030 {
3031 u32 omask = ah->mask_reg;
3032 u32 mask, mask2;
3033 struct ath9k_hw_capabilities *pCap = &ah->caps;
3034
3035 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
3036
3037 if (omask & ATH9K_INT_GLOBAL) {
3038 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n");
3039 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3040 (void) REG_READ(ah, AR_IER);
3041 if (!AR_SREV_9100(ah)) {
3042 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
3043 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
3044
3045 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
3046 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
3047 }
3048 }
3049
3050 mask = ints & ATH9K_INT_COMMON;
3051 mask2 = 0;
3052
3053 if (ints & ATH9K_INT_TX) {
3054 if (ah->txok_interrupt_mask)
3055 mask |= AR_IMR_TXOK;
3056 if (ah->txdesc_interrupt_mask)
3057 mask |= AR_IMR_TXDESC;
3058 if (ah->txerr_interrupt_mask)
3059 mask |= AR_IMR_TXERR;
3060 if (ah->txeol_interrupt_mask)
3061 mask |= AR_IMR_TXEOL;
3062 }
3063 if (ints & ATH9K_INT_RX) {
3064 mask |= AR_IMR_RXERR;
3065 if (ah->config.intr_mitigation)
3066 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
3067 else
3068 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
3069 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
3070 mask |= AR_IMR_GENTMR;
3071 }
3072
3073 if (ints & (ATH9K_INT_BMISC)) {
3074 mask |= AR_IMR_BCNMISC;
3075 if (ints & ATH9K_INT_TIM)
3076 mask2 |= AR_IMR_S2_TIM;
3077 if (ints & ATH9K_INT_DTIM)
3078 mask2 |= AR_IMR_S2_DTIM;
3079 if (ints & ATH9K_INT_DTIMSYNC)
3080 mask2 |= AR_IMR_S2_DTIMSYNC;
3081 if (ints & ATH9K_INT_CABEND)
3082 mask2 |= AR_IMR_S2_CABEND;
3083 if (ints & ATH9K_INT_TSFOOR)
3084 mask2 |= AR_IMR_S2_TSFOOR;
3085 }
3086
3087 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
3088 mask |= AR_IMR_BCNMISC;
3089 if (ints & ATH9K_INT_GTT)
3090 mask2 |= AR_IMR_S2_GTT;
3091 if (ints & ATH9K_INT_CST)
3092 mask2 |= AR_IMR_S2_CST;
3093 }
3094
3095 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3096 REG_WRITE(ah, AR_IMR, mask);
3097 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3098 AR_IMR_S2_DTIM |
3099 AR_IMR_S2_DTIMSYNC |
3100 AR_IMR_S2_CABEND |
3101 AR_IMR_S2_CABTO |
3102 AR_IMR_S2_TSFOOR |
3103 AR_IMR_S2_GTT | AR_IMR_S2_CST);
3104 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
3105 ah->mask_reg = ints;
3106
3107 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
3108 if (ints & ATH9K_INT_TIM_TIMER)
3109 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3110 else
3111 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
3112 }
3113
3114 if (ints & ATH9K_INT_GLOBAL) {
3115 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n");
3116 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3117 if (!AR_SREV_9100(ah)) {
3118 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
3119 AR_INTR_MAC_IRQ);
3120 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
3121
3122
3123 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
3124 AR_INTR_SYNC_DEFAULT);
3125 REG_WRITE(ah, AR_INTR_SYNC_MASK,
3126 AR_INTR_SYNC_DEFAULT);
3127 }
3128 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3129 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3130 }
3131
3132 return omask;
3133 }
3134
3135 /*******************/
3136 /* Beacon Handling */
3137 /*******************/
3138
3139 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3140 {
3141 int flags = 0;
3142
3143 ah->beacon_interval = beacon_period;
3144
3145 switch (ah->opmode) {
3146 case NL80211_IFTYPE_STATION:
3147 case NL80211_IFTYPE_MONITOR:
3148 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3149 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
3150 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
3151 flags |= AR_TBTT_TIMER_EN;
3152 break;
3153 case NL80211_IFTYPE_ADHOC:
3154 case NL80211_IFTYPE_MESH_POINT:
3155 REG_SET_BIT(ah, AR_TXCFG,
3156 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
3157 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
3158 TU_TO_USEC(next_beacon +
3159 (ah->atim_window ? ah->
3160 atim_window : 1)));
3161 flags |= AR_NDP_TIMER_EN;
3162 case NL80211_IFTYPE_AP:
3163 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
3164 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
3165 TU_TO_USEC(next_beacon -
3166 ah->config.
3167 dma_beacon_response_time));
3168 REG_WRITE(ah, AR_NEXT_SWBA,
3169 TU_TO_USEC(next_beacon -
3170 ah->config.
3171 sw_beacon_response_time));
3172 flags |=
3173 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3174 break;
3175 default:
3176 DPRINTF(ah->ah_sc, ATH_DBG_BEACON,
3177 "%s: unsupported opmode: %d\n",
3178 __func__, ah->opmode);
3179 return;
3180 break;
3181 }
3182
3183 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3184 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
3185 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
3186 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
3187
3188 beacon_period &= ~ATH9K_BEACON_ENA;
3189 if (beacon_period & ATH9K_BEACON_RESET_TSF) {
3190 beacon_period &= ~ATH9K_BEACON_RESET_TSF;
3191 ath9k_hw_reset_tsf(ah);
3192 }
3193
3194 REG_SET_BIT(ah, AR_TIMER_MODE, flags);
3195 }
3196
3197 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3198 const struct ath9k_beacon_state *bs)
3199 {
3200 u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
3201 struct ath9k_hw_capabilities *pCap = &ah->caps;
3202
3203 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
3204
3205 REG_WRITE(ah, AR_BEACON_PERIOD,
3206 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3207 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
3208 TU_TO_USEC(bs->bs_intval & ATH9K_BEACON_PERIOD));
3209
3210 REG_RMW_FIELD(ah, AR_RSSI_THR,
3211 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
3212
3213 beaconintval = bs->bs_intval & ATH9K_BEACON_PERIOD;
3214
3215 if (bs->bs_sleepduration > beaconintval)
3216 beaconintval = bs->bs_sleepduration;
3217
3218 dtimperiod = bs->bs_dtimperiod;
3219 if (bs->bs_sleepduration > dtimperiod)
3220 dtimperiod = bs->bs_sleepduration;
3221
3222 if (beaconintval == dtimperiod)
3223 nextTbtt = bs->bs_nextdtim;
3224 else
3225 nextTbtt = bs->bs_nexttbtt;
3226
3227 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3228 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3229 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3230 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3231
3232 REG_WRITE(ah, AR_NEXT_DTIM,
3233 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
3234 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
3235
3236 REG_WRITE(ah, AR_SLEEP1,
3237 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
3238 | AR_SLEEP1_ASSUME_DTIM);
3239
3240 if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
3241 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
3242 else
3243 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
3244
3245 REG_WRITE(ah, AR_SLEEP2,
3246 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
3247
3248 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
3249 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
3250
3251 REG_SET_BIT(ah, AR_TIMER_MODE,
3252 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
3253 AR_DTIM_TIMER_EN);
3254
3255 /* TSF Out of Range Threshold */
3256 REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
3257 }
3258
3259 /*******************/
3260 /* HW Capabilities */
3261 /*******************/
3262
3263 void ath9k_hw_fill_cap_info(struct ath_hw *ah)
3264 {
3265 struct ath9k_hw_capabilities *pCap = &ah->caps;
3266 u16 capField = 0, eeval;
3267
3268 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
3269 ah->regulatory.current_rd = eeval;
3270
3271 eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_1);
3272 if (AR_SREV_9285_10_OR_LATER(ah))
3273 eeval |= AR9285_RDEXT_DEFAULT;
3274 ah->regulatory.current_rd_ext = eeval;
3275
3276 capField = ah->eep_ops->get_eeprom(ah, EEP_OP_CAP);
3277
3278 if (ah->opmode != NL80211_IFTYPE_AP &&
3279 ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
3280 if (ah->regulatory.current_rd == 0x64 ||
3281 ah->regulatory.current_rd == 0x65)
3282 ah->regulatory.current_rd += 5;
3283 else if (ah->regulatory.current_rd == 0x41)
3284 ah->regulatory.current_rd = 0x43;
3285 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY,
3286 "regdomain mapped to 0x%x\n", ah->regulatory.current_rd);
3287 }
3288
3289 eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
3290 bitmap_zero(pCap->wireless_modes, ATH9K_MODE_MAX);
3291
3292 if (eeval & AR5416_OPFLAGS_11A) {
3293 set_bit(ATH9K_MODE_11A, pCap->wireless_modes);
3294 if (ah->config.ht_enable) {
3295 if (!(eeval & AR5416_OPFLAGS_N_5G_HT20))
3296 set_bit(ATH9K_MODE_11NA_HT20,
3297 pCap->wireless_modes);
3298 if (!(eeval & AR5416_OPFLAGS_N_5G_HT40)) {
3299 set_bit(ATH9K_MODE_11NA_HT40PLUS,
3300 pCap->wireless_modes);
3301 set_bit(ATH9K_MODE_11NA_HT40MINUS,
3302 pCap->wireless_modes);
3303 }
3304 }
3305 }
3306
3307 if (eeval & AR5416_OPFLAGS_11G) {
3308 set_bit(ATH9K_MODE_11B, pCap->wireless_modes);
3309 set_bit(ATH9K_MODE_11G, pCap->wireless_modes);
3310 if (ah->config.ht_enable) {
3311 if (!(eeval & AR5416_OPFLAGS_N_2G_HT20))
3312 set_bit(ATH9K_MODE_11NG_HT20,
3313 pCap->wireless_modes);
3314 if (!(eeval & AR5416_OPFLAGS_N_2G_HT40)) {
3315 set_bit(ATH9K_MODE_11NG_HT40PLUS,
3316 pCap->wireless_modes);
3317 set_bit(ATH9K_MODE_11NG_HT40MINUS,
3318 pCap->wireless_modes);
3319 }
3320 }
3321 }
3322
3323 pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
3324 if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
3325 !(eeval & AR5416_OPFLAGS_11A))
3326 pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
3327 else
3328 pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
3329
3330 if (!(AR_SREV_9280(ah) && (ah->hw_version.macRev == 0)))
3331 ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
3332
3333 pCap->low_2ghz_chan = 2312;
3334 pCap->high_2ghz_chan = 2732;
3335
3336 pCap->low_5ghz_chan = 4920;
3337 pCap->high_5ghz_chan = 6100;
3338
3339 pCap->hw_caps &= ~ATH9K_HW_CAP_CIPHER_CKIP;
3340 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_TKIP;
3341 pCap->hw_caps |= ATH9K_HW_CAP_CIPHER_AESCCM;
3342
3343 pCap->hw_caps &= ~ATH9K_HW_CAP_MIC_CKIP;
3344 pCap->hw_caps |= ATH9K_HW_CAP_MIC_TKIP;
3345 pCap->hw_caps |= ATH9K_HW_CAP_MIC_AESCCM;
3346
3347 if (ah->config.ht_enable)
3348 pCap->hw_caps |= ATH9K_HW_CAP_HT;
3349 else
3350 pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
3351
3352 pCap->hw_caps |= ATH9K_HW_CAP_GTT;
3353 pCap->hw_caps |= ATH9K_HW_CAP_VEOL;
3354 pCap->hw_caps |= ATH9K_HW_CAP_BSSIDMASK;
3355 pCap->hw_caps &= ~ATH9K_HW_CAP_MCAST_KEYSEARCH;
3356
3357 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3358 pCap->total_queues =
3359 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3360 else
3361 pCap->total_queues = ATH9K_NUM_TX_QUEUES;
3362
3363 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3364 pCap->keycache_size =
3365 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3366 else
3367 pCap->keycache_size = AR_KEYTABLE_SIZE;
3368
3369 pCap->hw_caps |= ATH9K_HW_CAP_FASTCC;
3370 pCap->tx_triglevel_max = MAX_TX_FIFO_THRESHOLD;
3371
3372 if (AR_SREV_9285_10_OR_LATER(ah))
3373 pCap->num_gpio_pins = AR9285_NUM_GPIO;
3374 else if (AR_SREV_9280_10_OR_LATER(ah))
3375 pCap->num_gpio_pins = AR928X_NUM_GPIO;
3376 else
3377 pCap->num_gpio_pins = AR_NUM_GPIO;
3378
3379 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3380 pCap->hw_caps |= ATH9K_HW_CAP_CST;
3381 pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
3382 } else {
3383 pCap->rts_aggr_limit = (8 * 1024);
3384 }
3385
3386 pCap->hw_caps |= ATH9K_HW_CAP_ENHANCEDPM;
3387
3388 #if defined(CONFIG_RFKILL) || defined(CONFIG_RFKILL_MODULE)
3389 ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
3390 if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
3391 ah->rfkill_gpio =
3392 MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
3393 ah->rfkill_polarity =
3394 MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
3395
3396 pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
3397 }
3398 #endif
3399
3400 if ((ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) ||
3401 (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE) ||
3402 (ah->hw_version.macVersion == AR_SREV_VERSION_9160) ||
3403 (ah->hw_version.macVersion == AR_SREV_VERSION_9100) ||
3404 (ah->hw_version.macVersion == AR_SREV_VERSION_9280) ||
3405 (ah->hw_version.macVersion == AR_SREV_VERSION_9285))
3406 pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
3407 else
3408 pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
3409
3410 if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
3411 pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
3412 else
3413 pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
3414
3415 if (ah->regulatory.current_rd_ext & (1 << REG_EXT_JAPAN_MIDBAND)) {
3416 pCap->reg_cap =
3417 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3418 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3419 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3420 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3421 } else {
3422 pCap->reg_cap =
3423 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3424 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3425 }
3426
3427 pCap->reg_cap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3428
3429 pCap->num_antcfg_5ghz =
3430 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_5GHZ);
3431 pCap->num_antcfg_2ghz =
3432 ah->eep_ops->get_num_ant_config(ah, ATH9K_HAL_FREQ_BAND_2GHZ);
3433
3434 if (AR_SREV_9280_10_OR_LATER(ah) && btcoex_enable) {
3435 pCap->hw_caps |= ATH9K_HW_CAP_BT_COEX;
3436 ah->btactive_gpio = 6;
3437 ah->wlanactive_gpio = 5;
3438 }
3439 }
3440
3441 bool ath9k_hw_getcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3442 u32 capability, u32 *result)
3443 {
3444 switch (type) {
3445 case ATH9K_CAP_CIPHER:
3446 switch (capability) {
3447 case ATH9K_CIPHER_AES_CCM:
3448 case ATH9K_CIPHER_AES_OCB:
3449 case ATH9K_CIPHER_TKIP:
3450 case ATH9K_CIPHER_WEP:
3451 case ATH9K_CIPHER_MIC:
3452 case ATH9K_CIPHER_CLR:
3453 return true;
3454 default:
3455 return false;
3456 }
3457 case ATH9K_CAP_TKIP_MIC:
3458 switch (capability) {
3459 case 0:
3460 return true;
3461 case 1:
3462 return (ah->sta_id1_defaults &
3463 AR_STA_ID1_CRPT_MIC_ENABLE) ? true :
3464 false;
3465 }
3466 case ATH9K_CAP_TKIP_SPLIT:
3467 return (ah->misc_mode & AR_PCU_MIC_NEW_LOC_ENA) ?
3468 false : true;
3469 case ATH9K_CAP_DIVERSITY:
3470 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
3471 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
3472 true : false;
3473 case ATH9K_CAP_MCAST_KEYSRCH:
3474 switch (capability) {
3475 case 0:
3476 return true;
3477 case 1:
3478 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
3479 return false;
3480 } else {
3481 return (ah->sta_id1_defaults &
3482 AR_STA_ID1_MCAST_KSRCH) ? true :
3483 false;
3484 }
3485 }
3486 return false;
3487 case ATH9K_CAP_TXPOW:
3488 switch (capability) {
3489 case 0:
3490 return 0;
3491 case 1:
3492 *result = ah->regulatory.power_limit;
3493 return 0;
3494 case 2:
3495 *result = ah->regulatory.max_power_level;
3496 return 0;
3497 case 3:
3498 *result = ah->regulatory.tp_scale;
3499 return 0;
3500 }
3501 return false;
3502 case ATH9K_CAP_DS:
3503 return (AR_SREV_9280_20_OR_LATER(ah) &&
3504 (ah->eep_ops->get_eeprom(ah, EEP_RC_CHAIN_MASK) == 1))
3505 ? false : true;
3506 default:
3507 return false;
3508 }
3509 }
3510
3511 bool ath9k_hw_setcapability(struct ath_hw *ah, enum ath9k_capability_type type,
3512 u32 capability, u32 setting, int *status)
3513 {
3514 u32 v;
3515
3516 switch (type) {
3517 case ATH9K_CAP_TKIP_MIC:
3518 if (setting)
3519 ah->sta_id1_defaults |=
3520 AR_STA_ID1_CRPT_MIC_ENABLE;
3521 else
3522 ah->sta_id1_defaults &=
3523 ~AR_STA_ID1_CRPT_MIC_ENABLE;
3524 return true;
3525 case ATH9K_CAP_DIVERSITY:
3526 v = REG_READ(ah, AR_PHY_CCK_DETECT);
3527 if (setting)
3528 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3529 else
3530 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
3531 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
3532 return true;
3533 case ATH9K_CAP_MCAST_KEYSRCH:
3534 if (setting)
3535 ah->sta_id1_defaults |= AR_STA_ID1_MCAST_KSRCH;
3536 else
3537 ah->sta_id1_defaults &= ~AR_STA_ID1_MCAST_KSRCH;
3538 return true;
3539 default:
3540 return false;
3541 }
3542 }
3543
3544 /****************************/
3545 /* GPIO / RFKILL / Antennae */
3546 /****************************/
3547
3548 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah,
3549 u32 gpio, u32 type)
3550 {
3551 int addr;
3552 u32 gpio_shift, tmp;
3553
3554 if (gpio > 11)
3555 addr = AR_GPIO_OUTPUT_MUX3;
3556 else if (gpio > 5)
3557 addr = AR_GPIO_OUTPUT_MUX2;
3558 else
3559 addr = AR_GPIO_OUTPUT_MUX1;
3560
3561 gpio_shift = (gpio % 6) * 5;
3562
3563 if (AR_SREV_9280_20_OR_LATER(ah)
3564 || (addr != AR_GPIO_OUTPUT_MUX1)) {
3565 REG_RMW(ah, addr, (type << gpio_shift),
3566 (0x1f << gpio_shift));
3567 } else {
3568 tmp = REG_READ(ah, addr);
3569 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
3570 tmp &= ~(0x1f << gpio_shift);
3571 tmp |= (type << gpio_shift);
3572 REG_WRITE(ah, addr, tmp);
3573 }
3574 }
3575
3576 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio)
3577 {
3578 u32 gpio_shift;
3579
3580 ASSERT(gpio < ah->caps.num_gpio_pins);
3581
3582 gpio_shift = gpio << 1;
3583
3584 REG_RMW(ah,
3585 AR_GPIO_OE_OUT,
3586 (AR_GPIO_OE_OUT_DRV_NO << gpio_shift),
3587 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3588 }
3589
3590 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
3591 {
3592 #define MS_REG_READ(x, y) \
3593 (MS(REG_READ(ah, AR_GPIO_IN_OUT), x##_GPIO_IN_VAL) & (AR_GPIO_BIT(y)))
3594
3595 if (gpio >= ah->caps.num_gpio_pins)
3596 return 0xffffffff;
3597
3598 if (AR_SREV_9285_10_OR_LATER(ah))
3599 return MS_REG_READ(AR9285, gpio) != 0;
3600 else if (AR_SREV_9280_10_OR_LATER(ah))
3601 return MS_REG_READ(AR928X, gpio) != 0;
3602 else
3603 return MS_REG_READ(AR, gpio) != 0;
3604 }
3605
3606 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
3607 u32 ah_signal_type)
3608 {
3609 u32 gpio_shift;
3610
3611 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
3612
3613 gpio_shift = 2 * gpio;
3614
3615 REG_RMW(ah,
3616 AR_GPIO_OE_OUT,
3617 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
3618 (AR_GPIO_OE_OUT_DRV << gpio_shift));
3619 }
3620
3621 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
3622 {
3623 REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
3624 AR_GPIO_BIT(gpio));
3625 }
3626
3627 u32 ath9k_hw_getdefantenna(struct ath_hw *ah)
3628 {
3629 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
3630 }
3631
3632 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
3633 {
3634 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
3635 }
3636
3637 bool ath9k_hw_setantennaswitch(struct ath_hw *ah,
3638 enum ath9k_ant_setting settings,
3639 struct ath9k_channel *chan,
3640 u8 *tx_chainmask,
3641 u8 *rx_chainmask,
3642 u8 *antenna_cfgd)
3643 {
3644 static u8 tx_chainmask_cfg, rx_chainmask_cfg;
3645
3646 if (AR_SREV_9280(ah)) {
3647 if (!tx_chainmask_cfg) {
3648
3649 tx_chainmask_cfg = *tx_chainmask;
3650 rx_chainmask_cfg = *rx_chainmask;
3651 }
3652
3653 switch (settings) {
3654 case ATH9K_ANT_FIXED_A:
3655 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3656 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
3657 *antenna_cfgd = true;
3658 break;
3659 case ATH9K_ANT_FIXED_B:
3660 if (ah->caps.tx_chainmask >
3661 ATH9K_ANTENNA1_CHAINMASK) {
3662 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3663 }
3664 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
3665 *antenna_cfgd = true;
3666 break;
3667 case ATH9K_ANT_VARIABLE:
3668 *tx_chainmask = tx_chainmask_cfg;
3669 *rx_chainmask = rx_chainmask_cfg;
3670 *antenna_cfgd = true;
3671 break;
3672 default:
3673 break;
3674 }
3675 } else {
3676 ah->diversity_control = settings;
3677 }
3678
3679 return true;
3680 }
3681
3682 /*********************/
3683 /* General Operation */
3684 /*********************/
3685
3686 u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
3687 {
3688 u32 bits = REG_READ(ah, AR_RX_FILTER);
3689 u32 phybits = REG_READ(ah, AR_PHY_ERR);
3690
3691 if (phybits & AR_PHY_ERR_RADAR)
3692 bits |= ATH9K_RX_FILTER_PHYRADAR;
3693 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
3694 bits |= ATH9K_RX_FILTER_PHYERR;
3695
3696 return bits;
3697 }
3698
3699 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
3700 {
3701 u32 phybits;
3702
3703 REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
3704 phybits = 0;
3705 if (bits & ATH9K_RX_FILTER_PHYRADAR)
3706 phybits |= AR_PHY_ERR_RADAR;
3707 if (bits & ATH9K_RX_FILTER_PHYERR)
3708 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
3709 REG_WRITE(ah, AR_PHY_ERR, phybits);
3710
3711 if (phybits)
3712 REG_WRITE(ah, AR_RXCFG,
3713 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
3714 else
3715 REG_WRITE(ah, AR_RXCFG,
3716 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
3717 }
3718
3719 bool ath9k_hw_phy_disable(struct ath_hw *ah)
3720 {
3721 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM);
3722 }
3723
3724 bool ath9k_hw_disable(struct ath_hw *ah)
3725 {
3726 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
3727 return false;
3728
3729 return ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD);
3730 }
3731
3732 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit)
3733 {
3734 struct ath9k_channel *chan = ah->curchan;
3735 struct ieee80211_channel *channel = chan->chan;
3736
3737 ah->regulatory.power_limit = min(limit, (u32) MAX_RATE_POWER);
3738
3739 ah->eep_ops->set_txpower(ah, chan,
3740 ath9k_regd_get_ctl(&ah->regulatory, chan),
3741 channel->max_antenna_gain * 2,
3742 channel->max_power * 2,
3743 min((u32) MAX_RATE_POWER,
3744 (u32) ah->regulatory.power_limit));
3745 }
3746
3747 void ath9k_hw_setmac(struct ath_hw *ah, const u8 *mac)
3748 {
3749 memcpy(ah->macaddr, mac, ETH_ALEN);
3750 }
3751
3752 void ath9k_hw_setopmode(struct ath_hw *ah)
3753 {
3754 ath9k_hw_set_operating_mode(ah, ah->opmode);
3755 }
3756
3757 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
3758 {
3759 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
3760 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
3761 }
3762
3763 void ath9k_hw_setbssidmask(struct ath_softc *sc)
3764 {
3765 REG_WRITE(sc->sc_ah, AR_BSSMSKL, get_unaligned_le32(sc->bssidmask));
3766 REG_WRITE(sc->sc_ah, AR_BSSMSKU, get_unaligned_le16(sc->bssidmask + 4));
3767 }
3768
3769 void ath9k_hw_write_associd(struct ath_softc *sc)
3770 {
3771 REG_WRITE(sc->sc_ah, AR_BSS_ID0, get_unaligned_le32(sc->curbssid));
3772 REG_WRITE(sc->sc_ah, AR_BSS_ID1, get_unaligned_le16(sc->curbssid + 4) |
3773 ((sc->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3774 }
3775
3776 u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3777 {
3778 u64 tsf;
3779
3780 tsf = REG_READ(ah, AR_TSF_U32);
3781 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
3782
3783 return tsf;
3784 }
3785
3786 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3787 {
3788 REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3789 REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3790 }
3791
3792 void ath9k_hw_reset_tsf(struct ath_hw *ah)
3793 {
3794 int count;
3795
3796 count = 0;
3797 while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
3798 count++;
3799 if (count > 10) {
3800 DPRINTF(ah->ah_sc, ATH_DBG_RESET,
3801 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3802 break;
3803 }
3804 udelay(10);
3805 }
3806 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3807 }
3808
3809 bool ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
3810 {
3811 if (setting)
3812 ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3813 else
3814 ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3815
3816 return true;
3817 }
3818
3819 bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
3820 {
3821 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
3822 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us);
3823 ah->slottime = (u32) -1;
3824 return false;
3825 } else {
3826 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
3827 ah->slottime = us;
3828 return true;
3829 }
3830 }
3831
3832 void ath9k_hw_set11nmac2040(struct ath_hw *ah, enum ath9k_ht_macmode mode)
3833 {
3834 u32 macmode;
3835
3836 if (mode == ATH9K_HT_MACMODE_2040 &&
3837 !ah->config.cwm_ignore_extcca)
3838 macmode = AR_2040_JOINED_RX_CLEAR;
3839 else
3840 macmode = 0;
3841
3842 REG_WRITE(ah, AR_2040_MODE, macmode);
3843 }
3844
3845 /***************************/
3846 /* Bluetooth Coexistence */
3847 /***************************/
3848
3849 void ath9k_hw_btcoex_enable(struct ath_hw *ah)
3850 {
3851 /* connect bt_active to baseband */
3852 REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3853 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF |
3854 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF));
3855
3856 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
3857 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB);
3858
3859 /* Set input mux for bt_active to gpio pin */
3860 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1,
3861 AR_GPIO_INPUT_MUX1_BT_ACTIVE,
3862 ah->btactive_gpio);
3863
3864 /* Configure the desired gpio port for input */
3865 ath9k_hw_cfg_gpio_input(ah, ah->btactive_gpio);
3866
3867 /* Configure the desired GPIO port for TX_FRAME output */
3868 ath9k_hw_cfg_output(ah, ah->wlanactive_gpio,
3869 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME);
3870 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree