2 * Copyright (c) 2008-2011 Atheros Communications Inc.
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <linux/dma-mapping.h>
19 #include "ar9003_mac.h"
21 #define BITS_PER_BYTE 8
22 #define OFDM_PLCP_BITS 22
23 #define HT_RC_2_STREAMS(_rc) ((((_rc) & 0x78) >> 3) + 1)
29 #define HT_LTF(_ns) (4 * (_ns))
30 #define SYMBOL_TIME(_ns) ((_ns) << 2) /* ns * 4 us */
31 #define SYMBOL_TIME_HALFGI(_ns) (((_ns) * 18 + 4) / 5) /* ns * 3.6 us */
32 #define NUM_SYMBOLS_PER_USEC(_usec) (_usec >> 2)
33 #define NUM_SYMBOLS_PER_USEC_HALFGI(_usec) (((_usec*5)-4)/18)
36 static u16 bits_per_symbol
[][2] = {
38 { 26, 54 }, /* 0: BPSK */
39 { 52, 108 }, /* 1: QPSK 1/2 */
40 { 78, 162 }, /* 2: QPSK 3/4 */
41 { 104, 216 }, /* 3: 16-QAM 1/2 */
42 { 156, 324 }, /* 4: 16-QAM 3/4 */
43 { 208, 432 }, /* 5: 64-QAM 2/3 */
44 { 234, 486 }, /* 6: 64-QAM 3/4 */
45 { 260, 540 }, /* 7: 64-QAM 5/6 */
48 #define IS_HT_RATE(_rate) ((_rate) & 0x80)
50 static void ath_tx_send_normal(struct ath_softc
*sc
, struct ath_txq
*txq
,
51 struct ath_atx_tid
*tid
, struct sk_buff
*skb
);
52 static void ath_tx_complete(struct ath_softc
*sc
, struct sk_buff
*skb
,
53 int tx_flags
, struct ath_txq
*txq
);
54 static void ath_tx_complete_buf(struct ath_softc
*sc
, struct ath_buf
*bf
,
55 struct ath_txq
*txq
, struct list_head
*bf_q
,
56 struct ath_tx_status
*ts
, int txok
, int sendbar
);
57 static void ath_tx_txqaddbuf(struct ath_softc
*sc
, struct ath_txq
*txq
,
58 struct list_head
*head
, bool internal
);
59 static void ath_tx_rc_status(struct ath_softc
*sc
, struct ath_buf
*bf
,
60 struct ath_tx_status
*ts
, int nframes
, int nbad
,
62 static void ath_tx_update_baw(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
64 static struct ath_buf
*ath_tx_setup_buffer(struct ath_softc
*sc
,
66 struct ath_atx_tid
*tid
,
76 static int ath_max_4ms_framelen
[4][32] = {
78 3212, 6432, 9648, 12864, 19300, 25736, 28952, 32172,
79 6424, 12852, 19280, 25708, 38568, 51424, 57852, 64280,
80 9628, 19260, 28896, 38528, 57792, 65532, 65532, 65532,
81 12828, 25656, 38488, 51320, 65532, 65532, 65532, 65532,
84 3572, 7144, 10720, 14296, 21444, 28596, 32172, 35744,
85 7140, 14284, 21428, 28568, 42856, 57144, 64288, 65532,
86 10700, 21408, 32112, 42816, 64228, 65532, 65532, 65532,
87 14256, 28516, 42780, 57040, 65532, 65532, 65532, 65532,
90 6680, 13360, 20044, 26724, 40092, 53456, 60140, 65532,
91 13348, 26700, 40052, 53400, 65532, 65532, 65532, 65532,
92 20004, 40008, 60016, 65532, 65532, 65532, 65532, 65532,
93 26644, 53292, 65532, 65532, 65532, 65532, 65532, 65532,
96 7420, 14844, 22272, 29696, 44544, 59396, 65532, 65532,
97 14832, 29668, 44504, 59340, 65532, 65532, 65532, 65532,
98 22232, 44464, 65532, 65532, 65532, 65532, 65532, 65532,
99 29616, 59232, 65532, 65532, 65532, 65532, 65532, 65532,
103 /*********************/
104 /* Aggregation logic */
105 /*********************/
107 static void ath_tx_queue_tid(struct ath_txq
*txq
, struct ath_atx_tid
*tid
)
109 struct ath_atx_ac
*ac
= tid
->ac
;
118 list_add_tail(&tid
->list
, &ac
->tid_q
);
124 list_add_tail(&ac
->list
, &txq
->axq_acq
);
127 static void ath_tx_resume_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
129 struct ath_txq
*txq
= tid
->ac
->txq
;
131 WARN_ON(!tid
->paused
);
133 spin_lock_bh(&txq
->axq_lock
);
136 if (skb_queue_empty(&tid
->buf_q
))
139 ath_tx_queue_tid(txq
, tid
);
140 ath_txq_schedule(sc
, txq
);
142 spin_unlock_bh(&txq
->axq_lock
);
145 static struct ath_frame_info
*get_frame_info(struct sk_buff
*skb
)
147 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
148 BUILD_BUG_ON(sizeof(struct ath_frame_info
) >
149 sizeof(tx_info
->rate_driver_data
));
150 return (struct ath_frame_info
*) &tx_info
->rate_driver_data
[0];
153 static void ath_tx_flush_tid(struct ath_softc
*sc
, struct ath_atx_tid
*tid
)
155 struct ath_txq
*txq
= tid
->ac
->txq
;
158 struct list_head bf_head
;
159 struct ath_tx_status ts
;
160 struct ath_frame_info
*fi
;
162 INIT_LIST_HEAD(&bf_head
);
164 memset(&ts
, 0, sizeof(ts
));
165 spin_lock_bh(&txq
->axq_lock
);
167 while ((skb
= __skb_dequeue(&tid
->buf_q
))) {
168 fi
= get_frame_info(skb
);
171 spin_unlock_bh(&txq
->axq_lock
);
172 if (bf
&& fi
->retries
) {
173 list_add_tail(&bf
->list
, &bf_head
);
174 ath_tx_update_baw(sc
, tid
, bf
->bf_state
.seqno
);
175 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, &ts
, 0, 1);
177 ath_tx_send_normal(sc
, txq
, NULL
, skb
);
179 spin_lock_bh(&txq
->axq_lock
);
182 spin_unlock_bh(&txq
->axq_lock
);
185 static void ath_tx_update_baw(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
190 index
= ATH_BA_INDEX(tid
->seq_start
, seqno
);
191 cindex
= (tid
->baw_head
+ index
) & (ATH_TID_MAX_BUFS
- 1);
193 __clear_bit(cindex
, tid
->tx_buf
);
195 while (tid
->baw_head
!= tid
->baw_tail
&& !test_bit(tid
->baw_head
, tid
->tx_buf
)) {
196 INCR(tid
->seq_start
, IEEE80211_SEQ_MAX
);
197 INCR(tid
->baw_head
, ATH_TID_MAX_BUFS
);
201 static void ath_tx_addto_baw(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
206 index
= ATH_BA_INDEX(tid
->seq_start
, seqno
);
207 cindex
= (tid
->baw_head
+ index
) & (ATH_TID_MAX_BUFS
- 1);
208 __set_bit(cindex
, tid
->tx_buf
);
210 if (index
>= ((tid
->baw_tail
- tid
->baw_head
) &
211 (ATH_TID_MAX_BUFS
- 1))) {
212 tid
->baw_tail
= cindex
;
213 INCR(tid
->baw_tail
, ATH_TID_MAX_BUFS
);
218 * TODO: For frame(s) that are in the retry state, we will reuse the
219 * sequence number(s) without setting the retry bit. The
220 * alternative is to give up on these and BAR the receiver's window
223 static void ath_tid_drain(struct ath_softc
*sc
, struct ath_txq
*txq
,
224 struct ath_atx_tid
*tid
)
229 struct list_head bf_head
;
230 struct ath_tx_status ts
;
231 struct ath_frame_info
*fi
;
233 memset(&ts
, 0, sizeof(ts
));
234 INIT_LIST_HEAD(&bf_head
);
236 while ((skb
= __skb_dequeue(&tid
->buf_q
))) {
237 fi
= get_frame_info(skb
);
241 spin_unlock(&txq
->axq_lock
);
242 ath_tx_complete(sc
, skb
, ATH_TX_ERROR
, txq
);
243 spin_lock(&txq
->axq_lock
);
247 list_add_tail(&bf
->list
, &bf_head
);
250 ath_tx_update_baw(sc
, tid
, bf
->bf_state
.seqno
);
252 spin_unlock(&txq
->axq_lock
);
253 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, &ts
, 0, 0);
254 spin_lock(&txq
->axq_lock
);
257 tid
->seq_next
= tid
->seq_start
;
258 tid
->baw_tail
= tid
->baw_head
;
261 static void ath_tx_set_retry(struct ath_softc
*sc
, struct ath_txq
*txq
,
264 struct ath_frame_info
*fi
= get_frame_info(skb
);
265 struct ieee80211_hdr
*hdr
;
267 TX_STAT_INC(txq
->axq_qnum
, a_retries
);
268 if (fi
->retries
++ > 0)
271 hdr
= (struct ieee80211_hdr
*)skb
->data
;
272 hdr
->frame_control
|= cpu_to_le16(IEEE80211_FCTL_RETRY
);
275 static struct ath_buf
*ath_tx_get_buffer(struct ath_softc
*sc
)
277 struct ath_buf
*bf
= NULL
;
279 spin_lock_bh(&sc
->tx
.txbuflock
);
281 if (unlikely(list_empty(&sc
->tx
.txbuf
))) {
282 spin_unlock_bh(&sc
->tx
.txbuflock
);
286 bf
= list_first_entry(&sc
->tx
.txbuf
, struct ath_buf
, list
);
289 spin_unlock_bh(&sc
->tx
.txbuflock
);
294 static void ath_tx_return_buffer(struct ath_softc
*sc
, struct ath_buf
*bf
)
296 spin_lock_bh(&sc
->tx
.txbuflock
);
297 list_add_tail(&bf
->list
, &sc
->tx
.txbuf
);
298 spin_unlock_bh(&sc
->tx
.txbuflock
);
301 static struct ath_buf
* ath_clone_txbuf(struct ath_softc
*sc
, struct ath_buf
*bf
)
305 tbf
= ath_tx_get_buffer(sc
);
309 ATH_TXBUF_RESET(tbf
);
311 tbf
->bf_mpdu
= bf
->bf_mpdu
;
312 tbf
->bf_buf_addr
= bf
->bf_buf_addr
;
313 memcpy(tbf
->bf_desc
, bf
->bf_desc
, sc
->sc_ah
->caps
.tx_desc_len
);
314 tbf
->bf_state
= bf
->bf_state
;
319 static void ath_tx_count_frames(struct ath_softc
*sc
, struct ath_buf
*bf
,
320 struct ath_tx_status
*ts
, int txok
,
321 int *nframes
, int *nbad
)
323 struct ath_frame_info
*fi
;
325 u32 ba
[WME_BA_BMP_SIZE
>> 5];
332 isaggr
= bf_isaggr(bf
);
334 seq_st
= ts
->ts_seqnum
;
335 memcpy(ba
, &ts
->ba_low
, WME_BA_BMP_SIZE
>> 3);
339 fi
= get_frame_info(bf
->bf_mpdu
);
340 ba_index
= ATH_BA_INDEX(seq_st
, bf
->bf_state
.seqno
);
343 if (!txok
|| (isaggr
&& !ATH_BA_ISSET(ba
, ba_index
)))
351 static void ath_tx_complete_aggr(struct ath_softc
*sc
, struct ath_txq
*txq
,
352 struct ath_buf
*bf
, struct list_head
*bf_q
,
353 struct ath_tx_status
*ts
, int txok
, bool retry
)
355 struct ath_node
*an
= NULL
;
357 struct ieee80211_sta
*sta
;
358 struct ieee80211_hw
*hw
= sc
->hw
;
359 struct ieee80211_hdr
*hdr
;
360 struct ieee80211_tx_info
*tx_info
;
361 struct ath_atx_tid
*tid
= NULL
;
362 struct ath_buf
*bf_next
, *bf_last
= bf
->bf_lastbf
;
363 struct list_head bf_head
;
364 struct sk_buff_head bf_pending
;
365 u16 seq_st
= 0, acked_cnt
= 0, txfail_cnt
= 0;
366 u32 ba
[WME_BA_BMP_SIZE
>> 5];
367 int isaggr
, txfail
, txpending
, sendbar
= 0, needreset
= 0, nbad
= 0;
368 bool rc_update
= true;
369 struct ieee80211_tx_rate rates
[4];
370 struct ath_frame_info
*fi
;
376 hdr
= (struct ieee80211_hdr
*)skb
->data
;
378 tx_info
= IEEE80211_SKB_CB(skb
);
380 memcpy(rates
, tx_info
->control
.rates
, sizeof(rates
));
384 sta
= ieee80211_find_sta_by_ifaddr(hw
, hdr
->addr1
, hdr
->addr2
);
388 INIT_LIST_HEAD(&bf_head
);
390 bf_next
= bf
->bf_next
;
392 if (!bf
->bf_stale
|| bf_next
!= NULL
)
393 list_move_tail(&bf
->list
, &bf_head
);
395 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, ts
,
403 an
= (struct ath_node
*)sta
->drv_priv
;
404 tidno
= ieee80211_get_qos_ctl(hdr
)[0] & IEEE80211_QOS_CTL_TID_MASK
;
405 tid
= ATH_AN_2_TID(an
, tidno
);
408 * The hardware occasionally sends a tx status for the wrong TID.
409 * In this case, the BA status cannot be considered valid and all
410 * subframes need to be retransmitted
412 if (tidno
!= ts
->tid
)
415 isaggr
= bf_isaggr(bf
);
416 memset(ba
, 0, WME_BA_BMP_SIZE
>> 3);
418 if (isaggr
&& txok
) {
419 if (ts
->ts_flags
& ATH9K_TX_BA
) {
420 seq_st
= ts
->ts_seqnum
;
421 memcpy(ba
, &ts
->ba_low
, WME_BA_BMP_SIZE
>> 3);
424 * AR5416 can become deaf/mute when BA
425 * issue happens. Chip needs to be reset.
426 * But AP code may have sychronization issues
427 * when perform internal reset in this routine.
428 * Only enable reset in STA mode for now.
430 if (sc
->sc_ah
->opmode
== NL80211_IFTYPE_STATION
)
435 __skb_queue_head_init(&bf_pending
);
437 ath_tx_count_frames(sc
, bf
, ts
, txok
, &nframes
, &nbad
);
439 u16 seqno
= bf
->bf_state
.seqno
;
441 txfail
= txpending
= sendbar
= 0;
442 bf_next
= bf
->bf_next
;
445 tx_info
= IEEE80211_SKB_CB(skb
);
446 fi
= get_frame_info(skb
);
448 if (ATH_BA_ISSET(ba
, ATH_BA_INDEX(seq_st
, seqno
))) {
449 /* transmit completion, subframe is
450 * acked by block ack */
452 } else if (!isaggr
&& txok
) {
453 /* transmit completion */
456 if ((tid
->state
& AGGR_CLEANUP
) || !retry
) {
458 * cleanup in progress, just fail
459 * the un-acked sub-frames
462 } else if (fi
->retries
< ATH_MAX_SW_RETRIES
) {
463 if (!(ts
->ts_status
& ATH9K_TXERR_FILT
) ||
465 ath_tx_set_retry(sc
, txq
, bf
->bf_mpdu
);
477 * Make sure the last desc is reclaimed if it
478 * not a holding desc.
480 INIT_LIST_HEAD(&bf_head
);
481 if ((sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
) ||
482 bf_next
!= NULL
|| !bf_last
->bf_stale
)
483 list_move_tail(&bf
->list
, &bf_head
);
485 if (!txpending
|| (tid
->state
& AGGR_CLEANUP
)) {
487 * complete the acked-ones/xretried ones; update
490 spin_lock_bh(&txq
->axq_lock
);
491 ath_tx_update_baw(sc
, tid
, seqno
);
492 spin_unlock_bh(&txq
->axq_lock
);
494 if (rc_update
&& (acked_cnt
== 1 || txfail_cnt
== 1)) {
495 memcpy(tx_info
->control
.rates
, rates
, sizeof(rates
));
496 ath_tx_rc_status(sc
, bf
, ts
, nframes
, nbad
, txok
);
500 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, ts
,
503 /* retry the un-acked ones */
504 if (!(sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
)) {
505 if (bf
->bf_next
== NULL
&& bf_last
->bf_stale
) {
508 tbf
= ath_clone_txbuf(sc
, bf_last
);
510 * Update tx baw and complete the
511 * frame with failed status if we
515 spin_lock_bh(&txq
->axq_lock
);
516 ath_tx_update_baw(sc
, tid
, seqno
);
517 spin_unlock_bh(&txq
->axq_lock
);
519 ath_tx_complete_buf(sc
, bf
, txq
,
530 * Put this buffer to the temporary pending
531 * queue to retain ordering
533 __skb_queue_tail(&bf_pending
, skb
);
539 /* prepend un-acked frames to the beginning of the pending frame queue */
540 if (!skb_queue_empty(&bf_pending
)) {
542 ieee80211_sta_set_tim(sta
);
544 spin_lock_bh(&txq
->axq_lock
);
546 tid
->ac
->clear_ps_filter
= true;
547 skb_queue_splice(&bf_pending
, &tid
->buf_q
);
549 ath_tx_queue_tid(txq
, tid
);
550 spin_unlock_bh(&txq
->axq_lock
);
553 if (tid
->state
& AGGR_CLEANUP
) {
554 ath_tx_flush_tid(sc
, tid
);
556 if (tid
->baw_head
== tid
->baw_tail
) {
557 tid
->state
&= ~AGGR_ADDBA_COMPLETE
;
558 tid
->state
&= ~AGGR_CLEANUP
;
565 ieee80211_queue_work(sc
->hw
, &sc
->hw_reset_work
);
568 static bool ath_lookup_legacy(struct ath_buf
*bf
)
571 struct ieee80211_tx_info
*tx_info
;
572 struct ieee80211_tx_rate
*rates
;
576 tx_info
= IEEE80211_SKB_CB(skb
);
577 rates
= tx_info
->control
.rates
;
579 for (i
= 0; i
< 4; i
++) {
580 if (!rates
[i
].count
|| rates
[i
].idx
< 0)
583 if (!(rates
[i
].flags
& IEEE80211_TX_RC_MCS
))
590 static u32
ath_lookup_rate(struct ath_softc
*sc
, struct ath_buf
*bf
,
591 struct ath_atx_tid
*tid
)
594 struct ieee80211_tx_info
*tx_info
;
595 struct ieee80211_tx_rate
*rates
;
596 u32 max_4ms_framelen
, frmlen
;
597 u16 aggr_limit
, legacy
= 0;
601 tx_info
= IEEE80211_SKB_CB(skb
);
602 rates
= tx_info
->control
.rates
;
605 * Find the lowest frame length among the rate series that will have a
606 * 4ms transmit duration.
607 * TODO - TXOP limit needs to be considered.
609 max_4ms_framelen
= ATH_AMPDU_LIMIT_MAX
;
611 for (i
= 0; i
< 4; i
++) {
612 if (rates
[i
].count
) {
614 if (!(rates
[i
].flags
& IEEE80211_TX_RC_MCS
)) {
619 if (rates
[i
].flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
)
624 if (rates
[i
].flags
& IEEE80211_TX_RC_SHORT_GI
)
627 frmlen
= ath_max_4ms_framelen
[modeidx
][rates
[i
].idx
];
628 max_4ms_framelen
= min(max_4ms_framelen
, frmlen
);
633 * limit aggregate size by the minimum rate if rate selected is
634 * not a probe rate, if rate selected is a probe rate then
635 * avoid aggregation of this packet.
637 if (tx_info
->flags
& IEEE80211_TX_CTL_RATE_CTRL_PROBE
|| legacy
)
640 if (sc
->sc_flags
& SC_OP_BT_PRIORITY_DETECTED
)
641 aggr_limit
= min((max_4ms_framelen
* 3) / 8,
642 (u32
)ATH_AMPDU_LIMIT_MAX
);
644 aggr_limit
= min(max_4ms_framelen
,
645 (u32
)ATH_AMPDU_LIMIT_MAX
);
648 * h/w can accept aggregates up to 16 bit lengths (65535).
649 * The IE, however can hold up to 65536, which shows up here
650 * as zero. Ignore 65536 since we are constrained by hw.
652 if (tid
->an
->maxampdu
)
653 aggr_limit
= min(aggr_limit
, tid
->an
->maxampdu
);
659 * Returns the number of delimiters to be added to
660 * meet the minimum required mpdudensity.
662 static int ath_compute_num_delims(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
663 struct ath_buf
*bf
, u16 frmlen
,
666 #define FIRST_DESC_NDELIMS 60
667 struct sk_buff
*skb
= bf
->bf_mpdu
;
668 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
669 u32 nsymbits
, nsymbols
;
672 int width
, streams
, half_gi
, ndelim
, mindelim
;
673 struct ath_frame_info
*fi
= get_frame_info(bf
->bf_mpdu
);
675 /* Select standard number of delimiters based on frame length alone */
676 ndelim
= ATH_AGGR_GET_NDELIM(frmlen
);
679 * If encryption enabled, hardware requires some more padding between
681 * TODO - this could be improved to be dependent on the rate.
682 * The hardware can keep up at lower rates, but not higher rates
684 if ((fi
->keyix
!= ATH9K_TXKEYIX_INVALID
) &&
685 !(sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
))
686 ndelim
+= ATH_AGGR_ENCRYPTDELIM
;
689 * Add delimiter when using RTS/CTS with aggregation
690 * and non enterprise AR9003 card
692 if (first_subfrm
&& !AR_SREV_9580_10_OR_LATER(sc
->sc_ah
) &&
693 (sc
->sc_ah
->ent_mode
& AR_ENT_OTP_MIN_PKT_SIZE_DISABLE
))
694 ndelim
= max(ndelim
, FIRST_DESC_NDELIMS
);
697 * Convert desired mpdu density from microeconds to bytes based
698 * on highest rate in rate series (i.e. first rate) to determine
699 * required minimum length for subframe. Take into account
700 * whether high rate is 20 or 40Mhz and half or full GI.
702 * If there is no mpdu density restriction, no further calculation
706 if (tid
->an
->mpdudensity
== 0)
709 rix
= tx_info
->control
.rates
[0].idx
;
710 flags
= tx_info
->control
.rates
[0].flags
;
711 width
= (flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
) ? 1 : 0;
712 half_gi
= (flags
& IEEE80211_TX_RC_SHORT_GI
) ? 1 : 0;
715 nsymbols
= NUM_SYMBOLS_PER_USEC_HALFGI(tid
->an
->mpdudensity
);
717 nsymbols
= NUM_SYMBOLS_PER_USEC(tid
->an
->mpdudensity
);
722 streams
= HT_RC_2_STREAMS(rix
);
723 nsymbits
= bits_per_symbol
[rix
% 8][width
] * streams
;
724 minlen
= (nsymbols
* nsymbits
) / BITS_PER_BYTE
;
726 if (frmlen
< minlen
) {
727 mindelim
= (minlen
- frmlen
) / ATH_AGGR_DELIM_SZ
;
728 ndelim
= max(mindelim
, ndelim
);
734 static enum ATH_AGGR_STATUS
ath_tx_form_aggr(struct ath_softc
*sc
,
736 struct ath_atx_tid
*tid
,
737 struct list_head
*bf_q
,
740 #define PADBYTES(_len) ((4 - ((_len) % 4)) % 4)
741 struct ath_buf
*bf
, *bf_first
= NULL
, *bf_prev
= NULL
;
742 int rl
= 0, nframes
= 0, ndelim
, prev_al
= 0;
743 u16 aggr_limit
= 0, al
= 0, bpad
= 0,
744 al_delta
, h_baw
= tid
->baw_size
/ 2;
745 enum ATH_AGGR_STATUS status
= ATH_AGGR_DONE
;
746 struct ieee80211_tx_info
*tx_info
;
747 struct ath_frame_info
*fi
;
752 skb
= skb_peek(&tid
->buf_q
);
753 fi
= get_frame_info(skb
);
756 bf
= ath_tx_setup_buffer(sc
, txq
, tid
, skb
);
761 bf
->bf_state
.bf_type
= BUF_AMPDU
| BUF_AGGR
;
762 seqno
= bf
->bf_state
.seqno
;
766 /* do not step over block-ack window */
767 if (!BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, seqno
)) {
768 status
= ATH_AGGR_BAW_CLOSED
;
773 aggr_limit
= ath_lookup_rate(sc
, bf
, tid
);
777 /* do not exceed aggregation limit */
778 al_delta
= ATH_AGGR_DELIM_SZ
+ fi
->framelen
;
781 ((aggr_limit
< (al
+ bpad
+ al_delta
+ prev_al
)) ||
782 ath_lookup_legacy(bf
))) {
783 status
= ATH_AGGR_LIMITED
;
787 tx_info
= IEEE80211_SKB_CB(bf
->bf_mpdu
);
788 if (nframes
&& (tx_info
->flags
& IEEE80211_TX_CTL_RATE_CTRL_PROBE
))
791 /* do not exceed subframe limit */
792 if (nframes
>= min((int)h_baw
, ATH_AMPDU_SUBFRAME_DEFAULT
)) {
793 status
= ATH_AGGR_LIMITED
;
797 /* add padding for previous frame to aggregation length */
798 al
+= bpad
+ al_delta
;
801 * Get the delimiters needed to meet the MPDU
802 * density for this node.
804 ndelim
= ath_compute_num_delims(sc
, tid
, bf_first
, fi
->framelen
,
806 bpad
= PADBYTES(al_delta
) + (ndelim
<< 2);
811 /* link buffers of this frame to the aggregate */
813 ath_tx_addto_baw(sc
, tid
, seqno
);
814 bf
->bf_state
.ndelim
= ndelim
;
816 __skb_unlink(skb
, &tid
->buf_q
);
817 list_add_tail(&bf
->list
, bf_q
);
819 bf_prev
->bf_next
= bf
;
823 } while (!skb_queue_empty(&tid
->buf_q
));
833 * pktlen - total bytes (delims + data + fcs + pads + pad delims)
834 * width - 0 for 20 MHz, 1 for 40 MHz
835 * half_gi - to use 4us v/s 3.6 us for symbol time
837 static u32
ath_pkt_duration(struct ath_softc
*sc
, u8 rix
, int pktlen
,
838 int width
, int half_gi
, bool shortPreamble
)
840 u32 nbits
, nsymbits
, duration
, nsymbols
;
843 /* find number of symbols: PLCP + data */
844 streams
= HT_RC_2_STREAMS(rix
);
845 nbits
= (pktlen
<< 3) + OFDM_PLCP_BITS
;
846 nsymbits
= bits_per_symbol
[rix
% 8][width
] * streams
;
847 nsymbols
= (nbits
+ nsymbits
- 1) / nsymbits
;
850 duration
= SYMBOL_TIME(nsymbols
);
852 duration
= SYMBOL_TIME_HALFGI(nsymbols
);
854 /* addup duration for legacy/ht training and signal fields */
855 duration
+= L_STF
+ L_LTF
+ L_SIG
+ HT_SIG
+ HT_STF
+ HT_LTF(streams
);
860 static void ath_buf_set_rate(struct ath_softc
*sc
, struct ath_buf
*bf
,
861 struct ath_tx_info
*info
, int len
)
863 struct ath_hw
*ah
= sc
->sc_ah
;
865 struct ieee80211_tx_info
*tx_info
;
866 struct ieee80211_tx_rate
*rates
;
867 const struct ieee80211_rate
*rate
;
868 struct ieee80211_hdr
*hdr
;
873 tx_info
= IEEE80211_SKB_CB(skb
);
874 rates
= tx_info
->control
.rates
;
875 hdr
= (struct ieee80211_hdr
*)skb
->data
;
877 /* set dur_update_en for l-sig computation except for PS-Poll frames */
878 info
->dur_update
= !ieee80211_is_pspoll(hdr
->frame_control
);
881 * We check if Short Preamble is needed for the CTS rate by
882 * checking the BSS's global flag.
883 * But for the rate series, IEEE80211_TX_RC_USE_SHORT_PREAMBLE is used.
885 rate
= ieee80211_get_rts_cts_rate(sc
->hw
, tx_info
);
886 info
->rtscts_rate
= rate
->hw_value
;
887 if (sc
->sc_flags
& SC_OP_PREAMBLE_SHORT
)
888 info
->rtscts_rate
|= rate
->hw_value_short
;
890 for (i
= 0; i
< 4; i
++) {
891 bool is_40
, is_sgi
, is_sp
;
894 if (!rates
[i
].count
|| (rates
[i
].idx
< 0))
898 info
->rates
[i
].Tries
= rates
[i
].count
;
900 if (rates
[i
].flags
& IEEE80211_TX_RC_USE_RTS_CTS
) {
901 info
->rates
[i
].RateFlags
|= ATH9K_RATESERIES_RTS_CTS
;
902 info
->flags
|= ATH9K_TXDESC_RTSENA
;
903 } else if (rates
[i
].flags
& IEEE80211_TX_RC_USE_CTS_PROTECT
) {
904 info
->rates
[i
].RateFlags
|= ATH9K_RATESERIES_RTS_CTS
;
905 info
->flags
|= ATH9K_TXDESC_CTSENA
;
908 if (rates
[i
].flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
)
909 info
->rates
[i
].RateFlags
|= ATH9K_RATESERIES_2040
;
910 if (rates
[i
].flags
& IEEE80211_TX_RC_SHORT_GI
)
911 info
->rates
[i
].RateFlags
|= ATH9K_RATESERIES_HALFGI
;
913 is_sgi
= !!(rates
[i
].flags
& IEEE80211_TX_RC_SHORT_GI
);
914 is_40
= !!(rates
[i
].flags
& IEEE80211_TX_RC_40_MHZ_WIDTH
);
915 is_sp
= !!(rates
[i
].flags
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
);
917 if (rates
[i
].flags
& IEEE80211_TX_RC_MCS
) {
919 info
->rates
[i
].Rate
= rix
| 0x80;
920 info
->rates
[i
].ChSel
= ath_txchainmask_reduction(sc
,
921 ah
->txchainmask
, info
->rates
[i
].Rate
);
922 info
->rates
[i
].PktDuration
= ath_pkt_duration(sc
, rix
, len
,
923 is_40
, is_sgi
, is_sp
);
924 if (rix
< 8 && (tx_info
->flags
& IEEE80211_TX_CTL_STBC
))
925 info
->rates
[i
].RateFlags
|= ATH9K_RATESERIES_STBC
;
930 if ((tx_info
->band
== IEEE80211_BAND_2GHZ
) &&
931 !(rate
->flags
& IEEE80211_RATE_ERP_G
))
932 phy
= WLAN_RC_PHY_CCK
;
934 phy
= WLAN_RC_PHY_OFDM
;
936 rate
= &sc
->sbands
[tx_info
->band
].bitrates
[rates
[i
].idx
];
937 info
->rates
[i
].Rate
= rate
->hw_value
;
938 if (rate
->hw_value_short
) {
939 if (rates
[i
].flags
& IEEE80211_TX_RC_USE_SHORT_PREAMBLE
)
940 info
->rates
[i
].Rate
|= rate
->hw_value_short
;
945 if (bf
->bf_state
.bfs_paprd
)
946 info
->rates
[i
].ChSel
= ah
->txchainmask
;
948 info
->rates
[i
].ChSel
= ath_txchainmask_reduction(sc
,
949 ah
->txchainmask
, info
->rates
[i
].Rate
);
951 info
->rates
[i
].PktDuration
= ath9k_hw_computetxtime(sc
->sc_ah
,
952 phy
, rate
->bitrate
* 100, len
, rix
, is_sp
);
955 /* For AR5416 - RTS cannot be followed by a frame larger than 8K */
956 if (bf_isaggr(bf
) && (len
> sc
->sc_ah
->caps
.rts_aggr_limit
))
957 info
->flags
&= ~ATH9K_TXDESC_RTSENA
;
959 /* ATH9K_TXDESC_RTSENA and ATH9K_TXDESC_CTSENA are mutually exclusive. */
960 if (info
->flags
& ATH9K_TXDESC_RTSENA
)
961 info
->flags
&= ~ATH9K_TXDESC_CTSENA
;
964 static enum ath9k_pkt_type
get_hw_packet_type(struct sk_buff
*skb
)
966 struct ieee80211_hdr
*hdr
;
967 enum ath9k_pkt_type htype
;
970 hdr
= (struct ieee80211_hdr
*)skb
->data
;
971 fc
= hdr
->frame_control
;
973 if (ieee80211_is_beacon(fc
))
974 htype
= ATH9K_PKT_TYPE_BEACON
;
975 else if (ieee80211_is_probe_resp(fc
))
976 htype
= ATH9K_PKT_TYPE_PROBE_RESP
;
977 else if (ieee80211_is_atim(fc
))
978 htype
= ATH9K_PKT_TYPE_ATIM
;
979 else if (ieee80211_is_pspoll(fc
))
980 htype
= ATH9K_PKT_TYPE_PSPOLL
;
982 htype
= ATH9K_PKT_TYPE_NORMAL
;
987 static void ath_tx_fill_desc(struct ath_softc
*sc
, struct ath_buf
*bf
,
988 struct ath_txq
*txq
, int len
)
990 struct ath_hw
*ah
= sc
->sc_ah
;
991 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(bf
->bf_mpdu
);
992 struct ath_buf
*bf_first
= bf
;
993 struct ath_tx_info info
;
994 bool aggr
= !!(bf
->bf_state
.bf_type
& BUF_AGGR
);
996 memset(&info
, 0, sizeof(info
));
997 info
.is_first
= true;
999 info
.txpower
= MAX_RATE_POWER
;
1000 info
.qcu
= txq
->axq_qnum
;
1002 info
.flags
= ATH9K_TXDESC_INTREQ
;
1003 if (tx_info
->flags
& IEEE80211_TX_CTL_NO_ACK
)
1004 info
.flags
|= ATH9K_TXDESC_NOACK
;
1005 if (tx_info
->flags
& IEEE80211_TX_CTL_LDPC
)
1006 info
.flags
|= ATH9K_TXDESC_LDPC
;
1008 ath_buf_set_rate(sc
, bf
, &info
, len
);
1010 if (tx_info
->flags
& IEEE80211_TX_CTL_CLEAR_PS_FILT
)
1011 info
.flags
|= ATH9K_TXDESC_CLRDMASK
;
1013 if (bf
->bf_state
.bfs_paprd
)
1014 info
.flags
|= (u32
) bf
->bf_state
.bfs_paprd
<< ATH9K_TXDESC_PAPRD_S
;
1018 struct sk_buff
*skb
= bf
->bf_mpdu
;
1019 struct ath_frame_info
*fi
= get_frame_info(skb
);
1021 info
.type
= get_hw_packet_type(skb
);
1023 info
.link
= bf
->bf_next
->bf_daddr
;
1027 info
.buf_addr
[0] = bf
->bf_buf_addr
;
1028 info
.buf_len
[0] = skb
->len
;
1029 info
.pkt_len
= fi
->framelen
;
1030 info
.keyix
= fi
->keyix
;
1031 info
.keytype
= fi
->keytype
;
1035 info
.aggr
= AGGR_BUF_FIRST
;
1036 else if (!bf
->bf_next
)
1037 info
.aggr
= AGGR_BUF_LAST
;
1039 info
.aggr
= AGGR_BUF_MIDDLE
;
1041 info
.ndelim
= bf
->bf_state
.ndelim
;
1042 info
.aggr_len
= len
;
1045 ath9k_hw_set_txdesc(ah
, bf
->bf_desc
, &info
);
1050 static void ath_tx_sched_aggr(struct ath_softc
*sc
, struct ath_txq
*txq
,
1051 struct ath_atx_tid
*tid
)
1054 enum ATH_AGGR_STATUS status
;
1055 struct ieee80211_tx_info
*tx_info
;
1056 struct list_head bf_q
;
1060 if (skb_queue_empty(&tid
->buf_q
))
1063 INIT_LIST_HEAD(&bf_q
);
1065 status
= ath_tx_form_aggr(sc
, txq
, tid
, &bf_q
, &aggr_len
);
1068 * no frames picked up to be aggregated;
1069 * block-ack window is not open.
1071 if (list_empty(&bf_q
))
1074 bf
= list_first_entry(&bf_q
, struct ath_buf
, list
);
1075 bf
->bf_lastbf
= list_entry(bf_q
.prev
, struct ath_buf
, list
);
1076 tx_info
= IEEE80211_SKB_CB(bf
->bf_mpdu
);
1078 if (tid
->ac
->clear_ps_filter
) {
1079 tid
->ac
->clear_ps_filter
= false;
1080 tx_info
->flags
|= IEEE80211_TX_CTL_CLEAR_PS_FILT
;
1082 tx_info
->flags
&= ~IEEE80211_TX_CTL_CLEAR_PS_FILT
;
1085 /* if only one frame, send as non-aggregate */
1086 if (bf
== bf
->bf_lastbf
) {
1087 aggr_len
= get_frame_info(bf
->bf_mpdu
)->framelen
;
1088 bf
->bf_state
.bf_type
= BUF_AMPDU
;
1090 TX_STAT_INC(txq
->axq_qnum
, a_aggr
);
1093 ath_tx_fill_desc(sc
, bf
, txq
, aggr_len
);
1094 ath_tx_txqaddbuf(sc
, txq
, &bf_q
, false);
1095 } while (txq
->axq_ampdu_depth
< ATH_AGGR_MIN_QDEPTH
&&
1096 status
!= ATH_AGGR_BAW_CLOSED
);
1099 int ath_tx_aggr_start(struct ath_softc
*sc
, struct ieee80211_sta
*sta
,
1102 struct ath_atx_tid
*txtid
;
1103 struct ath_node
*an
;
1105 an
= (struct ath_node
*)sta
->drv_priv
;
1106 txtid
= ATH_AN_2_TID(an
, tid
);
1108 if (txtid
->state
& (AGGR_CLEANUP
| AGGR_ADDBA_COMPLETE
))
1111 txtid
->state
|= AGGR_ADDBA_PROGRESS
;
1112 txtid
->paused
= true;
1113 *ssn
= txtid
->seq_start
= txtid
->seq_next
;
1115 memset(txtid
->tx_buf
, 0, sizeof(txtid
->tx_buf
));
1116 txtid
->baw_head
= txtid
->baw_tail
= 0;
1121 void ath_tx_aggr_stop(struct ath_softc
*sc
, struct ieee80211_sta
*sta
, u16 tid
)
1123 struct ath_node
*an
= (struct ath_node
*)sta
->drv_priv
;
1124 struct ath_atx_tid
*txtid
= ATH_AN_2_TID(an
, tid
);
1125 struct ath_txq
*txq
= txtid
->ac
->txq
;
1127 if (txtid
->state
& AGGR_CLEANUP
)
1130 if (!(txtid
->state
& AGGR_ADDBA_COMPLETE
)) {
1131 txtid
->state
&= ~AGGR_ADDBA_PROGRESS
;
1135 spin_lock_bh(&txq
->axq_lock
);
1136 txtid
->paused
= true;
1139 * If frames are still being transmitted for this TID, they will be
1140 * cleaned up during tx completion. To prevent race conditions, this
1141 * TID can only be reused after all in-progress subframes have been
1144 if (txtid
->baw_head
!= txtid
->baw_tail
)
1145 txtid
->state
|= AGGR_CLEANUP
;
1147 txtid
->state
&= ~AGGR_ADDBA_COMPLETE
;
1148 spin_unlock_bh(&txq
->axq_lock
);
1150 ath_tx_flush_tid(sc
, txtid
);
1153 bool ath_tx_aggr_sleep(struct ath_softc
*sc
, struct ath_node
*an
)
1155 struct ath_atx_tid
*tid
;
1156 struct ath_atx_ac
*ac
;
1157 struct ath_txq
*txq
;
1158 bool buffered
= false;
1161 for (tidno
= 0, tid
= &an
->tid
[tidno
];
1162 tidno
< WME_NUM_TID
; tidno
++, tid
++) {
1170 spin_lock_bh(&txq
->axq_lock
);
1172 if (!skb_queue_empty(&tid
->buf_q
))
1176 list_del(&tid
->list
);
1180 list_del(&ac
->list
);
1183 spin_unlock_bh(&txq
->axq_lock
);
1189 void ath_tx_aggr_wakeup(struct ath_softc
*sc
, struct ath_node
*an
)
1191 struct ath_atx_tid
*tid
;
1192 struct ath_atx_ac
*ac
;
1193 struct ath_txq
*txq
;
1196 for (tidno
= 0, tid
= &an
->tid
[tidno
];
1197 tidno
< WME_NUM_TID
; tidno
++, tid
++) {
1202 spin_lock_bh(&txq
->axq_lock
);
1203 ac
->clear_ps_filter
= true;
1205 if (!skb_queue_empty(&tid
->buf_q
) && !tid
->paused
) {
1206 ath_tx_queue_tid(txq
, tid
);
1207 ath_txq_schedule(sc
, txq
);
1210 spin_unlock_bh(&txq
->axq_lock
);
1214 void ath_tx_aggr_resume(struct ath_softc
*sc
, struct ieee80211_sta
*sta
, u16 tid
)
1216 struct ath_atx_tid
*txtid
;
1217 struct ath_node
*an
;
1219 an
= (struct ath_node
*)sta
->drv_priv
;
1221 if (sc
->sc_flags
& SC_OP_TXAGGR
) {
1222 txtid
= ATH_AN_2_TID(an
, tid
);
1224 IEEE80211_MIN_AMPDU_BUF
<< sta
->ht_cap
.ampdu_factor
;
1225 txtid
->state
|= AGGR_ADDBA_COMPLETE
;
1226 txtid
->state
&= ~AGGR_ADDBA_PROGRESS
;
1227 ath_tx_resume_tid(sc
, txtid
);
1231 /********************/
1232 /* Queue Management */
1233 /********************/
1235 static void ath_txq_drain_pending_buffers(struct ath_softc
*sc
,
1236 struct ath_txq
*txq
)
1238 struct ath_atx_ac
*ac
, *ac_tmp
;
1239 struct ath_atx_tid
*tid
, *tid_tmp
;
1241 list_for_each_entry_safe(ac
, ac_tmp
, &txq
->axq_acq
, list
) {
1242 list_del(&ac
->list
);
1244 list_for_each_entry_safe(tid
, tid_tmp
, &ac
->tid_q
, list
) {
1245 list_del(&tid
->list
);
1247 ath_tid_drain(sc
, txq
, tid
);
1252 struct ath_txq
*ath_txq_setup(struct ath_softc
*sc
, int qtype
, int subtype
)
1254 struct ath_hw
*ah
= sc
->sc_ah
;
1255 struct ath_common
*common
= ath9k_hw_common(ah
);
1256 struct ath9k_tx_queue_info qi
;
1257 static const int subtype_txq_to_hwq
[] = {
1258 [WME_AC_BE
] = ATH_TXQ_AC_BE
,
1259 [WME_AC_BK
] = ATH_TXQ_AC_BK
,
1260 [WME_AC_VI
] = ATH_TXQ_AC_VI
,
1261 [WME_AC_VO
] = ATH_TXQ_AC_VO
,
1265 memset(&qi
, 0, sizeof(qi
));
1266 qi
.tqi_subtype
= subtype_txq_to_hwq
[subtype
];
1267 qi
.tqi_aifs
= ATH9K_TXQ_USEDEFAULT
;
1268 qi
.tqi_cwmin
= ATH9K_TXQ_USEDEFAULT
;
1269 qi
.tqi_cwmax
= ATH9K_TXQ_USEDEFAULT
;
1270 qi
.tqi_physCompBuf
= 0;
1273 * Enable interrupts only for EOL and DESC conditions.
1274 * We mark tx descriptors to receive a DESC interrupt
1275 * when a tx queue gets deep; otherwise waiting for the
1276 * EOL to reap descriptors. Note that this is done to
1277 * reduce interrupt load and this only defers reaping
1278 * descriptors, never transmitting frames. Aside from
1279 * reducing interrupts this also permits more concurrency.
1280 * The only potential downside is if the tx queue backs
1281 * up in which case the top half of the kernel may backup
1282 * due to a lack of tx descriptors.
1284 * The UAPSD queue is an exception, since we take a desc-
1285 * based intr on the EOSP frames.
1287 if (ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
) {
1288 qi
.tqi_qflags
= TXQ_FLAG_TXOKINT_ENABLE
|
1289 TXQ_FLAG_TXERRINT_ENABLE
;
1291 if (qtype
== ATH9K_TX_QUEUE_UAPSD
)
1292 qi
.tqi_qflags
= TXQ_FLAG_TXDESCINT_ENABLE
;
1294 qi
.tqi_qflags
= TXQ_FLAG_TXEOLINT_ENABLE
|
1295 TXQ_FLAG_TXDESCINT_ENABLE
;
1297 axq_qnum
= ath9k_hw_setuptxqueue(ah
, qtype
, &qi
);
1298 if (axq_qnum
== -1) {
1300 * NB: don't print a message, this happens
1301 * normally on parts with too few tx queues
1305 if (axq_qnum
>= ARRAY_SIZE(sc
->tx
.txq
)) {
1306 ath_err(common
, "qnum %u out of range, max %zu!\n",
1307 axq_qnum
, ARRAY_SIZE(sc
->tx
.txq
));
1308 ath9k_hw_releasetxqueue(ah
, axq_qnum
);
1311 if (!ATH_TXQ_SETUP(sc
, axq_qnum
)) {
1312 struct ath_txq
*txq
= &sc
->tx
.txq
[axq_qnum
];
1314 txq
->axq_qnum
= axq_qnum
;
1315 txq
->mac80211_qnum
= -1;
1316 txq
->axq_link
= NULL
;
1317 INIT_LIST_HEAD(&txq
->axq_q
);
1318 INIT_LIST_HEAD(&txq
->axq_acq
);
1319 spin_lock_init(&txq
->axq_lock
);
1321 txq
->axq_ampdu_depth
= 0;
1322 txq
->axq_tx_inprogress
= false;
1323 sc
->tx
.txqsetup
|= 1<<axq_qnum
;
1325 txq
->txq_headidx
= txq
->txq_tailidx
= 0;
1326 for (i
= 0; i
< ATH_TXFIFO_DEPTH
; i
++)
1327 INIT_LIST_HEAD(&txq
->txq_fifo
[i
]);
1329 return &sc
->tx
.txq
[axq_qnum
];
1332 int ath_txq_update(struct ath_softc
*sc
, int qnum
,
1333 struct ath9k_tx_queue_info
*qinfo
)
1335 struct ath_hw
*ah
= sc
->sc_ah
;
1337 struct ath9k_tx_queue_info qi
;
1339 if (qnum
== sc
->beacon
.beaconq
) {
1341 * XXX: for beacon queue, we just save the parameter.
1342 * It will be picked up by ath_beaconq_config when
1345 sc
->beacon
.beacon_qi
= *qinfo
;
1349 BUG_ON(sc
->tx
.txq
[qnum
].axq_qnum
!= qnum
);
1351 ath9k_hw_get_txq_props(ah
, qnum
, &qi
);
1352 qi
.tqi_aifs
= qinfo
->tqi_aifs
;
1353 qi
.tqi_cwmin
= qinfo
->tqi_cwmin
;
1354 qi
.tqi_cwmax
= qinfo
->tqi_cwmax
;
1355 qi
.tqi_burstTime
= qinfo
->tqi_burstTime
;
1356 qi
.tqi_readyTime
= qinfo
->tqi_readyTime
;
1358 if (!ath9k_hw_set_txq_props(ah
, qnum
, &qi
)) {
1359 ath_err(ath9k_hw_common(sc
->sc_ah
),
1360 "Unable to update hardware queue %u!\n", qnum
);
1363 ath9k_hw_resettxqueue(ah
, qnum
);
1369 int ath_cabq_update(struct ath_softc
*sc
)
1371 struct ath9k_tx_queue_info qi
;
1372 struct ath_beacon_config
*cur_conf
= &sc
->cur_beacon_conf
;
1373 int qnum
= sc
->beacon
.cabq
->axq_qnum
;
1375 ath9k_hw_get_txq_props(sc
->sc_ah
, qnum
, &qi
);
1377 * Ensure the readytime % is within the bounds.
1379 if (sc
->config
.cabqReadytime
< ATH9K_READY_TIME_LO_BOUND
)
1380 sc
->config
.cabqReadytime
= ATH9K_READY_TIME_LO_BOUND
;
1381 else if (sc
->config
.cabqReadytime
> ATH9K_READY_TIME_HI_BOUND
)
1382 sc
->config
.cabqReadytime
= ATH9K_READY_TIME_HI_BOUND
;
1384 qi
.tqi_readyTime
= (cur_conf
->beacon_interval
*
1385 sc
->config
.cabqReadytime
) / 100;
1386 ath_txq_update(sc
, qnum
, &qi
);
1391 static bool bf_is_ampdu_not_probing(struct ath_buf
*bf
)
1393 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(bf
->bf_mpdu
);
1394 return bf_isampdu(bf
) && !(info
->flags
& IEEE80211_TX_CTL_RATE_CTRL_PROBE
);
1397 static void ath_drain_txq_list(struct ath_softc
*sc
, struct ath_txq
*txq
,
1398 struct list_head
*list
, bool retry_tx
)
1399 __releases(txq
->axq_lock
)
1400 __acquires(txq
->axq_lock
)
1402 struct ath_buf
*bf
, *lastbf
;
1403 struct list_head bf_head
;
1404 struct ath_tx_status ts
;
1406 memset(&ts
, 0, sizeof(ts
));
1407 INIT_LIST_HEAD(&bf_head
);
1409 while (!list_empty(list
)) {
1410 bf
= list_first_entry(list
, struct ath_buf
, list
);
1413 list_del(&bf
->list
);
1415 ath_tx_return_buffer(sc
, bf
);
1419 lastbf
= bf
->bf_lastbf
;
1420 list_cut_position(&bf_head
, list
, &lastbf
->list
);
1423 if (bf_is_ampdu_not_probing(bf
))
1424 txq
->axq_ampdu_depth
--;
1426 spin_unlock_bh(&txq
->axq_lock
);
1428 ath_tx_complete_aggr(sc
, txq
, bf
, &bf_head
, &ts
, 0,
1431 ath_tx_complete_buf(sc
, bf
, txq
, &bf_head
, &ts
, 0, 0);
1432 spin_lock_bh(&txq
->axq_lock
);
1437 * Drain a given TX queue (could be Beacon or Data)
1439 * This assumes output has been stopped and
1440 * we do not need to block ath_tx_tasklet.
1442 void ath_draintxq(struct ath_softc
*sc
, struct ath_txq
*txq
, bool retry_tx
)
1444 spin_lock_bh(&txq
->axq_lock
);
1445 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
) {
1446 int idx
= txq
->txq_tailidx
;
1448 while (!list_empty(&txq
->txq_fifo
[idx
])) {
1449 ath_drain_txq_list(sc
, txq
, &txq
->txq_fifo
[idx
],
1452 INCR(idx
, ATH_TXFIFO_DEPTH
);
1454 txq
->txq_tailidx
= idx
;
1457 txq
->axq_link
= NULL
;
1458 txq
->axq_tx_inprogress
= false;
1459 ath_drain_txq_list(sc
, txq
, &txq
->axq_q
, retry_tx
);
1461 /* flush any pending frames if aggregation is enabled */
1462 if ((sc
->sc_flags
& SC_OP_TXAGGR
) && !retry_tx
)
1463 ath_txq_drain_pending_buffers(sc
, txq
);
1465 spin_unlock_bh(&txq
->axq_lock
);
1468 bool ath_drain_all_txq(struct ath_softc
*sc
, bool retry_tx
)
1470 struct ath_hw
*ah
= sc
->sc_ah
;
1471 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
1472 struct ath_txq
*txq
;
1475 if (sc
->sc_flags
& SC_OP_INVALID
)
1478 ath9k_hw_abort_tx_dma(ah
);
1480 /* Check if any queue remains active */
1481 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
1482 if (!ATH_TXQ_SETUP(sc
, i
))
1485 npend
+= ath9k_hw_numtxpending(ah
, sc
->tx
.txq
[i
].axq_qnum
);
1489 ath_err(common
, "Failed to stop TX DMA!\n");
1491 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
1492 if (!ATH_TXQ_SETUP(sc
, i
))
1496 * The caller will resume queues with ieee80211_wake_queues.
1497 * Mark the queue as not stopped to prevent ath_tx_complete
1498 * from waking the queue too early.
1500 txq
= &sc
->tx
.txq
[i
];
1501 txq
->stopped
= false;
1502 ath_draintxq(sc
, txq
, retry_tx
);
1508 void ath_tx_cleanupq(struct ath_softc
*sc
, struct ath_txq
*txq
)
1510 ath9k_hw_releasetxqueue(sc
->sc_ah
, txq
->axq_qnum
);
1511 sc
->tx
.txqsetup
&= ~(1<<txq
->axq_qnum
);
1514 /* For each axq_acq entry, for each tid, try to schedule packets
1515 * for transmit until ampdu_depth has reached min Q depth.
1517 void ath_txq_schedule(struct ath_softc
*sc
, struct ath_txq
*txq
)
1519 struct ath_atx_ac
*ac
, *ac_tmp
, *last_ac
;
1520 struct ath_atx_tid
*tid
, *last_tid
;
1522 if (work_pending(&sc
->hw_reset_work
) || list_empty(&txq
->axq_acq
) ||
1523 txq
->axq_ampdu_depth
>= ATH_AGGR_MIN_QDEPTH
)
1526 ac
= list_first_entry(&txq
->axq_acq
, struct ath_atx_ac
, list
);
1527 last_ac
= list_entry(txq
->axq_acq
.prev
, struct ath_atx_ac
, list
);
1529 list_for_each_entry_safe(ac
, ac_tmp
, &txq
->axq_acq
, list
) {
1530 last_tid
= list_entry(ac
->tid_q
.prev
, struct ath_atx_tid
, list
);
1531 list_del(&ac
->list
);
1534 while (!list_empty(&ac
->tid_q
)) {
1535 tid
= list_first_entry(&ac
->tid_q
, struct ath_atx_tid
,
1537 list_del(&tid
->list
);
1543 ath_tx_sched_aggr(sc
, txq
, tid
);
1546 * add tid to round-robin queue if more frames
1547 * are pending for the tid
1549 if (!skb_queue_empty(&tid
->buf_q
))
1550 ath_tx_queue_tid(txq
, tid
);
1552 if (tid
== last_tid
||
1553 txq
->axq_ampdu_depth
>= ATH_AGGR_MIN_QDEPTH
)
1557 if (!list_empty(&ac
->tid_q
)) {
1560 list_add_tail(&ac
->list
, &txq
->axq_acq
);
1564 if (ac
== last_ac
||
1565 txq
->axq_ampdu_depth
>= ATH_AGGR_MIN_QDEPTH
)
1575 * Insert a chain of ath_buf (descriptors) on a txq and
1576 * assume the descriptors are already chained together by caller.
1578 static void ath_tx_txqaddbuf(struct ath_softc
*sc
, struct ath_txq
*txq
,
1579 struct list_head
*head
, bool internal
)
1581 struct ath_hw
*ah
= sc
->sc_ah
;
1582 struct ath_common
*common
= ath9k_hw_common(ah
);
1583 struct ath_buf
*bf
, *bf_last
;
1584 bool puttxbuf
= false;
1588 * Insert the frame on the outbound list and
1589 * pass it on to the hardware.
1592 if (list_empty(head
))
1595 edma
= !!(ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
);
1596 bf
= list_first_entry(head
, struct ath_buf
, list
);
1597 bf_last
= list_entry(head
->prev
, struct ath_buf
, list
);
1599 ath_dbg(common
, ATH_DBG_QUEUE
,
1600 "qnum: %d, txq depth: %d\n", txq
->axq_qnum
, txq
->axq_depth
);
1602 if (edma
&& list_empty(&txq
->txq_fifo
[txq
->txq_headidx
])) {
1603 list_splice_tail_init(head
, &txq
->txq_fifo
[txq
->txq_headidx
]);
1604 INCR(txq
->txq_headidx
, ATH_TXFIFO_DEPTH
);
1607 list_splice_tail_init(head
, &txq
->axq_q
);
1609 if (txq
->axq_link
) {
1610 ath9k_hw_set_desc_link(ah
, txq
->axq_link
, bf
->bf_daddr
);
1611 ath_dbg(common
, ATH_DBG_XMIT
,
1612 "link[%u] (%p)=%llx (%p)\n",
1613 txq
->axq_qnum
, txq
->axq_link
,
1614 ito64(bf
->bf_daddr
), bf
->bf_desc
);
1618 txq
->axq_link
= bf_last
->bf_desc
;
1622 TX_STAT_INC(txq
->axq_qnum
, puttxbuf
);
1623 ath9k_hw_puttxbuf(ah
, txq
->axq_qnum
, bf
->bf_daddr
);
1624 ath_dbg(common
, ATH_DBG_XMIT
, "TXDP[%u] = %llx (%p)\n",
1625 txq
->axq_qnum
, ito64(bf
->bf_daddr
), bf
->bf_desc
);
1629 TX_STAT_INC(txq
->axq_qnum
, txstart
);
1630 ath9k_hw_txstart(ah
, txq
->axq_qnum
);
1635 if (bf_is_ampdu_not_probing(bf
))
1636 txq
->axq_ampdu_depth
++;
1640 static void ath_tx_send_ampdu(struct ath_softc
*sc
, struct ath_atx_tid
*tid
,
1641 struct sk_buff
*skb
, struct ath_tx_control
*txctl
)
1643 struct ath_frame_info
*fi
= get_frame_info(skb
);
1644 struct list_head bf_head
;
1648 * Do not queue to h/w when any of the following conditions is true:
1649 * - there are pending frames in software queue
1650 * - the TID is currently paused for ADDBA/BAR request
1651 * - seqno is not within block-ack window
1652 * - h/w queue depth exceeds low water mark
1654 if (!skb_queue_empty(&tid
->buf_q
) || tid
->paused
||
1655 !BAW_WITHIN(tid
->seq_start
, tid
->baw_size
, tid
->seq_next
) ||
1656 txctl
->txq
->axq_ampdu_depth
>= ATH_AGGR_MIN_QDEPTH
) {
1658 * Add this frame to software queue for scheduling later
1661 TX_STAT_INC(txctl
->txq
->axq_qnum
, a_queued_sw
);
1662 __skb_queue_tail(&tid
->buf_q
, skb
);
1663 if (!txctl
->an
|| !txctl
->an
->sleeping
)
1664 ath_tx_queue_tid(txctl
->txq
, tid
);
1668 bf
= ath_tx_setup_buffer(sc
, txctl
->txq
, tid
, skb
);
1672 bf
->bf_state
.bf_type
= BUF_AMPDU
;
1673 INIT_LIST_HEAD(&bf_head
);
1674 list_add(&bf
->list
, &bf_head
);
1676 /* Add sub-frame to BAW */
1677 ath_tx_addto_baw(sc
, tid
, bf
->bf_state
.seqno
);
1679 /* Queue to h/w without aggregation */
1680 TX_STAT_INC(txctl
->txq
->axq_qnum
, a_queued_hw
);
1682 ath_tx_fill_desc(sc
, bf
, txctl
->txq
, fi
->framelen
);
1683 ath_tx_txqaddbuf(sc
, txctl
->txq
, &bf_head
, false);
1686 static void ath_tx_send_normal(struct ath_softc
*sc
, struct ath_txq
*txq
,
1687 struct ath_atx_tid
*tid
, struct sk_buff
*skb
)
1689 struct ath_frame_info
*fi
= get_frame_info(skb
);
1690 struct list_head bf_head
;
1695 bf
= ath_tx_setup_buffer(sc
, txq
, tid
, skb
);
1700 INIT_LIST_HEAD(&bf_head
);
1701 list_add_tail(&bf
->list
, &bf_head
);
1702 bf
->bf_state
.bf_type
= 0;
1704 /* update starting sequence number for subsequent ADDBA request */
1706 INCR(tid
->seq_start
, IEEE80211_SEQ_MAX
);
1709 ath_tx_fill_desc(sc
, bf
, txq
, fi
->framelen
);
1710 ath_tx_txqaddbuf(sc
, txq
, &bf_head
, false);
1711 TX_STAT_INC(txq
->axq_qnum
, queued
);
1714 static void setup_frame_info(struct ieee80211_hw
*hw
, struct sk_buff
*skb
,
1717 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1718 struct ieee80211_sta
*sta
= tx_info
->control
.sta
;
1719 struct ieee80211_key_conf
*hw_key
= tx_info
->control
.hw_key
;
1720 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1721 struct ath_frame_info
*fi
= get_frame_info(skb
);
1722 struct ath_node
*an
= NULL
;
1723 enum ath9k_key_type keytype
;
1725 keytype
= ath9k_cmn_get_hw_crypto_keytype(skb
);
1728 an
= (struct ath_node
*) sta
->drv_priv
;
1730 memset(fi
, 0, sizeof(*fi
));
1732 fi
->keyix
= hw_key
->hw_key_idx
;
1733 else if (an
&& ieee80211_is_data(hdr
->frame_control
) && an
->ps_key
> 0)
1734 fi
->keyix
= an
->ps_key
;
1736 fi
->keyix
= ATH9K_TXKEYIX_INVALID
;
1737 fi
->keytype
= keytype
;
1738 fi
->framelen
= framelen
;
1741 u8
ath_txchainmask_reduction(struct ath_softc
*sc
, u8 chainmask
, u32 rate
)
1743 struct ath_hw
*ah
= sc
->sc_ah
;
1744 struct ath9k_channel
*curchan
= ah
->curchan
;
1745 if ((ah
->caps
.hw_caps
& ATH9K_HW_CAP_APM
) &&
1746 (curchan
->channelFlags
& CHANNEL_5GHZ
) &&
1747 (chainmask
== 0x7) && (rate
< 0x90))
1754 * Assign a descriptor (and sequence number if necessary,
1755 * and map buffer for DMA. Frees skb on error
1757 static struct ath_buf
*ath_tx_setup_buffer(struct ath_softc
*sc
,
1758 struct ath_txq
*txq
,
1759 struct ath_atx_tid
*tid
,
1760 struct sk_buff
*skb
)
1762 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
1763 struct ath_frame_info
*fi
= get_frame_info(skb
);
1764 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1768 bf
= ath_tx_get_buffer(sc
);
1770 ath_dbg(common
, ATH_DBG_XMIT
, "TX buffers are full\n");
1774 ATH_TXBUF_RESET(bf
);
1777 seqno
= tid
->seq_next
;
1778 hdr
->seq_ctrl
= cpu_to_le16(tid
->seq_next
<< IEEE80211_SEQ_SEQ_SHIFT
);
1779 INCR(tid
->seq_next
, IEEE80211_SEQ_MAX
);
1780 bf
->bf_state
.seqno
= seqno
;
1785 bf
->bf_buf_addr
= dma_map_single(sc
->dev
, skb
->data
,
1786 skb
->len
, DMA_TO_DEVICE
);
1787 if (unlikely(dma_mapping_error(sc
->dev
, bf
->bf_buf_addr
))) {
1789 bf
->bf_buf_addr
= 0;
1790 ath_err(ath9k_hw_common(sc
->sc_ah
),
1791 "dma_mapping_error() on TX\n");
1792 ath_tx_return_buffer(sc
, bf
);
1801 dev_kfree_skb_any(skb
);
1805 /* FIXME: tx power */
1806 static void ath_tx_start_dma(struct ath_softc
*sc
, struct sk_buff
*skb
,
1807 struct ath_tx_control
*txctl
)
1809 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1810 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
1811 struct ath_atx_tid
*tid
= NULL
;
1815 spin_lock_bh(&txctl
->txq
->axq_lock
);
1816 if ((sc
->sc_flags
& SC_OP_TXAGGR
) && txctl
->an
&&
1817 ieee80211_is_data_qos(hdr
->frame_control
)) {
1818 tidno
= ieee80211_get_qos_ctl(hdr
)[0] &
1819 IEEE80211_QOS_CTL_TID_MASK
;
1820 tid
= ATH_AN_2_TID(txctl
->an
, tidno
);
1822 WARN_ON(tid
->ac
->txq
!= txctl
->txq
);
1825 if ((tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
) && tid
) {
1827 * Try aggregation if it's a unicast data frame
1828 * and the destination is HT capable.
1830 ath_tx_send_ampdu(sc
, tid
, skb
, txctl
);
1832 bf
= ath_tx_setup_buffer(sc
, txctl
->txq
, tid
, skb
);
1836 bf
->bf_state
.bfs_paprd
= txctl
->paprd
;
1839 bf
->bf_state
.bfs_paprd_timestamp
= jiffies
;
1841 ath_tx_send_normal(sc
, txctl
->txq
, tid
, skb
);
1845 spin_unlock_bh(&txctl
->txq
->axq_lock
);
1848 /* Upon failure caller should free skb */
1849 int ath_tx_start(struct ieee80211_hw
*hw
, struct sk_buff
*skb
,
1850 struct ath_tx_control
*txctl
)
1852 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*) skb
->data
;
1853 struct ieee80211_tx_info
*info
= IEEE80211_SKB_CB(skb
);
1854 struct ieee80211_sta
*sta
= info
->control
.sta
;
1855 struct ieee80211_vif
*vif
= info
->control
.vif
;
1856 struct ath_softc
*sc
= hw
->priv
;
1857 struct ath_txq
*txq
= txctl
->txq
;
1858 int padpos
, padsize
;
1859 int frmlen
= skb
->len
+ FCS_LEN
;
1862 /* NOTE: sta can be NULL according to net/mac80211.h */
1864 txctl
->an
= (struct ath_node
*)sta
->drv_priv
;
1866 if (info
->control
.hw_key
)
1867 frmlen
+= info
->control
.hw_key
->icv_len
;
1870 * As a temporary workaround, assign seq# here; this will likely need
1871 * to be cleaned up to work better with Beacon transmission and virtual
1874 if (info
->flags
& IEEE80211_TX_CTL_ASSIGN_SEQ
) {
1875 if (info
->flags
& IEEE80211_TX_CTL_FIRST_FRAGMENT
)
1876 sc
->tx
.seq_no
+= 0x10;
1877 hdr
->seq_ctrl
&= cpu_to_le16(IEEE80211_SCTL_FRAG
);
1878 hdr
->seq_ctrl
|= cpu_to_le16(sc
->tx
.seq_no
);
1881 /* Add the padding after the header if this is not already done */
1882 padpos
= ath9k_cmn_padpos(hdr
->frame_control
);
1883 padsize
= padpos
& 3;
1884 if (padsize
&& skb
->len
> padpos
) {
1885 if (skb_headroom(skb
) < padsize
)
1888 skb_push(skb
, padsize
);
1889 memmove(skb
->data
, skb
->data
+ padsize
, padpos
);
1892 if ((vif
&& vif
->type
!= NL80211_IFTYPE_AP
&&
1893 vif
->type
!= NL80211_IFTYPE_AP_VLAN
) ||
1894 !ieee80211_is_data(hdr
->frame_control
))
1895 info
->flags
|= IEEE80211_TX_CTL_CLEAR_PS_FILT
;
1897 setup_frame_info(hw
, skb
, frmlen
);
1900 * At this point, the vif, hw_key and sta pointers in the tx control
1901 * info are no longer valid (overwritten by the ath_frame_info data.
1904 q
= skb_get_queue_mapping(skb
);
1905 spin_lock_bh(&txq
->axq_lock
);
1906 if (txq
== sc
->tx
.txq_map
[q
] &&
1907 ++txq
->pending_frames
> ATH_MAX_QDEPTH
&& !txq
->stopped
) {
1908 ieee80211_stop_queue(sc
->hw
, q
);
1911 spin_unlock_bh(&txq
->axq_lock
);
1913 ath_tx_start_dma(sc
, skb
, txctl
);
1921 static void ath_tx_complete(struct ath_softc
*sc
, struct sk_buff
*skb
,
1922 int tx_flags
, struct ath_txq
*txq
)
1924 struct ieee80211_hw
*hw
= sc
->hw
;
1925 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1926 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
1927 struct ieee80211_hdr
* hdr
= (struct ieee80211_hdr
*)skb
->data
;
1928 int q
, padpos
, padsize
;
1930 ath_dbg(common
, ATH_DBG_XMIT
, "TX complete: skb: %p\n", skb
);
1932 if (tx_flags
& ATH_TX_BAR
)
1933 tx_info
->flags
|= IEEE80211_TX_STAT_AMPDU_NO_BACK
;
1935 if (!(tx_flags
& ATH_TX_ERROR
))
1936 /* Frame was ACKed */
1937 tx_info
->flags
|= IEEE80211_TX_STAT_ACK
;
1939 padpos
= ath9k_cmn_padpos(hdr
->frame_control
);
1940 padsize
= padpos
& 3;
1941 if (padsize
&& skb
->len
>padpos
+padsize
) {
1943 * Remove MAC header padding before giving the frame back to
1946 memmove(skb
->data
+ padsize
, skb
->data
, padpos
);
1947 skb_pull(skb
, padsize
);
1950 if (sc
->ps_flags
& PS_WAIT_FOR_TX_ACK
) {
1951 sc
->ps_flags
&= ~PS_WAIT_FOR_TX_ACK
;
1952 ath_dbg(common
, ATH_DBG_PS
,
1953 "Going back to sleep after having received TX status (0x%lx)\n",
1954 sc
->ps_flags
& (PS_WAIT_FOR_BEACON
|
1956 PS_WAIT_FOR_PSPOLL_DATA
|
1957 PS_WAIT_FOR_TX_ACK
));
1960 q
= skb_get_queue_mapping(skb
);
1961 if (txq
== sc
->tx
.txq_map
[q
]) {
1962 spin_lock_bh(&txq
->axq_lock
);
1963 if (WARN_ON(--txq
->pending_frames
< 0))
1964 txq
->pending_frames
= 0;
1966 if (txq
->stopped
&& txq
->pending_frames
< ATH_MAX_QDEPTH
) {
1967 ieee80211_wake_queue(sc
->hw
, q
);
1970 spin_unlock_bh(&txq
->axq_lock
);
1973 ieee80211_tx_status(hw
, skb
);
1976 static void ath_tx_complete_buf(struct ath_softc
*sc
, struct ath_buf
*bf
,
1977 struct ath_txq
*txq
, struct list_head
*bf_q
,
1978 struct ath_tx_status
*ts
, int txok
, int sendbar
)
1980 struct sk_buff
*skb
= bf
->bf_mpdu
;
1981 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
1982 unsigned long flags
;
1986 tx_flags
= ATH_TX_BAR
;
1989 tx_flags
|= ATH_TX_ERROR
;
1991 if (ts
->ts_status
& ATH9K_TXERR_FILT
)
1992 tx_info
->flags
|= IEEE80211_TX_STAT_TX_FILTERED
;
1994 dma_unmap_single(sc
->dev
, bf
->bf_buf_addr
, skb
->len
, DMA_TO_DEVICE
);
1995 bf
->bf_buf_addr
= 0;
1997 if (bf
->bf_state
.bfs_paprd
) {
1998 if (time_after(jiffies
,
1999 bf
->bf_state
.bfs_paprd_timestamp
+
2000 msecs_to_jiffies(ATH_PAPRD_TIMEOUT
)))
2001 dev_kfree_skb_any(skb
);
2003 complete(&sc
->paprd_complete
);
2005 ath_debug_stat_tx(sc
, bf
, ts
, txq
, tx_flags
);
2006 ath_tx_complete(sc
, skb
, tx_flags
, txq
);
2008 /* At this point, skb (bf->bf_mpdu) is consumed...make sure we don't
2009 * accidentally reference it later.
2014 * Return the list of ath_buf of this mpdu to free queue
2016 spin_lock_irqsave(&sc
->tx
.txbuflock
, flags
);
2017 list_splice_tail_init(bf_q
, &sc
->tx
.txbuf
);
2018 spin_unlock_irqrestore(&sc
->tx
.txbuflock
, flags
);
2021 static void ath_tx_rc_status(struct ath_softc
*sc
, struct ath_buf
*bf
,
2022 struct ath_tx_status
*ts
, int nframes
, int nbad
,
2025 struct sk_buff
*skb
= bf
->bf_mpdu
;
2026 struct ieee80211_hdr
*hdr
= (struct ieee80211_hdr
*)skb
->data
;
2027 struct ieee80211_tx_info
*tx_info
= IEEE80211_SKB_CB(skb
);
2028 struct ieee80211_hw
*hw
= sc
->hw
;
2029 struct ath_hw
*ah
= sc
->sc_ah
;
2033 tx_info
->status
.ack_signal
= ts
->ts_rssi
;
2035 tx_rateindex
= ts
->ts_rateindex
;
2036 WARN_ON(tx_rateindex
>= hw
->max_rates
);
2038 if (tx_info
->flags
& IEEE80211_TX_CTL_AMPDU
) {
2039 tx_info
->flags
|= IEEE80211_TX_STAT_AMPDU
;
2041 BUG_ON(nbad
> nframes
);
2043 tx_info
->status
.ampdu_len
= nframes
;
2044 tx_info
->status
.ampdu_ack_len
= nframes
- nbad
;
2047 if ((ts
->ts_status
& ATH9K_TXERR_FILT
) == 0 &&
2048 (tx_info
->flags
& IEEE80211_TX_CTL_NO_ACK
) == 0) {
2050 * If an underrun error is seen assume it as an excessive
2051 * retry only if max frame trigger level has been reached
2052 * (2 KB for single stream, and 4 KB for dual stream).
2053 * Adjust the long retry as if the frame was tried
2054 * hw->max_rate_tries times to affect how rate control updates
2055 * PER for the failed rate.
2056 * In case of congestion on the bus penalizing this type of
2057 * underruns should help hardware actually transmit new frames
2058 * successfully by eventually preferring slower rates.
2059 * This itself should also alleviate congestion on the bus.
2061 if (unlikely(ts
->ts_flags
& (ATH9K_TX_DATA_UNDERRUN
|
2062 ATH9K_TX_DELIM_UNDERRUN
)) &&
2063 ieee80211_is_data(hdr
->frame_control
) &&
2064 ah
->tx_trig_level
>= sc
->sc_ah
->config
.max_txtrig_level
)
2065 tx_info
->status
.rates
[tx_rateindex
].count
=
2069 for (i
= tx_rateindex
+ 1; i
< hw
->max_rates
; i
++) {
2070 tx_info
->status
.rates
[i
].count
= 0;
2071 tx_info
->status
.rates
[i
].idx
= -1;
2074 tx_info
->status
.rates
[tx_rateindex
].count
= ts
->ts_longretry
+ 1;
2077 static void ath_tx_process_buffer(struct ath_softc
*sc
, struct ath_txq
*txq
,
2078 struct ath_tx_status
*ts
, struct ath_buf
*bf
,
2079 struct list_head
*bf_head
)
2080 __releases(txq
->axq_lock
)
2081 __acquires(txq
->axq_lock
)
2086 txok
= !(ts
->ts_status
& ATH9K_TXERR_MASK
);
2087 txq
->axq_tx_inprogress
= false;
2088 if (bf_is_ampdu_not_probing(bf
))
2089 txq
->axq_ampdu_depth
--;
2091 spin_unlock_bh(&txq
->axq_lock
);
2093 if (!bf_isampdu(bf
)) {
2094 ath_tx_rc_status(sc
, bf
, ts
, 1, txok
? 0 : 1, txok
);
2095 ath_tx_complete_buf(sc
, bf
, txq
, bf_head
, ts
, txok
, 0);
2097 ath_tx_complete_aggr(sc
, txq
, bf
, bf_head
, ts
, txok
, true);
2099 spin_lock_bh(&txq
->axq_lock
);
2101 if (sc
->sc_flags
& SC_OP_TXAGGR
)
2102 ath_txq_schedule(sc
, txq
);
2105 static void ath_tx_processq(struct ath_softc
*sc
, struct ath_txq
*txq
)
2107 struct ath_hw
*ah
= sc
->sc_ah
;
2108 struct ath_common
*common
= ath9k_hw_common(ah
);
2109 struct ath_buf
*bf
, *lastbf
, *bf_held
= NULL
;
2110 struct list_head bf_head
;
2111 struct ath_desc
*ds
;
2112 struct ath_tx_status ts
;
2115 ath_dbg(common
, ATH_DBG_QUEUE
, "tx queue %d (%x), link %p\n",
2116 txq
->axq_qnum
, ath9k_hw_gettxbuf(sc
->sc_ah
, txq
->axq_qnum
),
2119 spin_lock_bh(&txq
->axq_lock
);
2121 if (work_pending(&sc
->hw_reset_work
))
2124 if (list_empty(&txq
->axq_q
)) {
2125 txq
->axq_link
= NULL
;
2126 if (sc
->sc_flags
& SC_OP_TXAGGR
)
2127 ath_txq_schedule(sc
, txq
);
2130 bf
= list_first_entry(&txq
->axq_q
, struct ath_buf
, list
);
2133 * There is a race condition that a BH gets scheduled
2134 * after sw writes TxE and before hw re-load the last
2135 * descriptor to get the newly chained one.
2136 * Software must keep the last DONE descriptor as a
2137 * holding descriptor - software does so by marking
2138 * it with the STALE flag.
2143 if (list_is_last(&bf_held
->list
, &txq
->axq_q
))
2146 bf
= list_entry(bf_held
->list
.next
, struct ath_buf
,
2150 lastbf
= bf
->bf_lastbf
;
2151 ds
= lastbf
->bf_desc
;
2153 memset(&ts
, 0, sizeof(ts
));
2154 status
= ath9k_hw_txprocdesc(ah
, ds
, &ts
);
2155 if (status
== -EINPROGRESS
)
2158 TX_STAT_INC(txq
->axq_qnum
, txprocdesc
);
2161 * Remove ath_buf's of the same transmit unit from txq,
2162 * however leave the last descriptor back as the holding
2163 * descriptor for hw.
2165 lastbf
->bf_stale
= true;
2166 INIT_LIST_HEAD(&bf_head
);
2167 if (!list_is_singular(&lastbf
->list
))
2168 list_cut_position(&bf_head
,
2169 &txq
->axq_q
, lastbf
->list
.prev
);
2172 list_del(&bf_held
->list
);
2173 ath_tx_return_buffer(sc
, bf_held
);
2176 ath_tx_process_buffer(sc
, txq
, &ts
, bf
, &bf_head
);
2178 spin_unlock_bh(&txq
->axq_lock
);
2181 static void ath_tx_complete_poll_work(struct work_struct
*work
)
2183 struct ath_softc
*sc
= container_of(work
, struct ath_softc
,
2184 tx_complete_work
.work
);
2185 struct ath_txq
*txq
;
2187 bool needreset
= false;
2188 #ifdef CONFIG_ATH9K_DEBUGFS
2189 sc
->tx_complete_poll_work_seen
++;
2192 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++)
2193 if (ATH_TXQ_SETUP(sc
, i
)) {
2194 txq
= &sc
->tx
.txq
[i
];
2195 spin_lock_bh(&txq
->axq_lock
);
2196 if (txq
->axq_depth
) {
2197 if (txq
->axq_tx_inprogress
) {
2199 spin_unlock_bh(&txq
->axq_lock
);
2202 txq
->axq_tx_inprogress
= true;
2205 spin_unlock_bh(&txq
->axq_lock
);
2209 ath_dbg(ath9k_hw_common(sc
->sc_ah
), ATH_DBG_RESET
,
2210 "tx hung, resetting the chip\n");
2211 ieee80211_queue_work(sc
->hw
, &sc
->hw_reset_work
);
2214 ieee80211_queue_delayed_work(sc
->hw
, &sc
->tx_complete_work
,
2215 msecs_to_jiffies(ATH_TX_COMPLETE_POLL_INT
));
2220 void ath_tx_tasklet(struct ath_softc
*sc
)
2223 u32 qcumask
= ((1 << ATH9K_NUM_TX_QUEUES
) - 1);
2225 ath9k_hw_gettxintrtxqs(sc
->sc_ah
, &qcumask
);
2227 for (i
= 0; i
< ATH9K_NUM_TX_QUEUES
; i
++) {
2228 if (ATH_TXQ_SETUP(sc
, i
) && (qcumask
& (1 << i
)))
2229 ath_tx_processq(sc
, &sc
->tx
.txq
[i
]);
2233 void ath_tx_edma_tasklet(struct ath_softc
*sc
)
2235 struct ath_tx_status ts
;
2236 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
2237 struct ath_hw
*ah
= sc
->sc_ah
;
2238 struct ath_txq
*txq
;
2239 struct ath_buf
*bf
, *lastbf
;
2240 struct list_head bf_head
;
2244 if (work_pending(&sc
->hw_reset_work
))
2247 status
= ath9k_hw_txprocdesc(ah
, NULL
, (void *)&ts
);
2248 if (status
== -EINPROGRESS
)
2250 if (status
== -EIO
) {
2251 ath_dbg(common
, ATH_DBG_XMIT
,
2252 "Error processing tx status\n");
2256 /* Skip beacon completions */
2257 if (ts
.qid
== sc
->beacon
.beaconq
)
2260 txq
= &sc
->tx
.txq
[ts
.qid
];
2262 spin_lock_bh(&txq
->axq_lock
);
2264 if (list_empty(&txq
->txq_fifo
[txq
->txq_tailidx
])) {
2265 spin_unlock_bh(&txq
->axq_lock
);
2269 bf
= list_first_entry(&txq
->txq_fifo
[txq
->txq_tailidx
],
2270 struct ath_buf
, list
);
2271 lastbf
= bf
->bf_lastbf
;
2273 INIT_LIST_HEAD(&bf_head
);
2274 list_cut_position(&bf_head
, &txq
->txq_fifo
[txq
->txq_tailidx
],
2277 if (list_empty(&txq
->txq_fifo
[txq
->txq_tailidx
])) {
2278 INCR(txq
->txq_tailidx
, ATH_TXFIFO_DEPTH
);
2280 if (!list_empty(&txq
->axq_q
)) {
2281 struct list_head bf_q
;
2283 INIT_LIST_HEAD(&bf_q
);
2284 txq
->axq_link
= NULL
;
2285 list_splice_tail_init(&txq
->axq_q
, &bf_q
);
2286 ath_tx_txqaddbuf(sc
, txq
, &bf_q
, true);
2290 ath_tx_process_buffer(sc
, txq
, &ts
, bf
, &bf_head
);
2291 spin_unlock_bh(&txq
->axq_lock
);
2299 static int ath_txstatus_setup(struct ath_softc
*sc
, int size
)
2301 struct ath_descdma
*dd
= &sc
->txsdma
;
2302 u8 txs_len
= sc
->sc_ah
->caps
.txs_len
;
2304 dd
->dd_desc_len
= size
* txs_len
;
2305 dd
->dd_desc
= dma_alloc_coherent(sc
->dev
, dd
->dd_desc_len
,
2306 &dd
->dd_desc_paddr
, GFP_KERNEL
);
2313 static int ath_tx_edma_init(struct ath_softc
*sc
)
2317 err
= ath_txstatus_setup(sc
, ATH_TXSTATUS_RING_SIZE
);
2319 ath9k_hw_setup_statusring(sc
->sc_ah
, sc
->txsdma
.dd_desc
,
2320 sc
->txsdma
.dd_desc_paddr
,
2321 ATH_TXSTATUS_RING_SIZE
);
2326 static void ath_tx_edma_cleanup(struct ath_softc
*sc
)
2328 struct ath_descdma
*dd
= &sc
->txsdma
;
2330 dma_free_coherent(sc
->dev
, dd
->dd_desc_len
, dd
->dd_desc
,
2334 int ath_tx_init(struct ath_softc
*sc
, int nbufs
)
2336 struct ath_common
*common
= ath9k_hw_common(sc
->sc_ah
);
2339 spin_lock_init(&sc
->tx
.txbuflock
);
2341 error
= ath_descdma_setup(sc
, &sc
->tx
.txdma
, &sc
->tx
.txbuf
,
2345 "Failed to allocate tx descriptors: %d\n", error
);
2349 error
= ath_descdma_setup(sc
, &sc
->beacon
.bdma
, &sc
->beacon
.bbuf
,
2350 "beacon", ATH_BCBUF
, 1, 1);
2353 "Failed to allocate beacon descriptors: %d\n", error
);
2357 INIT_DELAYED_WORK(&sc
->tx_complete_work
, ath_tx_complete_poll_work
);
2359 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
) {
2360 error
= ath_tx_edma_init(sc
);
2372 void ath_tx_cleanup(struct ath_softc
*sc
)
2374 if (sc
->beacon
.bdma
.dd_desc_len
!= 0)
2375 ath_descdma_cleanup(sc
, &sc
->beacon
.bdma
, &sc
->beacon
.bbuf
);
2377 if (sc
->tx
.txdma
.dd_desc_len
!= 0)
2378 ath_descdma_cleanup(sc
, &sc
->tx
.txdma
, &sc
->tx
.txbuf
);
2380 if (sc
->sc_ah
->caps
.hw_caps
& ATH9K_HW_CAP_EDMA
)
2381 ath_tx_edma_cleanup(sc
);
2384 void ath_tx_node_init(struct ath_softc
*sc
, struct ath_node
*an
)
2386 struct ath_atx_tid
*tid
;
2387 struct ath_atx_ac
*ac
;
2390 for (tidno
= 0, tid
= &an
->tid
[tidno
];
2391 tidno
< WME_NUM_TID
;
2395 tid
->seq_start
= tid
->seq_next
= 0;
2396 tid
->baw_size
= WME_MAX_BA
;
2397 tid
->baw_head
= tid
->baw_tail
= 0;
2399 tid
->paused
= false;
2400 tid
->state
&= ~AGGR_CLEANUP
;
2401 __skb_queue_head_init(&tid
->buf_q
);
2402 acno
= TID_TO_WME_AC(tidno
);
2403 tid
->ac
= &an
->ac
[acno
];
2404 tid
->state
&= ~AGGR_ADDBA_COMPLETE
;
2405 tid
->state
&= ~AGGR_ADDBA_PROGRESS
;
2408 for (acno
= 0, ac
= &an
->ac
[acno
];
2409 acno
< WME_NUM_AC
; acno
++, ac
++) {
2411 ac
->txq
= sc
->tx
.txq_map
[acno
];
2412 INIT_LIST_HEAD(&ac
->tid_q
);
2416 void ath_tx_node_cleanup(struct ath_softc
*sc
, struct ath_node
*an
)
2418 struct ath_atx_ac
*ac
;
2419 struct ath_atx_tid
*tid
;
2420 struct ath_txq
*txq
;
2423 for (tidno
= 0, tid
= &an
->tid
[tidno
];
2424 tidno
< WME_NUM_TID
; tidno
++, tid
++) {
2429 spin_lock_bh(&txq
->axq_lock
);
2432 list_del(&tid
->list
);
2437 list_del(&ac
->list
);
2438 tid
->ac
->sched
= false;
2441 ath_tid_drain(sc
, txq
, tid
);
2442 tid
->state
&= ~AGGR_ADDBA_COMPLETE
;
2443 tid
->state
&= ~AGGR_CLEANUP
;
2445 spin_unlock_bh(&txq
->axq_lock
);