2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26 #include <linux/crc32.h>
27 #include <linux/kernel.h>
28 #include <linux/version.h>
29 #include <linux/module.h>
30 #include <linux/netdevice.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/etherdevice.h>
33 #include <linux/ethtool.h>
34 #include <linux/pci.h>
36 #include <linux/tcp.h>
38 #include <linux/delay.h>
39 #include <linux/workqueue.h>
40 #include <linux/if_vlan.h>
41 #include <linux/prefetch.h>
42 #include <linux/mii.h>
46 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
47 #define SKY2_VLAN_TAG_USED 1
52 #define DRV_NAME "sky2"
53 #define DRV_VERSION "1.9"
54 #define PFX DRV_NAME " "
57 * The Yukon II chipset takes 64 bit command blocks (called list elements)
58 * that are organized into three (receive, transmit, status) different rings
62 #define RX_LE_SIZE 1024
63 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
64 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
65 #define RX_DEF_PENDING RX_MAX_PENDING
66 #define RX_SKB_ALIGN 8
67 #define RX_BUF_WRITE 16
69 #define TX_RING_SIZE 512
70 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
71 #define TX_MIN_PENDING 64
72 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
74 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
75 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
76 #define TX_WATCHDOG (5 * HZ)
77 #define NAPI_WEIGHT 64
78 #define PHY_RETRIES 1000
80 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
82 static const u32 default_msg
=
83 NETIF_MSG_DRV
| NETIF_MSG_PROBE
| NETIF_MSG_LINK
84 | NETIF_MSG_TIMER
| NETIF_MSG_TX_ERR
| NETIF_MSG_RX_ERR
85 | NETIF_MSG_IFUP
| NETIF_MSG_IFDOWN
;
87 static int debug
= -1; /* defaults above */
88 module_param(debug
, int, 0);
89 MODULE_PARM_DESC(debug
, "Debug level (0=none,...,16=all)");
91 static int copybreak __read_mostly
= 128;
92 module_param(copybreak
, int, 0);
93 MODULE_PARM_DESC(copybreak
, "Receive copy threshold");
95 static int disable_msi
= 0;
96 module_param(disable_msi
, int, 0);
97 MODULE_PARM_DESC(disable_msi
, "Disable Message Signaled Interrupt (MSI)");
99 static int idle_timeout
= 100;
100 module_param(idle_timeout
, int, 0);
101 MODULE_PARM_DESC(idle_timeout
, "Idle timeout workaround for lost interrupts (ms)");
103 static const struct pci_device_id sky2_id_table
[] = {
104 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9000) },
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT
, 0x9E00) },
106 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4b00) }, /* DGE-560T */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK
, 0x4001) }, /* DGE-550SX */
108 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4340) },
109 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4341) },
110 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4342) },
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4343) },
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4344) },
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4345) },
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4346) },
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4347) },
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4350) },
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4351) },
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4352) },
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4353) },
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4360) },
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4361) },
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4362) },
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4363) },
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4364) },
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4365) },
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4366) },
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4367) },
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4368) },
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL
, 0x4369) },
133 MODULE_DEVICE_TABLE(pci
, sky2_id_table
);
135 /* Avoid conditionals by using array */
136 static const unsigned txqaddr
[] = { Q_XA1
, Q_XA2
};
137 static const unsigned rxqaddr
[] = { Q_R1
, Q_R2
};
138 static const u32 portirq_msk
[] = { Y2_IS_PORT_1
, Y2_IS_PORT_2
};
140 /* This driver supports yukon2 chipset only */
141 static const char *yukon2_name
[] = {
143 "EC Ultra", /* 0xb4 */
144 "UNKNOWN", /* 0xb5 */
149 /* Access to external PHY */
150 static int gm_phy_write(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16 val
)
154 gma_write16(hw
, port
, GM_SMI_DATA
, val
);
155 gma_write16(hw
, port
, GM_SMI_CTRL
,
156 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
) | GM_SMI_CT_REG_AD(reg
));
158 for (i
= 0; i
< PHY_RETRIES
; i
++) {
159 if (!(gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_BUSY
))
164 printk(KERN_WARNING PFX
"%s: phy write timeout\n", hw
->dev
[port
]->name
);
168 static int __gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
, u16
*val
)
172 gma_write16(hw
, port
, GM_SMI_CTRL
, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV
)
173 | GM_SMI_CT_REG_AD(reg
) | GM_SMI_CT_OP_RD
);
175 for (i
= 0; i
< PHY_RETRIES
; i
++) {
176 if (gma_read16(hw
, port
, GM_SMI_CTRL
) & GM_SMI_CT_RD_VAL
) {
177 *val
= gma_read16(hw
, port
, GM_SMI_DATA
);
187 static u16
gm_phy_read(struct sky2_hw
*hw
, unsigned port
, u16 reg
)
191 if (__gm_phy_read(hw
, port
, reg
, &v
) != 0)
192 printk(KERN_WARNING PFX
"%s: phy read timeout\n", hw
->dev
[port
]->name
);
196 static void sky2_set_power_state(struct sky2_hw
*hw
, pci_power_t state
)
201 pr_debug("sky2_set_power_state %d\n", state
);
202 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
204 power_control
= sky2_pci_read16(hw
, hw
->pm_cap
+ PCI_PM_PMC
);
205 vaux
= (sky2_read16(hw
, B0_CTST
) & Y2_VAUX_AVAIL
) &&
206 (power_control
& PCI_PM_CAP_PME_D3cold
);
208 power_control
= sky2_pci_read16(hw
, hw
->pm_cap
+ PCI_PM_CTRL
);
210 power_control
|= PCI_PM_CTRL_PME_STATUS
;
211 power_control
&= ~(PCI_PM_CTRL_STATE_MASK
);
215 /* switch power to VCC (WA for VAUX problem) */
216 sky2_write8(hw
, B0_POWER_CTRL
,
217 PC_VAUX_ENA
| PC_VCC_ENA
| PC_VAUX_OFF
| PC_VCC_ON
);
219 /* disable Core Clock Division, */
220 sky2_write32(hw
, B2_Y2_CLK_CTRL
, Y2_CLK_DIV_DIS
);
222 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
223 /* enable bits are inverted */
224 sky2_write8(hw
, B2_Y2_CLK_GATE
,
225 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
226 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
227 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
229 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
231 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
234 sky2_pci_write32(hw
, PCI_DEV_REG3
, 0);
235 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG4
);
236 reg1
&= P_ASPM_CONTROL_MSK
;
237 sky2_pci_write32(hw
, PCI_DEV_REG4
, reg1
);
238 sky2_pci_write32(hw
, PCI_DEV_REG5
, 0);
245 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
246 sky2_write8(hw
, B2_Y2_CLK_GATE
, 0);
248 /* enable bits are inverted */
249 sky2_write8(hw
, B2_Y2_CLK_GATE
,
250 Y2_PCI_CLK_LNK1_DIS
| Y2_COR_CLK_LNK1_DIS
|
251 Y2_CLK_GAT_LNK1_DIS
| Y2_PCI_CLK_LNK2_DIS
|
252 Y2_COR_CLK_LNK2_DIS
| Y2_CLK_GAT_LNK2_DIS
);
254 /* switch power to VAUX */
255 if (vaux
&& state
!= PCI_D3cold
)
256 sky2_write8(hw
, B0_POWER_CTRL
,
257 (PC_VAUX_ENA
| PC_VCC_ENA
|
258 PC_VAUX_ON
| PC_VCC_OFF
));
261 printk(KERN_ERR PFX
"Unknown power state %d\n", state
);
264 sky2_pci_write16(hw
, hw
->pm_cap
+ PCI_PM_CTRL
, power_control
);
265 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
268 static void sky2_gmac_reset(struct sky2_hw
*hw
, unsigned port
)
272 /* disable all GMAC IRQ's */
273 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), 0);
274 /* disable PHY IRQs */
275 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
277 gma_write16(hw
, port
, GM_MC_ADDR_H1
, 0); /* clear MC hash */
278 gma_write16(hw
, port
, GM_MC_ADDR_H2
, 0);
279 gma_write16(hw
, port
, GM_MC_ADDR_H3
, 0);
280 gma_write16(hw
, port
, GM_MC_ADDR_H4
, 0);
282 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
283 reg
|= GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
;
284 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
287 static void sky2_phy_init(struct sky2_hw
*hw
, unsigned port
)
289 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
290 u16 ctrl
, ct1000
, adv
, pg
, ledctrl
, ledover
, reg
;
292 if (sky2
->autoneg
== AUTONEG_ENABLE
&&
293 !(hw
->chip_id
== CHIP_ID_YUKON_XL
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
)) {
294 u16 ectrl
= gm_phy_read(hw
, port
, PHY_MARV_EXT_CTRL
);
296 ectrl
&= ~(PHY_M_EC_M_DSC_MSK
| PHY_M_EC_S_DSC_MSK
|
298 ectrl
|= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ
);
300 if (hw
->chip_id
== CHIP_ID_YUKON_EC
)
301 ectrl
|= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA
;
303 ectrl
|= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
305 gm_phy_write(hw
, port
, PHY_MARV_EXT_CTRL
, ectrl
);
308 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
309 if (sky2_is_copper(hw
)) {
310 if (hw
->chip_id
== CHIP_ID_YUKON_FE
) {
311 /* enable automatic crossover */
312 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
) >> 1;
314 /* disable energy detect */
315 ctrl
&= ~PHY_M_PC_EN_DET_MSK
;
317 /* enable automatic crossover */
318 ctrl
|= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO
);
320 if (sky2
->autoneg
== AUTONEG_ENABLE
&&
321 (hw
->chip_id
== CHIP_ID_YUKON_XL
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
)) {
322 ctrl
&= ~PHY_M_PC_DSC_MSK
;
323 ctrl
|= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA
;
327 /* workaround for deviation #4.88 (CRC errors) */
328 /* disable Automatic Crossover */
330 ctrl
&= ~PHY_M_PC_MDIX_MSK
;
333 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
335 /* special setup for PHY 88E1112 Fiber */
336 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& !sky2_is_copper(hw
)) {
337 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
339 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
340 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 2);
341 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
342 ctrl
&= ~PHY_M_MAC_MD_MSK
;
343 ctrl
|= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX
);
344 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ctrl
);
346 if (hw
->pmd_type
== 'P') {
347 /* select page 1 to access Fiber registers */
348 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 1);
350 /* for SFP-module set SIGDET polarity to low */
351 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
352 ctrl
|= PHY_M_FIB_SIGD_POL
;
353 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
356 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
359 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_CTRL
);
360 if (sky2
->autoneg
== AUTONEG_DISABLE
)
365 ctrl
|= PHY_CT_RESET
;
366 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
373 if (sky2
->autoneg
== AUTONEG_ENABLE
) {
374 if (sky2_is_copper(hw
)) {
375 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
376 ct1000
|= PHY_M_1000C_AFD
;
377 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
378 ct1000
|= PHY_M_1000C_AHD
;
379 if (sky2
->advertising
& ADVERTISED_100baseT_Full
)
380 adv
|= PHY_M_AN_100_FD
;
381 if (sky2
->advertising
& ADVERTISED_100baseT_Half
)
382 adv
|= PHY_M_AN_100_HD
;
383 if (sky2
->advertising
& ADVERTISED_10baseT_Full
)
384 adv
|= PHY_M_AN_10_FD
;
385 if (sky2
->advertising
& ADVERTISED_10baseT_Half
)
386 adv
|= PHY_M_AN_10_HD
;
387 } else { /* special defines for FIBER (88E1040S only) */
388 if (sky2
->advertising
& ADVERTISED_1000baseT_Full
)
389 adv
|= PHY_M_AN_1000X_AFD
;
390 if (sky2
->advertising
& ADVERTISED_1000baseT_Half
)
391 adv
|= PHY_M_AN_1000X_AHD
;
394 /* Set Flow-control capabilities */
395 if (sky2
->tx_pause
&& sky2
->rx_pause
)
396 adv
|= PHY_AN_PAUSE_CAP
; /* symmetric */
397 else if (sky2
->rx_pause
&& !sky2
->tx_pause
)
398 adv
|= PHY_AN_PAUSE_ASYM
| PHY_AN_PAUSE_CAP
;
399 else if (!sky2
->rx_pause
&& sky2
->tx_pause
)
400 adv
|= PHY_AN_PAUSE_ASYM
; /* local */
402 /* Restart Auto-negotiation */
403 ctrl
|= PHY_CT_ANE
| PHY_CT_RE_CFG
;
405 /* forced speed/duplex settings */
406 ct1000
= PHY_M_1000C_MSE
;
408 /* Disable auto update for duplex flow control and speed */
409 reg
|= GM_GPCR_AU_ALL_DIS
;
411 switch (sky2
->speed
) {
413 ctrl
|= PHY_CT_SP1000
;
414 reg
|= GM_GPCR_SPEED_1000
;
417 ctrl
|= PHY_CT_SP100
;
418 reg
|= GM_GPCR_SPEED_100
;
422 if (sky2
->duplex
== DUPLEX_FULL
) {
423 reg
|= GM_GPCR_DUP_FULL
;
424 ctrl
|= PHY_CT_DUP_MD
;
425 } else if (sky2
->speed
!= SPEED_1000
&& hw
->chip_id
!= CHIP_ID_YUKON_EC_U
) {
426 /* Turn off flow control for 10/100mbps */
432 reg
|= GM_GPCR_FC_RX_DIS
;
435 reg
|= GM_GPCR_FC_TX_DIS
;
437 /* Forward pause packets to GMAC? */
438 if (sky2
->tx_pause
|| sky2
->rx_pause
)
439 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
441 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
443 ctrl
|= PHY_CT_RESET
;
446 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
448 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
449 gm_phy_write(hw
, port
, PHY_MARV_1000T_CTRL
, ct1000
);
451 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
, adv
);
452 gm_phy_write(hw
, port
, PHY_MARV_CTRL
, ctrl
);
454 /* Setup Phy LED's */
455 ledctrl
= PHY_M_LED_PULS_DUR(PULS_170MS
);
458 switch (hw
->chip_id
) {
459 case CHIP_ID_YUKON_FE
:
460 /* on 88E3082 these bits are at 11..9 (shifted left) */
461 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) << 1;
463 ctrl
= gm_phy_read(hw
, port
, PHY_MARV_FE_LED_PAR
);
465 /* delete ACT LED control bits */
466 ctrl
&= ~PHY_M_FELP_LED1_MSK
;
467 /* change ACT LED control to blink mode */
468 ctrl
|= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL
);
469 gm_phy_write(hw
, port
, PHY_MARV_FE_LED_PAR
, ctrl
);
472 case CHIP_ID_YUKON_XL
:
473 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
475 /* select page 3 to access LED control register */
476 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
478 /* set LED Function Control register */
479 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
480 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
481 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
482 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
483 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
485 /* set Polarity Control register */
486 gm_phy_write(hw
, port
, PHY_MARV_PHY_STAT
,
487 (PHY_M_POLC_LS1_P_MIX(4) |
488 PHY_M_POLC_IS0_P_MIX(4) |
489 PHY_M_POLC_LOS_CTRL(2) |
490 PHY_M_POLC_INIT_CTRL(2) |
491 PHY_M_POLC_STA1_CTRL(2) |
492 PHY_M_POLC_STA0_CTRL(2)));
494 /* restore page register */
495 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
497 case CHIP_ID_YUKON_EC_U
:
498 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
500 /* select page 3 to access LED control register */
501 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
503 /* set LED Function Control register */
504 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
505 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
506 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
507 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
508 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
510 /* set Blink Rate in LED Timer Control Register */
511 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
,
512 ledctrl
| PHY_M_LED_BLINK_RT(BLINK_84MS
));
513 /* restore page register */
514 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
518 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
519 ledctrl
|= PHY_M_LED_BLINK_RT(BLINK_84MS
) | PHY_M_LEDC_TX_CTRL
;
520 /* turn off the Rx LED (LED_RX) */
521 ledover
|= PHY_M_LED_MO_RX(MO_LED_OFF
);
524 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& hw
->chip_rev
== CHIP_REV_YU_EC_A1
) {
525 /* apply fixes in PHY AFE */
526 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
527 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 255);
529 /* increase differential signal amplitude in 10BASE-T */
530 gm_phy_write(hw
, port
, 0x18, 0xaa99);
531 gm_phy_write(hw
, port
, 0x17, 0x2011);
533 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
534 gm_phy_write(hw
, port
, 0x18, 0xa204);
535 gm_phy_write(hw
, port
, 0x17, 0x2002);
537 /* set page register to 0 */
538 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
540 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
542 if (sky2
->autoneg
== AUTONEG_DISABLE
|| sky2
->speed
== SPEED_100
) {
543 /* turn on 100 Mbps LED (LED_LINK100) */
544 ledover
|= PHY_M_LED_MO_100(MO_LED_ON
);
548 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
552 /* Enable phy interrupt on auto-negotiation complete (or link up) */
553 if (sky2
->autoneg
== AUTONEG_ENABLE
)
554 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_IS_AN_COMPL
);
556 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
559 static void sky2_phy_power(struct sky2_hw
*hw
, unsigned port
, int onoff
)
562 static const u32 phy_power
[]
563 = { PCI_Y2_PHY1_POWD
, PCI_Y2_PHY2_POWD
};
565 /* looks like this XL is back asswards .. */
566 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
> 1)
569 reg1
= sky2_pci_read32(hw
, PCI_DEV_REG1
);
572 /* Turn off phy power saving */
573 reg1
&= ~phy_power
[port
];
575 reg1
|= phy_power
[port
];
577 sky2_pci_write32(hw
, PCI_DEV_REG1
, reg1
);
578 sky2_pci_read32(hw
, PCI_DEV_REG1
);
582 /* Force a renegotiation */
583 static void sky2_phy_reinit(struct sky2_port
*sky2
)
585 spin_lock_bh(&sky2
->phy_lock
);
586 sky2_phy_init(sky2
->hw
, sky2
->port
);
587 spin_unlock_bh(&sky2
->phy_lock
);
590 static void sky2_mac_init(struct sky2_hw
*hw
, unsigned port
)
592 struct sky2_port
*sky2
= netdev_priv(hw
->dev
[port
]);
595 const u8
*addr
= hw
->dev
[port
]->dev_addr
;
597 sky2_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
598 sky2_write32(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_CLR
|GPC_ENA_PAUSE
);
600 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_CLR
);
602 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0 && port
== 1) {
603 /* WA DEV_472 -- looks like crossed wires on port 2 */
604 /* clear GMAC 1 Control reset */
605 sky2_write8(hw
, SK_REG(0, GMAC_CTRL
), GMC_RST_CLR
);
607 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_SET
);
608 sky2_write8(hw
, SK_REG(1, GMAC_CTRL
), GMC_RST_CLR
);
609 } while (gm_phy_read(hw
, 1, PHY_MARV_ID0
) != PHY_MARV_ID0_VAL
||
610 gm_phy_read(hw
, 1, PHY_MARV_ID1
) != PHY_MARV_ID1_Y2
||
611 gm_phy_read(hw
, 1, PHY_MARV_INT_MASK
) != 0);
614 sky2_read16(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
616 /* Enable Transmit FIFO Underrun */
617 sky2_write8(hw
, SK_REG(port
, GMAC_IRQ_MSK
), GMAC_DEF_MSK
);
619 spin_lock_bh(&sky2
->phy_lock
);
620 sky2_phy_init(hw
, port
);
621 spin_unlock_bh(&sky2
->phy_lock
);
624 reg
= gma_read16(hw
, port
, GM_PHY_ADDR
);
625 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
| GM_PAR_MIB_CLR
);
627 for (i
= GM_MIB_CNT_BASE
; i
<= GM_MIB_CNT_END
; i
+= 4)
628 gma_read16(hw
, port
, i
);
629 gma_write16(hw
, port
, GM_PHY_ADDR
, reg
);
631 /* transmit control */
632 gma_write16(hw
, port
, GM_TX_CTRL
, TX_COL_THR(TX_COL_DEF
));
634 /* receive control reg: unicast + multicast + no FCS */
635 gma_write16(hw
, port
, GM_RX_CTRL
,
636 GM_RXCR_UCF_ENA
| GM_RXCR_CRC_DIS
| GM_RXCR_MCF_ENA
);
638 /* transmit flow control */
639 gma_write16(hw
, port
, GM_TX_FLOW_CTRL
, 0xffff);
641 /* transmit parameter */
642 gma_write16(hw
, port
, GM_TX_PARAM
,
643 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF
) |
644 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF
) |
645 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF
) |
646 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF
));
648 /* serial mode register */
649 reg
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
650 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
652 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
)
653 reg
|= GM_SMOD_JUMBO_ENA
;
655 gma_write16(hw
, port
, GM_SERIAL_MODE
, reg
);
657 /* virtual address for data */
658 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, addr
);
660 /* physical address: used for pause frames */
661 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, addr
);
663 /* ignore counter overflows */
664 gma_write16(hw
, port
, GM_TX_IRQ_MSK
, 0);
665 gma_write16(hw
, port
, GM_RX_IRQ_MSK
, 0);
666 gma_write16(hw
, port
, GM_TR_IRQ_MSK
, 0);
668 /* Configure Rx MAC FIFO */
669 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_CLR
);
670 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
),
671 GMF_OPER_ON
| GMF_RX_F_FL_ON
);
673 /* Flush Rx MAC FIFO on any flow control or error */
674 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_MSK
), GMR_FS_ANY_ERR
);
676 /* Set threshold to 0xa (64 bytes)
677 * ASF disabled so no need to do WA dev #4.30
679 sky2_write16(hw
, SK_REG(port
, RX_GMF_FL_THR
), RX_GMF_FL_THR_DEF
);
681 /* Configure Tx MAC FIFO */
682 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_CLR
);
683 sky2_write16(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_OPER_ON
);
685 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
686 sky2_write8(hw
, SK_REG(port
, RX_GMF_LP_THR
), 512/8);
687 sky2_write8(hw
, SK_REG(port
, RX_GMF_UP_THR
), 1024/8);
688 if (hw
->dev
[port
]->mtu
> ETH_DATA_LEN
) {
689 /* set Tx GMAC FIFO Almost Empty Threshold */
690 sky2_write32(hw
, SK_REG(port
, TX_GMF_AE_THR
), 0x180);
691 /* Disable Store & Forward mode for TX */
692 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_STFW_DIS
);
698 /* Assign Ram Buffer allocation.
699 * start and end are in units of 4k bytes
700 * ram registers are in units of 64bit words
702 static void sky2_ramset(struct sky2_hw
*hw
, u16 q
, u8 startk
, u8 endk
)
706 start
= startk
* 4096/8;
707 end
= (endk
* 4096/8) - 1;
709 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_RST_CLR
);
710 sky2_write32(hw
, RB_ADDR(q
, RB_START
), start
);
711 sky2_write32(hw
, RB_ADDR(q
, RB_END
), end
);
712 sky2_write32(hw
, RB_ADDR(q
, RB_WP
), start
);
713 sky2_write32(hw
, RB_ADDR(q
, RB_RP
), start
);
715 if (q
== Q_R1
|| q
== Q_R2
) {
716 u32 space
= (endk
- startk
) * 4096/8;
717 u32 tp
= space
- space
/4;
719 /* On receive queue's set the thresholds
720 * give receiver priority when > 3/4 full
721 * send pause when down to 2K
723 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTHP
), tp
);
724 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTHP
), space
/2);
727 sky2_write32(hw
, RB_ADDR(q
, RB_RX_UTPP
), tp
);
728 sky2_write32(hw
, RB_ADDR(q
, RB_RX_LTPP
), space
/4);
730 /* Enable store & forward on Tx queue's because
731 * Tx FIFO is only 1K on Yukon
733 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_STFWD
);
736 sky2_write8(hw
, RB_ADDR(q
, RB_CTRL
), RB_ENA_OP_MD
);
737 sky2_read8(hw
, RB_ADDR(q
, RB_CTRL
));
740 /* Setup Bus Memory Interface */
741 static void sky2_qset(struct sky2_hw
*hw
, u16 q
)
743 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_CLR_RESET
);
744 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_OPER_INIT
);
745 sky2_write32(hw
, Q_ADDR(q
, Q_CSR
), BMU_FIFO_OP_ON
);
746 sky2_write32(hw
, Q_ADDR(q
, Q_WM
), BMU_WM_DEFAULT
);
749 /* Setup prefetch unit registers. This is the interface between
750 * hardware and driver list elements
752 static void sky2_prefetch_init(struct sky2_hw
*hw
, u32 qaddr
,
755 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
756 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_RST_CLR
);
757 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_HI
), addr
>> 32);
758 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_ADDR_LO
), (u32
) addr
);
759 sky2_write16(hw
, Y2_QADDR(qaddr
, PREF_UNIT_LAST_IDX
), last
);
760 sky2_write32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
), PREF_UNIT_OP_ON
);
762 sky2_read32(hw
, Y2_QADDR(qaddr
, PREF_UNIT_CTRL
));
765 static inline struct sky2_tx_le
*get_tx_le(struct sky2_port
*sky2
)
767 struct sky2_tx_le
*le
= sky2
->tx_le
+ sky2
->tx_prod
;
769 sky2
->tx_prod
= RING_NEXT(sky2
->tx_prod
, TX_RING_SIZE
);
774 static inline struct tx_ring_info
*tx_le_re(struct sky2_port
*sky2
,
775 struct sky2_tx_le
*le
)
777 return sky2
->tx_ring
+ (le
- sky2
->tx_le
);
780 /* Update chip's next pointer */
781 static inline void sky2_put_idx(struct sky2_hw
*hw
, unsigned q
, u16 idx
)
783 q
= Y2_QADDR(q
, PREF_UNIT_PUT_IDX
);
785 sky2_write16(hw
, q
, idx
);
790 static inline struct sky2_rx_le
*sky2_next_rx(struct sky2_port
*sky2
)
792 struct sky2_rx_le
*le
= sky2
->rx_le
+ sky2
->rx_put
;
793 sky2
->rx_put
= RING_NEXT(sky2
->rx_put
, RX_LE_SIZE
);
798 /* Return high part of DMA address (could be 32 or 64 bit) */
799 static inline u32
high32(dma_addr_t a
)
801 return sizeof(a
) > sizeof(u32
) ? (a
>> 16) >> 16 : 0;
804 /* Build description to hardware for one receive segment */
805 static void sky2_rx_add(struct sky2_port
*sky2
, u8 op
,
806 dma_addr_t map
, unsigned len
)
808 struct sky2_rx_le
*le
;
809 u32 hi
= high32(map
);
811 if (sky2
->rx_addr64
!= hi
) {
812 le
= sky2_next_rx(sky2
);
813 le
->addr
= cpu_to_le32(hi
);
814 le
->opcode
= OP_ADDR64
| HW_OWNER
;
815 sky2
->rx_addr64
= high32(map
+ len
);
818 le
= sky2_next_rx(sky2
);
819 le
->addr
= cpu_to_le32((u32
) map
);
820 le
->length
= cpu_to_le16(len
);
821 le
->opcode
= op
| HW_OWNER
;
824 /* Build description to hardware for one possibly fragmented skb */
825 static void sky2_rx_submit(struct sky2_port
*sky2
,
826 const struct rx_ring_info
*re
)
830 sky2_rx_add(sky2
, OP_PACKET
, re
->data_addr
, sky2
->rx_data_size
);
832 for (i
= 0; i
< skb_shinfo(re
->skb
)->nr_frags
; i
++)
833 sky2_rx_add(sky2
, OP_BUFFER
, re
->frag_addr
[i
], PAGE_SIZE
);
837 static void sky2_rx_map_skb(struct pci_dev
*pdev
, struct rx_ring_info
*re
,
840 struct sk_buff
*skb
= re
->skb
;
843 re
->data_addr
= pci_map_single(pdev
, skb
->data
, size
, PCI_DMA_FROMDEVICE
);
844 pci_unmap_len_set(re
, data_size
, size
);
846 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++)
847 re
->frag_addr
[i
] = pci_map_page(pdev
,
848 skb_shinfo(skb
)->frags
[i
].page
,
849 skb_shinfo(skb
)->frags
[i
].page_offset
,
850 skb_shinfo(skb
)->frags
[i
].size
,
854 static void sky2_rx_unmap_skb(struct pci_dev
*pdev
, struct rx_ring_info
*re
)
856 struct sk_buff
*skb
= re
->skb
;
859 pci_unmap_single(pdev
, re
->data_addr
, pci_unmap_len(re
, data_size
),
862 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++)
863 pci_unmap_page(pdev
, re
->frag_addr
[i
],
864 skb_shinfo(skb
)->frags
[i
].size
,
868 /* Tell chip where to start receive checksum.
869 * Actually has two checksums, but set both same to avoid possible byte
872 static void rx_set_checksum(struct sky2_port
*sky2
)
874 struct sky2_rx_le
*le
;
876 le
= sky2_next_rx(sky2
);
877 le
->addr
= cpu_to_le32((ETH_HLEN
<< 16) | ETH_HLEN
);
879 le
->opcode
= OP_TCPSTART
| HW_OWNER
;
881 sky2_write32(sky2
->hw
,
882 Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
883 sky2
->rx_csum
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
888 * The RX Stop command will not work for Yukon-2 if the BMU does not
889 * reach the end of packet and since we can't make sure that we have
890 * incoming data, we must reset the BMU while it is not doing a DMA
891 * transfer. Since it is possible that the RX path is still active,
892 * the RX RAM buffer will be stopped first, so any possible incoming
893 * data will not trigger a DMA. After the RAM buffer is stopped, the
894 * BMU is polled until any DMA in progress is ended and only then it
897 static void sky2_rx_stop(struct sky2_port
*sky2
)
899 struct sky2_hw
*hw
= sky2
->hw
;
900 unsigned rxq
= rxqaddr
[sky2
->port
];
903 /* disable the RAM Buffer receive queue */
904 sky2_write8(hw
, RB_ADDR(rxq
, RB_CTRL
), RB_DIS_OP_MD
);
906 for (i
= 0; i
< 0xffff; i
++)
907 if (sky2_read8(hw
, RB_ADDR(rxq
, Q_RSL
))
908 == sky2_read8(hw
, RB_ADDR(rxq
, Q_RL
)))
911 printk(KERN_WARNING PFX
"%s: receiver stop failed\n",
914 sky2_write32(hw
, Q_ADDR(rxq
, Q_CSR
), BMU_RST_SET
| BMU_FIFO_RST
);
916 /* reset the Rx prefetch unit */
917 sky2_write32(hw
, Y2_QADDR(rxq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
920 /* Clean out receive buffer area, assumes receiver hardware stopped */
921 static void sky2_rx_clean(struct sky2_port
*sky2
)
925 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
926 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
927 struct rx_ring_info
*re
= sky2
->rx_ring
+ i
;
930 sky2_rx_unmap_skb(sky2
->hw
->pdev
, re
);
937 /* Basic MII support */
938 static int sky2_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
940 struct mii_ioctl_data
*data
= if_mii(ifr
);
941 struct sky2_port
*sky2
= netdev_priv(dev
);
942 struct sky2_hw
*hw
= sky2
->hw
;
943 int err
= -EOPNOTSUPP
;
945 if (!netif_running(dev
))
946 return -ENODEV
; /* Phy still in reset */
950 data
->phy_id
= PHY_ADDR_MARV
;
956 spin_lock_bh(&sky2
->phy_lock
);
957 err
= __gm_phy_read(hw
, sky2
->port
, data
->reg_num
& 0x1f, &val
);
958 spin_unlock_bh(&sky2
->phy_lock
);
965 if (!capable(CAP_NET_ADMIN
))
968 spin_lock_bh(&sky2
->phy_lock
);
969 err
= gm_phy_write(hw
, sky2
->port
, data
->reg_num
& 0x1f,
971 spin_unlock_bh(&sky2
->phy_lock
);
977 #ifdef SKY2_VLAN_TAG_USED
978 static void sky2_vlan_rx_register(struct net_device
*dev
, struct vlan_group
*grp
)
980 struct sky2_port
*sky2
= netdev_priv(dev
);
981 struct sky2_hw
*hw
= sky2
->hw
;
982 u16 port
= sky2
->port
;
984 netif_tx_lock_bh(dev
);
986 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), RX_VLAN_STRIP_ON
);
987 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_VLAN_TAG_ON
);
990 netif_tx_unlock_bh(dev
);
993 static void sky2_vlan_rx_kill_vid(struct net_device
*dev
, unsigned short vid
)
995 struct sky2_port
*sky2
= netdev_priv(dev
);
996 struct sky2_hw
*hw
= sky2
->hw
;
997 u16 port
= sky2
->port
;
999 netif_tx_lock_bh(dev
);
1001 sky2_write32(hw
, SK_REG(port
, RX_GMF_CTRL_T
), RX_VLAN_STRIP_OFF
);
1002 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
), TX_VLAN_TAG_OFF
);
1004 sky2
->vlgrp
->vlan_devices
[vid
] = NULL
;
1006 netif_tx_unlock_bh(dev
);
1011 * Allocate an skb for receiving. If the MTU is large enough
1012 * make the skb non-linear with a fragment list of pages.
1014 * It appears the hardware has a bug in the FIFO logic that
1015 * cause it to hang if the FIFO gets overrun and the receive buffer
1016 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1017 * aligned except if slab debugging is enabled.
1019 static struct sk_buff
*sky2_rx_alloc(struct sky2_port
*sky2
)
1021 struct sk_buff
*skb
;
1025 skb
= netdev_alloc_skb(sky2
->netdev
, sky2
->rx_data_size
+ RX_SKB_ALIGN
);
1029 p
= (unsigned long) skb
->data
;
1030 skb_reserve(skb
, ALIGN(p
, RX_SKB_ALIGN
) - p
);
1032 for (i
= 0; i
< sky2
->rx_nfrags
; i
++) {
1033 struct page
*page
= alloc_page(GFP_ATOMIC
);
1037 skb_fill_page_desc(skb
, i
, page
, 0, PAGE_SIZE
);
1048 * Allocate and setup receiver buffer pool.
1049 * Normal case this ends up creating one list element for skb
1050 * in the receive ring. Worst case if using large MTU and each
1051 * allocation falls on a different 64 bit region, that results
1052 * in 6 list elements per ring entry.
1053 * One element is used for checksum enable/disable, and one
1054 * extra to avoid wrap.
1056 static int sky2_rx_start(struct sky2_port
*sky2
)
1058 struct sky2_hw
*hw
= sky2
->hw
;
1059 struct rx_ring_info
*re
;
1060 unsigned rxq
= rxqaddr
[sky2
->port
];
1061 unsigned i
, size
, space
, thresh
;
1063 sky2
->rx_put
= sky2
->rx_next
= 0;
1066 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& hw
->chip_rev
>= 2) {
1067 /* MAC Rx RAM Read is controlled by hardware */
1068 sky2_write32(hw
, Q_ADDR(rxq
, Q_F
), F_M_RX_RAM_DIS
);
1071 sky2_prefetch_init(hw
, rxq
, sky2
->rx_le_map
, RX_LE_SIZE
- 1);
1073 rx_set_checksum(sky2
);
1075 /* Space needed for frame data + headers rounded up */
1076 size
= ALIGN(sky2
->netdev
->mtu
+ ETH_HLEN
+ VLAN_HLEN
, 8)
1079 /* Stopping point for hardware truncation */
1080 thresh
= (size
- 8) / sizeof(u32
);
1082 /* Account for overhead of skb - to avoid order > 0 allocation */
1083 space
= SKB_DATA_ALIGN(size
) + NET_SKB_PAD
1084 + sizeof(struct skb_shared_info
);
1086 sky2
->rx_nfrags
= space
>> PAGE_SHIFT
;
1087 BUG_ON(sky2
->rx_nfrags
> ARRAY_SIZE(re
->frag_addr
));
1089 if (sky2
->rx_nfrags
!= 0) {
1090 /* Compute residue after pages */
1091 space
= sky2
->rx_nfrags
<< PAGE_SHIFT
;
1098 /* Optimize to handle small packets and headers */
1099 if (size
< copybreak
)
1101 if (size
< ETH_HLEN
)
1104 sky2
->rx_data_size
= size
;
1107 for (i
= 0; i
< sky2
->rx_pending
; i
++) {
1108 re
= sky2
->rx_ring
+ i
;
1110 re
->skb
= sky2_rx_alloc(sky2
);
1114 sky2_rx_map_skb(hw
->pdev
, re
, sky2
->rx_data_size
);
1115 sky2_rx_submit(sky2
, re
);
1119 * The receiver hangs if it receives frames larger than the
1120 * packet buffer. As a workaround, truncate oversize frames, but
1121 * the register is limited to 9 bits, so if you do frames > 2052
1122 * you better get the MTU right!
1125 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_OFF
);
1127 sky2_write16(hw
, SK_REG(sky2
->port
, RX_GMF_TR_THR
), thresh
);
1128 sky2_write32(hw
, SK_REG(sky2
->port
, RX_GMF_CTRL_T
), RX_TRUNC_ON
);
1131 /* Tell chip about available buffers */
1132 sky2_write16(hw
, Y2_QADDR(rxq
, PREF_UNIT_PUT_IDX
), sky2
->rx_put
);
1135 sky2_rx_clean(sky2
);
1139 /* Bring up network interface. */
1140 static int sky2_up(struct net_device
*dev
)
1142 struct sky2_port
*sky2
= netdev_priv(dev
);
1143 struct sky2_hw
*hw
= sky2
->hw
;
1144 unsigned port
= sky2
->port
;
1145 u32 ramsize
, rxspace
, imask
;
1146 int cap
, err
= -ENOMEM
;
1147 struct net_device
*otherdev
= hw
->dev
[sky2
->port
^1];
1150 * On dual port PCI-X card, there is an problem where status
1151 * can be received out of order due to split transactions
1153 if (otherdev
&& netif_running(otherdev
) &&
1154 (cap
= pci_find_capability(hw
->pdev
, PCI_CAP_ID_PCIX
))) {
1155 struct sky2_port
*osky2
= netdev_priv(otherdev
);
1158 cmd
= sky2_pci_read16(hw
, cap
+ PCI_X_CMD
);
1159 cmd
&= ~PCI_X_CMD_MAX_SPLIT
;
1160 sky2_pci_write16(hw
, cap
+ PCI_X_CMD
, cmd
);
1166 if (netif_msg_ifup(sky2
))
1167 printk(KERN_INFO PFX
"%s: enabling interface\n", dev
->name
);
1169 /* must be power of 2 */
1170 sky2
->tx_le
= pci_alloc_consistent(hw
->pdev
,
1172 sizeof(struct sky2_tx_le
),
1177 sky2
->tx_ring
= kcalloc(TX_RING_SIZE
, sizeof(struct tx_ring_info
),
1181 sky2
->tx_prod
= sky2
->tx_cons
= 0;
1183 sky2
->rx_le
= pci_alloc_consistent(hw
->pdev
, RX_LE_BYTES
,
1187 memset(sky2
->rx_le
, 0, RX_LE_BYTES
);
1189 sky2
->rx_ring
= kcalloc(sky2
->rx_pending
, sizeof(struct rx_ring_info
),
1194 sky2_phy_power(hw
, port
, 1);
1196 sky2_mac_init(hw
, port
);
1198 /* Determine available ram buffer space (in 4K blocks).
1199 * Note: not sure about the FE setting below yet
1201 if (hw
->chip_id
== CHIP_ID_YUKON_FE
)
1204 ramsize
= sky2_read8(hw
, B2_E_0
);
1206 /* Give transmitter one third (rounded up) */
1207 rxspace
= ramsize
- (ramsize
+ 2) / 3;
1209 sky2_ramset(hw
, rxqaddr
[port
], 0, rxspace
);
1210 sky2_ramset(hw
, txqaddr
[port
], rxspace
, ramsize
);
1212 /* Make sure SyncQ is disabled */
1213 sky2_write8(hw
, RB_ADDR(port
== 0 ? Q_XS1
: Q_XS2
, RB_CTRL
),
1216 sky2_qset(hw
, txqaddr
[port
]);
1218 /* Set almost empty threshold */
1219 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
1220 && hw
->chip_rev
== CHIP_REV_YU_EC_U_A0
)
1221 sky2_write16(hw
, Q_ADDR(txqaddr
[port
], Q_AL
), 0x1a0);
1223 sky2_prefetch_init(hw
, txqaddr
[port
], sky2
->tx_le_map
,
1226 err
= sky2_rx_start(sky2
);
1230 /* Enable interrupts from phy/mac for port */
1231 imask
= sky2_read32(hw
, B0_IMSK
);
1232 imask
|= portirq_msk
[port
];
1233 sky2_write32(hw
, B0_IMSK
, imask
);
1239 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1240 sky2
->rx_le
, sky2
->rx_le_map
);
1244 pci_free_consistent(hw
->pdev
,
1245 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1246 sky2
->tx_le
, sky2
->tx_le_map
);
1249 kfree(sky2
->tx_ring
);
1250 kfree(sky2
->rx_ring
);
1252 sky2
->tx_ring
= NULL
;
1253 sky2
->rx_ring
= NULL
;
1257 /* Modular subtraction in ring */
1258 static inline int tx_dist(unsigned tail
, unsigned head
)
1260 return (head
- tail
) & (TX_RING_SIZE
- 1);
1263 /* Number of list elements available for next tx */
1264 static inline int tx_avail(const struct sky2_port
*sky2
)
1266 return sky2
->tx_pending
- tx_dist(sky2
->tx_cons
, sky2
->tx_prod
);
1269 /* Estimate of number of transmit list elements required */
1270 static unsigned tx_le_req(const struct sk_buff
*skb
)
1274 count
= sizeof(dma_addr_t
) / sizeof(u32
);
1275 count
+= skb_shinfo(skb
)->nr_frags
* count
;
1277 if (skb_is_gso(skb
))
1280 if (skb
->ip_summed
== CHECKSUM_PARTIAL
)
1287 * Put one packet in ring for transmit.
1288 * A single packet can generate multiple list elements, and
1289 * the number of ring elements will probably be less than the number
1290 * of list elements used.
1292 static int sky2_xmit_frame(struct sk_buff
*skb
, struct net_device
*dev
)
1294 struct sky2_port
*sky2
= netdev_priv(dev
);
1295 struct sky2_hw
*hw
= sky2
->hw
;
1296 struct sky2_tx_le
*le
= NULL
;
1297 struct tx_ring_info
*re
;
1304 if (unlikely(tx_avail(sky2
) < tx_le_req(skb
)))
1305 return NETDEV_TX_BUSY
;
1307 if (unlikely(netif_msg_tx_queued(sky2
)))
1308 printk(KERN_DEBUG
"%s: tx queued, slot %u, len %d\n",
1309 dev
->name
, sky2
->tx_prod
, skb
->len
);
1311 len
= skb_headlen(skb
);
1312 mapping
= pci_map_single(hw
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
1313 addr64
= high32(mapping
);
1315 /* Send high bits if changed or crosses boundary */
1316 if (addr64
!= sky2
->tx_addr64
|| high32(mapping
+ len
) != sky2
->tx_addr64
) {
1317 le
= get_tx_le(sky2
);
1318 le
->addr
= cpu_to_le32(addr64
);
1319 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1320 sky2
->tx_addr64
= high32(mapping
+ len
);
1323 /* Check for TCP Segmentation Offload */
1324 mss
= skb_shinfo(skb
)->gso_size
;
1326 mss
+= ((skb
->h
.th
->doff
- 5) * 4); /* TCP options */
1327 mss
+= (skb
->nh
.iph
->ihl
* 4) + sizeof(struct tcphdr
);
1330 if (mss
!= sky2
->tx_last_mss
) {
1331 le
= get_tx_le(sky2
);
1332 le
->addr
= cpu_to_le32(mss
);
1333 le
->opcode
= OP_LRGLEN
| HW_OWNER
;
1334 sky2
->tx_last_mss
= mss
;
1339 #ifdef SKY2_VLAN_TAG_USED
1340 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1341 if (sky2
->vlgrp
&& vlan_tx_tag_present(skb
)) {
1343 le
= get_tx_le(sky2
);
1345 le
->opcode
= OP_VLAN
|HW_OWNER
;
1347 le
->opcode
|= OP_VLAN
;
1348 le
->length
= cpu_to_be16(vlan_tx_tag_get(skb
));
1353 /* Handle TCP checksum offload */
1354 if (skb
->ip_summed
== CHECKSUM_PARTIAL
) {
1355 unsigned offset
= skb
->h
.raw
- skb
->data
;
1358 tcpsum
= offset
<< 16; /* sum start */
1359 tcpsum
|= offset
+ skb
->csum
; /* sum write */
1361 ctrl
= CALSUM
| WR_SUM
| INIT_SUM
| LOCK_SUM
;
1362 if (skb
->nh
.iph
->protocol
== IPPROTO_UDP
)
1365 if (tcpsum
!= sky2
->tx_tcpsum
) {
1366 sky2
->tx_tcpsum
= tcpsum
;
1368 le
= get_tx_le(sky2
);
1369 le
->addr
= cpu_to_le32(tcpsum
);
1370 le
->length
= 0; /* initial checksum value */
1371 le
->ctrl
= 1; /* one packet */
1372 le
->opcode
= OP_TCPLISW
| HW_OWNER
;
1376 le
= get_tx_le(sky2
);
1377 le
->addr
= cpu_to_le32((u32
) mapping
);
1378 le
->length
= cpu_to_le16(len
);
1380 le
->opcode
= mss
? (OP_LARGESEND
| HW_OWNER
) : (OP_PACKET
| HW_OWNER
);
1382 re
= tx_le_re(sky2
, le
);
1384 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1385 pci_unmap_len_set(re
, maplen
, len
);
1387 for (i
= 0; i
< skb_shinfo(skb
)->nr_frags
; i
++) {
1388 const skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1390 mapping
= pci_map_page(hw
->pdev
, frag
->page
, frag
->page_offset
,
1391 frag
->size
, PCI_DMA_TODEVICE
);
1392 addr64
= high32(mapping
);
1393 if (addr64
!= sky2
->tx_addr64
) {
1394 le
= get_tx_le(sky2
);
1395 le
->addr
= cpu_to_le32(addr64
);
1397 le
->opcode
= OP_ADDR64
| HW_OWNER
;
1398 sky2
->tx_addr64
= addr64
;
1401 le
= get_tx_le(sky2
);
1402 le
->addr
= cpu_to_le32((u32
) mapping
);
1403 le
->length
= cpu_to_le16(frag
->size
);
1405 le
->opcode
= OP_BUFFER
| HW_OWNER
;
1407 re
= tx_le_re(sky2
, le
);
1409 pci_unmap_addr_set(re
, mapaddr
, mapping
);
1410 pci_unmap_len_set(re
, maplen
, frag
->size
);
1415 if (tx_avail(sky2
) <= MAX_SKB_TX_LE
)
1416 netif_stop_queue(dev
);
1418 sky2_put_idx(hw
, txqaddr
[sky2
->port
], sky2
->tx_prod
);
1420 dev
->trans_start
= jiffies
;
1421 return NETDEV_TX_OK
;
1425 * Free ring elements from starting at tx_cons until "done"
1427 * NB: the hardware will tell us about partial completion of multi-part
1428 * buffers so make sure not to free skb to early.
1430 static void sky2_tx_complete(struct sky2_port
*sky2
, u16 done
)
1432 struct net_device
*dev
= sky2
->netdev
;
1433 struct pci_dev
*pdev
= sky2
->hw
->pdev
;
1436 BUG_ON(done
>= TX_RING_SIZE
);
1438 for (idx
= sky2
->tx_cons
; idx
!= done
;
1439 idx
= RING_NEXT(idx
, TX_RING_SIZE
)) {
1440 struct sky2_tx_le
*le
= sky2
->tx_le
+ idx
;
1441 struct tx_ring_info
*re
= sky2
->tx_ring
+ idx
;
1443 switch(le
->opcode
& ~HW_OWNER
) {
1446 pci_unmap_single(pdev
,
1447 pci_unmap_addr(re
, mapaddr
),
1448 pci_unmap_len(re
, maplen
),
1452 pci_unmap_page(pdev
, pci_unmap_addr(re
, mapaddr
),
1453 pci_unmap_len(re
, maplen
),
1458 if (le
->ctrl
& EOP
) {
1459 if (unlikely(netif_msg_tx_done(sky2
)))
1460 printk(KERN_DEBUG
"%s: tx done %u\n",
1462 dev_kfree_skb(re
->skb
);
1465 le
->opcode
= 0; /* paranoia */
1468 sky2
->tx_cons
= idx
;
1469 if (tx_avail(sky2
) > MAX_SKB_TX_LE
+ 4)
1470 netif_wake_queue(dev
);
1473 /* Cleanup all untransmitted buffers, assume transmitter not running */
1474 static void sky2_tx_clean(struct net_device
*dev
)
1476 struct sky2_port
*sky2
= netdev_priv(dev
);
1478 netif_tx_lock_bh(dev
);
1479 sky2_tx_complete(sky2
, sky2
->tx_prod
);
1480 netif_tx_unlock_bh(dev
);
1483 /* Network shutdown */
1484 static int sky2_down(struct net_device
*dev
)
1486 struct sky2_port
*sky2
= netdev_priv(dev
);
1487 struct sky2_hw
*hw
= sky2
->hw
;
1488 unsigned port
= sky2
->port
;
1492 /* Never really got started! */
1496 if (netif_msg_ifdown(sky2
))
1497 printk(KERN_INFO PFX
"%s: disabling interface\n", dev
->name
);
1499 /* Stop more packets from being queued */
1500 netif_stop_queue(dev
);
1502 sky2_gmac_reset(hw
, port
);
1504 /* Stop transmitter */
1505 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_STOP
);
1506 sky2_read32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
));
1508 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
),
1509 RB_RST_SET
| RB_DIS_OP_MD
);
1511 /* WA for dev. #4.209 */
1512 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
1513 && hw
->chip_rev
== CHIP_REV_YU_EC_U_A1
)
1514 sky2_write32(hw
, SK_REG(port
, TX_GMF_CTRL_T
),
1515 sky2
->speed
!= SPEED_1000
?
1516 TX_STFW_ENA
: TX_STFW_DIS
);
1518 ctrl
= gma_read16(hw
, port
, GM_GP_CTRL
);
1519 ctrl
&= ~(GM_GPCR_TX_ENA
| GM_GPCR_RX_ENA
);
1520 gma_write16(hw
, port
, GM_GP_CTRL
, ctrl
);
1522 sky2_write8(hw
, SK_REG(port
, GPHY_CTRL
), GPC_RST_SET
);
1524 /* Workaround shared GMAC reset */
1525 if (!(hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0
1526 && port
== 0 && hw
->dev
[1] && netif_running(hw
->dev
[1])))
1527 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_RST_SET
);
1529 /* Disable Force Sync bit and Enable Alloc bit */
1530 sky2_write8(hw
, SK_REG(port
, TXA_CTRL
),
1531 TXA_DIS_FSYNC
| TXA_DIS_ALLOC
| TXA_STOP_RC
);
1533 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1534 sky2_write32(hw
, SK_REG(port
, TXA_ITI_INI
), 0L);
1535 sky2_write32(hw
, SK_REG(port
, TXA_LIM_INI
), 0L);
1537 /* Reset the PCI FIFO of the async Tx queue */
1538 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
),
1539 BMU_RST_SET
| BMU_FIFO_RST
);
1541 /* Reset the Tx prefetch units */
1542 sky2_write32(hw
, Y2_QADDR(txqaddr
[port
], PREF_UNIT_CTRL
),
1545 sky2_write32(hw
, RB_ADDR(txqaddr
[port
], RB_CTRL
), RB_RST_SET
);
1549 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_RST_SET
);
1550 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_RST_SET
);
1552 /* Disable port IRQ */
1553 imask
= sky2_read32(hw
, B0_IMSK
);
1554 imask
&= ~portirq_msk
[port
];
1555 sky2_write32(hw
, B0_IMSK
, imask
);
1557 sky2_phy_power(hw
, port
, 0);
1559 /* turn off LED's */
1560 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
1562 synchronize_irq(hw
->pdev
->irq
);
1565 sky2_rx_clean(sky2
);
1567 pci_free_consistent(hw
->pdev
, RX_LE_BYTES
,
1568 sky2
->rx_le
, sky2
->rx_le_map
);
1569 kfree(sky2
->rx_ring
);
1571 pci_free_consistent(hw
->pdev
,
1572 TX_RING_SIZE
* sizeof(struct sky2_tx_le
),
1573 sky2
->tx_le
, sky2
->tx_le_map
);
1574 kfree(sky2
->tx_ring
);
1579 sky2
->rx_ring
= NULL
;
1580 sky2
->tx_ring
= NULL
;
1585 static u16
sky2_phy_speed(const struct sky2_hw
*hw
, u16 aux
)
1587 if (!sky2_is_copper(hw
))
1590 if (hw
->chip_id
== CHIP_ID_YUKON_FE
)
1591 return (aux
& PHY_M_PS_SPEED_100
) ? SPEED_100
: SPEED_10
;
1593 switch (aux
& PHY_M_PS_SPEED_MSK
) {
1594 case PHY_M_PS_SPEED_1000
:
1596 case PHY_M_PS_SPEED_100
:
1603 static void sky2_link_up(struct sky2_port
*sky2
)
1605 struct sky2_hw
*hw
= sky2
->hw
;
1606 unsigned port
= sky2
->port
;
1610 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1611 reg
|= GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
;
1612 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1614 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, PHY_M_DEF_MSK
);
1616 netif_carrier_on(sky2
->netdev
);
1617 netif_wake_queue(sky2
->netdev
);
1619 /* Turn on link LED */
1620 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
),
1621 LINKLED_ON
| LINKLED_BLINK_OFF
| LINKLED_LINKSYNC_OFF
);
1623 if (hw
->chip_id
== CHIP_ID_YUKON_XL
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
) {
1624 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
1625 u16 led
= PHY_M_LEDC_LOS_CTRL(1); /* link active */
1627 switch(sky2
->speed
) {
1629 led
|= PHY_M_LEDC_INIT_CTRL(7);
1633 led
|= PHY_M_LEDC_STA1_CTRL(7);
1637 led
|= PHY_M_LEDC_STA0_CTRL(7);
1641 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
1642 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, led
);
1643 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
1646 if (netif_msg_link(sky2
))
1647 printk(KERN_INFO PFX
1648 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1649 sky2
->netdev
->name
, sky2
->speed
,
1650 sky2
->duplex
== DUPLEX_FULL
? "full" : "half",
1651 (sky2
->tx_pause
&& sky2
->rx_pause
) ? "both" :
1652 sky2
->tx_pause
? "tx" : sky2
->rx_pause
? "rx" : "none");
1655 static void sky2_link_down(struct sky2_port
*sky2
)
1657 struct sky2_hw
*hw
= sky2
->hw
;
1658 unsigned port
= sky2
->port
;
1661 gm_phy_write(hw
, port
, PHY_MARV_INT_MASK
, 0);
1663 reg
= gma_read16(hw
, port
, GM_GP_CTRL
);
1664 reg
&= ~(GM_GPCR_RX_ENA
| GM_GPCR_TX_ENA
);
1665 gma_write16(hw
, port
, GM_GP_CTRL
, reg
);
1667 if (sky2
->rx_pause
&& !sky2
->tx_pause
) {
1668 /* restore Asymmetric Pause bit */
1669 gm_phy_write(hw
, port
, PHY_MARV_AUNE_ADV
,
1670 gm_phy_read(hw
, port
, PHY_MARV_AUNE_ADV
)
1674 netif_carrier_off(sky2
->netdev
);
1675 netif_stop_queue(sky2
->netdev
);
1677 /* Turn on link LED */
1678 sky2_write8(hw
, SK_REG(port
, LNK_LED_REG
), LINKLED_OFF
);
1680 if (netif_msg_link(sky2
))
1681 printk(KERN_INFO PFX
"%s: Link is down.\n", sky2
->netdev
->name
);
1683 sky2_phy_init(hw
, port
);
1686 static int sky2_autoneg_done(struct sky2_port
*sky2
, u16 aux
)
1688 struct sky2_hw
*hw
= sky2
->hw
;
1689 unsigned port
= sky2
->port
;
1692 lpa
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_LP
);
1694 if (lpa
& PHY_M_AN_RF
) {
1695 printk(KERN_ERR PFX
"%s: remote fault", sky2
->netdev
->name
);
1699 if (!(aux
& PHY_M_PS_SPDUP_RES
)) {
1700 printk(KERN_ERR PFX
"%s: speed/duplex mismatch",
1701 sky2
->netdev
->name
);
1705 sky2
->speed
= sky2_phy_speed(hw
, aux
);
1706 if (sky2
->speed
== SPEED_1000
) {
1707 u16 ctl2
= gm_phy_read(hw
, port
, PHY_MARV_1000T_CTRL
);
1708 u16 lpa2
= gm_phy_read(hw
, port
, PHY_MARV_1000T_STAT
);
1709 if (lpa2
& PHY_B_1000S_MSF
) {
1710 printk(KERN_ERR PFX
"%s: master/slave fault",
1711 sky2
->netdev
->name
);
1715 if ((ctl2
& PHY_M_1000C_AFD
) && (lpa2
& PHY_B_1000S_LP_FD
))
1716 sky2
->duplex
= DUPLEX_FULL
;
1718 sky2
->duplex
= DUPLEX_HALF
;
1720 u16 adv
= gm_phy_read(hw
, port
, PHY_MARV_AUNE_ADV
);
1721 if ((aux
& adv
) & PHY_AN_FULL
)
1722 sky2
->duplex
= DUPLEX_FULL
;
1724 sky2
->duplex
= DUPLEX_HALF
;
1727 /* Pause bits are offset (9..8) */
1728 if (hw
->chip_id
== CHIP_ID_YUKON_XL
|| hw
->chip_id
== CHIP_ID_YUKON_EC_U
)
1731 sky2
->rx_pause
= (aux
& PHY_M_PS_RX_P_EN
) != 0;
1732 sky2
->tx_pause
= (aux
& PHY_M_PS_TX_P_EN
) != 0;
1734 if (sky2
->duplex
== DUPLEX_HALF
&& sky2
->speed
!= SPEED_1000
1735 && hw
->chip_id
!= CHIP_ID_YUKON_EC_U
)
1736 sky2
->rx_pause
= sky2
->tx_pause
= 0;
1738 if (sky2
->rx_pause
|| sky2
->tx_pause
)
1739 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_ON
);
1741 sky2_write8(hw
, SK_REG(port
, GMAC_CTRL
), GMC_PAUSE_OFF
);
1746 /* Interrupt from PHY */
1747 static void sky2_phy_intr(struct sky2_hw
*hw
, unsigned port
)
1749 struct net_device
*dev
= hw
->dev
[port
];
1750 struct sky2_port
*sky2
= netdev_priv(dev
);
1751 u16 istatus
, phystat
;
1753 spin_lock(&sky2
->phy_lock
);
1754 istatus
= gm_phy_read(hw
, port
, PHY_MARV_INT_STAT
);
1755 phystat
= gm_phy_read(hw
, port
, PHY_MARV_PHY_STAT
);
1757 if (!netif_running(dev
))
1760 if (netif_msg_intr(sky2
))
1761 printk(KERN_INFO PFX
"%s: phy interrupt status 0x%x 0x%x\n",
1762 sky2
->netdev
->name
, istatus
, phystat
);
1764 if (sky2
->autoneg
== AUTONEG_ENABLE
&& (istatus
& PHY_M_IS_AN_COMPL
)) {
1765 if (sky2_autoneg_done(sky2
, phystat
) == 0)
1770 if (istatus
& PHY_M_IS_LSP_CHANGE
)
1771 sky2
->speed
= sky2_phy_speed(hw
, phystat
);
1773 if (istatus
& PHY_M_IS_DUP_CHANGE
)
1775 (phystat
& PHY_M_PS_FULL_DUP
) ? DUPLEX_FULL
: DUPLEX_HALF
;
1777 if (istatus
& PHY_M_IS_LST_CHANGE
) {
1778 if (phystat
& PHY_M_PS_LINK_UP
)
1781 sky2_link_down(sky2
);
1784 spin_unlock(&sky2
->phy_lock
);
1788 /* Transmit timeout is only called if we are running, carries is up
1789 * and tx queue is full (stopped).
1791 static void sky2_tx_timeout(struct net_device
*dev
)
1793 struct sky2_port
*sky2
= netdev_priv(dev
);
1794 struct sky2_hw
*hw
= sky2
->hw
;
1795 unsigned txq
= txqaddr
[sky2
->port
];
1798 if (netif_msg_timer(sky2
))
1799 printk(KERN_ERR PFX
"%s: tx timeout\n", dev
->name
);
1801 report
= sky2_read16(hw
, sky2
->port
== 0 ? STAT_TXA1_RIDX
: STAT_TXA2_RIDX
);
1802 done
= sky2_read16(hw
, Q_ADDR(txq
, Q_DONE
));
1804 printk(KERN_DEBUG PFX
"%s: transmit ring %u .. %u report=%u done=%u\n",
1806 sky2
->tx_cons
, sky2
->tx_prod
, report
, done
);
1808 if (report
!= done
) {
1809 printk(KERN_INFO PFX
"status burst pending (irq moderation?)\n");
1811 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
1812 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
1813 } else if (report
!= sky2
->tx_cons
) {
1814 printk(KERN_INFO PFX
"status report lost?\n");
1816 netif_tx_lock_bh(dev
);
1817 sky2_tx_complete(sky2
, report
);
1818 netif_tx_unlock_bh(dev
);
1820 printk(KERN_INFO PFX
"hardware hung? flushing\n");
1822 sky2_write32(hw
, Q_ADDR(txq
, Q_CSR
), BMU_STOP
);
1823 sky2_write32(hw
, Y2_QADDR(txq
, PREF_UNIT_CTRL
), PREF_UNIT_RST_SET
);
1828 sky2_prefetch_init(hw
, txq
, sky2
->tx_le_map
, TX_RING_SIZE
- 1);
1832 static int sky2_change_mtu(struct net_device
*dev
, int new_mtu
)
1834 struct sky2_port
*sky2
= netdev_priv(dev
);
1835 struct sky2_hw
*hw
= sky2
->hw
;
1840 if (new_mtu
< ETH_ZLEN
|| new_mtu
> ETH_JUMBO_MTU
)
1843 if (hw
->chip_id
== CHIP_ID_YUKON_EC_U
&& new_mtu
> ETH_DATA_LEN
)
1846 if (!netif_running(dev
)) {
1851 imask
= sky2_read32(hw
, B0_IMSK
);
1852 sky2_write32(hw
, B0_IMSK
, 0);
1854 dev
->trans_start
= jiffies
; /* prevent tx timeout */
1855 netif_stop_queue(dev
);
1856 netif_poll_disable(hw
->dev
[0]);
1858 synchronize_irq(hw
->pdev
->irq
);
1860 ctl
= gma_read16(hw
, sky2
->port
, GM_GP_CTRL
);
1861 gma_write16(hw
, sky2
->port
, GM_GP_CTRL
, ctl
& ~GM_GPCR_RX_ENA
);
1863 sky2_rx_clean(sky2
);
1867 mode
= DATA_BLIND_VAL(DATA_BLIND_DEF
) |
1868 GM_SMOD_VLAN_ENA
| IPG_DATA_VAL(IPG_DATA_DEF
);
1870 if (dev
->mtu
> ETH_DATA_LEN
)
1871 mode
|= GM_SMOD_JUMBO_ENA
;
1873 gma_write16(hw
, sky2
->port
, GM_SERIAL_MODE
, mode
);
1875 sky2_write8(hw
, RB_ADDR(rxqaddr
[sky2
->port
], RB_CTRL
), RB_ENA_OP_MD
);
1877 err
= sky2_rx_start(sky2
);
1878 sky2_write32(hw
, B0_IMSK
, imask
);
1883 gma_write16(hw
, sky2
->port
, GM_GP_CTRL
, ctl
);
1885 netif_poll_enable(hw
->dev
[0]);
1886 netif_wake_queue(dev
);
1892 /* For small just reuse existing skb for next receive */
1893 static struct sk_buff
*receive_copy(struct sky2_port
*sky2
,
1894 const struct rx_ring_info
*re
,
1897 struct sk_buff
*skb
;
1899 skb
= netdev_alloc_skb(sky2
->netdev
, length
+ 2);
1901 skb_reserve(skb
, 2);
1902 pci_dma_sync_single_for_cpu(sky2
->hw
->pdev
, re
->data_addr
,
1903 length
, PCI_DMA_FROMDEVICE
);
1904 memcpy(skb
->data
, re
->skb
->data
, length
);
1905 skb
->ip_summed
= re
->skb
->ip_summed
;
1906 skb
->csum
= re
->skb
->csum
;
1907 pci_dma_sync_single_for_device(sky2
->hw
->pdev
, re
->data_addr
,
1908 length
, PCI_DMA_FROMDEVICE
);
1909 re
->skb
->ip_summed
= CHECKSUM_NONE
;
1910 skb_put(skb
, length
);
1915 /* Adjust length of skb with fragments to match received data */
1916 static void skb_put_frags(struct sk_buff
*skb
, unsigned int hdr_space
,
1917 unsigned int length
)
1922 /* put header into skb */
1923 size
= min(length
, hdr_space
);
1928 num_frags
= skb_shinfo(skb
)->nr_frags
;
1929 for (i
= 0; i
< num_frags
; i
++) {
1930 skb_frag_t
*frag
= &skb_shinfo(skb
)->frags
[i
];
1933 /* don't need this page */
1934 __free_page(frag
->page
);
1935 --skb_shinfo(skb
)->nr_frags
;
1937 size
= min(length
, (unsigned) PAGE_SIZE
);
1940 skb
->data_len
+= size
;
1941 skb
->truesize
+= size
;
1948 /* Normal packet - take skb from ring element and put in a new one */
1949 static struct sk_buff
*receive_new(struct sky2_port
*sky2
,
1950 struct rx_ring_info
*re
,
1951 unsigned int length
)
1953 struct sk_buff
*skb
, *nskb
;
1954 unsigned hdr_space
= sky2
->rx_data_size
;
1956 pr_debug(PFX
"receive new length=%d\n", length
);
1958 /* Don't be tricky about reusing pages (yet) */
1959 nskb
= sky2_rx_alloc(sky2
);
1960 if (unlikely(!nskb
))
1964 sky2_rx_unmap_skb(sky2
->hw
->pdev
, re
);
1966 prefetch(skb
->data
);
1968 sky2_rx_map_skb(sky2
->hw
->pdev
, re
, hdr_space
);
1970 if (skb_shinfo(skb
)->nr_frags
)
1971 skb_put_frags(skb
, hdr_space
, length
);
1973 skb_put(skb
, length
);
1978 * Receive one packet.
1979 * For larger packets, get new buffer.
1981 static struct sk_buff
*sky2_receive(struct net_device
*dev
,
1982 u16 length
, u32 status
)
1984 struct sky2_port
*sky2
= netdev_priv(dev
);
1985 struct rx_ring_info
*re
= sky2
->rx_ring
+ sky2
->rx_next
;
1986 struct sk_buff
*skb
= NULL
;
1988 if (unlikely(netif_msg_rx_status(sky2
)))
1989 printk(KERN_DEBUG PFX
"%s: rx slot %u status 0x%x len %d\n",
1990 dev
->name
, sky2
->rx_next
, status
, length
);
1992 sky2
->rx_next
= (sky2
->rx_next
+ 1) % sky2
->rx_pending
;
1993 prefetch(sky2
->rx_ring
+ sky2
->rx_next
);
1995 if (status
& GMR_FS_ANY_ERR
)
1998 if (!(status
& GMR_FS_RX_OK
))
2001 if (length
> dev
->mtu
+ ETH_HLEN
)
2004 if (length
< copybreak
)
2005 skb
= receive_copy(sky2
, re
, length
);
2007 skb
= receive_new(sky2
, re
, length
);
2009 sky2_rx_submit(sky2
, re
);
2014 ++sky2
->net_stats
.rx_over_errors
;
2018 ++sky2
->net_stats
.rx_errors
;
2020 if (netif_msg_rx_err(sky2
) && net_ratelimit())
2021 printk(KERN_INFO PFX
"%s: rx error, status 0x%x length %d\n",
2022 dev
->name
, status
, length
);
2024 if (status
& (GMR_FS_LONG_ERR
| GMR_FS_UN_SIZE
))
2025 sky2
->net_stats
.rx_length_errors
++;
2026 if (status
& GMR_FS_FRAGMENT
)
2027 sky2
->net_stats
.rx_frame_errors
++;
2028 if (status
& GMR_FS_CRC_ERR
)
2029 sky2
->net_stats
.rx_crc_errors
++;
2030 if (status
& GMR_FS_RX_FF_OV
)
2031 sky2
->net_stats
.rx_fifo_errors
++;
2036 /* Transmit complete */
2037 static inline void sky2_tx_done(struct net_device
*dev
, u16 last
)
2039 struct sky2_port
*sky2
= netdev_priv(dev
);
2041 if (netif_running(dev
)) {
2043 sky2_tx_complete(sky2
, last
);
2044 netif_tx_unlock(dev
);
2048 /* Process status response ring */
2049 static int sky2_status_intr(struct sky2_hw
*hw
, int to_do
)
2051 struct sky2_port
*sky2
;
2053 unsigned buf_write
[2] = { 0, 0 };
2054 u16 hwidx
= sky2_read16(hw
, STAT_PUT_IDX
);
2058 while (hw
->st_idx
!= hwidx
) {
2059 struct sky2_status_le
*le
= hw
->st_le
+ hw
->st_idx
;
2060 struct net_device
*dev
;
2061 struct sk_buff
*skb
;
2065 hw
->st_idx
= RING_NEXT(hw
->st_idx
, STATUS_RING_SIZE
);
2067 BUG_ON(le
->link
>= 2);
2068 dev
= hw
->dev
[le
->link
];
2070 sky2
= netdev_priv(dev
);
2071 length
= le16_to_cpu(le
->length
);
2072 status
= le32_to_cpu(le
->status
);
2074 switch (le
->opcode
& ~HW_OWNER
) {
2076 skb
= sky2_receive(dev
, length
, status
);
2080 skb
->protocol
= eth_type_trans(skb
, dev
);
2081 dev
->last_rx
= jiffies
;
2083 #ifdef SKY2_VLAN_TAG_USED
2084 if (sky2
->vlgrp
&& (status
& GMR_FS_VLAN
)) {
2085 vlan_hwaccel_receive_skb(skb
,
2087 be16_to_cpu(sky2
->rx_tag
));
2090 netif_receive_skb(skb
);
2092 /* Update receiver after 16 frames */
2093 if (++buf_write
[le
->link
] == RX_BUF_WRITE
) {
2094 sky2_put_idx(hw
, rxqaddr
[le
->link
],
2096 buf_write
[le
->link
] = 0;
2099 /* Stop after net poll weight */
2100 if (++work_done
>= to_do
)
2104 #ifdef SKY2_VLAN_TAG_USED
2106 sky2
->rx_tag
= length
;
2110 sky2
->rx_tag
= length
;
2114 skb
= sky2
->rx_ring
[sky2
->rx_next
].skb
;
2115 skb
->ip_summed
= CHECKSUM_COMPLETE
;
2116 skb
->csum
= status
& 0xffff;
2120 /* TX index reports status for both ports */
2121 BUILD_BUG_ON(TX_RING_SIZE
> 0x1000);
2122 sky2_tx_done(hw
->dev
[0], status
& 0xfff);
2124 sky2_tx_done(hw
->dev
[1],
2125 ((status
>> 24) & 0xff)
2126 | (u16
)(length
& 0xf) << 8);
2130 if (net_ratelimit())
2131 printk(KERN_WARNING PFX
2132 "unknown status opcode 0x%x\n", le
->opcode
);
2137 /* Fully processed status ring so clear irq */
2138 sky2_write32(hw
, STAT_CTRL
, SC_STAT_CLR_IRQ
);
2142 sky2
= netdev_priv(hw
->dev
[0]);
2143 sky2_put_idx(hw
, Q_R1
, sky2
->rx_put
);
2147 sky2
= netdev_priv(hw
->dev
[1]);
2148 sky2_put_idx(hw
, Q_R2
, sky2
->rx_put
);
2154 static void sky2_hw_error(struct sky2_hw
*hw
, unsigned port
, u32 status
)
2156 struct net_device
*dev
= hw
->dev
[port
];
2158 if (net_ratelimit())
2159 printk(KERN_INFO PFX
"%s: hw error interrupt status 0x%x\n",
2162 if (status
& Y2_IS_PAR_RD1
) {
2163 if (net_ratelimit())
2164 printk(KERN_ERR PFX
"%s: ram data read parity error\n",
2167 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_RD_PERR
);
2170 if (status
& Y2_IS_PAR_WR1
) {
2171 if (net_ratelimit())
2172 printk(KERN_ERR PFX
"%s: ram data write parity error\n",
2175 sky2_write16(hw
, RAM_BUFFER(port
, B3_RI_CTRL
), RI_CLR_WR_PERR
);
2178 if (status
& Y2_IS_PAR_MAC1
) {
2179 if (net_ratelimit())
2180 printk(KERN_ERR PFX
"%s: MAC parity error\n", dev
->name
);
2181 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_PE
);
2184 if (status
& Y2_IS_PAR_RX1
) {
2185 if (net_ratelimit())
2186 printk(KERN_ERR PFX
"%s: RX parity error\n", dev
->name
);
2187 sky2_write32(hw
, Q_ADDR(rxqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_PAR
);
2190 if (status
& Y2_IS_TCP_TXA1
) {
2191 if (net_ratelimit())
2192 printk(KERN_ERR PFX
"%s: TCP segmentation error\n",
2194 sky2_write32(hw
, Q_ADDR(txqaddr
[port
], Q_CSR
), BMU_CLR_IRQ_TCP
);
2198 static void sky2_hw_intr(struct sky2_hw
*hw
)
2200 u32 status
= sky2_read32(hw
, B0_HWE_ISRC
);
2202 if (status
& Y2_IS_TIST_OV
)
2203 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2205 if (status
& (Y2_IS_MST_ERR
| Y2_IS_IRQ_STAT
)) {
2208 pci_err
= sky2_pci_read16(hw
, PCI_STATUS
);
2209 if (net_ratelimit())
2210 printk(KERN_ERR PFX
"%s: pci hw error (0x%x)\n",
2211 pci_name(hw
->pdev
), pci_err
);
2213 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2214 sky2_pci_write16(hw
, PCI_STATUS
,
2215 pci_err
| PCI_STATUS_ERROR_BITS
);
2216 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2219 if (status
& Y2_IS_PCI_EXP
) {
2220 /* PCI-Express uncorrectable Error occurred */
2223 pex_err
= sky2_pci_read32(hw
, PEX_UNC_ERR_STAT
);
2225 if (net_ratelimit())
2226 printk(KERN_ERR PFX
"%s: pci express error (0x%x)\n",
2227 pci_name(hw
->pdev
), pex_err
);
2229 /* clear the interrupt */
2230 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2231 sky2_pci_write32(hw
, PEX_UNC_ERR_STAT
,
2233 sky2_write32(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2235 if (pex_err
& PEX_FATAL_ERRORS
) {
2236 u32 hwmsk
= sky2_read32(hw
, B0_HWE_IMSK
);
2237 hwmsk
&= ~Y2_IS_PCI_EXP
;
2238 sky2_write32(hw
, B0_HWE_IMSK
, hwmsk
);
2242 if (status
& Y2_HWE_L1_MASK
)
2243 sky2_hw_error(hw
, 0, status
);
2245 if (status
& Y2_HWE_L1_MASK
)
2246 sky2_hw_error(hw
, 1, status
);
2249 static void sky2_mac_intr(struct sky2_hw
*hw
, unsigned port
)
2251 struct net_device
*dev
= hw
->dev
[port
];
2252 struct sky2_port
*sky2
= netdev_priv(dev
);
2253 u8 status
= sky2_read8(hw
, SK_REG(port
, GMAC_IRQ_SRC
));
2255 if (netif_msg_intr(sky2
))
2256 printk(KERN_INFO PFX
"%s: mac interrupt status 0x%x\n",
2259 if (status
& GM_IS_RX_FF_OR
) {
2260 ++sky2
->net_stats
.rx_fifo_errors
;
2261 sky2_write8(hw
, SK_REG(port
, RX_GMF_CTRL_T
), GMF_CLI_RX_FO
);
2264 if (status
& GM_IS_TX_FF_UR
) {
2265 ++sky2
->net_stats
.tx_fifo_errors
;
2266 sky2_write8(hw
, SK_REG(port
, TX_GMF_CTRL_T
), GMF_CLI_TX_FU
);
2270 /* This should never happen it is a fatal situation */
2271 static void sky2_descriptor_error(struct sky2_hw
*hw
, unsigned port
,
2272 const char *rxtx
, u32 mask
)
2274 struct net_device
*dev
= hw
->dev
[port
];
2275 struct sky2_port
*sky2
= netdev_priv(dev
);
2278 printk(KERN_ERR PFX
"%s: %s descriptor error (hardware problem)\n",
2279 dev
? dev
->name
: "<not registered>", rxtx
);
2281 imask
= sky2_read32(hw
, B0_IMSK
);
2283 sky2_write32(hw
, B0_IMSK
, imask
);
2286 spin_lock(&sky2
->phy_lock
);
2287 sky2_link_down(sky2
);
2288 spin_unlock(&sky2
->phy_lock
);
2292 /* If idle then force a fake soft NAPI poll once a second
2293 * to work around cases where sharing an edge triggered interrupt.
2295 static inline void sky2_idle_start(struct sky2_hw
*hw
)
2297 if (idle_timeout
> 0)
2298 mod_timer(&hw
->idle_timer
,
2299 jiffies
+ msecs_to_jiffies(idle_timeout
));
2302 static void sky2_idle(unsigned long arg
)
2304 struct sky2_hw
*hw
= (struct sky2_hw
*) arg
;
2305 struct net_device
*dev
= hw
->dev
[0];
2307 if (__netif_rx_schedule_prep(dev
))
2308 __netif_rx_schedule(dev
);
2310 mod_timer(&hw
->idle_timer
, jiffies
+ msecs_to_jiffies(idle_timeout
));
2314 static int sky2_poll(struct net_device
*dev0
, int *budget
)
2316 struct sky2_hw
*hw
= ((struct sky2_port
*) netdev_priv(dev0
))->hw
;
2317 int work_limit
= min(dev0
->quota
, *budget
);
2319 u32 status
= sky2_read32(hw
, B0_Y2_SP_EISR
);
2321 if (status
& Y2_IS_HW_ERR
)
2324 if (status
& Y2_IS_IRQ_PHY1
)
2325 sky2_phy_intr(hw
, 0);
2327 if (status
& Y2_IS_IRQ_PHY2
)
2328 sky2_phy_intr(hw
, 1);
2330 if (status
& Y2_IS_IRQ_MAC1
)
2331 sky2_mac_intr(hw
, 0);
2333 if (status
& Y2_IS_IRQ_MAC2
)
2334 sky2_mac_intr(hw
, 1);
2336 if (status
& Y2_IS_CHK_RX1
)
2337 sky2_descriptor_error(hw
, 0, "receive", Y2_IS_CHK_RX1
);
2339 if (status
& Y2_IS_CHK_RX2
)
2340 sky2_descriptor_error(hw
, 1, "receive", Y2_IS_CHK_RX2
);
2342 if (status
& Y2_IS_CHK_TXA1
)
2343 sky2_descriptor_error(hw
, 0, "transmit", Y2_IS_CHK_TXA1
);
2345 if (status
& Y2_IS_CHK_TXA2
)
2346 sky2_descriptor_error(hw
, 1, "transmit", Y2_IS_CHK_TXA2
);
2348 work_done
= sky2_status_intr(hw
, work_limit
);
2349 if (work_done
< work_limit
) {
2350 netif_rx_complete(dev0
);
2352 sky2_read32(hw
, B0_Y2_SP_LISR
);
2355 *budget
-= work_done
;
2356 dev0
->quota
-= work_done
;
2361 static irqreturn_t
sky2_intr(int irq
, void *dev_id
)
2363 struct sky2_hw
*hw
= dev_id
;
2364 struct net_device
*dev0
= hw
->dev
[0];
2367 /* Reading this mask interrupts as side effect */
2368 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
2369 if (status
== 0 || status
== ~0)
2372 prefetch(&hw
->st_le
[hw
->st_idx
]);
2373 if (likely(__netif_rx_schedule_prep(dev0
)))
2374 __netif_rx_schedule(dev0
);
2379 #ifdef CONFIG_NET_POLL_CONTROLLER
2380 static void sky2_netpoll(struct net_device
*dev
)
2382 struct sky2_port
*sky2
= netdev_priv(dev
);
2383 struct net_device
*dev0
= sky2
->hw
->dev
[0];
2385 if (netif_running(dev
) && __netif_rx_schedule_prep(dev0
))
2386 __netif_rx_schedule(dev0
);
2390 /* Chip internal frequency for clock calculations */
2391 static inline u32
sky2_mhz(const struct sky2_hw
*hw
)
2393 switch (hw
->chip_id
) {
2394 case CHIP_ID_YUKON_EC
:
2395 case CHIP_ID_YUKON_EC_U
:
2396 return 125; /* 125 Mhz */
2397 case CHIP_ID_YUKON_FE
:
2398 return 100; /* 100 Mhz */
2399 default: /* YUKON_XL */
2400 return 156; /* 156 Mhz */
2404 static inline u32
sky2_us2clk(const struct sky2_hw
*hw
, u32 us
)
2406 return sky2_mhz(hw
) * us
;
2409 static inline u32
sky2_clk2us(const struct sky2_hw
*hw
, u32 clk
)
2411 return clk
/ sky2_mhz(hw
);
2415 static int sky2_reset(struct sky2_hw
*hw
)
2421 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2423 hw
->chip_id
= sky2_read8(hw
, B2_CHIP_ID
);
2424 if (hw
->chip_id
< CHIP_ID_YUKON_XL
|| hw
->chip_id
> CHIP_ID_YUKON_FE
) {
2425 printk(KERN_ERR PFX
"%s: unsupported chip type 0x%x\n",
2426 pci_name(hw
->pdev
), hw
->chip_id
);
2430 hw
->chip_rev
= (sky2_read8(hw
, B2_MAC_CFG
) & CFG_CHIP_R_MSK
) >> 4;
2432 /* This rev is really old, and requires untested workarounds */
2433 if (hw
->chip_id
== CHIP_ID_YUKON_EC
&& hw
->chip_rev
== CHIP_REV_YU_EC_A1
) {
2434 printk(KERN_ERR PFX
"%s: unsupported revision Yukon-%s (0x%x) rev %d\n",
2435 pci_name(hw
->pdev
), yukon2_name
[hw
->chip_id
- CHIP_ID_YUKON_XL
],
2436 hw
->chip_id
, hw
->chip_rev
);
2441 if (hw
->chip_id
<= CHIP_ID_YUKON_EC
) {
2442 sky2_write8(hw
, B28_Y2_ASF_STAT_CMD
, Y2_ASF_RESET
);
2443 sky2_write16(hw
, B0_CTST
, Y2_ASF_DISABLE
);
2447 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
2448 sky2_write8(hw
, B0_CTST
, CS_RST_CLR
);
2450 /* clear PCI errors, if any */
2451 status
= sky2_pci_read16(hw
, PCI_STATUS
);
2453 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_ON
);
2454 sky2_pci_write16(hw
, PCI_STATUS
, status
| PCI_STATUS_ERROR_BITS
);
2457 sky2_write8(hw
, B0_CTST
, CS_MRST_CLR
);
2459 /* clear any PEX errors */
2460 if (pci_find_capability(hw
->pdev
, PCI_CAP_ID_EXP
))
2461 sky2_pci_write32(hw
, PEX_UNC_ERR_STAT
, 0xffffffffUL
);
2464 hw
->pmd_type
= sky2_read8(hw
, B2_PMD_TYP
);
2466 t8
= sky2_read8(hw
, B2_Y2_HW_RES
);
2467 if ((t8
& CFG_DUAL_MAC_MSK
) == CFG_DUAL_MAC_MSK
) {
2468 if (!(sky2_read8(hw
, B2_Y2_CLK_GATE
) & Y2_STATUS_LNK2_INAC
))
2472 sky2_set_power_state(hw
, PCI_D0
);
2474 for (i
= 0; i
< hw
->ports
; i
++) {
2475 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_SET
);
2476 sky2_write8(hw
, SK_REG(i
, GMAC_LINK_CTRL
), GMLC_RST_CLR
);
2479 sky2_write8(hw
, B2_TST_CTRL1
, TST_CFG_WRITE_OFF
);
2481 /* Clear I2C IRQ noise */
2482 sky2_write32(hw
, B2_I2C_IRQ
, 1);
2484 /* turn off hardware timer (unused) */
2485 sky2_write8(hw
, B2_TI_CTRL
, TIM_STOP
);
2486 sky2_write8(hw
, B2_TI_CTRL
, TIM_CLR_IRQ
);
2488 sky2_write8(hw
, B0_Y2LED
, LED_STAT_ON
);
2490 /* Turn off descriptor polling */
2491 sky2_write32(hw
, B28_DPT_CTRL
, DPT_STOP
);
2493 /* Turn off receive timestamp */
2494 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_STOP
);
2495 sky2_write8(hw
, GMAC_TI_ST_CTRL
, GMT_ST_CLR_IRQ
);
2497 /* enable the Tx Arbiters */
2498 for (i
= 0; i
< hw
->ports
; i
++)
2499 sky2_write8(hw
, SK_REG(i
, TXA_CTRL
), TXA_ENA_ARB
);
2501 /* Initialize ram interface */
2502 for (i
= 0; i
< hw
->ports
; i
++) {
2503 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_CTRL
), RI_RST_CLR
);
2505 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R1
), SK_RI_TO_53
);
2506 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA1
), SK_RI_TO_53
);
2507 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS1
), SK_RI_TO_53
);
2508 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R1
), SK_RI_TO_53
);
2509 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA1
), SK_RI_TO_53
);
2510 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS1
), SK_RI_TO_53
);
2511 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_R2
), SK_RI_TO_53
);
2512 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XA2
), SK_RI_TO_53
);
2513 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_WTO_XS2
), SK_RI_TO_53
);
2514 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_R2
), SK_RI_TO_53
);
2515 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XA2
), SK_RI_TO_53
);
2516 sky2_write8(hw
, RAM_BUFFER(i
, B3_RI_RTO_XS2
), SK_RI_TO_53
);
2519 sky2_write32(hw
, B0_HWE_IMSK
, Y2_HWE_ALL_MASK
);
2521 for (i
= 0; i
< hw
->ports
; i
++)
2522 sky2_gmac_reset(hw
, i
);
2524 memset(hw
->st_le
, 0, STATUS_LE_BYTES
);
2527 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_SET
);
2528 sky2_write32(hw
, STAT_CTRL
, SC_STAT_RST_CLR
);
2530 sky2_write32(hw
, STAT_LIST_ADDR_LO
, hw
->st_dma
);
2531 sky2_write32(hw
, STAT_LIST_ADDR_HI
, (u64
) hw
->st_dma
>> 32);
2533 /* Set the list last index */
2534 sky2_write16(hw
, STAT_LAST_IDX
, STATUS_RING_SIZE
- 1);
2536 sky2_write16(hw
, STAT_TX_IDX_TH
, 10);
2537 sky2_write8(hw
, STAT_FIFO_WM
, 16);
2539 /* set Status-FIFO ISR watermark */
2540 if (hw
->chip_id
== CHIP_ID_YUKON_XL
&& hw
->chip_rev
== 0)
2541 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 4);
2543 sky2_write8(hw
, STAT_FIFO_ISR_WM
, 16);
2545 sky2_write32(hw
, STAT_TX_TIMER_INI
, sky2_us2clk(hw
, 1000));
2546 sky2_write32(hw
, STAT_ISR_TIMER_INI
, sky2_us2clk(hw
, 20));
2547 sky2_write32(hw
, STAT_LEV_TIMER_INI
, sky2_us2clk(hw
, 100));
2549 /* enable status unit */
2550 sky2_write32(hw
, STAT_CTRL
, SC_STAT_OP_ON
);
2552 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
2553 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
2554 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
2559 static u32
sky2_supported_modes(const struct sky2_hw
*hw
)
2561 if (sky2_is_copper(hw
)) {
2562 u32 modes
= SUPPORTED_10baseT_Half
2563 | SUPPORTED_10baseT_Full
2564 | SUPPORTED_100baseT_Half
2565 | SUPPORTED_100baseT_Full
2566 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2568 if (hw
->chip_id
!= CHIP_ID_YUKON_FE
)
2569 modes
|= SUPPORTED_1000baseT_Half
2570 | SUPPORTED_1000baseT_Full
;
2573 return SUPPORTED_1000baseT_Half
2574 | SUPPORTED_1000baseT_Full
2579 static int sky2_get_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2581 struct sky2_port
*sky2
= netdev_priv(dev
);
2582 struct sky2_hw
*hw
= sky2
->hw
;
2584 ecmd
->transceiver
= XCVR_INTERNAL
;
2585 ecmd
->supported
= sky2_supported_modes(hw
);
2586 ecmd
->phy_address
= PHY_ADDR_MARV
;
2587 if (sky2_is_copper(hw
)) {
2588 ecmd
->supported
= SUPPORTED_10baseT_Half
2589 | SUPPORTED_10baseT_Full
2590 | SUPPORTED_100baseT_Half
2591 | SUPPORTED_100baseT_Full
2592 | SUPPORTED_1000baseT_Half
2593 | SUPPORTED_1000baseT_Full
2594 | SUPPORTED_Autoneg
| SUPPORTED_TP
;
2595 ecmd
->port
= PORT_TP
;
2596 ecmd
->speed
= sky2
->speed
;
2598 ecmd
->speed
= SPEED_1000
;
2599 ecmd
->port
= PORT_FIBRE
;
2602 ecmd
->advertising
= sky2
->advertising
;
2603 ecmd
->autoneg
= sky2
->autoneg
;
2604 ecmd
->duplex
= sky2
->duplex
;
2608 static int sky2_set_settings(struct net_device
*dev
, struct ethtool_cmd
*ecmd
)
2610 struct sky2_port
*sky2
= netdev_priv(dev
);
2611 const struct sky2_hw
*hw
= sky2
->hw
;
2612 u32 supported
= sky2_supported_modes(hw
);
2614 if (ecmd
->autoneg
== AUTONEG_ENABLE
) {
2615 ecmd
->advertising
= supported
;
2621 switch (ecmd
->speed
) {
2623 if (ecmd
->duplex
== DUPLEX_FULL
)
2624 setting
= SUPPORTED_1000baseT_Full
;
2625 else if (ecmd
->duplex
== DUPLEX_HALF
)
2626 setting
= SUPPORTED_1000baseT_Half
;
2631 if (ecmd
->duplex
== DUPLEX_FULL
)
2632 setting
= SUPPORTED_100baseT_Full
;
2633 else if (ecmd
->duplex
== DUPLEX_HALF
)
2634 setting
= SUPPORTED_100baseT_Half
;
2640 if (ecmd
->duplex
== DUPLEX_FULL
)
2641 setting
= SUPPORTED_10baseT_Full
;
2642 else if (ecmd
->duplex
== DUPLEX_HALF
)
2643 setting
= SUPPORTED_10baseT_Half
;
2651 if ((setting
& supported
) == 0)
2654 sky2
->speed
= ecmd
->speed
;
2655 sky2
->duplex
= ecmd
->duplex
;
2658 sky2
->autoneg
= ecmd
->autoneg
;
2659 sky2
->advertising
= ecmd
->advertising
;
2661 if (netif_running(dev
))
2662 sky2_phy_reinit(sky2
);
2667 static void sky2_get_drvinfo(struct net_device
*dev
,
2668 struct ethtool_drvinfo
*info
)
2670 struct sky2_port
*sky2
= netdev_priv(dev
);
2672 strcpy(info
->driver
, DRV_NAME
);
2673 strcpy(info
->version
, DRV_VERSION
);
2674 strcpy(info
->fw_version
, "N/A");
2675 strcpy(info
->bus_info
, pci_name(sky2
->hw
->pdev
));
2678 static const struct sky2_stat
{
2679 char name
[ETH_GSTRING_LEN
];
2682 { "tx_bytes", GM_TXO_OK_HI
},
2683 { "rx_bytes", GM_RXO_OK_HI
},
2684 { "tx_broadcast", GM_TXF_BC_OK
},
2685 { "rx_broadcast", GM_RXF_BC_OK
},
2686 { "tx_multicast", GM_TXF_MC_OK
},
2687 { "rx_multicast", GM_RXF_MC_OK
},
2688 { "tx_unicast", GM_TXF_UC_OK
},
2689 { "rx_unicast", GM_RXF_UC_OK
},
2690 { "tx_mac_pause", GM_TXF_MPAUSE
},
2691 { "rx_mac_pause", GM_RXF_MPAUSE
},
2692 { "collisions", GM_TXF_COL
},
2693 { "late_collision",GM_TXF_LAT_COL
},
2694 { "aborted", GM_TXF_ABO_COL
},
2695 { "single_collisions", GM_TXF_SNG_COL
},
2696 { "multi_collisions", GM_TXF_MUL_COL
},
2698 { "rx_short", GM_RXF_SHT
},
2699 { "rx_runt", GM_RXE_FRAG
},
2700 { "rx_64_byte_packets", GM_RXF_64B
},
2701 { "rx_65_to_127_byte_packets", GM_RXF_127B
},
2702 { "rx_128_to_255_byte_packets", GM_RXF_255B
},
2703 { "rx_256_to_511_byte_packets", GM_RXF_511B
},
2704 { "rx_512_to_1023_byte_packets", GM_RXF_1023B
},
2705 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B
},
2706 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ
},
2707 { "rx_too_long", GM_RXF_LNG_ERR
},
2708 { "rx_fifo_overflow", GM_RXE_FIFO_OV
},
2709 { "rx_jabber", GM_RXF_JAB_PKT
},
2710 { "rx_fcs_error", GM_RXF_FCS_ERR
},
2712 { "tx_64_byte_packets", GM_TXF_64B
},
2713 { "tx_65_to_127_byte_packets", GM_TXF_127B
},
2714 { "tx_128_to_255_byte_packets", GM_TXF_255B
},
2715 { "tx_256_to_511_byte_packets", GM_TXF_511B
},
2716 { "tx_512_to_1023_byte_packets", GM_TXF_1023B
},
2717 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B
},
2718 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ
},
2719 { "tx_fifo_underrun", GM_TXE_FIFO_UR
},
2722 static u32
sky2_get_rx_csum(struct net_device
*dev
)
2724 struct sky2_port
*sky2
= netdev_priv(dev
);
2726 return sky2
->rx_csum
;
2729 static int sky2_set_rx_csum(struct net_device
*dev
, u32 data
)
2731 struct sky2_port
*sky2
= netdev_priv(dev
);
2733 sky2
->rx_csum
= data
;
2735 sky2_write32(sky2
->hw
, Q_ADDR(rxqaddr
[sky2
->port
], Q_CSR
),
2736 data
? BMU_ENA_RX_CHKSUM
: BMU_DIS_RX_CHKSUM
);
2741 static u32
sky2_get_msglevel(struct net_device
*netdev
)
2743 struct sky2_port
*sky2
= netdev_priv(netdev
);
2744 return sky2
->msg_enable
;
2747 static int sky2_nway_reset(struct net_device
*dev
)
2749 struct sky2_port
*sky2
= netdev_priv(dev
);
2751 if (sky2
->autoneg
!= AUTONEG_ENABLE
)
2754 sky2_phy_reinit(sky2
);
2759 static void sky2_phy_stats(struct sky2_port
*sky2
, u64
* data
, unsigned count
)
2761 struct sky2_hw
*hw
= sky2
->hw
;
2762 unsigned port
= sky2
->port
;
2765 data
[0] = (u64
) gma_read32(hw
, port
, GM_TXO_OK_HI
) << 32
2766 | (u64
) gma_read32(hw
, port
, GM_TXO_OK_LO
);
2767 data
[1] = (u64
) gma_read32(hw
, port
, GM_RXO_OK_HI
) << 32
2768 | (u64
) gma_read32(hw
, port
, GM_RXO_OK_LO
);
2770 for (i
= 2; i
< count
; i
++)
2771 data
[i
] = (u64
) gma_read32(hw
, port
, sky2_stats
[i
].offset
);
2774 static void sky2_set_msglevel(struct net_device
*netdev
, u32 value
)
2776 struct sky2_port
*sky2
= netdev_priv(netdev
);
2777 sky2
->msg_enable
= value
;
2780 static int sky2_get_stats_count(struct net_device
*dev
)
2782 return ARRAY_SIZE(sky2_stats
);
2785 static void sky2_get_ethtool_stats(struct net_device
*dev
,
2786 struct ethtool_stats
*stats
, u64
* data
)
2788 struct sky2_port
*sky2
= netdev_priv(dev
);
2790 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(sky2_stats
));
2793 static void sky2_get_strings(struct net_device
*dev
, u32 stringset
, u8
* data
)
2797 switch (stringset
) {
2799 for (i
= 0; i
< ARRAY_SIZE(sky2_stats
); i
++)
2800 memcpy(data
+ i
* ETH_GSTRING_LEN
,
2801 sky2_stats
[i
].name
, ETH_GSTRING_LEN
);
2806 /* Use hardware MIB variables for critical path statistics and
2807 * transmit feedback not reported at interrupt.
2808 * Other errors are accounted for in interrupt handler.
2810 static struct net_device_stats
*sky2_get_stats(struct net_device
*dev
)
2812 struct sky2_port
*sky2
= netdev_priv(dev
);
2815 sky2_phy_stats(sky2
, data
, ARRAY_SIZE(data
));
2817 sky2
->net_stats
.tx_bytes
= data
[0];
2818 sky2
->net_stats
.rx_bytes
= data
[1];
2819 sky2
->net_stats
.tx_packets
= data
[2] + data
[4] + data
[6];
2820 sky2
->net_stats
.rx_packets
= data
[3] + data
[5] + data
[7];
2821 sky2
->net_stats
.multicast
= data
[3] + data
[5];
2822 sky2
->net_stats
.collisions
= data
[10];
2823 sky2
->net_stats
.tx_aborted_errors
= data
[12];
2825 return &sky2
->net_stats
;
2828 static int sky2_set_mac_address(struct net_device
*dev
, void *p
)
2830 struct sky2_port
*sky2
= netdev_priv(dev
);
2831 struct sky2_hw
*hw
= sky2
->hw
;
2832 unsigned port
= sky2
->port
;
2833 const struct sockaddr
*addr
= p
;
2835 if (!is_valid_ether_addr(addr
->sa_data
))
2836 return -EADDRNOTAVAIL
;
2838 memcpy(dev
->dev_addr
, addr
->sa_data
, ETH_ALEN
);
2839 memcpy_toio(hw
->regs
+ B2_MAC_1
+ port
* 8,
2840 dev
->dev_addr
, ETH_ALEN
);
2841 memcpy_toio(hw
->regs
+ B2_MAC_2
+ port
* 8,
2842 dev
->dev_addr
, ETH_ALEN
);
2844 /* virtual address for data */
2845 gma_set_addr(hw
, port
, GM_SRC_ADDR_2L
, dev
->dev_addr
);
2847 /* physical address: used for pause frames */
2848 gma_set_addr(hw
, port
, GM_SRC_ADDR_1L
, dev
->dev_addr
);
2853 static void sky2_set_multicast(struct net_device
*dev
)
2855 struct sky2_port
*sky2
= netdev_priv(dev
);
2856 struct sky2_hw
*hw
= sky2
->hw
;
2857 unsigned port
= sky2
->port
;
2858 struct dev_mc_list
*list
= dev
->mc_list
;
2862 memset(filter
, 0, sizeof(filter
));
2864 reg
= gma_read16(hw
, port
, GM_RX_CTRL
);
2865 reg
|= GM_RXCR_UCF_ENA
;
2867 if (dev
->flags
& IFF_PROMISC
) /* promiscuous */
2868 reg
&= ~(GM_RXCR_UCF_ENA
| GM_RXCR_MCF_ENA
);
2869 else if ((dev
->flags
& IFF_ALLMULTI
) || dev
->mc_count
> 16) /* all multicast */
2870 memset(filter
, 0xff, sizeof(filter
));
2871 else if (dev
->mc_count
== 0) /* no multicast */
2872 reg
&= ~GM_RXCR_MCF_ENA
;
2875 reg
|= GM_RXCR_MCF_ENA
;
2877 for (i
= 0; list
&& i
< dev
->mc_count
; i
++, list
= list
->next
) {
2878 u32 bit
= ether_crc(ETH_ALEN
, list
->dmi_addr
) & 0x3f;
2879 filter
[bit
/ 8] |= 1 << (bit
% 8);
2883 gma_write16(hw
, port
, GM_MC_ADDR_H1
,
2884 (u16
) filter
[0] | ((u16
) filter
[1] << 8));
2885 gma_write16(hw
, port
, GM_MC_ADDR_H2
,
2886 (u16
) filter
[2] | ((u16
) filter
[3] << 8));
2887 gma_write16(hw
, port
, GM_MC_ADDR_H3
,
2888 (u16
) filter
[4] | ((u16
) filter
[5] << 8));
2889 gma_write16(hw
, port
, GM_MC_ADDR_H4
,
2890 (u16
) filter
[6] | ((u16
) filter
[7] << 8));
2892 gma_write16(hw
, port
, GM_RX_CTRL
, reg
);
2895 /* Can have one global because blinking is controlled by
2896 * ethtool and that is always under RTNL mutex
2898 static void sky2_led(struct sky2_hw
*hw
, unsigned port
, int on
)
2902 switch (hw
->chip_id
) {
2903 case CHIP_ID_YUKON_XL
:
2904 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
2905 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
2906 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
,
2907 on
? (PHY_M_LEDC_LOS_CTRL(1) |
2908 PHY_M_LEDC_INIT_CTRL(7) |
2909 PHY_M_LEDC_STA1_CTRL(7) |
2910 PHY_M_LEDC_STA0_CTRL(7))
2913 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
2917 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, 0);
2918 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
,
2919 on
? PHY_M_LED_MO_DUP(MO_LED_ON
) |
2920 PHY_M_LED_MO_10(MO_LED_ON
) |
2921 PHY_M_LED_MO_100(MO_LED_ON
) |
2922 PHY_M_LED_MO_1000(MO_LED_ON
) |
2923 PHY_M_LED_MO_RX(MO_LED_ON
)
2924 : PHY_M_LED_MO_DUP(MO_LED_OFF
) |
2925 PHY_M_LED_MO_10(MO_LED_OFF
) |
2926 PHY_M_LED_MO_100(MO_LED_OFF
) |
2927 PHY_M_LED_MO_1000(MO_LED_OFF
) |
2928 PHY_M_LED_MO_RX(MO_LED_OFF
));
2933 /* blink LED's for finding board */
2934 static int sky2_phys_id(struct net_device
*dev
, u32 data
)
2936 struct sky2_port
*sky2
= netdev_priv(dev
);
2937 struct sky2_hw
*hw
= sky2
->hw
;
2938 unsigned port
= sky2
->port
;
2939 u16 ledctrl
, ledover
= 0;
2944 if (!data
|| data
> (u32
) (MAX_SCHEDULE_TIMEOUT
/ HZ
))
2945 ms
= jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT
);
2949 /* save initial values */
2950 spin_lock_bh(&sky2
->phy_lock
);
2951 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
2952 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
2953 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
2954 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_PHY_CTRL
);
2955 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
2957 ledctrl
= gm_phy_read(hw
, port
, PHY_MARV_LED_CTRL
);
2958 ledover
= gm_phy_read(hw
, port
, PHY_MARV_LED_OVER
);
2962 while (!interrupted
&& ms
> 0) {
2963 sky2_led(hw
, port
, onoff
);
2966 spin_unlock_bh(&sky2
->phy_lock
);
2967 interrupted
= msleep_interruptible(250);
2968 spin_lock_bh(&sky2
->phy_lock
);
2973 /* resume regularly scheduled programming */
2974 if (hw
->chip_id
== CHIP_ID_YUKON_XL
) {
2975 u16 pg
= gm_phy_read(hw
, port
, PHY_MARV_EXT_ADR
);
2976 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, 3);
2977 gm_phy_write(hw
, port
, PHY_MARV_PHY_CTRL
, ledctrl
);
2978 gm_phy_write(hw
, port
, PHY_MARV_EXT_ADR
, pg
);
2980 gm_phy_write(hw
, port
, PHY_MARV_LED_CTRL
, ledctrl
);
2981 gm_phy_write(hw
, port
, PHY_MARV_LED_OVER
, ledover
);
2983 spin_unlock_bh(&sky2
->phy_lock
);
2988 static void sky2_get_pauseparam(struct net_device
*dev
,
2989 struct ethtool_pauseparam
*ecmd
)
2991 struct sky2_port
*sky2
= netdev_priv(dev
);
2993 ecmd
->tx_pause
= sky2
->tx_pause
;
2994 ecmd
->rx_pause
= sky2
->rx_pause
;
2995 ecmd
->autoneg
= sky2
->autoneg
;
2998 static int sky2_set_pauseparam(struct net_device
*dev
,
2999 struct ethtool_pauseparam
*ecmd
)
3001 struct sky2_port
*sky2
= netdev_priv(dev
);
3003 sky2
->autoneg
= ecmd
->autoneg
;
3004 sky2
->tx_pause
= ecmd
->tx_pause
!= 0;
3005 sky2
->rx_pause
= ecmd
->rx_pause
!= 0;
3007 sky2_phy_reinit(sky2
);
3012 static int sky2_get_coalesce(struct net_device
*dev
,
3013 struct ethtool_coalesce
*ecmd
)
3015 struct sky2_port
*sky2
= netdev_priv(dev
);
3016 struct sky2_hw
*hw
= sky2
->hw
;
3018 if (sky2_read8(hw
, STAT_TX_TIMER_CTRL
) == TIM_STOP
)
3019 ecmd
->tx_coalesce_usecs
= 0;
3021 u32 clks
= sky2_read32(hw
, STAT_TX_TIMER_INI
);
3022 ecmd
->tx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
3024 ecmd
->tx_max_coalesced_frames
= sky2_read16(hw
, STAT_TX_IDX_TH
);
3026 if (sky2_read8(hw
, STAT_LEV_TIMER_CTRL
) == TIM_STOP
)
3027 ecmd
->rx_coalesce_usecs
= 0;
3029 u32 clks
= sky2_read32(hw
, STAT_LEV_TIMER_INI
);
3030 ecmd
->rx_coalesce_usecs
= sky2_clk2us(hw
, clks
);
3032 ecmd
->rx_max_coalesced_frames
= sky2_read8(hw
, STAT_FIFO_WM
);
3034 if (sky2_read8(hw
, STAT_ISR_TIMER_CTRL
) == TIM_STOP
)
3035 ecmd
->rx_coalesce_usecs_irq
= 0;
3037 u32 clks
= sky2_read32(hw
, STAT_ISR_TIMER_INI
);
3038 ecmd
->rx_coalesce_usecs_irq
= sky2_clk2us(hw
, clks
);
3041 ecmd
->rx_max_coalesced_frames_irq
= sky2_read8(hw
, STAT_FIFO_ISR_WM
);
3046 /* Note: this affect both ports */
3047 static int sky2_set_coalesce(struct net_device
*dev
,
3048 struct ethtool_coalesce
*ecmd
)
3050 struct sky2_port
*sky2
= netdev_priv(dev
);
3051 struct sky2_hw
*hw
= sky2
->hw
;
3052 const u32 tmax
= sky2_clk2us(hw
, 0x0ffffff);
3054 if (ecmd
->tx_coalesce_usecs
> tmax
||
3055 ecmd
->rx_coalesce_usecs
> tmax
||
3056 ecmd
->rx_coalesce_usecs_irq
> tmax
)
3059 if (ecmd
->tx_max_coalesced_frames
>= TX_RING_SIZE
-1)
3061 if (ecmd
->rx_max_coalesced_frames
> RX_MAX_PENDING
)
3063 if (ecmd
->rx_max_coalesced_frames_irq
>RX_MAX_PENDING
)
3066 if (ecmd
->tx_coalesce_usecs
== 0)
3067 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_STOP
);
3069 sky2_write32(hw
, STAT_TX_TIMER_INI
,
3070 sky2_us2clk(hw
, ecmd
->tx_coalesce_usecs
));
3071 sky2_write8(hw
, STAT_TX_TIMER_CTRL
, TIM_START
);
3073 sky2_write16(hw
, STAT_TX_IDX_TH
, ecmd
->tx_max_coalesced_frames
);
3075 if (ecmd
->rx_coalesce_usecs
== 0)
3076 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_STOP
);
3078 sky2_write32(hw
, STAT_LEV_TIMER_INI
,
3079 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs
));
3080 sky2_write8(hw
, STAT_LEV_TIMER_CTRL
, TIM_START
);
3082 sky2_write8(hw
, STAT_FIFO_WM
, ecmd
->rx_max_coalesced_frames
);
3084 if (ecmd
->rx_coalesce_usecs_irq
== 0)
3085 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_STOP
);
3087 sky2_write32(hw
, STAT_ISR_TIMER_INI
,
3088 sky2_us2clk(hw
, ecmd
->rx_coalesce_usecs_irq
));
3089 sky2_write8(hw
, STAT_ISR_TIMER_CTRL
, TIM_START
);
3091 sky2_write8(hw
, STAT_FIFO_ISR_WM
, ecmd
->rx_max_coalesced_frames_irq
);
3095 static void sky2_get_ringparam(struct net_device
*dev
,
3096 struct ethtool_ringparam
*ering
)
3098 struct sky2_port
*sky2
= netdev_priv(dev
);
3100 ering
->rx_max_pending
= RX_MAX_PENDING
;
3101 ering
->rx_mini_max_pending
= 0;
3102 ering
->rx_jumbo_max_pending
= 0;
3103 ering
->tx_max_pending
= TX_RING_SIZE
- 1;
3105 ering
->rx_pending
= sky2
->rx_pending
;
3106 ering
->rx_mini_pending
= 0;
3107 ering
->rx_jumbo_pending
= 0;
3108 ering
->tx_pending
= sky2
->tx_pending
;
3111 static int sky2_set_ringparam(struct net_device
*dev
,
3112 struct ethtool_ringparam
*ering
)
3114 struct sky2_port
*sky2
= netdev_priv(dev
);
3117 if (ering
->rx_pending
> RX_MAX_PENDING
||
3118 ering
->rx_pending
< 8 ||
3119 ering
->tx_pending
< MAX_SKB_TX_LE
||
3120 ering
->tx_pending
> TX_RING_SIZE
- 1)
3123 if (netif_running(dev
))
3126 sky2
->rx_pending
= ering
->rx_pending
;
3127 sky2
->tx_pending
= ering
->tx_pending
;
3129 if (netif_running(dev
)) {
3134 sky2_set_multicast(dev
);
3140 static int sky2_get_regs_len(struct net_device
*dev
)
3146 * Returns copy of control register region
3147 * Note: access to the RAM address register set will cause timeouts.
3149 static void sky2_get_regs(struct net_device
*dev
, struct ethtool_regs
*regs
,
3152 const struct sky2_port
*sky2
= netdev_priv(dev
);
3153 const void __iomem
*io
= sky2
->hw
->regs
;
3155 BUG_ON(regs
->len
< B3_RI_WTO_R1
);
3157 memset(p
, 0, regs
->len
);
3159 memcpy_fromio(p
, io
, B3_RAM_ADDR
);
3161 memcpy_fromio(p
+ B3_RI_WTO_R1
,
3163 regs
->len
- B3_RI_WTO_R1
);
3166 static const struct ethtool_ops sky2_ethtool_ops
= {
3167 .get_settings
= sky2_get_settings
,
3168 .set_settings
= sky2_set_settings
,
3169 .get_drvinfo
= sky2_get_drvinfo
,
3170 .get_msglevel
= sky2_get_msglevel
,
3171 .set_msglevel
= sky2_set_msglevel
,
3172 .nway_reset
= sky2_nway_reset
,
3173 .get_regs_len
= sky2_get_regs_len
,
3174 .get_regs
= sky2_get_regs
,
3175 .get_link
= ethtool_op_get_link
,
3176 .get_sg
= ethtool_op_get_sg
,
3177 .set_sg
= ethtool_op_set_sg
,
3178 .get_tx_csum
= ethtool_op_get_tx_csum
,
3179 .set_tx_csum
= ethtool_op_set_tx_csum
,
3180 .get_tso
= ethtool_op_get_tso
,
3181 .set_tso
= ethtool_op_set_tso
,
3182 .get_rx_csum
= sky2_get_rx_csum
,
3183 .set_rx_csum
= sky2_set_rx_csum
,
3184 .get_strings
= sky2_get_strings
,
3185 .get_coalesce
= sky2_get_coalesce
,
3186 .set_coalesce
= sky2_set_coalesce
,
3187 .get_ringparam
= sky2_get_ringparam
,
3188 .set_ringparam
= sky2_set_ringparam
,
3189 .get_pauseparam
= sky2_get_pauseparam
,
3190 .set_pauseparam
= sky2_set_pauseparam
,
3191 .phys_id
= sky2_phys_id
,
3192 .get_stats_count
= sky2_get_stats_count
,
3193 .get_ethtool_stats
= sky2_get_ethtool_stats
,
3194 .get_perm_addr
= ethtool_op_get_perm_addr
,
3197 /* Initialize network device */
3198 static __devinit
struct net_device
*sky2_init_netdev(struct sky2_hw
*hw
,
3199 unsigned port
, int highmem
)
3201 struct sky2_port
*sky2
;
3202 struct net_device
*dev
= alloc_etherdev(sizeof(*sky2
));
3205 printk(KERN_ERR
"sky2 etherdev alloc failed");
3209 SET_MODULE_OWNER(dev
);
3210 SET_NETDEV_DEV(dev
, &hw
->pdev
->dev
);
3211 dev
->irq
= hw
->pdev
->irq
;
3212 dev
->open
= sky2_up
;
3213 dev
->stop
= sky2_down
;
3214 dev
->do_ioctl
= sky2_ioctl
;
3215 dev
->hard_start_xmit
= sky2_xmit_frame
;
3216 dev
->get_stats
= sky2_get_stats
;
3217 dev
->set_multicast_list
= sky2_set_multicast
;
3218 dev
->set_mac_address
= sky2_set_mac_address
;
3219 dev
->change_mtu
= sky2_change_mtu
;
3220 SET_ETHTOOL_OPS(dev
, &sky2_ethtool_ops
);
3221 dev
->tx_timeout
= sky2_tx_timeout
;
3222 dev
->watchdog_timeo
= TX_WATCHDOG
;
3224 dev
->poll
= sky2_poll
;
3225 dev
->weight
= NAPI_WEIGHT
;
3226 #ifdef CONFIG_NET_POLL_CONTROLLER
3227 dev
->poll_controller
= sky2_netpoll
;
3230 sky2
= netdev_priv(dev
);
3233 sky2
->msg_enable
= netif_msg_init(debug
, default_msg
);
3235 /* Auto speed and flow control */
3236 sky2
->autoneg
= AUTONEG_ENABLE
;
3241 sky2
->advertising
= sky2_supported_modes(hw
);
3244 spin_lock_init(&sky2
->phy_lock
);
3245 sky2
->tx_pending
= TX_DEF_PENDING
;
3246 sky2
->rx_pending
= RX_DEF_PENDING
;
3248 hw
->dev
[port
] = dev
;
3252 if (hw
->chip_id
!= CHIP_ID_YUKON_EC_U
)
3253 dev
->features
|= NETIF_F_TSO
;
3255 dev
->features
|= NETIF_F_HIGHDMA
;
3256 dev
->features
|= NETIF_F_IP_CSUM
| NETIF_F_SG
;
3258 #ifdef SKY2_VLAN_TAG_USED
3259 dev
->features
|= NETIF_F_HW_VLAN_TX
| NETIF_F_HW_VLAN_RX
;
3260 dev
->vlan_rx_register
= sky2_vlan_rx_register
;
3261 dev
->vlan_rx_kill_vid
= sky2_vlan_rx_kill_vid
;
3264 /* read the mac address */
3265 memcpy_fromio(dev
->dev_addr
, hw
->regs
+ B2_MAC_1
+ port
* 8, ETH_ALEN
);
3266 memcpy(dev
->perm_addr
, dev
->dev_addr
, dev
->addr_len
);
3268 /* device is off until link detection */
3269 netif_carrier_off(dev
);
3270 netif_stop_queue(dev
);
3275 static void __devinit
sky2_show_addr(struct net_device
*dev
)
3277 const struct sky2_port
*sky2
= netdev_priv(dev
);
3279 if (netif_msg_probe(sky2
))
3280 printk(KERN_INFO PFX
"%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3282 dev
->dev_addr
[0], dev
->dev_addr
[1], dev
->dev_addr
[2],
3283 dev
->dev_addr
[3], dev
->dev_addr
[4], dev
->dev_addr
[5]);
3286 /* Handle software interrupt used during MSI test */
3287 static irqreturn_t __devinit
sky2_test_intr(int irq
, void *dev_id
)
3289 struct sky2_hw
*hw
= dev_id
;
3290 u32 status
= sky2_read32(hw
, B0_Y2_SP_ISRC2
);
3295 if (status
& Y2_IS_IRQ_SW
) {
3296 hw
->msi_detected
= 1;
3297 wake_up(&hw
->msi_wait
);
3298 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
3300 sky2_write32(hw
, B0_Y2_SP_ICR
, 2);
3305 /* Test interrupt path by forcing a a software IRQ */
3306 static int __devinit
sky2_test_msi(struct sky2_hw
*hw
)
3308 struct pci_dev
*pdev
= hw
->pdev
;
3311 init_waitqueue_head (&hw
->msi_wait
);
3313 sky2_write32(hw
, B0_IMSK
, Y2_IS_IRQ_SW
);
3315 err
= request_irq(pdev
->irq
, sky2_test_intr
, IRQF_SHARED
, DRV_NAME
, hw
);
3317 printk(KERN_ERR PFX
"%s: cannot assign irq %d\n",
3318 pci_name(pdev
), pdev
->irq
);
3322 sky2_write8(hw
, B0_CTST
, CS_ST_SW_IRQ
);
3323 sky2_read8(hw
, B0_CTST
);
3325 wait_event_timeout(hw
->msi_wait
, hw
->msi_detected
, HZ
/10);
3327 if (!hw
->msi_detected
) {
3328 /* MSI test failed, go back to INTx mode */
3329 printk(KERN_WARNING PFX
"%s: No interrupt was generated using MSI, "
3330 "switching to INTx mode. Please report this failure to "
3331 "the PCI maintainer and include system chipset information.\n",
3335 sky2_write8(hw
, B0_CTST
, CS_CL_SW_IRQ
);
3338 sky2_write32(hw
, B0_IMSK
, 0);
3340 free_irq(pdev
->irq
, hw
);
3345 static int __devinit
sky2_probe(struct pci_dev
*pdev
,
3346 const struct pci_device_id
*ent
)
3348 struct net_device
*dev
, *dev1
= NULL
;
3350 int err
, pm_cap
, using_dac
= 0;
3352 err
= pci_enable_device(pdev
);
3354 printk(KERN_ERR PFX
"%s cannot enable PCI device\n",
3359 err
= pci_request_regions(pdev
, DRV_NAME
);
3361 printk(KERN_ERR PFX
"%s cannot obtain PCI resources\n",
3366 pci_set_master(pdev
);
3368 /* Find power-management capability. */
3369 pm_cap
= pci_find_capability(pdev
, PCI_CAP_ID_PM
);
3371 printk(KERN_ERR PFX
"Cannot find PowerManagement capability, "
3374 goto err_out_free_regions
;
3377 if (sizeof(dma_addr_t
) > sizeof(u32
) &&
3378 !(err
= pci_set_dma_mask(pdev
, DMA_64BIT_MASK
))) {
3380 err
= pci_set_consistent_dma_mask(pdev
, DMA_64BIT_MASK
);
3382 printk(KERN_ERR PFX
"%s unable to obtain 64 bit DMA "
3383 "for consistent allocations\n", pci_name(pdev
));
3384 goto err_out_free_regions
;
3388 err
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
3390 printk(KERN_ERR PFX
"%s no usable DMA configuration\n",
3392 goto err_out_free_regions
;
3397 hw
= kzalloc(sizeof(*hw
), GFP_KERNEL
);
3399 printk(KERN_ERR PFX
"%s: cannot allocate hardware struct\n",
3401 goto err_out_free_regions
;
3406 hw
->regs
= ioremap_nocache(pci_resource_start(pdev
, 0), 0x4000);
3408 printk(KERN_ERR PFX
"%s: cannot map device registers\n",
3410 goto err_out_free_hw
;
3412 hw
->pm_cap
= pm_cap
;
3415 /* The sk98lin vendor driver uses hardware byte swapping but
3416 * this driver uses software swapping.
3420 reg
= sky2_pci_read32(hw
, PCI_DEV_REG2
);
3421 reg
&= ~PCI_REV_DESC
;
3422 sky2_pci_write32(hw
, PCI_DEV_REG2
, reg
);
3426 /* ring for status responses */
3427 hw
->st_le
= pci_alloc_consistent(hw
->pdev
, STATUS_LE_BYTES
,
3430 goto err_out_iounmap
;
3432 err
= sky2_reset(hw
);
3434 goto err_out_iounmap
;
3436 printk(KERN_INFO PFX
"v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3437 DRV_VERSION
, (unsigned long long)pci_resource_start(pdev
, 0),
3438 pdev
->irq
, yukon2_name
[hw
->chip_id
- CHIP_ID_YUKON_XL
],
3439 hw
->chip_id
, hw
->chip_rev
);
3441 dev
= sky2_init_netdev(hw
, 0, using_dac
);
3443 goto err_out_free_pci
;
3445 if (!disable_msi
&& pci_enable_msi(pdev
) == 0) {
3446 err
= sky2_test_msi(hw
);
3447 if (err
== -EOPNOTSUPP
)
3448 pci_disable_msi(pdev
);
3450 goto err_out_free_netdev
;
3453 err
= register_netdev(dev
);
3455 printk(KERN_ERR PFX
"%s: cannot register net device\n",
3457 goto err_out_free_netdev
;
3460 err
= request_irq(pdev
->irq
, sky2_intr
, IRQF_SHARED
, dev
->name
, hw
);
3462 printk(KERN_ERR PFX
"%s: cannot assign irq %d\n",
3463 pci_name(pdev
), pdev
->irq
);
3464 goto err_out_unregister
;
3466 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
3468 sky2_show_addr(dev
);
3470 if (hw
->ports
> 1 && (dev1
= sky2_init_netdev(hw
, 1, using_dac
))) {
3471 if (register_netdev(dev1
) == 0)
3472 sky2_show_addr(dev1
);
3474 /* Failure to register second port need not be fatal */
3475 printk(KERN_WARNING PFX
3476 "register of second port failed\n");
3482 setup_timer(&hw
->idle_timer
, sky2_idle
, (unsigned long) hw
);
3483 sky2_idle_start(hw
);
3485 pci_set_drvdata(pdev
, hw
);
3490 pci_disable_msi(pdev
);
3491 unregister_netdev(dev
);
3492 err_out_free_netdev
:
3495 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
3496 pci_free_consistent(hw
->pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
3501 err_out_free_regions
:
3502 pci_release_regions(pdev
);
3503 pci_disable_device(pdev
);
3508 static void __devexit
sky2_remove(struct pci_dev
*pdev
)
3510 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3511 struct net_device
*dev0
, *dev1
;
3516 del_timer_sync(&hw
->idle_timer
);
3518 sky2_write32(hw
, B0_IMSK
, 0);
3519 synchronize_irq(hw
->pdev
->irq
);
3524 unregister_netdev(dev1
);
3525 unregister_netdev(dev0
);
3527 sky2_set_power_state(hw
, PCI_D3hot
);
3528 sky2_write16(hw
, B0_Y2LED
, LED_STAT_OFF
);
3529 sky2_write8(hw
, B0_CTST
, CS_RST_SET
);
3530 sky2_read8(hw
, B0_CTST
);
3532 free_irq(pdev
->irq
, hw
);
3533 pci_disable_msi(pdev
);
3534 pci_free_consistent(pdev
, STATUS_LE_BYTES
, hw
->st_le
, hw
->st_dma
);
3535 pci_release_regions(pdev
);
3536 pci_disable_device(pdev
);
3544 pci_set_drvdata(pdev
, NULL
);
3548 static int sky2_suspend(struct pci_dev
*pdev
, pm_message_t state
)
3550 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3552 pci_power_t pstate
= pci_choose_state(pdev
, state
);
3554 if (!(pstate
== PCI_D3hot
|| pstate
== PCI_D3cold
))
3557 del_timer_sync(&hw
->idle_timer
);
3558 netif_poll_disable(hw
->dev
[0]);
3560 for (i
= 0; i
< hw
->ports
; i
++) {
3561 struct net_device
*dev
= hw
->dev
[i
];
3563 if (netif_running(dev
)) {
3565 netif_device_detach(dev
);
3569 sky2_write32(hw
, B0_IMSK
, 0);
3570 pci_save_state(pdev
);
3571 sky2_set_power_state(hw
, pstate
);
3575 static int sky2_resume(struct pci_dev
*pdev
)
3577 struct sky2_hw
*hw
= pci_get_drvdata(pdev
);
3580 pci_restore_state(pdev
);
3581 pci_enable_wake(pdev
, PCI_D0
, 0);
3582 sky2_set_power_state(hw
, PCI_D0
);
3584 err
= sky2_reset(hw
);
3588 sky2_write32(hw
, B0_IMSK
, Y2_IS_BASE
);
3590 for (i
= 0; i
< hw
->ports
; i
++) {
3591 struct net_device
*dev
= hw
->dev
[i
];
3592 if (netif_running(dev
)) {
3593 netif_device_attach(dev
);
3597 printk(KERN_ERR PFX
"%s: could not up: %d\n",
3605 netif_poll_enable(hw
->dev
[0]);
3606 sky2_idle_start(hw
);
3612 static struct pci_driver sky2_driver
= {
3614 .id_table
= sky2_id_table
,
3615 .probe
= sky2_probe
,
3616 .remove
= __devexit_p(sky2_remove
),
3618 .suspend
= sky2_suspend
,
3619 .resume
= sky2_resume
,
3623 static int __init
sky2_init_module(void)
3625 return pci_register_driver(&sky2_driver
);
3628 static void __exit
sky2_cleanup_module(void)
3630 pci_unregister_driver(&sky2_driver
);
3633 module_init(sky2_init_module
);
3634 module_exit(sky2_cleanup_module
);
3636 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3637 MODULE_AUTHOR("Stephen Hemminger <shemminger@osdl.org>");
3638 MODULE_LICENSE("GPL");
3639 MODULE_VERSION(DRV_VERSION
);