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TTY: serial, move 68360 driver to staging
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / dma / ste_dma40.c
blobcd3a7c726bf87bef330f882981afc2fc42be964e
1 /*
2 * Copyright (C) Ericsson AB 2007-2008
3 * Copyright (C) ST-Ericsson SA 2008-2010
4 * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
5 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
6 * License terms: GNU General Public License (GPL) version 2
7 */
8
9 #include <linux/dma-mapping.h>
10 #include <linux/kernel.h>
11 #include <linux/slab.h>
12 #include <linux/dmaengine.h>
13 #include <linux/platform_device.h>
14 #include <linux/clk.h>
15 #include <linux/delay.h>
16 #include <linux/err.h>
17 #include <linux/amba/bus.h>
18
19 #include <plat/ste_dma40.h>
20
21 #include "ste_dma40_ll.h"
22
23 #define D40_NAME "dma40"
24
25 #define D40_PHY_CHAN -1
26
27 /* For masking out/in 2 bit channel positions */
28 #define D40_CHAN_POS(chan) (2 * (chan / 2))
29 #define D40_CHAN_POS_MASK(chan) (0x3 << D40_CHAN_POS(chan))
30
31 /* Maximum iterations taken before giving up suspending a channel */
32 #define D40_SUSPEND_MAX_IT 500
33
34 /* Hardware requirement on LCLA alignment */
35 #define LCLA_ALIGNMENT 0x40000
36
37 /* Max number of links per event group */
38 #define D40_LCLA_LINK_PER_EVENT_GRP 128
39 #define D40_LCLA_END D40_LCLA_LINK_PER_EVENT_GRP
40
41 /* Attempts before giving up to trying to get pages that are aligned */
42 #define MAX_LCLA_ALLOC_ATTEMPTS 256
43
44 /* Bit markings for allocation map */
45 #define D40_ALLOC_FREE (1 << 31)
46 #define D40_ALLOC_PHY (1 << 30)
47 #define D40_ALLOC_LOG_FREE 0
48
49 /**
50 * enum 40_command - The different commands and/or statuses.
51 *
52 * @D40_DMA_STOP: DMA channel command STOP or status STOPPED,
53 * @D40_DMA_RUN: The DMA channel is RUNNING of the command RUN.
54 * @D40_DMA_SUSPEND_REQ: Request the DMA to SUSPEND as soon as possible.
55 * @D40_DMA_SUSPENDED: The DMA channel is SUSPENDED.
56 */
57 enum d40_command {
58 D40_DMA_STOP = 0,
59 D40_DMA_RUN = 1,
60 D40_DMA_SUSPEND_REQ = 2,
61 D40_DMA_SUSPENDED = 3
62 };
63
64 /**
65 * struct d40_lli_pool - Structure for keeping LLIs in memory
66 *
67 * @base: Pointer to memory area when the pre_alloc_lli's are not large
68 * enough, IE bigger than the most common case, 1 dst and 1 src. NULL if
69 * pre_alloc_lli is used.
70 * @dma_addr: DMA address, if mapped
71 * @size: The size in bytes of the memory at base or the size of pre_alloc_lli.
72 * @pre_alloc_lli: Pre allocated area for the most common case of transfers,
73 * one buffer to one buffer.
74 */
75 struct d40_lli_pool {
76 void *base;
77 int size;
78 dma_addr_t dma_addr;
79 /* Space for dst and src, plus an extra for padding */
80 u8 pre_alloc_lli[3 * sizeof(struct d40_phy_lli)];
81 };
82
83 /**
84 * struct d40_desc - A descriptor is one DMA job.
85 *
86 * @lli_phy: LLI settings for physical channel. Both src and dst=
87 * points into the lli_pool, to base if lli_len > 1 or to pre_alloc_lli if
88 * lli_len equals one.
89 * @lli_log: Same as above but for logical channels.
90 * @lli_pool: The pool with two entries pre-allocated.
91 * @lli_len: Number of llis of current descriptor.
92 * @lli_current: Number of transferred llis.
93 * @lcla_alloc: Number of LCLA entries allocated.
94 * @txd: DMA engine struct. Used for among other things for communication
95 * during a transfer.
96 * @node: List entry.
97 * @is_in_client_list: true if the client owns this descriptor.
98 * the previous one.
99 *
100 * This descriptor is used for both logical and physical transfers.
101 */
102 struct d40_desc {
103 /* LLI physical */
104 struct d40_phy_lli_bidir lli_phy;
105 /* LLI logical */
106 struct d40_log_lli_bidir lli_log;
107
108 struct d40_lli_pool lli_pool;
109 int lli_len;
110 int lli_current;
111 int lcla_alloc;
112
113 struct dma_async_tx_descriptor txd;
114 struct list_head node;
115
116 bool is_in_client_list;
117 bool cyclic;
118 };
119
120 /**
121 * struct d40_lcla_pool - LCLA pool settings and data.
122 *
123 * @base: The virtual address of LCLA. 18 bit aligned.
124 * @base_unaligned: The orignal kmalloc pointer, if kmalloc is used.
125 * This pointer is only there for clean-up on error.
126 * @pages: The number of pages needed for all physical channels.
127 * Only used later for clean-up on error
128 * @lock: Lock to protect the content in this struct.
129 * @alloc_map: big map over which LCLA entry is own by which job.
130 */
131 struct d40_lcla_pool {
132 void *base;
133 dma_addr_t dma_addr;
134 void *base_unaligned;
135 int pages;
136 spinlock_t lock;
137 struct d40_desc **alloc_map;
138 };
139
140 /**
141 * struct d40_phy_res - struct for handling eventlines mapped to physical
142 * channels.
143 *
144 * @lock: A lock protection this entity.
145 * @num: The physical channel number of this entity.
146 * @allocated_src: Bit mapped to show which src event line's are mapped to
147 * this physical channel. Can also be free or physically allocated.
148 * @allocated_dst: Same as for src but is dst.
149 * allocated_dst and allocated_src uses the D40_ALLOC* defines as well as
150 * event line number.
151 */
152 struct d40_phy_res {
153 spinlock_t lock;
154 int num;
155 u32 allocated_src;
156 u32 allocated_dst;
157 };
158
159 struct d40_base;
160
161 /**
162 * struct d40_chan - Struct that describes a channel.
163 *
164 * @lock: A spinlock to protect this struct.
165 * @log_num: The logical number, if any of this channel.
166 * @completed: Starts with 1, after first interrupt it is set to dma engine's
167 * current cookie.
168 * @pending_tx: The number of pending transfers. Used between interrupt handler
169 * and tasklet.
170 * @busy: Set to true when transfer is ongoing on this channel.
171 * @phy_chan: Pointer to physical channel which this instance runs on. If this
172 * point is NULL, then the channel is not allocated.
173 * @chan: DMA engine handle.
174 * @tasklet: Tasklet that gets scheduled from interrupt context to complete a
175 * transfer and call client callback.
176 * @client: Cliented owned descriptor list.
177 * @active: Active descriptor.
178 * @queue: Queued jobs.
179 * @dma_cfg: The client configuration of this dma channel.
180 * @configured: whether the dma_cfg configuration is valid
181 * @base: Pointer to the device instance struct.
182 * @src_def_cfg: Default cfg register setting for src.
183 * @dst_def_cfg: Default cfg register setting for dst.
184 * @log_def: Default logical channel settings.
185 * @lcla: Space for one dst src pair for logical channel transfers.
186 * @lcpa: Pointer to dst and src lcpa settings.
187 * @runtime_addr: runtime configured address.
188 * @runtime_direction: runtime configured direction.
189 *
190 * This struct can either "be" a logical or a physical channel.
191 */
192 struct d40_chan {
193 spinlock_t lock;
194 int log_num;
195 /* ID of the most recent completed transfer */
196 int completed;
197 int pending_tx;
198 bool busy;
199 struct d40_phy_res *phy_chan;
200 struct dma_chan chan;
201 struct tasklet_struct tasklet;
202 struct list_head client;
203 struct list_head pending_queue;
204 struct list_head active;
205 struct list_head queue;
206 struct stedma40_chan_cfg dma_cfg;
207 bool configured;
208 struct d40_base *base;
209 /* Default register configurations */
210 u32 src_def_cfg;
211 u32 dst_def_cfg;
212 struct d40_def_lcsp log_def;
213 struct d40_log_lli_full *lcpa;
214 /* Runtime reconfiguration */
215 dma_addr_t runtime_addr;
216 enum dma_data_direction runtime_direction;
217 };
218
219 /**
220 * struct d40_base - The big global struct, one for each probe'd instance.
221 *
222 * @interrupt_lock: Lock used to make sure one interrupt is handle a time.
223 * @execmd_lock: Lock for execute command usage since several channels share
224 * the same physical register.
225 * @dev: The device structure.
226 * @virtbase: The virtual base address of the DMA's register.
227 * @rev: silicon revision detected.
228 * @clk: Pointer to the DMA clock structure.
229 * @phy_start: Physical memory start of the DMA registers.
230 * @phy_size: Size of the DMA register map.
231 * @irq: The IRQ number.
232 * @num_phy_chans: The number of physical channels. Read from HW. This
233 * is the number of available channels for this driver, not counting "Secure
234 * mode" allocated physical channels.
235 * @num_log_chans: The number of logical channels. Calculated from
236 * num_phy_chans.
237 * @dma_both: dma_device channels that can do both memcpy and slave transfers.
238 * @dma_slave: dma_device channels that can do only do slave transfers.
239 * @dma_memcpy: dma_device channels that can do only do memcpy transfers.
240 * @log_chans: Room for all possible logical channels in system.
241 * @lookup_log_chans: Used to map interrupt number to logical channel. Points
242 * to log_chans entries.
243 * @lookup_phy_chans: Used to map interrupt number to physical channel. Points
244 * to phy_chans entries.
245 * @plat_data: Pointer to provided platform_data which is the driver
246 * configuration.
247 * @phy_res: Vector containing all physical channels.
248 * @lcla_pool: lcla pool settings and data.
249 * @lcpa_base: The virtual mapped address of LCPA.
250 * @phy_lcpa: The physical address of the LCPA.
251 * @lcpa_size: The size of the LCPA area.
252 * @desc_slab: cache for descriptors.
253 */
254 struct d40_base {
255 spinlock_t interrupt_lock;
256 spinlock_t execmd_lock;
257 struct device *dev;
258 void __iomem *virtbase;
259 u8 rev:4;
260 struct clk *clk;
261 phys_addr_t phy_start;
262 resource_size_t phy_size;
263 int irq;
264 int num_phy_chans;
265 int num_log_chans;
266 struct dma_device dma_both;
267 struct dma_device dma_slave;
268 struct dma_device dma_memcpy;
269 struct d40_chan *phy_chans;
270 struct d40_chan *log_chans;
271 struct d40_chan **lookup_log_chans;
272 struct d40_chan **lookup_phy_chans;
273 struct stedma40_platform_data *plat_data;
274 /* Physical half channels */
275 struct d40_phy_res *phy_res;
276 struct d40_lcla_pool lcla_pool;
277 void *lcpa_base;
278 dma_addr_t phy_lcpa;
279 resource_size_t lcpa_size;
280 struct kmem_cache *desc_slab;
281 };
282
283 /**
284 * struct d40_interrupt_lookup - lookup table for interrupt handler
285 *
286 * @src: Interrupt mask register.
287 * @clr: Interrupt clear register.
288 * @is_error: true if this is an error interrupt.
289 * @offset: start delta in the lookup_log_chans in d40_base. If equals to
290 * D40_PHY_CHAN, the lookup_phy_chans shall be used instead.
291 */
292 struct d40_interrupt_lookup {
293 u32 src;
294 u32 clr;
295 bool is_error;
296 int offset;
297 };
298
299 /**
300 * struct d40_reg_val - simple lookup struct
301 *
302 * @reg: The register.
303 * @val: The value that belongs to the register in reg.
304 */
305 struct d40_reg_val {
306 unsigned int reg;
307 unsigned int val;
308 };
309
310 static struct device *chan2dev(struct d40_chan *d40c)
311 {
312 return &d40c->chan.dev->device;
313 }
314
315 static bool chan_is_physical(struct d40_chan *chan)
316 {
317 return chan->log_num == D40_PHY_CHAN;
318 }
319
320 static bool chan_is_logical(struct d40_chan *chan)
321 {
322 return !chan_is_physical(chan);
323 }
324
325 static void __iomem *chan_base(struct d40_chan *chan)
326 {
327 return chan->base->virtbase + D40_DREG_PCBASE +
328 chan->phy_chan->num * D40_DREG_PCDELTA;
329 }
330
331 #define d40_err(dev, format, arg...) \
332 dev_err(dev, "[%s] " format, __func__, ## arg)
333
334 #define chan_err(d40c, format, arg...) \
335 d40_err(chan2dev(d40c), format, ## arg)
336
337 static int d40_pool_lli_alloc(struct d40_chan *d40c, struct d40_desc *d40d,
338 int lli_len)
339 {
340 bool is_log = chan_is_logical(d40c);
341 u32 align;
342 void *base;
343
344 if (is_log)
345 align = sizeof(struct d40_log_lli);
346 else
347 align = sizeof(struct d40_phy_lli);
348
349 if (lli_len == 1) {
350 base = d40d->lli_pool.pre_alloc_lli;
351 d40d->lli_pool.size = sizeof(d40d->lli_pool.pre_alloc_lli);
352 d40d->lli_pool.base = NULL;
353 } else {
354 d40d->lli_pool.size = lli_len * 2 * align;
355
356 base = kmalloc(d40d->lli_pool.size + align, GFP_NOWAIT);
357 d40d->lli_pool.base = base;
358
359 if (d40d->lli_pool.base == NULL)
360 return -ENOMEM;
361 }
362
363 if (is_log) {
364 d40d->lli_log.src = PTR_ALIGN(base, align);
365 d40d->lli_log.dst = d40d->lli_log.src + lli_len;
366
367 d40d->lli_pool.dma_addr = 0;
368 } else {
369 d40d->lli_phy.src = PTR_ALIGN(base, align);
370 d40d->lli_phy.dst = d40d->lli_phy.src + lli_len;
371
372 d40d->lli_pool.dma_addr = dma_map_single(d40c->base->dev,
373 d40d->lli_phy.src,
374 d40d->lli_pool.size,
375 DMA_TO_DEVICE);
376
377 if (dma_mapping_error(d40c->base->dev,
378 d40d->lli_pool.dma_addr)) {
379 kfree(d40d->lli_pool.base);
380 d40d->lli_pool.base = NULL;
381 d40d->lli_pool.dma_addr = 0;
382 return -ENOMEM;
383 }
384 }
385
386 return 0;
387 }
388
389 static void d40_pool_lli_free(struct d40_chan *d40c, struct d40_desc *d40d)
390 {
391 if (d40d->lli_pool.dma_addr)
392 dma_unmap_single(d40c->base->dev, d40d->lli_pool.dma_addr,
393 d40d->lli_pool.size, DMA_TO_DEVICE);
394
395 kfree(d40d->lli_pool.base);
396 d40d->lli_pool.base = NULL;
397 d40d->lli_pool.size = 0;
398 d40d->lli_log.src = NULL;
399 d40d->lli_log.dst = NULL;
400 d40d->lli_phy.src = NULL;
401 d40d->lli_phy.dst = NULL;
402 }
403
404 static int d40_lcla_alloc_one(struct d40_chan *d40c,
405 struct d40_desc *d40d)
406 {
407 unsigned long flags;
408 int i;
409 int ret = -EINVAL;
410 int p;
411
412 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
413
414 p = d40c->phy_chan->num * D40_LCLA_LINK_PER_EVENT_GRP;
415
416 /*
417 * Allocate both src and dst at the same time, therefore the half
418 * start on 1 since 0 can't be used since zero is used as end marker.
419 */
420 for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
421 if (!d40c->base->lcla_pool.alloc_map[p + i]) {
422 d40c->base->lcla_pool.alloc_map[p + i] = d40d;
423 d40d->lcla_alloc++;
424 ret = i;
425 break;
426 }
427 }
428
429 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
430
431 return ret;
432 }
433
434 static int d40_lcla_free_all(struct d40_chan *d40c,
435 struct d40_desc *d40d)
436 {
437 unsigned long flags;
438 int i;
439 int ret = -EINVAL;
440
441 if (chan_is_physical(d40c))
442 return 0;
443
444 spin_lock_irqsave(&d40c->base->lcla_pool.lock, flags);
445
446 for (i = 1 ; i < D40_LCLA_LINK_PER_EVENT_GRP / 2; i++) {
447 if (d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num *
448 D40_LCLA_LINK_PER_EVENT_GRP + i] == d40d) {
449 d40c->base->lcla_pool.alloc_map[d40c->phy_chan->num *
450 D40_LCLA_LINK_PER_EVENT_GRP + i] = NULL;
451 d40d->lcla_alloc--;
452 if (d40d->lcla_alloc == 0) {
453 ret = 0;
454 break;
455 }
456 }
457 }
458
459 spin_unlock_irqrestore(&d40c->base->lcla_pool.lock, flags);
460
461 return ret;
462
463 }
464
465 static void d40_desc_remove(struct d40_desc *d40d)
466 {
467 list_del(&d40d->node);
468 }
469
470 static struct d40_desc *d40_desc_get(struct d40_chan *d40c)
471 {
472 struct d40_desc *desc = NULL;
473
474 if (!list_empty(&d40c->client)) {
475 struct d40_desc *d;
476 struct d40_desc *_d;
477
478 list_for_each_entry_safe(d, _d, &d40c->client, node)
479 if (async_tx_test_ack(&d->txd)) {
480 d40_pool_lli_free(d40c, d);
481 d40_desc_remove(d);
482 desc = d;
483 memset(desc, 0, sizeof(*desc));
484 break;
485 }
486 }
487
488 if (!desc)
489 desc = kmem_cache_zalloc(d40c->base->desc_slab, GFP_NOWAIT);
490
491 if (desc)
492 INIT_LIST_HEAD(&desc->node);
493
494 return desc;
495 }
496
497 static void d40_desc_free(struct d40_chan *d40c, struct d40_desc *d40d)
498 {
499
500 d40_pool_lli_free(d40c, d40d);
501 d40_lcla_free_all(d40c, d40d);
502 kmem_cache_free(d40c->base->desc_slab, d40d);
503 }
504
505 static void d40_desc_submit(struct d40_chan *d40c, struct d40_desc *desc)
506 {
507 list_add_tail(&desc->node, &d40c->active);
508 }
509
510 static void d40_phy_lli_load(struct d40_chan *chan, struct d40_desc *desc)
511 {
512 struct d40_phy_lli *lli_dst = desc->lli_phy.dst;
513 struct d40_phy_lli *lli_src = desc->lli_phy.src;
514 void __iomem *base = chan_base(chan);
515
516 writel(lli_src->reg_cfg, base + D40_CHAN_REG_SSCFG);
517 writel(lli_src->reg_elt, base + D40_CHAN_REG_SSELT);
518 writel(lli_src->reg_ptr, base + D40_CHAN_REG_SSPTR);
519 writel(lli_src->reg_lnk, base + D40_CHAN_REG_SSLNK);
520
521 writel(lli_dst->reg_cfg, base + D40_CHAN_REG_SDCFG);
522 writel(lli_dst->reg_elt, base + D40_CHAN_REG_SDELT);
523 writel(lli_dst->reg_ptr, base + D40_CHAN_REG_SDPTR);
524 writel(lli_dst->reg_lnk, base + D40_CHAN_REG_SDLNK);
525 }
526
527 static void d40_log_lli_to_lcxa(struct d40_chan *chan, struct d40_desc *desc)
528 {
529 struct d40_lcla_pool *pool = &chan->base->lcla_pool;
530 struct d40_log_lli_bidir *lli = &desc->lli_log;
531 int lli_current = desc->lli_current;
532 int lli_len = desc->lli_len;
533 bool cyclic = desc->cyclic;
534 int curr_lcla = -EINVAL;
535 int first_lcla = 0;
536 bool linkback;
537
538 /*
539 * We may have partially running cyclic transfers, in case we did't get
540 * enough LCLA entries.
541 */
542 linkback = cyclic && lli_current == 0;
543
544 /*
545 * For linkback, we need one LCLA even with only one link, because we
546 * can't link back to the one in LCPA space
547 */
548 if (linkback || (lli_len - lli_current > 1)) {
549 curr_lcla = d40_lcla_alloc_one(chan, desc);
550 first_lcla = curr_lcla;
551 }
552
553 /*
554 * For linkback, we normally load the LCPA in the loop since we need to
555 * link it to the second LCLA and not the first. However, if we
556 * couldn't even get a first LCLA, then we have to run in LCPA and
557 * reload manually.
558 */
559 if (!linkback || curr_lcla == -EINVAL) {
560 unsigned int flags = 0;
561
562 if (curr_lcla == -EINVAL)
563 flags |= LLI_TERM_INT;
564
565 d40_log_lli_lcpa_write(chan->lcpa,
566 &lli->dst[lli_current],
567 &lli->src[lli_current],
568 curr_lcla,
569 flags);
570 lli_current++;
571 }
572
573 if (curr_lcla < 0)
574 goto out;
575
576 for (; lli_current < lli_len; lli_current++) {
577 unsigned int lcla_offset = chan->phy_chan->num * 1024 +
578 8 * curr_lcla * 2;
579 struct d40_log_lli *lcla = pool->base + lcla_offset;
580 unsigned int flags = 0;
581 int next_lcla;
582
583 if (lli_current + 1 < lli_len)
584 next_lcla = d40_lcla_alloc_one(chan, desc);
585 else
586 next_lcla = linkback ? first_lcla : -EINVAL;
587
588 if (cyclic || next_lcla == -EINVAL)
589 flags |= LLI_TERM_INT;
590
591 if (linkback && curr_lcla == first_lcla) {
592 /* First link goes in both LCPA and LCLA */
593 d40_log_lli_lcpa_write(chan->lcpa,
594 &lli->dst[lli_current],
595 &lli->src[lli_current],
596 next_lcla, flags);
597 }
598
599 /*
600 * One unused LCLA in the cyclic case if the very first
601 * next_lcla fails...
602 */
603 d40_log_lli_lcla_write(lcla,
604 &lli->dst[lli_current],
605 &lli->src[lli_current],
606 next_lcla, flags);
607
608 dma_sync_single_range_for_device(chan->base->dev,
609 pool->dma_addr, lcla_offset,
610 2 * sizeof(struct d40_log_lli),
611 DMA_TO_DEVICE);
612
613 curr_lcla = next_lcla;
614
615 if (curr_lcla == -EINVAL || curr_lcla == first_lcla) {
616 lli_current++;
617 break;
618 }
619 }
620
621 out:
622 desc->lli_current = lli_current;
623 }
624
625 static void d40_desc_load(struct d40_chan *d40c, struct d40_desc *d40d)
626 {
627 if (chan_is_physical(d40c)) {
628 d40_phy_lli_load(d40c, d40d);
629 d40d->lli_current = d40d->lli_len;
630 } else
631 d40_log_lli_to_lcxa(d40c, d40d);
632 }
633
634 static struct d40_desc *d40_first_active_get(struct d40_chan *d40c)
635 {
636 struct d40_desc *d;
637
638 if (list_empty(&d40c->active))
639 return NULL;
640
641 d = list_first_entry(&d40c->active,
642 struct d40_desc,
643 node);
644 return d;
645 }
646
647 static void d40_desc_queue(struct d40_chan *d40c, struct d40_desc *desc)
648 {
649 list_add_tail(&desc->node, &d40c->pending_queue);
650 }
651
652 static struct d40_desc *d40_first_pending(struct d40_chan *d40c)
653 {
654 struct d40_desc *d;
655
656 if (list_empty(&d40c->pending_queue))
657 return NULL;
658
659 d = list_first_entry(&d40c->pending_queue,
660 struct d40_desc,
661 node);
662 return d;
663 }
664
665 static struct d40_desc *d40_first_queued(struct d40_chan *d40c)
666 {
667 struct d40_desc *d;
668
669 if (list_empty(&d40c->queue))
670 return NULL;
671
672 d = list_first_entry(&d40c->queue,
673 struct d40_desc,
674 node);
675 return d;
676 }
677
678 static int d40_psize_2_burst_size(bool is_log, int psize)
679 {
680 if (is_log) {
681 if (psize == STEDMA40_PSIZE_LOG_1)
682 return 1;
683 } else {
684 if (psize == STEDMA40_PSIZE_PHY_1)
685 return 1;
686 }
687
688 return 2 << psize;
689 }
690
691 /*
692 * The dma only supports transmitting packages up to
693 * STEDMA40_MAX_SEG_SIZE << data_width. Calculate the total number of
694 * dma elements required to send the entire sg list
695 */
696 static int d40_size_2_dmalen(int size, u32 data_width1, u32 data_width2)
697 {
698 int dmalen;
699 u32 max_w = max(data_width1, data_width2);
700 u32 min_w = min(data_width1, data_width2);
701 u32 seg_max = ALIGN(STEDMA40_MAX_SEG_SIZE << min_w, 1 << max_w);
702
703 if (seg_max > STEDMA40_MAX_SEG_SIZE)
704 seg_max -= (1 << max_w);
705
706 if (!IS_ALIGNED(size, 1 << max_w))
707 return -EINVAL;
708
709 if (size <= seg_max)
710 dmalen = 1;
711 else {
712 dmalen = size / seg_max;
713 if (dmalen * seg_max < size)
714 dmalen++;
715 }
716 return dmalen;
717 }
718
719 static int d40_sg_2_dmalen(struct scatterlist *sgl, int sg_len,
720 u32 data_width1, u32 data_width2)
721 {
722 struct scatterlist *sg;
723 int i;
724 int len = 0;
725 int ret;
726
727 for_each_sg(sgl, sg, sg_len, i) {
728 ret = d40_size_2_dmalen(sg_dma_len(sg),
729 data_width1, data_width2);
730 if (ret < 0)
731 return ret;
732 len += ret;
733 }
734 return len;
735 }
736
737 /* Support functions for logical channels */
738
739 static int d40_channel_execute_command(struct d40_chan *d40c,
740 enum d40_command command)
741 {
742 u32 status;
743 int i;
744 void __iomem *active_reg;
745 int ret = 0;
746 unsigned long flags;
747 u32 wmask;
748
749 spin_lock_irqsave(&d40c->base->execmd_lock, flags);
750
751 if (d40c->phy_chan->num % 2 == 0)
752 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
753 else
754 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
755
756 if (command == D40_DMA_SUSPEND_REQ) {
757 status = (readl(active_reg) &
758 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
759 D40_CHAN_POS(d40c->phy_chan->num);
760
761 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
762 goto done;
763 }
764
765 wmask = 0xffffffff & ~(D40_CHAN_POS_MASK(d40c->phy_chan->num));
766 writel(wmask | (command << D40_CHAN_POS(d40c->phy_chan->num)),
767 active_reg);
768
769 if (command == D40_DMA_SUSPEND_REQ) {
770
771 for (i = 0 ; i < D40_SUSPEND_MAX_IT; i++) {
772 status = (readl(active_reg) &
773 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
774 D40_CHAN_POS(d40c->phy_chan->num);
775
776 cpu_relax();
777 /*
778 * Reduce the number of bus accesses while
779 * waiting for the DMA to suspend.
780 */
781 udelay(3);
782
783 if (status == D40_DMA_STOP ||
784 status == D40_DMA_SUSPENDED)
785 break;
786 }
787
788 if (i == D40_SUSPEND_MAX_IT) {
789 chan_err(d40c,
790 "unable to suspend the chl %d (log: %d) status %x\n",
791 d40c->phy_chan->num, d40c->log_num,
792 status);
793 dump_stack();
794 ret = -EBUSY;
795 }
796
797 }
798 done:
799 spin_unlock_irqrestore(&d40c->base->execmd_lock, flags);
800 return ret;
801 }
802
803 static void d40_term_all(struct d40_chan *d40c)
804 {
805 struct d40_desc *d40d;
806
807 /* Release active descriptors */
808 while ((d40d = d40_first_active_get(d40c))) {
809 d40_desc_remove(d40d);
810 d40_desc_free(d40c, d40d);
811 }
812
813 /* Release queued descriptors waiting for transfer */
814 while ((d40d = d40_first_queued(d40c))) {
815 d40_desc_remove(d40d);
816 d40_desc_free(d40c, d40d);
817 }
818
819 /* Release pending descriptors */
820 while ((d40d = d40_first_pending(d40c))) {
821 d40_desc_remove(d40d);
822 d40_desc_free(d40c, d40d);
823 }
824
825 d40c->pending_tx = 0;
826 d40c->busy = false;
827 }
828
829 static void __d40_config_set_event(struct d40_chan *d40c, bool enable,
830 u32 event, int reg)
831 {
832 void __iomem *addr = chan_base(d40c) + reg;
833 int tries;
834
835 if (!enable) {
836 writel((D40_DEACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
837 | ~D40_EVENTLINE_MASK(event), addr);
838 return;
839 }
840
841 /*
842 * The hardware sometimes doesn't register the enable when src and dst
843 * event lines are active on the same logical channel. Retry to ensure
844 * it does. Usually only one retry is sufficient.
845 */
846 tries = 100;
847 while (--tries) {
848 writel((D40_ACTIVATE_EVENTLINE << D40_EVENTLINE_POS(event))
849 | ~D40_EVENTLINE_MASK(event), addr);
850
851 if (readl(addr) & D40_EVENTLINE_MASK(event))
852 break;
853 }
854
855 if (tries != 99)
856 dev_dbg(chan2dev(d40c),
857 "[%s] workaround enable S%cLNK (%d tries)\n",
858 __func__, reg == D40_CHAN_REG_SSLNK ? 'S' : 'D',
859 100 - tries);
860
861 WARN_ON(!tries);
862 }
863
864 static void d40_config_set_event(struct d40_chan *d40c, bool do_enable)
865 {
866 unsigned long flags;
867
868 spin_lock_irqsave(&d40c->phy_chan->lock, flags);
869
870 /* Enable event line connected to device (or memcpy) */
871 if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) ||
872 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH)) {
873 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
874
875 __d40_config_set_event(d40c, do_enable, event,
876 D40_CHAN_REG_SSLNK);
877 }
878
879 if (d40c->dma_cfg.dir != STEDMA40_PERIPH_TO_MEM) {
880 u32 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
881
882 __d40_config_set_event(d40c, do_enable, event,
883 D40_CHAN_REG_SDLNK);
884 }
885
886 spin_unlock_irqrestore(&d40c->phy_chan->lock, flags);
887 }
888
889 static u32 d40_chan_has_events(struct d40_chan *d40c)
890 {
891 void __iomem *chanbase = chan_base(d40c);
892 u32 val;
893
894 val = readl(chanbase + D40_CHAN_REG_SSLNK);
895 val |= readl(chanbase + D40_CHAN_REG_SDLNK);
896
897 return val;
898 }
899
900 static u32 d40_get_prmo(struct d40_chan *d40c)
901 {
902 static const unsigned int phy_map[] = {
903 [STEDMA40_PCHAN_BASIC_MODE]
904 = D40_DREG_PRMO_PCHAN_BASIC,
905 [STEDMA40_PCHAN_MODULO_MODE]
906 = D40_DREG_PRMO_PCHAN_MODULO,
907 [STEDMA40_PCHAN_DOUBLE_DST_MODE]
908 = D40_DREG_PRMO_PCHAN_DOUBLE_DST,
909 };
910 static const unsigned int log_map[] = {
911 [STEDMA40_LCHAN_SRC_PHY_DST_LOG]
912 = D40_DREG_PRMO_LCHAN_SRC_PHY_DST_LOG,
913 [STEDMA40_LCHAN_SRC_LOG_DST_PHY]
914 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_PHY,
915 [STEDMA40_LCHAN_SRC_LOG_DST_LOG]
916 = D40_DREG_PRMO_LCHAN_SRC_LOG_DST_LOG,
917 };
918
919 if (chan_is_physical(d40c))
920 return phy_map[d40c->dma_cfg.mode_opt];
921 else
922 return log_map[d40c->dma_cfg.mode_opt];
923 }
924
925 static void d40_config_write(struct d40_chan *d40c)
926 {
927 u32 addr_base;
928 u32 var;
929
930 /* Odd addresses are even addresses + 4 */
931 addr_base = (d40c->phy_chan->num % 2) * 4;
932 /* Setup channel mode to logical or physical */
933 var = ((u32)(chan_is_logical(d40c)) + 1) <<
934 D40_CHAN_POS(d40c->phy_chan->num);
935 writel(var, d40c->base->virtbase + D40_DREG_PRMSE + addr_base);
936
937 /* Setup operational mode option register */
938 var = d40_get_prmo(d40c) << D40_CHAN_POS(d40c->phy_chan->num);
939
940 writel(var, d40c->base->virtbase + D40_DREG_PRMOE + addr_base);
941
942 if (chan_is_logical(d40c)) {
943 int lidx = (d40c->phy_chan->num << D40_SREG_ELEM_LOG_LIDX_POS)
944 & D40_SREG_ELEM_LOG_LIDX_MASK;
945 void __iomem *chanbase = chan_base(d40c);
946
947 /* Set default config for CFG reg */
948 writel(d40c->src_def_cfg, chanbase + D40_CHAN_REG_SSCFG);
949 writel(d40c->dst_def_cfg, chanbase + D40_CHAN_REG_SDCFG);
950
951 /* Set LIDX for lcla */
952 writel(lidx, chanbase + D40_CHAN_REG_SSELT);
953 writel(lidx, chanbase + D40_CHAN_REG_SDELT);
954 }
955 }
956
957 static u32 d40_residue(struct d40_chan *d40c)
958 {
959 u32 num_elt;
960
961 if (chan_is_logical(d40c))
962 num_elt = (readl(&d40c->lcpa->lcsp2) & D40_MEM_LCSP2_ECNT_MASK)
963 >> D40_MEM_LCSP2_ECNT_POS;
964 else {
965 u32 val = readl(chan_base(d40c) + D40_CHAN_REG_SDELT);
966 num_elt = (val & D40_SREG_ELEM_PHY_ECNT_MASK)
967 >> D40_SREG_ELEM_PHY_ECNT_POS;
968 }
969
970 return num_elt * (1 << d40c->dma_cfg.dst_info.data_width);
971 }
972
973 static bool d40_tx_is_linked(struct d40_chan *d40c)
974 {
975 bool is_link;
976
977 if (chan_is_logical(d40c))
978 is_link = readl(&d40c->lcpa->lcsp3) & D40_MEM_LCSP3_DLOS_MASK;
979 else
980 is_link = readl(chan_base(d40c) + D40_CHAN_REG_SDLNK)
981 & D40_SREG_LNK_PHYS_LNK_MASK;
982
983 return is_link;
984 }
985
986 static int d40_pause(struct d40_chan *d40c)
987 {
988 int res = 0;
989 unsigned long flags;
990
991 if (!d40c->busy)
992 return 0;
993
994 spin_lock_irqsave(&d40c->lock, flags);
995
996 res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
997 if (res == 0) {
998 if (chan_is_logical(d40c)) {
999 d40_config_set_event(d40c, false);
1000 /* Resume the other logical channels if any */
1001 if (d40_chan_has_events(d40c))
1002 res = d40_channel_execute_command(d40c,
1003 D40_DMA_RUN);
1004 }
1005 }
1006
1007 spin_unlock_irqrestore(&d40c->lock, flags);
1008 return res;
1009 }
1010
1011 static int d40_resume(struct d40_chan *d40c)
1012 {
1013 int res = 0;
1014 unsigned long flags;
1015
1016 if (!d40c->busy)
1017 return 0;
1018
1019 spin_lock_irqsave(&d40c->lock, flags);
1020
1021 if (d40c->base->rev == 0)
1022 if (chan_is_logical(d40c)) {
1023 res = d40_channel_execute_command(d40c,
1024 D40_DMA_SUSPEND_REQ);
1025 goto no_suspend;
1026 }
1027
1028 /* If bytes left to transfer or linked tx resume job */
1029 if (d40_residue(d40c) || d40_tx_is_linked(d40c)) {
1030
1031 if (chan_is_logical(d40c))
1032 d40_config_set_event(d40c, true);
1033
1034 res = d40_channel_execute_command(d40c, D40_DMA_RUN);
1035 }
1036
1037 no_suspend:
1038 spin_unlock_irqrestore(&d40c->lock, flags);
1039 return res;
1040 }
1041
1042 static int d40_terminate_all(struct d40_chan *chan)
1043 {
1044 unsigned long flags;
1045 int ret = 0;
1046
1047 ret = d40_pause(chan);
1048 if (!ret && chan_is_physical(chan))
1049 ret = d40_channel_execute_command(chan, D40_DMA_STOP);
1050
1051 spin_lock_irqsave(&chan->lock, flags);
1052 d40_term_all(chan);
1053 spin_unlock_irqrestore(&chan->lock, flags);
1054
1055 return ret;
1056 }
1057
1058 static dma_cookie_t d40_tx_submit(struct dma_async_tx_descriptor *tx)
1059 {
1060 struct d40_chan *d40c = container_of(tx->chan,
1061 struct d40_chan,
1062 chan);
1063 struct d40_desc *d40d = container_of(tx, struct d40_desc, txd);
1064 unsigned long flags;
1065
1066 spin_lock_irqsave(&d40c->lock, flags);
1067
1068 d40c->chan.cookie++;
1069
1070 if (d40c->chan.cookie < 0)
1071 d40c->chan.cookie = 1;
1072
1073 d40d->txd.cookie = d40c->chan.cookie;
1074
1075 d40_desc_queue(d40c, d40d);
1076
1077 spin_unlock_irqrestore(&d40c->lock, flags);
1078
1079 return tx->cookie;
1080 }
1081
1082 static int d40_start(struct d40_chan *d40c)
1083 {
1084 if (d40c->base->rev == 0) {
1085 int err;
1086
1087 if (chan_is_logical(d40c)) {
1088 err = d40_channel_execute_command(d40c,
1089 D40_DMA_SUSPEND_REQ);
1090 if (err)
1091 return err;
1092 }
1093 }
1094
1095 if (chan_is_logical(d40c))
1096 d40_config_set_event(d40c, true);
1097
1098 return d40_channel_execute_command(d40c, D40_DMA_RUN);
1099 }
1100
1101 static struct d40_desc *d40_queue_start(struct d40_chan *d40c)
1102 {
1103 struct d40_desc *d40d;
1104 int err;
1105
1106 /* Start queued jobs, if any */
1107 d40d = d40_first_queued(d40c);
1108
1109 if (d40d != NULL) {
1110 d40c->busy = true;
1111
1112 /* Remove from queue */
1113 d40_desc_remove(d40d);
1114
1115 /* Add to active queue */
1116 d40_desc_submit(d40c, d40d);
1117
1118 /* Initiate DMA job */
1119 d40_desc_load(d40c, d40d);
1120
1121 /* Start dma job */
1122 err = d40_start(d40c);
1123
1124 if (err)
1125 return NULL;
1126 }
1127
1128 return d40d;
1129 }
1130
1131 /* called from interrupt context */
1132 static void dma_tc_handle(struct d40_chan *d40c)
1133 {
1134 struct d40_desc *d40d;
1135
1136 /* Get first active entry from list */
1137 d40d = d40_first_active_get(d40c);
1138
1139 if (d40d == NULL)
1140 return;
1141
1142 if (d40d->cyclic) {
1143 /*
1144 * If this was a paritially loaded list, we need to reloaded
1145 * it, and only when the list is completed. We need to check
1146 * for done because the interrupt will hit for every link, and
1147 * not just the last one.
1148 */
1149 if (d40d->lli_current < d40d->lli_len
1150 && !d40_tx_is_linked(d40c)
1151 && !d40_residue(d40c)) {
1152 d40_lcla_free_all(d40c, d40d);
1153 d40_desc_load(d40c, d40d);
1154 (void) d40_start(d40c);
1155
1156 if (d40d->lli_current == d40d->lli_len)
1157 d40d->lli_current = 0;
1158 }
1159 } else {
1160 d40_lcla_free_all(d40c, d40d);
1161
1162 if (d40d->lli_current < d40d->lli_len) {
1163 d40_desc_load(d40c, d40d);
1164 /* Start dma job */
1165 (void) d40_start(d40c);
1166 return;
1167 }
1168
1169 if (d40_queue_start(d40c) == NULL)
1170 d40c->busy = false;
1171 }
1172
1173 d40c->pending_tx++;
1174 tasklet_schedule(&d40c->tasklet);
1175
1176 }
1177
1178 static void dma_tasklet(unsigned long data)
1179 {
1180 struct d40_chan *d40c = (struct d40_chan *) data;
1181 struct d40_desc *d40d;
1182 unsigned long flags;
1183 dma_async_tx_callback callback;
1184 void *callback_param;
1185
1186 spin_lock_irqsave(&d40c->lock, flags);
1187
1188 /* Get first active entry from list */
1189 d40d = d40_first_active_get(d40c);
1190 if (d40d == NULL)
1191 goto err;
1192
1193 if (!d40d->cyclic)
1194 d40c->completed = d40d->txd.cookie;
1195
1196 /*
1197 * If terminating a channel pending_tx is set to zero.
1198 * This prevents any finished active jobs to return to the client.
1199 */
1200 if (d40c->pending_tx == 0) {
1201 spin_unlock_irqrestore(&d40c->lock, flags);
1202 return;
1203 }
1204
1205 /* Callback to client */
1206 callback = d40d->txd.callback;
1207 callback_param = d40d->txd.callback_param;
1208
1209 if (!d40d->cyclic) {
1210 if (async_tx_test_ack(&d40d->txd)) {
1211 d40_pool_lli_free(d40c, d40d);
1212 d40_desc_remove(d40d);
1213 d40_desc_free(d40c, d40d);
1214 } else {
1215 if (!d40d->is_in_client_list) {
1216 d40_desc_remove(d40d);
1217 d40_lcla_free_all(d40c, d40d);
1218 list_add_tail(&d40d->node, &d40c->client);
1219 d40d->is_in_client_list = true;
1220 }
1221 }
1222 }
1223
1224 d40c->pending_tx--;
1225
1226 if (d40c->pending_tx)
1227 tasklet_schedule(&d40c->tasklet);
1228
1229 spin_unlock_irqrestore(&d40c->lock, flags);
1230
1231 if (callback && (d40d->txd.flags & DMA_PREP_INTERRUPT))
1232 callback(callback_param);
1233
1234 return;
1235
1236 err:
1237 /* Rescue manoeuvre if receiving double interrupts */
1238 if (d40c->pending_tx > 0)
1239 d40c->pending_tx--;
1240 spin_unlock_irqrestore(&d40c->lock, flags);
1241 }
1242
1243 static irqreturn_t d40_handle_interrupt(int irq, void *data)
1244 {
1245 static const struct d40_interrupt_lookup il[] = {
1246 {D40_DREG_LCTIS0, D40_DREG_LCICR0, false, 0},
1247 {D40_DREG_LCTIS1, D40_DREG_LCICR1, false, 32},
1248 {D40_DREG_LCTIS2, D40_DREG_LCICR2, false, 64},
1249 {D40_DREG_LCTIS3, D40_DREG_LCICR3, false, 96},
1250 {D40_DREG_LCEIS0, D40_DREG_LCICR0, true, 0},
1251 {D40_DREG_LCEIS1, D40_DREG_LCICR1, true, 32},
1252 {D40_DREG_LCEIS2, D40_DREG_LCICR2, true, 64},
1253 {D40_DREG_LCEIS3, D40_DREG_LCICR3, true, 96},
1254 {D40_DREG_PCTIS, D40_DREG_PCICR, false, D40_PHY_CHAN},
1255 {D40_DREG_PCEIS, D40_DREG_PCICR, true, D40_PHY_CHAN},
1256 };
1257
1258 int i;
1259 u32 regs[ARRAY_SIZE(il)];
1260 u32 idx;
1261 u32 row;
1262 long chan = -1;
1263 struct d40_chan *d40c;
1264 unsigned long flags;
1265 struct d40_base *base = data;
1266
1267 spin_lock_irqsave(&base->interrupt_lock, flags);
1268
1269 /* Read interrupt status of both logical and physical channels */
1270 for (i = 0; i < ARRAY_SIZE(il); i++)
1271 regs[i] = readl(base->virtbase + il[i].src);
1272
1273 for (;;) {
1274
1275 chan = find_next_bit((unsigned long *)regs,
1276 BITS_PER_LONG * ARRAY_SIZE(il), chan + 1);
1277
1278 /* No more set bits found? */
1279 if (chan == BITS_PER_LONG * ARRAY_SIZE(il))
1280 break;
1281
1282 row = chan / BITS_PER_LONG;
1283 idx = chan & (BITS_PER_LONG - 1);
1284
1285 /* ACK interrupt */
1286 writel(1 << idx, base->virtbase + il[row].clr);
1287
1288 if (il[row].offset == D40_PHY_CHAN)
1289 d40c = base->lookup_phy_chans[idx];
1290 else
1291 d40c = base->lookup_log_chans[il[row].offset + idx];
1292 spin_lock(&d40c->lock);
1293
1294 if (!il[row].is_error)
1295 dma_tc_handle(d40c);
1296 else
1297 d40_err(base->dev, "IRQ chan: %ld offset %d idx %d\n",
1298 chan, il[row].offset, idx);
1299
1300 spin_unlock(&d40c->lock);
1301 }
1302
1303 spin_unlock_irqrestore(&base->interrupt_lock, flags);
1304
1305 return IRQ_HANDLED;
1306 }
1307
1308 static int d40_validate_conf(struct d40_chan *d40c,
1309 struct stedma40_chan_cfg *conf)
1310 {
1311 int res = 0;
1312 u32 dst_event_group = D40_TYPE_TO_GROUP(conf->dst_dev_type);
1313 u32 src_event_group = D40_TYPE_TO_GROUP(conf->src_dev_type);
1314 bool is_log = conf->mode == STEDMA40_MODE_LOGICAL;
1315
1316 if (!conf->dir) {
1317 chan_err(d40c, "Invalid direction.\n");
1318 res = -EINVAL;
1319 }
1320
1321 if (conf->dst_dev_type != STEDMA40_DEV_DST_MEMORY &&
1322 d40c->base->plat_data->dev_tx[conf->dst_dev_type] == 0 &&
1323 d40c->runtime_addr == 0) {
1324
1325 chan_err(d40c, "Invalid TX channel address (%d)\n",
1326 conf->dst_dev_type);
1327 res = -EINVAL;
1328 }
1329
1330 if (conf->src_dev_type != STEDMA40_DEV_SRC_MEMORY &&
1331 d40c->base->plat_data->dev_rx[conf->src_dev_type] == 0 &&
1332 d40c->runtime_addr == 0) {
1333 chan_err(d40c, "Invalid RX channel address (%d)\n",
1334 conf->src_dev_type);
1335 res = -EINVAL;
1336 }
1337
1338 if (conf->dir == STEDMA40_MEM_TO_PERIPH &&
1339 dst_event_group == STEDMA40_DEV_DST_MEMORY) {
1340 chan_err(d40c, "Invalid dst\n");
1341 res = -EINVAL;
1342 }
1343
1344 if (conf->dir == STEDMA40_PERIPH_TO_MEM &&
1345 src_event_group == STEDMA40_DEV_SRC_MEMORY) {
1346 chan_err(d40c, "Invalid src\n");
1347 res = -EINVAL;
1348 }
1349
1350 if (src_event_group == STEDMA40_DEV_SRC_MEMORY &&
1351 dst_event_group == STEDMA40_DEV_DST_MEMORY && is_log) {
1352 chan_err(d40c, "No event line\n");
1353 res = -EINVAL;
1354 }
1355
1356 if (conf->dir == STEDMA40_PERIPH_TO_PERIPH &&
1357 (src_event_group != dst_event_group)) {
1358 chan_err(d40c, "Invalid event group\n");
1359 res = -EINVAL;
1360 }
1361
1362 if (conf->dir == STEDMA40_PERIPH_TO_PERIPH) {
1363 /*
1364 * DMAC HW supports it. Will be added to this driver,
1365 * in case any dma client requires it.
1366 */
1367 chan_err(d40c, "periph to periph not supported\n");
1368 res = -EINVAL;
1369 }
1370
1371 if (d40_psize_2_burst_size(is_log, conf->src_info.psize) *
1372 (1 << conf->src_info.data_width) !=
1373 d40_psize_2_burst_size(is_log, conf->dst_info.psize) *
1374 (1 << conf->dst_info.data_width)) {
1375 /*
1376 * The DMAC hardware only supports
1377 * src (burst x width) == dst (burst x width)
1378 */
1379
1380 chan_err(d40c, "src (burst x width) != dst (burst x width)\n");
1381 res = -EINVAL;
1382 }
1383
1384 return res;
1385 }
1386
1387 static bool d40_alloc_mask_set(struct d40_phy_res *phy, bool is_src,
1388 int log_event_line, bool is_log)
1389 {
1390 unsigned long flags;
1391 spin_lock_irqsave(&phy->lock, flags);
1392 if (!is_log) {
1393 /* Physical interrupts are masked per physical full channel */
1394 if (phy->allocated_src == D40_ALLOC_FREE &&
1395 phy->allocated_dst == D40_ALLOC_FREE) {
1396 phy->allocated_dst = D40_ALLOC_PHY;
1397 phy->allocated_src = D40_ALLOC_PHY;
1398 goto found;
1399 } else
1400 goto not_found;
1401 }
1402
1403 /* Logical channel */
1404 if (is_src) {
1405 if (phy->allocated_src == D40_ALLOC_PHY)
1406 goto not_found;
1407
1408 if (phy->allocated_src == D40_ALLOC_FREE)
1409 phy->allocated_src = D40_ALLOC_LOG_FREE;
1410
1411 if (!(phy->allocated_src & (1 << log_event_line))) {
1412 phy->allocated_src |= 1 << log_event_line;
1413 goto found;
1414 } else
1415 goto not_found;
1416 } else {
1417 if (phy->allocated_dst == D40_ALLOC_PHY)
1418 goto not_found;
1419
1420 if (phy->allocated_dst == D40_ALLOC_FREE)
1421 phy->allocated_dst = D40_ALLOC_LOG_FREE;
1422
1423 if (!(phy->allocated_dst & (1 << log_event_line))) {
1424 phy->allocated_dst |= 1 << log_event_line;
1425 goto found;
1426 } else
1427 goto not_found;
1428 }
1429
1430 not_found:
1431 spin_unlock_irqrestore(&phy->lock, flags);
1432 return false;
1433 found:
1434 spin_unlock_irqrestore(&phy->lock, flags);
1435 return true;
1436 }
1437
1438 static bool d40_alloc_mask_free(struct d40_phy_res *phy, bool is_src,
1439 int log_event_line)
1440 {
1441 unsigned long flags;
1442 bool is_free = false;
1443
1444 spin_lock_irqsave(&phy->lock, flags);
1445 if (!log_event_line) {
1446 phy->allocated_dst = D40_ALLOC_FREE;
1447 phy->allocated_src = D40_ALLOC_FREE;
1448 is_free = true;
1449 goto out;
1450 }
1451
1452 /* Logical channel */
1453 if (is_src) {
1454 phy->allocated_src &= ~(1 << log_event_line);
1455 if (phy->allocated_src == D40_ALLOC_LOG_FREE)
1456 phy->allocated_src = D40_ALLOC_FREE;
1457 } else {
1458 phy->allocated_dst &= ~(1 << log_event_line);
1459 if (phy->allocated_dst == D40_ALLOC_LOG_FREE)
1460 phy->allocated_dst = D40_ALLOC_FREE;
1461 }
1462
1463 is_free = ((phy->allocated_src | phy->allocated_dst) ==
1464 D40_ALLOC_FREE);
1465
1466 out:
1467 spin_unlock_irqrestore(&phy->lock, flags);
1468
1469 return is_free;
1470 }
1471
1472 static int d40_allocate_channel(struct d40_chan *d40c)
1473 {
1474 int dev_type;
1475 int event_group;
1476 int event_line;
1477 struct d40_phy_res *phys;
1478 int i;
1479 int j;
1480 int log_num;
1481 bool is_src;
1482 bool is_log = d40c->dma_cfg.mode == STEDMA40_MODE_LOGICAL;
1483
1484 phys = d40c->base->phy_res;
1485
1486 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1487 dev_type = d40c->dma_cfg.src_dev_type;
1488 log_num = 2 * dev_type;
1489 is_src = true;
1490 } else if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1491 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1492 /* dst event lines are used for logical memcpy */
1493 dev_type = d40c->dma_cfg.dst_dev_type;
1494 log_num = 2 * dev_type + 1;
1495 is_src = false;
1496 } else
1497 return -EINVAL;
1498
1499 event_group = D40_TYPE_TO_GROUP(dev_type);
1500 event_line = D40_TYPE_TO_EVENT(dev_type);
1501
1502 if (!is_log) {
1503 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1504 /* Find physical half channel */
1505 for (i = 0; i < d40c->base->num_phy_chans; i++) {
1506
1507 if (d40_alloc_mask_set(&phys[i], is_src,
1508 0, is_log))
1509 goto found_phy;
1510 }
1511 } else
1512 for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1513 int phy_num = j + event_group * 2;
1514 for (i = phy_num; i < phy_num + 2; i++) {
1515 if (d40_alloc_mask_set(&phys[i],
1516 is_src,
1517 0,
1518 is_log))
1519 goto found_phy;
1520 }
1521 }
1522 return -EINVAL;
1523 found_phy:
1524 d40c->phy_chan = &phys[i];
1525 d40c->log_num = D40_PHY_CHAN;
1526 goto out;
1527 }
1528 if (dev_type == -1)
1529 return -EINVAL;
1530
1531 /* Find logical channel */
1532 for (j = 0; j < d40c->base->num_phy_chans; j += 8) {
1533 int phy_num = j + event_group * 2;
1534 /*
1535 * Spread logical channels across all available physical rather
1536 * than pack every logical channel at the first available phy
1537 * channels.
1538 */
1539 if (is_src) {
1540 for (i = phy_num; i < phy_num + 2; i++) {
1541 if (d40_alloc_mask_set(&phys[i], is_src,
1542 event_line, is_log))
1543 goto found_log;
1544 }
1545 } else {
1546 for (i = phy_num + 1; i >= phy_num; i--) {
1547 if (d40_alloc_mask_set(&phys[i], is_src,
1548 event_line, is_log))
1549 goto found_log;
1550 }
1551 }
1552 }
1553 return -EINVAL;
1554
1555 found_log:
1556 d40c->phy_chan = &phys[i];
1557 d40c->log_num = log_num;
1558 out:
1559
1560 if (is_log)
1561 d40c->base->lookup_log_chans[d40c->log_num] = d40c;
1562 else
1563 d40c->base->lookup_phy_chans[d40c->phy_chan->num] = d40c;
1564
1565 return 0;
1566
1567 }
1568
1569 static int d40_config_memcpy(struct d40_chan *d40c)
1570 {
1571 dma_cap_mask_t cap = d40c->chan.device->cap_mask;
1572
1573 if (dma_has_cap(DMA_MEMCPY, cap) && !dma_has_cap(DMA_SLAVE, cap)) {
1574 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_log;
1575 d40c->dma_cfg.src_dev_type = STEDMA40_DEV_SRC_MEMORY;
1576 d40c->dma_cfg.dst_dev_type = d40c->base->plat_data->
1577 memcpy[d40c->chan.chan_id];
1578
1579 } else if (dma_has_cap(DMA_MEMCPY, cap) &&
1580 dma_has_cap(DMA_SLAVE, cap)) {
1581 d40c->dma_cfg = *d40c->base->plat_data->memcpy_conf_phy;
1582 } else {
1583 chan_err(d40c, "No memcpy\n");
1584 return -EINVAL;
1585 }
1586
1587 return 0;
1588 }
1589
1590
1591 static int d40_free_dma(struct d40_chan *d40c)
1592 {
1593
1594 int res = 0;
1595 u32 event;
1596 struct d40_phy_res *phy = d40c->phy_chan;
1597 bool is_src;
1598 struct d40_desc *d;
1599 struct d40_desc *_d;
1600
1601
1602 /* Terminate all queued and active transfers */
1603 d40_term_all(d40c);
1604
1605 /* Release client owned descriptors */
1606 if (!list_empty(&d40c->client))
1607 list_for_each_entry_safe(d, _d, &d40c->client, node) {
1608 d40_pool_lli_free(d40c, d);
1609 d40_desc_remove(d);
1610 d40_desc_free(d40c, d);
1611 }
1612
1613 if (phy == NULL) {
1614 chan_err(d40c, "phy == null\n");
1615 return -EINVAL;
1616 }
1617
1618 if (phy->allocated_src == D40_ALLOC_FREE &&
1619 phy->allocated_dst == D40_ALLOC_FREE) {
1620 chan_err(d40c, "channel already free\n");
1621 return -EINVAL;
1622 }
1623
1624 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1625 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1626 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
1627 is_src = false;
1628 } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1629 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
1630 is_src = true;
1631 } else {
1632 chan_err(d40c, "Unknown direction\n");
1633 return -EINVAL;
1634 }
1635
1636 res = d40_channel_execute_command(d40c, D40_DMA_SUSPEND_REQ);
1637 if (res) {
1638 chan_err(d40c, "suspend failed\n");
1639 return res;
1640 }
1641
1642 if (chan_is_logical(d40c)) {
1643 /* Release logical channel, deactivate the event line */
1644
1645 d40_config_set_event(d40c, false);
1646 d40c->base->lookup_log_chans[d40c->log_num] = NULL;
1647
1648 /*
1649 * Check if there are more logical allocation
1650 * on this phy channel.
1651 */
1652 if (!d40_alloc_mask_free(phy, is_src, event)) {
1653 /* Resume the other logical channels if any */
1654 if (d40_chan_has_events(d40c)) {
1655 res = d40_channel_execute_command(d40c,
1656 D40_DMA_RUN);
1657 if (res) {
1658 chan_err(d40c,
1659 "Executing RUN command\n");
1660 return res;
1661 }
1662 }
1663 return 0;
1664 }
1665 } else {
1666 (void) d40_alloc_mask_free(phy, is_src, 0);
1667 }
1668
1669 /* Release physical channel */
1670 res = d40_channel_execute_command(d40c, D40_DMA_STOP);
1671 if (res) {
1672 chan_err(d40c, "Failed to stop channel\n");
1673 return res;
1674 }
1675 d40c->phy_chan = NULL;
1676 d40c->configured = false;
1677 d40c->base->lookup_phy_chans[phy->num] = NULL;
1678
1679 return 0;
1680 }
1681
1682 static bool d40_is_paused(struct d40_chan *d40c)
1683 {
1684 void __iomem *chanbase = chan_base(d40c);
1685 bool is_paused = false;
1686 unsigned long flags;
1687 void __iomem *active_reg;
1688 u32 status;
1689 u32 event;
1690
1691 spin_lock_irqsave(&d40c->lock, flags);
1692
1693 if (chan_is_physical(d40c)) {
1694 if (d40c->phy_chan->num % 2 == 0)
1695 active_reg = d40c->base->virtbase + D40_DREG_ACTIVE;
1696 else
1697 active_reg = d40c->base->virtbase + D40_DREG_ACTIVO;
1698
1699 status = (readl(active_reg) &
1700 D40_CHAN_POS_MASK(d40c->phy_chan->num)) >>
1701 D40_CHAN_POS(d40c->phy_chan->num);
1702 if (status == D40_DMA_SUSPENDED || status == D40_DMA_STOP)
1703 is_paused = true;
1704
1705 goto _exit;
1706 }
1707
1708 if (d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH ||
1709 d40c->dma_cfg.dir == STEDMA40_MEM_TO_MEM) {
1710 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.dst_dev_type);
1711 status = readl(chanbase + D40_CHAN_REG_SDLNK);
1712 } else if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) {
1713 event = D40_TYPE_TO_EVENT(d40c->dma_cfg.src_dev_type);
1714 status = readl(chanbase + D40_CHAN_REG_SSLNK);
1715 } else {
1716 chan_err(d40c, "Unknown direction\n");
1717 goto _exit;
1718 }
1719
1720 status = (status & D40_EVENTLINE_MASK(event)) >>
1721 D40_EVENTLINE_POS(event);
1722
1723 if (status != D40_DMA_RUN)
1724 is_paused = true;
1725 _exit:
1726 spin_unlock_irqrestore(&d40c->lock, flags);
1727 return is_paused;
1728
1729 }
1730
1731
1732 static u32 stedma40_residue(struct dma_chan *chan)
1733 {
1734 struct d40_chan *d40c =
1735 container_of(chan, struct d40_chan, chan);
1736 u32 bytes_left;
1737 unsigned long flags;
1738
1739 spin_lock_irqsave(&d40c->lock, flags);
1740 bytes_left = d40_residue(d40c);
1741 spin_unlock_irqrestore(&d40c->lock, flags);
1742
1743 return bytes_left;
1744 }
1745
1746 static int
1747 d40_prep_sg_log(struct d40_chan *chan, struct d40_desc *desc,
1748 struct scatterlist *sg_src, struct scatterlist *sg_dst,
1749 unsigned int sg_len, dma_addr_t src_dev_addr,
1750 dma_addr_t dst_dev_addr)
1751 {
1752 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
1753 struct stedma40_half_channel_info *src_info = &cfg->src_info;
1754 struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
1755 int ret;
1756
1757 ret = d40_log_sg_to_lli(sg_src, sg_len,
1758 src_dev_addr,
1759 desc->lli_log.src,
1760 chan->log_def.lcsp1,
1761 src_info->data_width,
1762 dst_info->data_width);
1763
1764 ret = d40_log_sg_to_lli(sg_dst, sg_len,
1765 dst_dev_addr,
1766 desc->lli_log.dst,
1767 chan->log_def.lcsp3,
1768 dst_info->data_width,
1769 src_info->data_width);
1770
1771 return ret < 0 ? ret : 0;
1772 }
1773
1774 static int
1775 d40_prep_sg_phy(struct d40_chan *chan, struct d40_desc *desc,
1776 struct scatterlist *sg_src, struct scatterlist *sg_dst,
1777 unsigned int sg_len, dma_addr_t src_dev_addr,
1778 dma_addr_t dst_dev_addr)
1779 {
1780 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
1781 struct stedma40_half_channel_info *src_info = &cfg->src_info;
1782 struct stedma40_half_channel_info *dst_info = &cfg->dst_info;
1783 unsigned long flags = 0;
1784 int ret;
1785
1786 if (desc->cyclic)
1787 flags |= LLI_CYCLIC | LLI_TERM_INT;
1788
1789 ret = d40_phy_sg_to_lli(sg_src, sg_len, src_dev_addr,
1790 desc->lli_phy.src,
1791 virt_to_phys(desc->lli_phy.src),
1792 chan->src_def_cfg,
1793 src_info, dst_info, flags);
1794
1795 ret = d40_phy_sg_to_lli(sg_dst, sg_len, dst_dev_addr,
1796 desc->lli_phy.dst,
1797 virt_to_phys(desc->lli_phy.dst),
1798 chan->dst_def_cfg,
1799 dst_info, src_info, flags);
1800
1801 dma_sync_single_for_device(chan->base->dev, desc->lli_pool.dma_addr,
1802 desc->lli_pool.size, DMA_TO_DEVICE);
1803
1804 return ret < 0 ? ret : 0;
1805 }
1806
1807
1808 static struct d40_desc *
1809 d40_prep_desc(struct d40_chan *chan, struct scatterlist *sg,
1810 unsigned int sg_len, unsigned long dma_flags)
1811 {
1812 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
1813 struct d40_desc *desc;
1814 int ret;
1815
1816 desc = d40_desc_get(chan);
1817 if (!desc)
1818 return NULL;
1819
1820 desc->lli_len = d40_sg_2_dmalen(sg, sg_len, cfg->src_info.data_width,
1821 cfg->dst_info.data_width);
1822 if (desc->lli_len < 0) {
1823 chan_err(chan, "Unaligned size\n");
1824 goto err;
1825 }
1826
1827 ret = d40_pool_lli_alloc(chan, desc, desc->lli_len);
1828 if (ret < 0) {
1829 chan_err(chan, "Could not allocate lli\n");
1830 goto err;
1831 }
1832
1833
1834 desc->lli_current = 0;
1835 desc->txd.flags = dma_flags;
1836 desc->txd.tx_submit = d40_tx_submit;
1837
1838 dma_async_tx_descriptor_init(&desc->txd, &chan->chan);
1839
1840 return desc;
1841
1842 err:
1843 d40_desc_free(chan, desc);
1844 return NULL;
1845 }
1846
1847 static dma_addr_t
1848 d40_get_dev_addr(struct d40_chan *chan, enum dma_data_direction direction)
1849 {
1850 struct stedma40_platform_data *plat = chan->base->plat_data;
1851 struct stedma40_chan_cfg *cfg = &chan->dma_cfg;
1852 dma_addr_t addr = 0;
1853
1854 if (chan->runtime_addr)
1855 return chan->runtime_addr;
1856
1857 if (direction == DMA_FROM_DEVICE)
1858 addr = plat->dev_rx[cfg->src_dev_type];
1859 else if (direction == DMA_TO_DEVICE)
1860 addr = plat->dev_tx[cfg->dst_dev_type];
1861
1862 return addr;
1863 }
1864
1865 static struct dma_async_tx_descriptor *
1866 d40_prep_sg(struct dma_chan *dchan, struct scatterlist *sg_src,
1867 struct scatterlist *sg_dst, unsigned int sg_len,
1868 enum dma_data_direction direction, unsigned long dma_flags)
1869 {
1870 struct d40_chan *chan = container_of(dchan, struct d40_chan, chan);
1871 dma_addr_t src_dev_addr = 0;
1872 dma_addr_t dst_dev_addr = 0;
1873 struct d40_desc *desc;
1874 unsigned long flags;
1875 int ret;
1876
1877 if (!chan->phy_chan) {
1878 chan_err(chan, "Cannot prepare unallocated channel\n");
1879 return NULL;
1880 }
1881
1882
1883 spin_lock_irqsave(&chan->lock, flags);
1884
1885 desc = d40_prep_desc(chan, sg_src, sg_len, dma_flags);
1886 if (desc == NULL)
1887 goto err;
1888
1889 if (sg_next(&sg_src[sg_len - 1]) == sg_src)
1890 desc->cyclic = true;
1891
1892 if (direction != DMA_NONE) {
1893 dma_addr_t dev_addr = d40_get_dev_addr(chan, direction);
1894
1895 if (direction == DMA_FROM_DEVICE)
1896 src_dev_addr = dev_addr;
1897 else if (direction == DMA_TO_DEVICE)
1898 dst_dev_addr = dev_addr;
1899 }
1900
1901 if (chan_is_logical(chan))
1902 ret = d40_prep_sg_log(chan, desc, sg_src, sg_dst,
1903 sg_len, src_dev_addr, dst_dev_addr);
1904 else
1905 ret = d40_prep_sg_phy(chan, desc, sg_src, sg_dst,
1906 sg_len, src_dev_addr, dst_dev_addr);
1907
1908 if (ret) {
1909 chan_err(chan, "Failed to prepare %s sg job: %d\n",
1910 chan_is_logical(chan) ? "log" : "phy", ret);
1911 goto err;
1912 }
1913
1914 spin_unlock_irqrestore(&chan->lock, flags);
1915
1916 return &desc->txd;
1917
1918 err:
1919 if (desc)
1920 d40_desc_free(chan, desc);
1921 spin_unlock_irqrestore(&chan->lock, flags);
1922 return NULL;
1923 }
1924
1925 bool stedma40_filter(struct dma_chan *chan, void *data)
1926 {
1927 struct stedma40_chan_cfg *info = data;
1928 struct d40_chan *d40c =
1929 container_of(chan, struct d40_chan, chan);
1930 int err;
1931
1932 if (data) {
1933 err = d40_validate_conf(d40c, info);
1934 if (!err)
1935 d40c->dma_cfg = *info;
1936 } else
1937 err = d40_config_memcpy(d40c);
1938
1939 if (!err)
1940 d40c->configured = true;
1941
1942 return err == 0;
1943 }
1944 EXPORT_SYMBOL(stedma40_filter);
1945
1946 static void __d40_set_prio_rt(struct d40_chan *d40c, int dev_type, bool src)
1947 {
1948 bool realtime = d40c->dma_cfg.realtime;
1949 bool highprio = d40c->dma_cfg.high_priority;
1950 u32 prioreg = highprio ? D40_DREG_PSEG1 : D40_DREG_PCEG1;
1951 u32 rtreg = realtime ? D40_DREG_RSEG1 : D40_DREG_RCEG1;
1952 u32 event = D40_TYPE_TO_EVENT(dev_type);
1953 u32 group = D40_TYPE_TO_GROUP(dev_type);
1954 u32 bit = 1 << event;
1955
1956 /* Destination event lines are stored in the upper halfword */
1957 if (!src)
1958 bit <<= 16;
1959
1960 writel(bit, d40c->base->virtbase + prioreg + group * 4);
1961 writel(bit, d40c->base->virtbase + rtreg + group * 4);
1962 }
1963
1964 static void d40_set_prio_realtime(struct d40_chan *d40c)
1965 {
1966 if (d40c->base->rev < 3)
1967 return;
1968
1969 if ((d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM) ||
1970 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
1971 __d40_set_prio_rt(d40c, d40c->dma_cfg.src_dev_type, true);
1972
1973 if ((d40c->dma_cfg.dir == STEDMA40_MEM_TO_PERIPH) ||
1974 (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_PERIPH))
1975 __d40_set_prio_rt(d40c, d40c->dma_cfg.dst_dev_type, false);
1976 }
1977
1978 /* DMA ENGINE functions */
1979 static int d40_alloc_chan_resources(struct dma_chan *chan)
1980 {
1981 int err;
1982 unsigned long flags;
1983 struct d40_chan *d40c =
1984 container_of(chan, struct d40_chan, chan);
1985 bool is_free_phy;
1986 spin_lock_irqsave(&d40c->lock, flags);
1987
1988 d40c->completed = chan->cookie = 1;
1989
1990 /* If no dma configuration is set use default configuration (memcpy) */
1991 if (!d40c->configured) {
1992 err = d40_config_memcpy(d40c);
1993 if (err) {
1994 chan_err(d40c, "Failed to configure memcpy channel\n");
1995 goto fail;
1996 }
1997 }
1998 is_free_phy = (d40c->phy_chan == NULL);
1999
2000 err = d40_allocate_channel(d40c);
2001 if (err) {
2002 chan_err(d40c, "Failed to allocate channel\n");
2003 goto fail;
2004 }
2005
2006 /* Fill in basic CFG register values */
2007 d40_phy_cfg(&d40c->dma_cfg, &d40c->src_def_cfg,
2008 &d40c->dst_def_cfg, chan_is_logical(d40c));
2009
2010 d40_set_prio_realtime(d40c);
2011
2012 if (chan_is_logical(d40c)) {
2013 d40_log_cfg(&d40c->dma_cfg,
2014 &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
2015
2016 if (d40c->dma_cfg.dir == STEDMA40_PERIPH_TO_MEM)
2017 d40c->lcpa = d40c->base->lcpa_base +
2018 d40c->dma_cfg.src_dev_type * D40_LCPA_CHAN_SIZE;
2019 else
2020 d40c->lcpa = d40c->base->lcpa_base +
2021 d40c->dma_cfg.dst_dev_type *
2022 D40_LCPA_CHAN_SIZE + D40_LCPA_CHAN_DST_DELTA;
2023 }
2024
2025 /*
2026 * Only write channel configuration to the DMA if the physical
2027 * resource is free. In case of multiple logical channels
2028 * on the same physical resource, only the first write is necessary.
2029 */
2030 if (is_free_phy)
2031 d40_config_write(d40c);
2032 fail:
2033 spin_unlock_irqrestore(&d40c->lock, flags);
2034 return err;
2035 }
2036
2037 static void d40_free_chan_resources(struct dma_chan *chan)
2038 {
2039 struct d40_chan *d40c =
2040 container_of(chan, struct d40_chan, chan);
2041 int err;
2042 unsigned long flags;
2043
2044 if (d40c->phy_chan == NULL) {
2045 chan_err(d40c, "Cannot free unallocated channel\n");
2046 return;
2047 }
2048
2049
2050 spin_lock_irqsave(&d40c->lock, flags);
2051
2052 err = d40_free_dma(d40c);
2053
2054 if (err)
2055 chan_err(d40c, "Failed to free channel\n");
2056 spin_unlock_irqrestore(&d40c->lock, flags);
2057 }
2058
2059 static struct dma_async_tx_descriptor *d40_prep_memcpy(struct dma_chan *chan,
2060 dma_addr_t dst,
2061 dma_addr_t src,
2062 size_t size,
2063 unsigned long dma_flags)
2064 {
2065 struct scatterlist dst_sg;
2066 struct scatterlist src_sg;
2067
2068 sg_init_table(&dst_sg, 1);
2069 sg_init_table(&src_sg, 1);
2070
2071 sg_dma_address(&dst_sg) = dst;
2072 sg_dma_address(&src_sg) = src;
2073
2074 sg_dma_len(&dst_sg) = size;
2075 sg_dma_len(&src_sg) = size;
2076
2077 return d40_prep_sg(chan, &src_sg, &dst_sg, 1, DMA_NONE, dma_flags);
2078 }
2079
2080 static struct dma_async_tx_descriptor *
2081 d40_prep_memcpy_sg(struct dma_chan *chan,
2082 struct scatterlist *dst_sg, unsigned int dst_nents,
2083 struct scatterlist *src_sg, unsigned int src_nents,
2084 unsigned long dma_flags)
2085 {
2086 if (dst_nents != src_nents)
2087 return NULL;
2088
2089 return d40_prep_sg(chan, src_sg, dst_sg, src_nents, DMA_NONE, dma_flags);
2090 }
2091
2092 static struct dma_async_tx_descriptor *d40_prep_slave_sg(struct dma_chan *chan,
2093 struct scatterlist *sgl,
2094 unsigned int sg_len,
2095 enum dma_data_direction direction,
2096 unsigned long dma_flags)
2097 {
2098 if (direction != DMA_FROM_DEVICE && direction != DMA_TO_DEVICE)
2099 return NULL;
2100
2101 return d40_prep_sg(chan, sgl, sgl, sg_len, direction, dma_flags);
2102 }
2103
2104 static struct dma_async_tx_descriptor *
2105 dma40_prep_dma_cyclic(struct dma_chan *chan, dma_addr_t dma_addr,
2106 size_t buf_len, size_t period_len,
2107 enum dma_data_direction direction)
2108 {
2109 unsigned int periods = buf_len / period_len;
2110 struct dma_async_tx_descriptor *txd;
2111 struct scatterlist *sg;
2112 int i;
2113
2114 sg = kcalloc(periods + 1, sizeof(struct scatterlist), GFP_NOWAIT);
2115 for (i = 0; i < periods; i++) {
2116 sg_dma_address(&sg[i]) = dma_addr;
2117 sg_dma_len(&sg[i]) = period_len;
2118 dma_addr += period_len;
2119 }
2120
2121 sg[periods].offset = 0;
2122 sg[periods].length = 0;
2123 sg[periods].page_link =
2124 ((unsigned long)sg | 0x01) & ~0x02;
2125
2126 txd = d40_prep_sg(chan, sg, sg, periods, direction,
2127 DMA_PREP_INTERRUPT);
2128
2129 kfree(sg);
2130
2131 return txd;
2132 }
2133
2134 static enum dma_status d40_tx_status(struct dma_chan *chan,
2135 dma_cookie_t cookie,
2136 struct dma_tx_state *txstate)
2137 {
2138 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2139 dma_cookie_t last_used;
2140 dma_cookie_t last_complete;
2141 int ret;
2142
2143 if (d40c->phy_chan == NULL) {
2144 chan_err(d40c, "Cannot read status of unallocated channel\n");
2145 return -EINVAL;
2146 }
2147
2148 last_complete = d40c->completed;
2149 last_used = chan->cookie;
2150
2151 if (d40_is_paused(d40c))
2152 ret = DMA_PAUSED;
2153 else
2154 ret = dma_async_is_complete(cookie, last_complete, last_used);
2155
2156 dma_set_tx_state(txstate, last_complete, last_used,
2157 stedma40_residue(chan));
2158
2159 return ret;
2160 }
2161
2162 static void d40_issue_pending(struct dma_chan *chan)
2163 {
2164 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2165 unsigned long flags;
2166
2167 if (d40c->phy_chan == NULL) {
2168 chan_err(d40c, "Channel is not allocated!\n");
2169 return;
2170 }
2171
2172 spin_lock_irqsave(&d40c->lock, flags);
2173
2174 list_splice_tail_init(&d40c->pending_queue, &d40c->queue);
2175
2176 /* Busy means that queued jobs are already being processed */
2177 if (!d40c->busy)
2178 (void) d40_queue_start(d40c);
2179
2180 spin_unlock_irqrestore(&d40c->lock, flags);
2181 }
2182
2183 static int
2184 dma40_config_to_halfchannel(struct d40_chan *d40c,
2185 struct stedma40_half_channel_info *info,
2186 enum dma_slave_buswidth width,
2187 u32 maxburst)
2188 {
2189 enum stedma40_periph_data_width addr_width;
2190 int psize;
2191
2192 switch (width) {
2193 case DMA_SLAVE_BUSWIDTH_1_BYTE:
2194 addr_width = STEDMA40_BYTE_WIDTH;
2195 break;
2196 case DMA_SLAVE_BUSWIDTH_2_BYTES:
2197 addr_width = STEDMA40_HALFWORD_WIDTH;
2198 break;
2199 case DMA_SLAVE_BUSWIDTH_4_BYTES:
2200 addr_width = STEDMA40_WORD_WIDTH;
2201 break;
2202 case DMA_SLAVE_BUSWIDTH_8_BYTES:
2203 addr_width = STEDMA40_DOUBLEWORD_WIDTH;
2204 break;
2205 default:
2206 dev_err(d40c->base->dev,
2207 "illegal peripheral address width "
2208 "requested (%d)\n",
2209 width);
2210 return -EINVAL;
2211 }
2212
2213 if (chan_is_logical(d40c)) {
2214 if (maxburst >= 16)
2215 psize = STEDMA40_PSIZE_LOG_16;
2216 else if (maxburst >= 8)
2217 psize = STEDMA40_PSIZE_LOG_8;
2218 else if (maxburst >= 4)
2219 psize = STEDMA40_PSIZE_LOG_4;
2220 else
2221 psize = STEDMA40_PSIZE_LOG_1;
2222 } else {
2223 if (maxburst >= 16)
2224 psize = STEDMA40_PSIZE_PHY_16;
2225 else if (maxburst >= 8)
2226 psize = STEDMA40_PSIZE_PHY_8;
2227 else if (maxburst >= 4)
2228 psize = STEDMA40_PSIZE_PHY_4;
2229 else
2230 psize = STEDMA40_PSIZE_PHY_1;
2231 }
2232
2233 info->data_width = addr_width;
2234 info->psize = psize;
2235 info->flow_ctrl = STEDMA40_NO_FLOW_CTRL;
2236
2237 return 0;
2238 }
2239
2240 /* Runtime reconfiguration extension */
2241 static int d40_set_runtime_config(struct dma_chan *chan,
2242 struct dma_slave_config *config)
2243 {
2244 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2245 struct stedma40_chan_cfg *cfg = &d40c->dma_cfg;
2246 enum dma_slave_buswidth src_addr_width, dst_addr_width;
2247 dma_addr_t config_addr;
2248 u32 src_maxburst, dst_maxburst;
2249 int ret;
2250
2251 src_addr_width = config->src_addr_width;
2252 src_maxburst = config->src_maxburst;
2253 dst_addr_width = config->dst_addr_width;
2254 dst_maxburst = config->dst_maxburst;
2255
2256 if (config->direction == DMA_FROM_DEVICE) {
2257 dma_addr_t dev_addr_rx =
2258 d40c->base->plat_data->dev_rx[cfg->src_dev_type];
2259
2260 config_addr = config->src_addr;
2261 if (dev_addr_rx)
2262 dev_dbg(d40c->base->dev,
2263 "channel has a pre-wired RX address %08x "
2264 "overriding with %08x\n",
2265 dev_addr_rx, config_addr);
2266 if (cfg->dir != STEDMA40_PERIPH_TO_MEM)
2267 dev_dbg(d40c->base->dev,
2268 "channel was not configured for peripheral "
2269 "to memory transfer (%d) overriding\n",
2270 cfg->dir);
2271 cfg->dir = STEDMA40_PERIPH_TO_MEM;
2272
2273 /* Configure the memory side */
2274 if (dst_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
2275 dst_addr_width = src_addr_width;
2276 if (dst_maxburst == 0)
2277 dst_maxburst = src_maxburst;
2278
2279 } else if (config->direction == DMA_TO_DEVICE) {
2280 dma_addr_t dev_addr_tx =
2281 d40c->base->plat_data->dev_tx[cfg->dst_dev_type];
2282
2283 config_addr = config->dst_addr;
2284 if (dev_addr_tx)
2285 dev_dbg(d40c->base->dev,
2286 "channel has a pre-wired TX address %08x "
2287 "overriding with %08x\n",
2288 dev_addr_tx, config_addr);
2289 if (cfg->dir != STEDMA40_MEM_TO_PERIPH)
2290 dev_dbg(d40c->base->dev,
2291 "channel was not configured for memory "
2292 "to peripheral transfer (%d) overriding\n",
2293 cfg->dir);
2294 cfg->dir = STEDMA40_MEM_TO_PERIPH;
2295
2296 /* Configure the memory side */
2297 if (src_addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
2298 src_addr_width = dst_addr_width;
2299 if (src_maxburst == 0)
2300 src_maxburst = dst_maxburst;
2301 } else {
2302 dev_err(d40c->base->dev,
2303 "unrecognized channel direction %d\n",
2304 config->direction);
2305 return -EINVAL;
2306 }
2307
2308 if (src_maxburst * src_addr_width != dst_maxburst * dst_addr_width) {
2309 dev_err(d40c->base->dev,
2310 "src/dst width/maxburst mismatch: %d*%d != %d*%d\n",
2311 src_maxburst,
2312 src_addr_width,
2313 dst_maxburst,
2314 dst_addr_width);
2315 return -EINVAL;
2316 }
2317
2318 ret = dma40_config_to_halfchannel(d40c, &cfg->src_info,
2319 src_addr_width,
2320 src_maxburst);
2321 if (ret)
2322 return ret;
2323
2324 ret = dma40_config_to_halfchannel(d40c, &cfg->dst_info,
2325 dst_addr_width,
2326 dst_maxburst);
2327 if (ret)
2328 return ret;
2329
2330 /* Fill in register values */
2331 if (chan_is_logical(d40c))
2332 d40_log_cfg(cfg, &d40c->log_def.lcsp1, &d40c->log_def.lcsp3);
2333 else
2334 d40_phy_cfg(cfg, &d40c->src_def_cfg,
2335 &d40c->dst_def_cfg, false);
2336
2337 /* These settings will take precedence later */
2338 d40c->runtime_addr = config_addr;
2339 d40c->runtime_direction = config->direction;
2340 dev_dbg(d40c->base->dev,
2341 "configured channel %s for %s, data width %d/%d, "
2342 "maxburst %d/%d elements, LE, no flow control\n",
2343 dma_chan_name(chan),
2344 (config->direction == DMA_FROM_DEVICE) ? "RX" : "TX",
2345 src_addr_width, dst_addr_width,
2346 src_maxburst, dst_maxburst);
2347
2348 return 0;
2349 }
2350
2351 static int d40_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
2352 unsigned long arg)
2353 {
2354 struct d40_chan *d40c = container_of(chan, struct d40_chan, chan);
2355
2356 if (d40c->phy_chan == NULL) {
2357 chan_err(d40c, "Channel is not allocated!\n");
2358 return -EINVAL;
2359 }
2360
2361 switch (cmd) {
2362 case DMA_TERMINATE_ALL:
2363 return d40_terminate_all(d40c);
2364 case DMA_PAUSE:
2365 return d40_pause(d40c);
2366 case DMA_RESUME:
2367 return d40_resume(d40c);
2368 case DMA_SLAVE_CONFIG:
2369 return d40_set_runtime_config(chan,
2370 (struct dma_slave_config *) arg);
2371 default:
2372 break;
2373 }
2374
2375 /* Other commands are unimplemented */
2376 return -ENXIO;
2377 }
2378
2379 /* Initialization functions */
2380
2381 static void __init d40_chan_init(struct d40_base *base, struct dma_device *dma,
2382 struct d40_chan *chans, int offset,
2383 int num_chans)
2384 {
2385 int i = 0;
2386 struct d40_chan *d40c;
2387
2388 INIT_LIST_HEAD(&dma->channels);
2389
2390 for (i = offset; i < offset + num_chans; i++) {
2391 d40c = &chans[i];
2392 d40c->base = base;
2393 d40c->chan.device = dma;
2394
2395 spin_lock_init(&d40c->lock);
2396
2397 d40c->log_num = D40_PHY_CHAN;
2398
2399 INIT_LIST_HEAD(&d40c->active);
2400 INIT_LIST_HEAD(&d40c->queue);
2401 INIT_LIST_HEAD(&d40c->pending_queue);
2402 INIT_LIST_HEAD(&d40c->client);
2403
2404 tasklet_init(&d40c->tasklet, dma_tasklet,
2405 (unsigned long) d40c);
2406
2407 list_add_tail(&d40c->chan.device_node,
2408 &dma->channels);
2409 }
2410 }
2411
2412 static void d40_ops_init(struct d40_base *base, struct dma_device *dev)
2413 {
2414 if (dma_has_cap(DMA_SLAVE, dev->cap_mask))
2415 dev->device_prep_slave_sg = d40_prep_slave_sg;
2416
2417 if (dma_has_cap(DMA_MEMCPY, dev->cap_mask)) {
2418 dev->device_prep_dma_memcpy = d40_prep_memcpy;
2419
2420 /*
2421 * This controller can only access address at even
2422 * 32bit boundaries, i.e. 2^2
2423 */
2424 dev->copy_align = 2;
2425 }
2426
2427 if (dma_has_cap(DMA_SG, dev->cap_mask))
2428 dev->device_prep_dma_sg = d40_prep_memcpy_sg;
2429
2430 if (dma_has_cap(DMA_CYCLIC, dev->cap_mask))
2431 dev->device_prep_dma_cyclic = dma40_prep_dma_cyclic;
2432
2433 dev->device_alloc_chan_resources = d40_alloc_chan_resources;
2434 dev->device_free_chan_resources = d40_free_chan_resources;
2435 dev->device_issue_pending = d40_issue_pending;
2436 dev->device_tx_status = d40_tx_status;
2437 dev->device_control = d40_control;
2438 dev->dev = base->dev;
2439 }
2440
2441 static int __init d40_dmaengine_init(struct d40_base *base,
2442 int num_reserved_chans)
2443 {
2444 int err ;
2445
2446 d40_chan_init(base, &base->dma_slave, base->log_chans,
2447 0, base->num_log_chans);
2448
2449 dma_cap_zero(base->dma_slave.cap_mask);
2450 dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
2451 dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask);
2452
2453 d40_ops_init(base, &base->dma_slave);
2454
2455 err = dma_async_device_register(&base->dma_slave);
2456
2457 if (err) {
2458 d40_err(base->dev, "Failed to register slave channels\n");
2459 goto failure1;
2460 }
2461
2462 d40_chan_init(base, &base->dma_memcpy, base->log_chans,
2463 base->num_log_chans, base->plat_data->memcpy_len);
2464
2465 dma_cap_zero(base->dma_memcpy.cap_mask);
2466 dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
2467 dma_cap_set(DMA_SG, base->dma_memcpy.cap_mask);
2468
2469 d40_ops_init(base, &base->dma_memcpy);
2470
2471 err = dma_async_device_register(&base->dma_memcpy);
2472
2473 if (err) {
2474 d40_err(base->dev,
2475 "Failed to regsiter memcpy only channels\n");
2476 goto failure2;
2477 }
2478
2479 d40_chan_init(base, &base->dma_both, base->phy_chans,
2480 0, num_reserved_chans);
2481
2482 dma_cap_zero(base->dma_both.cap_mask);
2483 dma_cap_set(DMA_SLAVE, base->dma_both.cap_mask);
2484 dma_cap_set(DMA_MEMCPY, base->dma_both.cap_mask);
2485 dma_cap_set(DMA_SG, base->dma_both.cap_mask);
2486 dma_cap_set(DMA_CYCLIC, base->dma_slave.cap_mask);
2487
2488 d40_ops_init(base, &base->dma_both);
2489 err = dma_async_device_register(&base->dma_both);
2490
2491 if (err) {
2492 d40_err(base->dev,
2493 "Failed to register logical and physical capable channels\n");
2494 goto failure3;
2495 }
2496 return 0;
2497 failure3:
2498 dma_async_device_unregister(&base->dma_memcpy);
2499 failure2:
2500 dma_async_device_unregister(&base->dma_slave);
2501 failure1:
2502 return err;
2503 }
2504
2505 /* Initialization functions. */
2506
2507 static int __init d40_phy_res_init(struct d40_base *base)
2508 {
2509 int i;
2510 int num_phy_chans_avail = 0;
2511 u32 val[2];
2512 int odd_even_bit = -2;
2513
2514 val[0] = readl(base->virtbase + D40_DREG_PRSME);
2515 val[1] = readl(base->virtbase + D40_DREG_PRSMO);
2516
2517 for (i = 0; i < base->num_phy_chans; i++) {
2518 base->phy_res[i].num = i;
2519 odd_even_bit += 2 * ((i % 2) == 0);
2520 if (((val[i % 2] >> odd_even_bit) & 3) == 1) {
2521 /* Mark security only channels as occupied */
2522 base->phy_res[i].allocated_src = D40_ALLOC_PHY;
2523 base->phy_res[i].allocated_dst = D40_ALLOC_PHY;
2524 } else {
2525 base->phy_res[i].allocated_src = D40_ALLOC_FREE;
2526 base->phy_res[i].allocated_dst = D40_ALLOC_FREE;
2527 num_phy_chans_avail++;
2528 }
2529 spin_lock_init(&base->phy_res[i].lock);
2530 }
2531
2532 /* Mark disabled channels as occupied */
2533 for (i = 0; base->plat_data->disabled_channels[i] != -1; i++) {
2534 int chan = base->plat_data->disabled_channels[i];
2535
2536 base->phy_res[chan].allocated_src = D40_ALLOC_PHY;
2537 base->phy_res[chan].allocated_dst = D40_ALLOC_PHY;
2538 num_phy_chans_avail--;
2539 }
2540
2541 dev_info(base->dev, "%d of %d physical DMA channels available\n",
2542 num_phy_chans_avail, base->num_phy_chans);
2543
2544 /* Verify settings extended vs standard */
2545 val[0] = readl(base->virtbase + D40_DREG_PRTYP);
2546
2547 for (i = 0; i < base->num_phy_chans; i++) {
2548
2549 if (base->phy_res[i].allocated_src == D40_ALLOC_FREE &&
2550 (val[0] & 0x3) != 1)
2551 dev_info(base->dev,
2552 "[%s] INFO: channel %d is misconfigured (%d)\n",
2553 __func__, i, val[0] & 0x3);
2554
2555 val[0] = val[0] >> 2;
2556 }
2557
2558 return num_phy_chans_avail;
2559 }
2560
2561 static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev)
2562 {
2563 struct stedma40_platform_data *plat_data;
2564 struct clk *clk = NULL;
2565 void __iomem *virtbase = NULL;
2566 struct resource *res = NULL;
2567 struct d40_base *base = NULL;
2568 int num_log_chans = 0;
2569 int num_phy_chans;
2570 int i;
2571 u32 pid;
2572 u32 cid;
2573 u8 rev;
2574
2575 clk = clk_get(&pdev->dev, NULL);
2576
2577 if (IS_ERR(clk)) {
2578 d40_err(&pdev->dev, "No matching clock found\n");
2579 goto failure;
2580 }
2581
2582 clk_enable(clk);
2583
2584 /* Get IO for DMAC base address */
2585 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "base");
2586 if (!res)
2587 goto failure;
2588
2589 if (request_mem_region(res->start, resource_size(res),
2590 D40_NAME " I/O base") == NULL)
2591 goto failure;
2592
2593 virtbase = ioremap(res->start, resource_size(res));
2594 if (!virtbase)
2595 goto failure;
2596
2597 /* This is just a regular AMBA PrimeCell ID actually */
2598 for (pid = 0, i = 0; i < 4; i++)
2599 pid |= (readl(virtbase + resource_size(res) - 0x20 + 4 * i)
2600 & 255) << (i * 8);
2601 for (cid = 0, i = 0; i < 4; i++)
2602 cid |= (readl(virtbase + resource_size(res) - 0x10 + 4 * i)
2603 & 255) << (i * 8);
2604
2605 if (cid != AMBA_CID) {
2606 d40_err(&pdev->dev, "Unknown hardware! No PrimeCell ID\n");
2607 goto failure;
2608 }
2609 if (AMBA_MANF_BITS(pid) != AMBA_VENDOR_ST) {
2610 d40_err(&pdev->dev, "Unknown designer! Got %x wanted %x\n",
2611 AMBA_MANF_BITS(pid),
2612 AMBA_VENDOR_ST);
2613 goto failure;
2614 }
2615 /*
2616 * HW revision:
2617 * DB8500ed has revision 0
2618 * ? has revision 1
2619 * DB8500v1 has revision 2
2620 * DB8500v2 has revision 3
2621 */
2622 rev = AMBA_REV_BITS(pid);
2623
2624 /* The number of physical channels on this HW */
2625 num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4;
2626
2627 dev_info(&pdev->dev, "hardware revision: %d @ 0x%x\n",
2628 rev, res->start);
2629
2630 plat_data = pdev->dev.platform_data;
2631
2632 /* Count the number of logical channels in use */
2633 for (i = 0; i < plat_data->dev_len; i++)
2634 if (plat_data->dev_rx[i] != 0)
2635 num_log_chans++;
2636
2637 for (i = 0; i < plat_data->dev_len; i++)
2638 if (plat_data->dev_tx[i] != 0)
2639 num_log_chans++;
2640
2641 base = kzalloc(ALIGN(sizeof(struct d40_base), 4) +
2642 (num_phy_chans + num_log_chans + plat_data->memcpy_len) *
2643 sizeof(struct d40_chan), GFP_KERNEL);
2644
2645 if (base == NULL) {
2646 d40_err(&pdev->dev, "Out of memory\n");
2647 goto failure;
2648 }
2649
2650 base->rev = rev;
2651 base->clk = clk;
2652 base->num_phy_chans = num_phy_chans;
2653 base->num_log_chans = num_log_chans;
2654 base->phy_start = res->start;
2655 base->phy_size = resource_size(res);
2656 base->virtbase = virtbase;
2657 base->plat_data = plat_data;
2658 base->dev = &pdev->dev;
2659 base->phy_chans = ((void *)base) + ALIGN(sizeof(struct d40_base), 4);
2660 base->log_chans = &base->phy_chans[num_phy_chans];
2661
2662 base->phy_res = kzalloc(num_phy_chans * sizeof(struct d40_phy_res),
2663 GFP_KERNEL);
2664 if (!base->phy_res)
2665 goto failure;
2666
2667 base->lookup_phy_chans = kzalloc(num_phy_chans *
2668 sizeof(struct d40_chan *),
2669 GFP_KERNEL);
2670 if (!base->lookup_phy_chans)
2671 goto failure;
2672
2673 if (num_log_chans + plat_data->memcpy_len) {
2674 /*
2675 * The max number of logical channels are event lines for all
2676 * src devices and dst devices
2677 */
2678 base->lookup_log_chans = kzalloc(plat_data->dev_len * 2 *
2679 sizeof(struct d40_chan *),
2680 GFP_KERNEL);
2681 if (!base->lookup_log_chans)
2682 goto failure;
2683 }
2684
2685 base->lcla_pool.alloc_map = kzalloc(num_phy_chans *
2686 sizeof(struct d40_desc *) *
2687 D40_LCLA_LINK_PER_EVENT_GRP,
2688 GFP_KERNEL);
2689 if (!base->lcla_pool.alloc_map)
2690 goto failure;
2691
2692 base->desc_slab = kmem_cache_create(D40_NAME, sizeof(struct d40_desc),
2693 0, SLAB_HWCACHE_ALIGN,
2694 NULL);
2695 if (base->desc_slab == NULL)
2696 goto failure;
2697
2698 return base;
2699
2700 failure:
2701 if (!IS_ERR(clk)) {
2702 clk_disable(clk);
2703 clk_put(clk);
2704 }
2705 if (virtbase)
2706 iounmap(virtbase);
2707 if (res)
2708 release_mem_region(res->start,
2709 resource_size(res));
2710 if (virtbase)
2711 iounmap(virtbase);
2712
2713 if (base) {
2714 kfree(base->lcla_pool.alloc_map);
2715 kfree(base->lookup_log_chans);
2716 kfree(base->lookup_phy_chans);
2717 kfree(base->phy_res);
2718 kfree(base);
2719 }
2720
2721 return NULL;
2722 }
2723
2724 static void __init d40_hw_init(struct d40_base *base)
2725 {
2726
2727 static const struct d40_reg_val dma_init_reg[] = {
2728 /* Clock every part of the DMA block from start */
2729 { .reg = D40_DREG_GCC, .val = 0x0000ff01},
2730
2731 /* Interrupts on all logical channels */
2732 { .reg = D40_DREG_LCMIS0, .val = 0xFFFFFFFF},
2733 { .reg = D40_DREG_LCMIS1, .val = 0xFFFFFFFF},
2734 { .reg = D40_DREG_LCMIS2, .val = 0xFFFFFFFF},
2735 { .reg = D40_DREG_LCMIS3, .val = 0xFFFFFFFF},
2736 { .reg = D40_DREG_LCICR0, .val = 0xFFFFFFFF},
2737 { .reg = D40_DREG_LCICR1, .val = 0xFFFFFFFF},
2738 { .reg = D40_DREG_LCICR2, .val = 0xFFFFFFFF},
2739 { .reg = D40_DREG_LCICR3, .val = 0xFFFFFFFF},
2740 { .reg = D40_DREG_LCTIS0, .val = 0xFFFFFFFF},
2741 { .reg = D40_DREG_LCTIS1, .val = 0xFFFFFFFF},
2742 { .reg = D40_DREG_LCTIS2, .val = 0xFFFFFFFF},
2743 { .reg = D40_DREG_LCTIS3, .val = 0xFFFFFFFF}
2744 };
2745 int i;
2746 u32 prmseo[2] = {0, 0};
2747 u32 activeo[2] = {0xFFFFFFFF, 0xFFFFFFFF};
2748 u32 pcmis = 0;
2749 u32 pcicr = 0;
2750
2751 for (i = 0; i < ARRAY_SIZE(dma_init_reg); i++)
2752 writel(dma_init_reg[i].val,
2753 base->virtbase + dma_init_reg[i].reg);
2754
2755 /* Configure all our dma channels to default settings */
2756 for (i = 0; i < base->num_phy_chans; i++) {
2757
2758 activeo[i % 2] = activeo[i % 2] << 2;
2759
2760 if (base->phy_res[base->num_phy_chans - i - 1].allocated_src
2761 == D40_ALLOC_PHY) {
2762 activeo[i % 2] |= 3;
2763 continue;
2764 }
2765
2766 /* Enable interrupt # */
2767 pcmis = (pcmis << 1) | 1;
2768
2769 /* Clear interrupt # */
2770 pcicr = (pcicr << 1) | 1;
2771
2772 /* Set channel to physical mode */
2773 prmseo[i % 2] = prmseo[i % 2] << 2;
2774 prmseo[i % 2] |= 1;
2775
2776 }
2777
2778 writel(prmseo[1], base->virtbase + D40_DREG_PRMSE);
2779 writel(prmseo[0], base->virtbase + D40_DREG_PRMSO);
2780 writel(activeo[1], base->virtbase + D40_DREG_ACTIVE);
2781 writel(activeo[0], base->virtbase + D40_DREG_ACTIVO);
2782
2783 /* Write which interrupt to enable */
2784 writel(pcmis, base->virtbase + D40_DREG_PCMIS);
2785
2786 /* Write which interrupt to clear */
2787 writel(pcicr, base->virtbase + D40_DREG_PCICR);
2788
2789 }
2790
2791 static int __init d40_lcla_allocate(struct d40_base *base)
2792 {
2793 struct d40_lcla_pool *pool = &base->lcla_pool;
2794 unsigned long *page_list;
2795 int i, j;
2796 int ret = 0;
2797
2798 /*
2799 * This is somewhat ugly. We need 8192 bytes that are 18 bit aligned,
2800 * To full fill this hardware requirement without wasting 256 kb
2801 * we allocate pages until we get an aligned one.
2802 */
2803 page_list = kmalloc(sizeof(unsigned long) * MAX_LCLA_ALLOC_ATTEMPTS,
2804 GFP_KERNEL);
2805
2806 if (!page_list) {
2807 ret = -ENOMEM;
2808 goto failure;
2809 }
2810
2811 /* Calculating how many pages that are required */
2812 base->lcla_pool.pages = SZ_1K * base->num_phy_chans / PAGE_SIZE;
2813
2814 for (i = 0; i < MAX_LCLA_ALLOC_ATTEMPTS; i++) {
2815 page_list[i] = __get_free_pages(GFP_KERNEL,
2816 base->lcla_pool.pages);
2817 if (!page_list[i]) {
2818
2819 d40_err(base->dev, "Failed to allocate %d pages.\n",
2820 base->lcla_pool.pages);
2821
2822 for (j = 0; j < i; j++)
2823 free_pages(page_list[j], base->lcla_pool.pages);
2824 goto failure;
2825 }
2826
2827 if ((virt_to_phys((void *)page_list[i]) &
2828 (LCLA_ALIGNMENT - 1)) == 0)
2829 break;
2830 }
2831
2832 for (j = 0; j < i; j++)
2833 free_pages(page_list[j], base->lcla_pool.pages);
2834
2835 if (i < MAX_LCLA_ALLOC_ATTEMPTS) {
2836 base->lcla_pool.base = (void *)page_list[i];
2837 } else {
2838 /*
2839 * After many attempts and no succees with finding the correct
2840 * alignment, try with allocating a big buffer.
2841 */
2842 dev_warn(base->dev,
2843 "[%s] Failed to get %d pages @ 18 bit align.\n",
2844 __func__, base->lcla_pool.pages);
2845 base->lcla_pool.base_unaligned = kmalloc(SZ_1K *
2846 base->num_phy_chans +
2847 LCLA_ALIGNMENT,
2848 GFP_KERNEL);
2849 if (!base->lcla_pool.base_unaligned) {
2850 ret = -ENOMEM;
2851 goto failure;
2852 }
2853
2854 base->lcla_pool.base = PTR_ALIGN(base->lcla_pool.base_unaligned,
2855 LCLA_ALIGNMENT);
2856 }
2857
2858 pool->dma_addr = dma_map_single(base->dev, pool->base,
2859 SZ_1K * base->num_phy_chans,
2860 DMA_TO_DEVICE);
2861 if (dma_mapping_error(base->dev, pool->dma_addr)) {
2862 pool->dma_addr = 0;
2863 ret = -ENOMEM;
2864 goto failure;
2865 }
2866
2867 writel(virt_to_phys(base->lcla_pool.base),
2868 base->virtbase + D40_DREG_LCLA);
2869 failure:
2870 kfree(page_list);
2871 return ret;
2872 }
2873
2874 static int __init d40_probe(struct platform_device *pdev)
2875 {
2876 int err;
2877 int ret = -ENOENT;
2878 struct d40_base *base;
2879 struct resource *res = NULL;
2880 int num_reserved_chans;
2881 u32 val;
2882
2883 base = d40_hw_detect_init(pdev);
2884
2885 if (!base)
2886 goto failure;
2887
2888 num_reserved_chans = d40_phy_res_init(base);
2889
2890 platform_set_drvdata(pdev, base);
2891
2892 spin_lock_init(&base->interrupt_lock);
2893 spin_lock_init(&base->execmd_lock);
2894
2895 /* Get IO for logical channel parameter address */
2896 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "lcpa");
2897 if (!res) {
2898 ret = -ENOENT;
2899 d40_err(&pdev->dev, "No \"lcpa\" memory resource\n");
2900 goto failure;
2901 }
2902 base->lcpa_size = resource_size(res);
2903 base->phy_lcpa = res->start;
2904
2905 if (request_mem_region(res->start, resource_size(res),
2906 D40_NAME " I/O lcpa") == NULL) {
2907 ret = -EBUSY;
2908 d40_err(&pdev->dev,
2909 "Failed to request LCPA region 0x%x-0x%x\n",
2910 res->start, res->end);
2911 goto failure;
2912 }
2913
2914 /* We make use of ESRAM memory for this. */
2915 val = readl(base->virtbase + D40_DREG_LCPA);
2916 if (res->start != val && val != 0) {
2917 dev_warn(&pdev->dev,
2918 "[%s] Mismatch LCPA dma 0x%x, def 0x%x\n",
2919 __func__, val, res->start);
2920 } else
2921 writel(res->start, base->virtbase + D40_DREG_LCPA);
2922
2923 base->lcpa_base = ioremap(res->start, resource_size(res));
2924 if (!base->lcpa_base) {
2925 ret = -ENOMEM;
2926 d40_err(&pdev->dev, "Failed to ioremap LCPA region\n");
2927 goto failure;
2928 }
2929
2930 ret = d40_lcla_allocate(base);
2931 if (ret) {
2932 d40_err(&pdev->dev, "Failed to allocate LCLA area\n");
2933 goto failure;
2934 }
2935
2936 spin_lock_init(&base->lcla_pool.lock);
2937
2938 base->irq = platform_get_irq(pdev, 0);
2939
2940 ret = request_irq(base->irq, d40_handle_interrupt, 0, D40_NAME, base);
2941 if (ret) {
2942 d40_err(&pdev->dev, "No IRQ defined\n");
2943 goto failure;
2944 }
2945
2946 err = d40_dmaengine_init(base, num_reserved_chans);
2947 if (err)
2948 goto failure;
2949
2950 d40_hw_init(base);
2951
2952 dev_info(base->dev, "initialized\n");
2953 return 0;
2954
2955 failure:
2956 if (base) {
2957 if (base->desc_slab)
2958 kmem_cache_destroy(base->desc_slab);
2959 if (base->virtbase)
2960 iounmap(base->virtbase);
2961
2962 if (base->lcla_pool.dma_addr)
2963 dma_unmap_single(base->dev, base->lcla_pool.dma_addr,
2964 SZ_1K * base->num_phy_chans,
2965 DMA_TO_DEVICE);
2966
2967 if (!base->lcla_pool.base_unaligned && base->lcla_pool.base)
2968 free_pages((unsigned long)base->lcla_pool.base,
2969 base->lcla_pool.pages);
2970
2971 kfree(base->lcla_pool.base_unaligned);
2972
2973 if (base->phy_lcpa)
2974 release_mem_region(base->phy_lcpa,
2975 base->lcpa_size);
2976 if (base->phy_start)
2977 release_mem_region(base->phy_start,
2978 base->phy_size);
2979 if (base->clk) {
2980 clk_disable(base->clk);
2981 clk_put(base->clk);
2982 }
2983
2984 kfree(base->lcla_pool.alloc_map);
2985 kfree(base->lookup_log_chans);
2986 kfree(base->lookup_phy_chans);
2987 kfree(base->phy_res);
2988 kfree(base);
2989 }
2990
2991 d40_err(&pdev->dev, "probe failed\n");
2992 return ret;
2993 }
2994
2995 static struct platform_driver d40_driver = {
2996 .driver = {
2997 .owner = THIS_MODULE,
2998 .name = D40_NAME,
2999 },
3000 };
3001
3002 static int __init stedma40_init(void)
3003 {
3004 return platform_driver_probe(&d40_driver, d40_probe);
3005 }
3006 subsys_initcall(stedma40_init);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree