sound/soc/omap/omap-mcbsp.c

   1 /*
   2  * omap-mcbsp.c  --  OMAP ALSA SoC DAI driver using McBSP port
   3  *
   4  * Copyright (C) 2008 Nokia Corporation
   5  *
   6  * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
   7  *          Peter Ujfalusi <peter.ujfalusi@ti.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * version 2 as published by the Free Software Foundation.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  21  * 02110-1301 USA
  22  *
  23  */
  24
  25 #include <linux/init.h>
  26 #include <linux/module.h>
  27 #include <linux/device.h>
  28 #include <linux/pm_runtime.h>
  29 #include <sound/core.h>
  30 #include <sound/pcm.h>
  31 #include <sound/pcm_params.h>
  32 #include <sound/initval.h>
  33 #include <sound/soc.h>
  34
  35 #include <plat/dma.h>
  36 #include <plat/mcbsp.h>
  37 #include "mcbsp.h"
  38 #include "omap-mcbsp.h"
  39 #include "omap-pcm.h"
  40
  41 #define OMAP_MCBSP_RATES        (SNDRV_PCM_RATE_8000_96000)
  42
  43 #define OMAP_MCBSP_SOC_SINGLE_S16_EXT(xname, xmin, xmax, \
  44         xhandler_get, xhandler_put) \
  45 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  46         .info = omap_mcbsp_st_info_volsw, \
  47         .get = xhandler_get, .put = xhandler_put, \
  48         .private_value = (unsigned long) &(struct soc_mixer_control) \
  49         {.min = xmin, .max = xmax} }
  50
  51 enum {
  52         OMAP_MCBSP_WORD_8 = 0,
  53         OMAP_MCBSP_WORD_12,
  54         OMAP_MCBSP_WORD_16,
  55         OMAP_MCBSP_WORD_20,
  56         OMAP_MCBSP_WORD_24,
  57         OMAP_MCBSP_WORD_32,
  58 };
  59
  60 /*
  61  * Stream DMA parameters. DMA request line and port address are set runtime
  62  * since they are different between OMAP1 and later OMAPs
  63  */
  64 static void omap_mcbsp_set_threshold(struct snd_pcm_substream *substream)
  65 {
  66         struct snd_soc_pcm_runtime *rtd = substream->private_data;
  67         struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
  68         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
  69         struct omap_pcm_dma_data *dma_data;
  70         int words;
  71
  72         dma_data = snd_soc_dai_get_dma_data(rtd->cpu_dai, substream);
  73
  74         /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */
  75         if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD)
  76                 /*
  77                  * Configure McBSP threshold based on either:
  78                  * packet_size, when the sDMA is in packet mode, or
  79                  * based on the period size.
  80                  */
  81                 if (dma_data->packet_size)
  82                         words = dma_data->packet_size;
  83                 else
  84                         words = snd_pcm_lib_period_bytes(substream) /
  85                                                         (mcbsp->wlen / 8);
  86         else
  87                 words = 1;
  88
  89         /* Configure McBSP internal buffer usage */
  90         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  91                 omap_mcbsp_set_tx_threshold(mcbsp, words);
  92         else
  93                 omap_mcbsp_set_rx_threshold(mcbsp, words);
  94 }
  95
  96 static int omap_mcbsp_hwrule_min_buffersize(struct snd_pcm_hw_params *params,
  97                                     struct snd_pcm_hw_rule *rule)
  98 {
  99         struct snd_interval *buffer_size = hw_param_interval(params,
 100                                         SNDRV_PCM_HW_PARAM_BUFFER_SIZE);
 101         struct snd_interval *channels = hw_param_interval(params,
 102                                         SNDRV_PCM_HW_PARAM_CHANNELS);
 103         struct omap_mcbsp *mcbsp = rule->private;
 104         struct snd_interval frames;
 105         int size;
 106
 107         snd_interval_any(&frames);
 108         size = mcbsp->pdata->buffer_size;
 109
 110         frames.min = size / channels->min;
 111         frames.integer = 1;
 112         return snd_interval_refine(buffer_size, &frames);
 113 }
 114
 115 static int omap_mcbsp_dai_startup(struct snd_pcm_substream *substream,
 116                                   struct snd_soc_dai *cpu_dai)
 117 {
 118         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 119         int err = 0;
 120
 121         if (!cpu_dai->active)
 122                 err = omap_mcbsp_request(mcbsp);
 123
 124         /*
 125          * OMAP3 McBSP FIFO is word structured.
 126          * McBSP2 has 1024 + 256 = 1280 word long buffer,
 127          * McBSP1,3,4,5 has 128 word long buffer
 128          * This means that the size of the FIFO depends on the sample format.
 129          * For example on McBSP3:
 130          * 16bit samples: size is 128 * 2 = 256 bytes
 131          * 32bit samples: size is 128 * 4 = 512 bytes
 132          * It is simpler to place constraint for buffer and period based on
 133          * channels.
 134          * McBSP3 as example again (16 or 32 bit samples):
 135          * 1 channel (mono): size is 128 frames (128 words)
 136          * 2 channels (stereo): size is 128 / 2 = 64 frames (2 * 64 words)
 137          * 4 channels: size is 128 / 4 = 32 frames (4 * 32 words)
 138          */
 139         if (mcbsp->pdata->buffer_size) {
 140                 /*
 141                 * Rule for the buffer size. We should not allow
 142                 * smaller buffer than the FIFO size to avoid underruns
 143                 */
 144                 snd_pcm_hw_rule_add(substream->runtime, 0,
 145                                     SNDRV_PCM_HW_PARAM_BUFFER_SIZE,
 146                                     omap_mcbsp_hwrule_min_buffersize,
 147                                     mcbsp,
 148                                     SNDRV_PCM_HW_PARAM_CHANNELS, -1);
 149
 150                 /* Make sure, that the period size is always even */
 151                 snd_pcm_hw_constraint_step(substream->runtime, 0,
 152                                            SNDRV_PCM_HW_PARAM_PERIOD_SIZE, 2);
 153         }
 154
 155         return err;
 156 }
 157
 158 static void omap_mcbsp_dai_shutdown(struct snd_pcm_substream *substream,
 159                                     struct snd_soc_dai *cpu_dai)
 160 {
 161         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 162
 163         if (!cpu_dai->active) {
 164                 omap_mcbsp_free(mcbsp);
 165                 mcbsp->configured = 0;
 166         }
 167 }
 168
 169 static int omap_mcbsp_dai_trigger(struct snd_pcm_substream *substream, int cmd,
 170                                   struct snd_soc_dai *cpu_dai)
 171 {
 172         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 173         int err = 0, play = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK);
 174
 175         switch (cmd) {
 176         case SNDRV_PCM_TRIGGER_START:
 177         case SNDRV_PCM_TRIGGER_RESUME:
 178         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 179                 mcbsp->active++;
 180                 omap_mcbsp_start(mcbsp, play, !play);
 181                 break;
 182
 183         case SNDRV_PCM_TRIGGER_STOP:
 184         case SNDRV_PCM_TRIGGER_SUSPEND:
 185         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 186                 omap_mcbsp_stop(mcbsp, play, !play);
 187                 mcbsp->active--;
 188                 break;
 189         default:
 190                 err = -EINVAL;
 191         }
 192
 193         return err;
 194 }
 195
 196 static snd_pcm_sframes_t omap_mcbsp_dai_delay(
 197                         struct snd_pcm_substream *substream,
 198                         struct snd_soc_dai *dai)
 199 {
 200         struct snd_soc_pcm_runtime *rtd = substream->private_data;
 201         struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
 202         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 203         u16 fifo_use;
 204         snd_pcm_sframes_t delay;
 205
 206         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 207                 fifo_use = omap_mcbsp_get_tx_delay(mcbsp);
 208         else
 209                 fifo_use = omap_mcbsp_get_rx_delay(mcbsp);
 210
 211         /*
 212          * Divide the used locations with the channel count to get the
 213          * FIFO usage in samples (don't care about partial samples in the
 214          * buffer).
 215          */
 216         delay = fifo_use / substream->runtime->channels;
 217
 218         return delay;
 219 }
 220
 221 static int omap_mcbsp_dai_hw_params(struct snd_pcm_substream *substream,
 222                                     struct snd_pcm_hw_params *params,
 223                                     struct snd_soc_dai *cpu_dai)
 224 {
 225         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 226         struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
 227         struct omap_pcm_dma_data *dma_data;
 228         int wlen, channels, wpf, sync_mode = OMAP_DMA_SYNC_ELEMENT;
 229         int pkt_size = 0;
 230         unsigned int format, div, framesize, master;
 231
 232         dma_data = &mcbsp->dma_data[substream->stream];
 233
 234         switch (params_format(params)) {
 235         case SNDRV_PCM_FORMAT_S16_LE:
 236                 dma_data->data_type = OMAP_DMA_DATA_TYPE_S16;
 237                 wlen = 16;
 238                 break;
 239         case SNDRV_PCM_FORMAT_S32_LE:
 240                 dma_data->data_type = OMAP_DMA_DATA_TYPE_S32;
 241                 wlen = 32;
 242                 break;
 243         default:
 244                 return -EINVAL;
 245         }
 246         if (mcbsp->pdata->buffer_size) {
 247                 dma_data->set_threshold = omap_mcbsp_set_threshold;
 248                 /* TODO: Currently, MODE_ELEMENT == MODE_FRAME */
 249                 if (mcbsp->dma_op_mode == MCBSP_DMA_MODE_THRESHOLD) {
 250                         int period_words, max_thrsh;
 251
 252                         period_words = params_period_bytes(params) / (wlen / 8);
 253                         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 254                                 max_thrsh = mcbsp->max_tx_thres;
 255                         else
 256                                 max_thrsh = mcbsp->max_rx_thres;
 257                         /*
 258                          * If the period contains less or equal number of words,
 259                          * we are using the original threshold mode setup:
 260                          * McBSP threshold = sDMA frame size = period_size
 261                          * Otherwise we switch to sDMA packet mode:
 262                          * McBSP threshold = sDMA packet size
 263                          * sDMA frame size = period size
 264                          */
 265                         if (period_words > max_thrsh) {
 266                                 int divider = 0;
 267
 268                                 /*
 269                                  * Look for the biggest threshold value, which
 270                                  * divides the period size evenly.
 271                                  */
 272                                 divider = period_words / max_thrsh;
 273                                 if (period_words % max_thrsh)
 274                                         divider++;
 275                                 while (period_words % divider &&
 276                                         divider < period_words)
 277                                         divider++;
 278                                 if (divider == period_words)
 279                                         return -EINVAL;
 280
 281                                 pkt_size = period_words / divider;
 282                                 sync_mode = OMAP_DMA_SYNC_PACKET;
 283                         } else {
 284                                 sync_mode = OMAP_DMA_SYNC_FRAME;
 285                         }
 286                 }
 287         }
 288
 289         dma_data->sync_mode = sync_mode;
 290         dma_data->packet_size = pkt_size;
 291
 292         snd_soc_dai_set_dma_data(cpu_dai, substream, dma_data);
 293
 294         if (mcbsp->configured) {
 295                 /* McBSP already configured by another stream */
 296                 return 0;
 297         }
 298
 299         regs->rcr2      &= ~(RPHASE | RFRLEN2(0x7f) | RWDLEN2(7));
 300         regs->xcr2      &= ~(RPHASE | XFRLEN2(0x7f) | XWDLEN2(7));
 301         regs->rcr1      &= ~(RFRLEN1(0x7f) | RWDLEN1(7));
 302         regs->xcr1      &= ~(XFRLEN1(0x7f) | XWDLEN1(7));
 303         format = mcbsp->fmt & SND_SOC_DAIFMT_FORMAT_MASK;
 304         wpf = channels = params_channels(params);
 305         if (channels == 2 && (format == SND_SOC_DAIFMT_I2S ||
 306                               format == SND_SOC_DAIFMT_LEFT_J)) {
 307                 /* Use dual-phase frames */
 308                 regs->rcr2      |= RPHASE;
 309                 regs->xcr2      |= XPHASE;
 310                 /* Set 1 word per (McBSP) frame for phase1 and phase2 */
 311                 wpf--;
 312                 regs->rcr2      |= RFRLEN2(wpf - 1);
 313                 regs->xcr2      |= XFRLEN2(wpf - 1);
 314         }
 315
 316         regs->rcr1      |= RFRLEN1(wpf - 1);
 317         regs->xcr1      |= XFRLEN1(wpf - 1);
 318
 319         switch (params_format(params)) {
 320         case SNDRV_PCM_FORMAT_S16_LE:
 321                 /* Set word lengths */
 322                 regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_16);
 323                 regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_16);
 324                 regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_16);
 325                 regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_16);
 326                 break;
 327         case SNDRV_PCM_FORMAT_S32_LE:
 328                 /* Set word lengths */
 329                 regs->rcr2      |= RWDLEN2(OMAP_MCBSP_WORD_32);
 330                 regs->rcr1      |= RWDLEN1(OMAP_MCBSP_WORD_32);
 331                 regs->xcr2      |= XWDLEN2(OMAP_MCBSP_WORD_32);
 332                 regs->xcr1      |= XWDLEN1(OMAP_MCBSP_WORD_32);
 333                 break;
 334         default:
 335                 /* Unsupported PCM format */
 336                 return -EINVAL;
 337         }
 338
 339         /* In McBSP master modes, FRAME (i.e. sample rate) is generated
 340          * by _counting_ BCLKs. Calculate frame size in BCLKs */
 341         master = mcbsp->fmt & SND_SOC_DAIFMT_MASTER_MASK;
 342         if (master ==   SND_SOC_DAIFMT_CBS_CFS) {
 343                 div = mcbsp->clk_div ? mcbsp->clk_div : 1;
 344                 framesize = (mcbsp->in_freq / div) / params_rate(params);
 345
 346                 if (framesize < wlen * channels) {
 347                         printk(KERN_ERR "%s: not enough bandwidth for desired rate and "
 348                                         "channels\n", __func__);
 349                         return -EINVAL;
 350                 }
 351         } else
 352                 framesize = wlen * channels;
 353
 354         /* Set FS period and length in terms of bit clock periods */
 355         regs->srgr2     &= ~FPER(0xfff);
 356         regs->srgr1     &= ~FWID(0xff);
 357         switch (format) {
 358         case SND_SOC_DAIFMT_I2S:
 359         case SND_SOC_DAIFMT_LEFT_J:
 360                 regs->srgr2     |= FPER(framesize - 1);
 361                 regs->srgr1     |= FWID((framesize >> 1) - 1);
 362                 break;
 363         case SND_SOC_DAIFMT_DSP_A:
 364         case SND_SOC_DAIFMT_DSP_B:
 365                 regs->srgr2     |= FPER(framesize - 1);
 366                 regs->srgr1     |= FWID(0);
 367                 break;
 368         }
 369
 370         omap_mcbsp_config(mcbsp, &mcbsp->cfg_regs);
 371         mcbsp->wlen = wlen;
 372         mcbsp->configured = 1;
 373
 374         return 0;
 375 }
 376
 377 /*
 378  * This must be called before _set_clkdiv and _set_sysclk since McBSP register
 379  * cache is initialized here
 380  */
 381 static int omap_mcbsp_dai_set_dai_fmt(struct snd_soc_dai *cpu_dai,
 382                                       unsigned int fmt)
 383 {
 384         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 385         struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
 386         bool inv_fs = false;
 387
 388         if (mcbsp->configured)
 389                 return 0;
 390
 391         mcbsp->fmt = fmt;
 392         memset(regs, 0, sizeof(*regs));
 393         /* Generic McBSP register settings */
 394         regs->spcr2     |= XINTM(3) | FREE;
 395         regs->spcr1     |= RINTM(3);
 396         /* RFIG and XFIG are not defined in 34xx */
 397         if (!cpu_is_omap34xx() && !cpu_is_omap44xx()) {
 398                 regs->rcr2      |= RFIG;
 399                 regs->xcr2      |= XFIG;
 400         }
 401         if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
 402                 regs->xccr = DXENDLY(1) | XDMAEN | XDISABLE;
 403                 regs->rccr = RFULL_CYCLE | RDMAEN | RDISABLE;
 404         }
 405
 406         switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 407         case SND_SOC_DAIFMT_I2S:
 408                 /* 1-bit data delay */
 409                 regs->rcr2      |= RDATDLY(1);
 410                 regs->xcr2      |= XDATDLY(1);
 411                 break;
 412         case SND_SOC_DAIFMT_LEFT_J:
 413                 /* 0-bit data delay */
 414                 regs->rcr2      |= RDATDLY(0);
 415                 regs->xcr2      |= XDATDLY(0);
 416                 regs->spcr1     |= RJUST(2);
 417                 /* Invert FS polarity configuration */
 418                 inv_fs = true;
 419                 break;
 420         case SND_SOC_DAIFMT_DSP_A:
 421                 /* 1-bit data delay */
 422                 regs->rcr2      |= RDATDLY(1);
 423                 regs->xcr2      |= XDATDLY(1);
 424                 /* Invert FS polarity configuration */
 425                 inv_fs = true;
 426                 break;
 427         case SND_SOC_DAIFMT_DSP_B:
 428                 /* 0-bit data delay */
 429                 regs->rcr2      |= RDATDLY(0);
 430                 regs->xcr2      |= XDATDLY(0);
 431                 /* Invert FS polarity configuration */
 432                 inv_fs = true;
 433                 break;
 434         default:
 435                 /* Unsupported data format */
 436                 return -EINVAL;
 437         }
 438
 439         switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 440         case SND_SOC_DAIFMT_CBS_CFS:
 441                 /* McBSP master. Set FS and bit clocks as outputs */
 442                 regs->pcr0      |= FSXM | FSRM |
 443                                    CLKXM | CLKRM;
 444                 /* Sample rate generator drives the FS */
 445                 regs->srgr2     |= FSGM;
 446                 break;
 447         case SND_SOC_DAIFMT_CBM_CFM:
 448                 /* McBSP slave */
 449                 break;
 450         default:
 451                 /* Unsupported master/slave configuration */
 452                 return -EINVAL;
 453         }
 454
 455         /* Set bit clock (CLKX/CLKR) and FS polarities */
 456         switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
 457         case SND_SOC_DAIFMT_NB_NF:
 458                 /*
 459                  * Normal BCLK + FS.
 460                  * FS active low. TX data driven on falling edge of bit clock
 461                  * and RX data sampled on rising edge of bit clock.
 462                  */
 463                 regs->pcr0      |= FSXP | FSRP |
 464                                    CLKXP | CLKRP;
 465                 break;
 466         case SND_SOC_DAIFMT_NB_IF:
 467                 regs->pcr0      |= CLKXP | CLKRP;
 468                 break;
 469         case SND_SOC_DAIFMT_IB_NF:
 470                 regs->pcr0      |= FSXP | FSRP;
 471                 break;
 472         case SND_SOC_DAIFMT_IB_IF:
 473                 break;
 474         default:
 475                 return -EINVAL;
 476         }
 477         if (inv_fs == true)
 478                 regs->pcr0 ^= FSXP | FSRP;
 479
 480         return 0;
 481 }
 482
 483 static int omap_mcbsp_dai_set_clkdiv(struct snd_soc_dai *cpu_dai,
 484                                      int div_id, int div)
 485 {
 486         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 487         struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
 488
 489         if (div_id != OMAP_MCBSP_CLKGDV)
 490                 return -ENODEV;
 491
 492         mcbsp->clk_div = div;
 493         regs->srgr1     &= ~CLKGDV(0xff);
 494         regs->srgr1     |= CLKGDV(div - 1);
 495
 496         return 0;
 497 }
 498
 499 static int omap_mcbsp_dai_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
 500                                          int clk_id, unsigned int freq,
 501                                          int dir)
 502 {
 503         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 504         struct omap_mcbsp_reg_cfg *regs = &mcbsp->cfg_regs;
 505         int err = 0;
 506
 507         if (mcbsp->active) {
 508                 if (freq == mcbsp->in_freq)
 509                         return 0;
 510                 else
 511                         return -EBUSY;
 512         }
 513
 514         if (clk_id == OMAP_MCBSP_SYSCLK_CLK ||
 515             clk_id == OMAP_MCBSP_SYSCLK_CLKS_FCLK ||
 516             clk_id == OMAP_MCBSP_SYSCLK_CLKS_EXT ||
 517             clk_id == OMAP_MCBSP_SYSCLK_CLKX_EXT ||
 518             clk_id == OMAP_MCBSP_SYSCLK_CLKR_EXT) {
 519                 mcbsp->in_freq = freq;
 520                 regs->srgr2     &= ~CLKSM;
 521                 regs->pcr0      &= ~SCLKME;
 522         } else if (cpu_class_is_omap1()) {
 523                 /*
 524                  * McBSP CLKR/FSR signal muxing functions are only available on
 525                  * OMAP2 or newer versions
 526                  */
 527                 return -EINVAL;
 528         }
 529
 530         switch (clk_id) {
 531         case OMAP_MCBSP_SYSCLK_CLK:
 532                 regs->srgr2     |= CLKSM;
 533                 break;
 534         case OMAP_MCBSP_SYSCLK_CLKS_FCLK:
 535                 if (cpu_class_is_omap1()) {
 536                         err = -EINVAL;
 537                         break;
 538                 }
 539                 err = omap2_mcbsp_set_clks_src(mcbsp,
 540                                                MCBSP_CLKS_PRCM_SRC);
 541                 break;
 542         case OMAP_MCBSP_SYSCLK_CLKS_EXT:
 543                 if (cpu_class_is_omap1()) {
 544                         err = 0;
 545                         break;
 546                 }
 547                 err = omap2_mcbsp_set_clks_src(mcbsp,
 548                                                MCBSP_CLKS_PAD_SRC);
 549                 break;
 550
 551         case OMAP_MCBSP_SYSCLK_CLKX_EXT:
 552                 regs->srgr2     |= CLKSM;
 553         case OMAP_MCBSP_SYSCLK_CLKR_EXT:
 554                 regs->pcr0      |= SCLKME;
 555                 break;
 556
 557
 558         case OMAP_MCBSP_CLKR_SRC_CLKR:
 559                 err = omap_mcbsp_6pin_src_mux(mcbsp, CLKR_SRC_CLKR);
 560                 break;
 561         case OMAP_MCBSP_CLKR_SRC_CLKX:
 562                 err = omap_mcbsp_6pin_src_mux(mcbsp, CLKR_SRC_CLKX);
 563                 break;
 564         case OMAP_MCBSP_FSR_SRC_FSR:
 565                 err = omap_mcbsp_6pin_src_mux(mcbsp, FSR_SRC_FSR);
 566                 break;
 567         case OMAP_MCBSP_FSR_SRC_FSX:
 568                 err = omap_mcbsp_6pin_src_mux(mcbsp, FSR_SRC_FSX);
 569                 break;
 570         default:
 571                 err = -ENODEV;
 572         }
 573
 574         return err;
 575 }
 576
 577 static const struct snd_soc_dai_ops mcbsp_dai_ops = {
 578         .startup        = omap_mcbsp_dai_startup,
 579         .shutdown       = omap_mcbsp_dai_shutdown,
 580         .trigger        = omap_mcbsp_dai_trigger,
 581         .delay          = omap_mcbsp_dai_delay,
 582         .hw_params      = omap_mcbsp_dai_hw_params,
 583         .set_fmt        = omap_mcbsp_dai_set_dai_fmt,
 584         .set_clkdiv     = omap_mcbsp_dai_set_clkdiv,
 585         .set_sysclk     = omap_mcbsp_dai_set_dai_sysclk,
 586 };
 587
 588 static int omap_mcbsp_probe(struct snd_soc_dai *dai)
 589 {
 590         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
 591
 592         pm_runtime_enable(mcbsp->dev);
 593
 594         return 0;
 595 }
 596
 597 static int omap_mcbsp_remove(struct snd_soc_dai *dai)
 598 {
 599         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(dai);
 600
 601         pm_runtime_disable(mcbsp->dev);
 602
 603         return 0;
 604 }
 605
 606 static struct snd_soc_dai_driver omap_mcbsp_dai = {
 607         .probe = omap_mcbsp_probe,
 608         .remove = omap_mcbsp_remove,
 609         .playback = {
 610                 .channels_min = 1,
 611                 .channels_max = 16,
 612                 .rates = OMAP_MCBSP_RATES,
 613                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
 614         },
 615         .capture = {
 616                 .channels_min = 1,
 617                 .channels_max = 16,
 618                 .rates = OMAP_MCBSP_RATES,
 619                 .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S32_LE,
 620         },
 621         .ops = &mcbsp_dai_ops,
 622 };
 623
 624 static int omap_mcbsp_st_info_volsw(struct snd_kcontrol *kcontrol,
 625                         struct snd_ctl_elem_info *uinfo)
 626 {
 627         struct soc_mixer_control *mc =
 628                 (struct soc_mixer_control *)kcontrol->private_value;
 629         int max = mc->max;
 630         int min = mc->min;
 631
 632         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
 633         uinfo->count = 1;
 634         uinfo->value.integer.min = min;
 635         uinfo->value.integer.max = max;
 636         return 0;
 637 }
 638
 639 #define OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(channel)                       \
 640 static int                                                              \
 641 omap_mcbsp_set_st_ch##channel##_volume(struct snd_kcontrol *kc, \
 642                                         struct snd_ctl_elem_value *uc)  \
 643 {                                                                       \
 644         struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kc);            \
 645         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);    \
 646         struct soc_mixer_control *mc =                                  \
 647                 (struct soc_mixer_control *)kc->private_value;          \
 648         int max = mc->max;                                              \
 649         int min = mc->min;                                              \
 650         int val = uc->value.integer.value[0];                           \
 651                                                                         \
 652         if (val < min || val > max)                                     \
 653                 return -EINVAL;                                         \
 654                                                                         \
 655         /* OMAP McBSP implementation uses index values 0..4 */          \
 656         return omap_st_set_chgain(mcbsp, channel, val);                 \
 657 }
 658
 659 #define OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(channel)                       \
 660 static int                                                              \
 661 omap_mcbsp_get_st_ch##channel##_volume(struct snd_kcontrol *kc, \
 662                                         struct snd_ctl_elem_value *uc)  \
 663 {                                                                       \
 664         struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kc);            \
 665         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);    \
 666         s16 chgain;                                                     \
 667                                                                         \
 668         if (omap_st_get_chgain(mcbsp, channel, &chgain))                \
 669                 return -EAGAIN;                                         \
 670                                                                         \
 671         uc->value.integer.value[0] = chgain;                            \
 672         return 0;                                                       \
 673 }
 674
 675 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(0)
 676 OMAP_MCBSP_ST_SET_CHANNEL_VOLUME(1)
 677 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(0)
 678 OMAP_MCBSP_ST_GET_CHANNEL_VOLUME(1)
 679
 680 static int omap_mcbsp_st_put_mode(struct snd_kcontrol *kcontrol,
 681                                 struct snd_ctl_elem_value *ucontrol)
 682 {
 683         struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
 684         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 685         u8 value = ucontrol->value.integer.value[0];
 686
 687         if (value == omap_st_is_enabled(mcbsp))
 688                 return 0;
 689
 690         if (value)
 691                 omap_st_enable(mcbsp);
 692         else
 693                 omap_st_disable(mcbsp);
 694
 695         return 1;
 696 }
 697
 698 static int omap_mcbsp_st_get_mode(struct snd_kcontrol *kcontrol,
 699                                 struct snd_ctl_elem_value *ucontrol)
 700 {
 701         struct snd_soc_dai *cpu_dai = snd_kcontrol_chip(kcontrol);
 702         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 703
 704         ucontrol->value.integer.value[0] = omap_st_is_enabled(mcbsp);
 705         return 0;
 706 }
 707
 708 static const struct snd_kcontrol_new omap_mcbsp2_st_controls[] = {
 709         SOC_SINGLE_EXT("McBSP2 Sidetone Switch", 1, 0, 1, 0,
 710                         omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),
 711         OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 0 Volume",
 712                                       -32768, 32767,
 713                                       omap_mcbsp_get_st_ch0_volume,
 714                                       omap_mcbsp_set_st_ch0_volume),
 715         OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP2 Sidetone Channel 1 Volume",
 716                                       -32768, 32767,
 717                                       omap_mcbsp_get_st_ch1_volume,
 718                                       omap_mcbsp_set_st_ch1_volume),
 719 };
 720
 721 static const struct snd_kcontrol_new omap_mcbsp3_st_controls[] = {
 722         SOC_SINGLE_EXT("McBSP3 Sidetone Switch", 2, 0, 1, 0,
 723                         omap_mcbsp_st_get_mode, omap_mcbsp_st_put_mode),
 724         OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 0 Volume",
 725                                       -32768, 32767,
 726                                       omap_mcbsp_get_st_ch0_volume,
 727                                       omap_mcbsp_set_st_ch0_volume),
 728         OMAP_MCBSP_SOC_SINGLE_S16_EXT("McBSP3 Sidetone Channel 1 Volume",
 729                                       -32768, 32767,
 730                                       omap_mcbsp_get_st_ch1_volume,
 731                                       omap_mcbsp_set_st_ch1_volume),
 732 };
 733
 734 int omap_mcbsp_st_add_controls(struct snd_soc_pcm_runtime *rtd)
 735 {
 736         struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
 737         struct omap_mcbsp *mcbsp = snd_soc_dai_get_drvdata(cpu_dai);
 738
 739         if (!mcbsp->st_data)
 740                 return -ENODEV;
 741
 742         switch (cpu_dai->id) {
 743         case 2: /* McBSP 2 */
 744                 return snd_soc_add_dai_controls(cpu_dai,
 745                                         omap_mcbsp2_st_controls,
 746                                         ARRAY_SIZE(omap_mcbsp2_st_controls));
 747         case 3: /* McBSP 3 */
 748                 return snd_soc_add_dai_controls(cpu_dai,
 749                                         omap_mcbsp3_st_controls,
 750                                         ARRAY_SIZE(omap_mcbsp3_st_controls));
 751         default:
 752                 break;
 753         }
 754
 755         return -EINVAL;
 756 }
 757 EXPORT_SYMBOL_GPL(omap_mcbsp_st_add_controls);
 758
 759 static __devinit int asoc_mcbsp_probe(struct platform_device *pdev)
 760 {
 761         struct omap_mcbsp_platform_data *pdata = dev_get_platdata(&pdev->dev);
 762         struct omap_mcbsp *mcbsp;
 763         int ret;
 764
 765         if (!pdata) {
 766                 dev_err(&pdev->dev, "missing platform data.\n");
 767                 return -EINVAL;
 768         }
 769         mcbsp = devm_kzalloc(&pdev->dev, sizeof(struct omap_mcbsp), GFP_KERNEL);
 770         if (!mcbsp)
 771                 return -ENOMEM;
 772
 773         mcbsp->id = pdev->id;
 774         mcbsp->pdata = pdata;
 775         mcbsp->dev = &pdev->dev;
 776         platform_set_drvdata(pdev, mcbsp);
 777
 778         ret = omap_mcbsp_init(pdev);
 779         if (!ret)
 780                 return snd_soc_register_dai(&pdev->dev, &omap_mcbsp_dai);
 781
 782         return ret;
 783 }
 784
 785 static int __devexit asoc_mcbsp_remove(struct platform_device *pdev)
 786 {
 787         struct omap_mcbsp *mcbsp = platform_get_drvdata(pdev);
 788
 789         snd_soc_unregister_dai(&pdev->dev);
 790
 791         if (mcbsp->pdata->ops && mcbsp->pdata->ops->free)
 792                 mcbsp->pdata->ops->free(mcbsp->id);
 793
 794         omap_mcbsp_sysfs_remove(mcbsp);
 795
 796         clk_put(mcbsp->fclk);
 797
 798         platform_set_drvdata(pdev, NULL);
 799
 800         return 0;
 801 }
 802
 803 static struct platform_driver asoc_mcbsp_driver = {
 804         .driver = {
 805                         .name = "omap-mcbsp",
 806                         .owner = THIS_MODULE,
 807         },
 808
 809         .probe = asoc_mcbsp_probe,
 810         .remove = __devexit_p(asoc_mcbsp_remove),
 811 };
 812
 813 module_platform_driver(asoc_mcbsp_driver);
 814
 815 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@bitmer.com>");
 816 MODULE_DESCRIPTION("OMAP I2S SoC Interface");
 817 MODULE_LICENSE("GPL");