2 * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
3 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
5 * Based on code from Freescale,
6 * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
22 #include <linux/init.h>
23 #include <linux/interrupt.h>
25 #include <linux/irq.h>
26 #include <linux/gpio.h>
27 #include <linux/platform_device.h>
28 #include <linux/slab.h>
29 #include <linux/basic_mmio_gpio.h>
31 #include <linux/of_device.h>
32 #include <asm-generic/bug.h>
33 #include <asm/mach/irq.h>
35 #define irq_to_gpio(irq) ((irq) - MXC_GPIO_IRQ_START)
37 enum mxc_gpio_hwtype
{
38 IMX1_GPIO
, /* runs on i.mx1 */
39 IMX21_GPIO
, /* runs on i.mx21 and i.mx27 */
40 IMX31_GPIO
, /* runs on all other i.mx */
43 /* device type dependent stuff */
44 struct mxc_gpio_hwdata
{
58 struct mxc_gpio_port
{
59 struct list_head node
;
63 int virtual_irq_start
;
64 struct bgpio_chip bgc
;
68 static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata
= {
82 static struct mxc_gpio_hwdata imx31_gpio_hwdata
= {
96 static enum mxc_gpio_hwtype mxc_gpio_hwtype
;
97 static struct mxc_gpio_hwdata
*mxc_gpio_hwdata
;
99 #define GPIO_DR (mxc_gpio_hwdata->dr_reg)
100 #define GPIO_GDIR (mxc_gpio_hwdata->gdir_reg)
101 #define GPIO_PSR (mxc_gpio_hwdata->psr_reg)
102 #define GPIO_ICR1 (mxc_gpio_hwdata->icr1_reg)
103 #define GPIO_ICR2 (mxc_gpio_hwdata->icr2_reg)
104 #define GPIO_IMR (mxc_gpio_hwdata->imr_reg)
105 #define GPIO_ISR (mxc_gpio_hwdata->isr_reg)
107 #define GPIO_INT_LOW_LEV (mxc_gpio_hwdata->low_level)
108 #define GPIO_INT_HIGH_LEV (mxc_gpio_hwdata->high_level)
109 #define GPIO_INT_RISE_EDGE (mxc_gpio_hwdata->rise_edge)
110 #define GPIO_INT_FALL_EDGE (mxc_gpio_hwdata->fall_edge)
111 #define GPIO_INT_NONE 0x4
113 static struct platform_device_id mxc_gpio_devtype
[] = {
116 .driver_data
= IMX1_GPIO
,
118 .name
= "imx21-gpio",
119 .driver_data
= IMX21_GPIO
,
121 .name
= "imx31-gpio",
122 .driver_data
= IMX31_GPIO
,
128 static const struct of_device_id mxc_gpio_dt_ids
[] = {
129 { .compatible
= "fsl,imx1-gpio", .data
= &mxc_gpio_devtype
[IMX1_GPIO
], },
130 { .compatible
= "fsl,imx21-gpio", .data
= &mxc_gpio_devtype
[IMX21_GPIO
], },
131 { .compatible
= "fsl,imx31-gpio", .data
= &mxc_gpio_devtype
[IMX31_GPIO
], },
136 * MX2 has one interrupt *for all* gpio ports. The list is used
137 * to save the references to all ports, so that mx2_gpio_irq_handler
138 * can walk through all interrupt status registers.
140 static LIST_HEAD(mxc_gpio_ports
);
142 /* Note: This driver assumes 32 GPIOs are handled in one register */
144 static int gpio_set_irq_type(struct irq_data
*d
, u32 type
)
146 u32 gpio
= irq_to_gpio(d
->irq
);
147 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
148 struct mxc_gpio_port
*port
= gc
->private;
151 void __iomem
*reg
= port
->base
;
153 port
->both_edges
&= ~(1 << (gpio
& 31));
155 case IRQ_TYPE_EDGE_RISING
:
156 edge
= GPIO_INT_RISE_EDGE
;
158 case IRQ_TYPE_EDGE_FALLING
:
159 edge
= GPIO_INT_FALL_EDGE
;
161 case IRQ_TYPE_EDGE_BOTH
:
162 val
= gpio_get_value(gpio
);
164 edge
= GPIO_INT_LOW_LEV
;
165 pr_debug("mxc: set GPIO %d to low trigger\n", gpio
);
167 edge
= GPIO_INT_HIGH_LEV
;
168 pr_debug("mxc: set GPIO %d to high trigger\n", gpio
);
170 port
->both_edges
|= 1 << (gpio
& 31);
172 case IRQ_TYPE_LEVEL_LOW
:
173 edge
= GPIO_INT_LOW_LEV
;
175 case IRQ_TYPE_LEVEL_HIGH
:
176 edge
= GPIO_INT_HIGH_LEV
;
182 reg
+= GPIO_ICR1
+ ((gpio
& 0x10) >> 2); /* lower or upper register */
184 val
= readl(reg
) & ~(0x3 << (bit
<< 1));
185 writel(val
| (edge
<< (bit
<< 1)), reg
);
186 writel(1 << (gpio
& 0x1f), port
->base
+ GPIO_ISR
);
191 static void mxc_flip_edge(struct mxc_gpio_port
*port
, u32 gpio
)
193 void __iomem
*reg
= port
->base
;
197 reg
+= GPIO_ICR1
+ ((gpio
& 0x10) >> 2); /* lower or upper register */
200 edge
= (val
>> (bit
<< 1)) & 3;
201 val
&= ~(0x3 << (bit
<< 1));
202 if (edge
== GPIO_INT_HIGH_LEV
) {
203 edge
= GPIO_INT_LOW_LEV
;
204 pr_debug("mxc: switch GPIO %d to low trigger\n", gpio
);
205 } else if (edge
== GPIO_INT_LOW_LEV
) {
206 edge
= GPIO_INT_HIGH_LEV
;
207 pr_debug("mxc: switch GPIO %d to high trigger\n", gpio
);
209 pr_err("mxc: invalid configuration for GPIO %d: %x\n",
213 writel(val
| (edge
<< (bit
<< 1)), reg
);
216 /* handle 32 interrupts in one status register */
217 static void mxc_gpio_irq_handler(struct mxc_gpio_port
*port
, u32 irq_stat
)
219 u32 gpio_irq_no_base
= port
->virtual_irq_start
;
221 while (irq_stat
!= 0) {
222 int irqoffset
= fls(irq_stat
) - 1;
224 if (port
->both_edges
& (1 << irqoffset
))
225 mxc_flip_edge(port
, irqoffset
);
227 generic_handle_irq(gpio_irq_no_base
+ irqoffset
);
229 irq_stat
&= ~(1 << irqoffset
);
233 /* MX1 and MX3 has one interrupt *per* gpio port */
234 static void mx3_gpio_irq_handler(u32 irq
, struct irq_desc
*desc
)
237 struct mxc_gpio_port
*port
= irq_get_handler_data(irq
);
238 struct irq_chip
*chip
= irq_get_chip(irq
);
240 chained_irq_enter(chip
, desc
);
242 irq_stat
= readl(port
->base
+ GPIO_ISR
) & readl(port
->base
+ GPIO_IMR
);
244 mxc_gpio_irq_handler(port
, irq_stat
);
246 chained_irq_exit(chip
, desc
);
249 /* MX2 has one interrupt *for all* gpio ports */
250 static void mx2_gpio_irq_handler(u32 irq
, struct irq_desc
*desc
)
252 u32 irq_msk
, irq_stat
;
253 struct mxc_gpio_port
*port
;
255 /* walk through all interrupt status registers */
256 list_for_each_entry(port
, &mxc_gpio_ports
, node
) {
257 irq_msk
= readl(port
->base
+ GPIO_IMR
);
261 irq_stat
= readl(port
->base
+ GPIO_ISR
) & irq_msk
;
263 mxc_gpio_irq_handler(port
, irq_stat
);
268 * Set interrupt number "irq" in the GPIO as a wake-up source.
269 * While system is running, all registered GPIO interrupts need to have
270 * wake-up enabled. When system is suspended, only selected GPIO interrupts
271 * need to have wake-up enabled.
272 * @param irq interrupt source number
273 * @param enable enable as wake-up if equal to non-zero
274 * @return This function returns 0 on success.
276 static int gpio_set_wake_irq(struct irq_data
*d
, u32 enable
)
278 u32 gpio
= irq_to_gpio(d
->irq
);
279 u32 gpio_idx
= gpio
& 0x1F;
280 struct irq_chip_generic
*gc
= irq_data_get_irq_chip_data(d
);
281 struct mxc_gpio_port
*port
= gc
->private;
284 if (port
->irq_high
&& (gpio_idx
>= 16))
285 enable_irq_wake(port
->irq_high
);
287 enable_irq_wake(port
->irq
);
289 if (port
->irq_high
&& (gpio_idx
>= 16))
290 disable_irq_wake(port
->irq_high
);
292 disable_irq_wake(port
->irq
);
298 static void __init
mxc_gpio_init_gc(struct mxc_gpio_port
*port
)
300 struct irq_chip_generic
*gc
;
301 struct irq_chip_type
*ct
;
303 gc
= irq_alloc_generic_chip("gpio-mxc", 1, port
->virtual_irq_start
,
304 port
->base
, handle_level_irq
);
308 ct
->chip
.irq_ack
= irq_gc_ack_set_bit
;
309 ct
->chip
.irq_mask
= irq_gc_mask_clr_bit
;
310 ct
->chip
.irq_unmask
= irq_gc_mask_set_bit
;
311 ct
->chip
.irq_set_type
= gpio_set_irq_type
;
312 ct
->chip
.irq_set_wake
= gpio_set_wake_irq
;
313 ct
->regs
.ack
= GPIO_ISR
;
314 ct
->regs
.mask
= GPIO_IMR
;
316 irq_setup_generic_chip(gc
, IRQ_MSK(32), IRQ_GC_INIT_NESTED_LOCK
,
320 static void __devinit
mxc_gpio_get_hw(struct platform_device
*pdev
)
322 const struct of_device_id
*of_id
=
323 of_match_device(mxc_gpio_dt_ids
, &pdev
->dev
);
324 enum mxc_gpio_hwtype hwtype
;
327 pdev
->id_entry
= of_id
->data
;
328 hwtype
= pdev
->id_entry
->driver_data
;
330 if (mxc_gpio_hwtype
) {
332 * The driver works with a reasonable presupposition,
333 * that is all gpio ports must be the same type when
334 * running on one soc.
336 BUG_ON(mxc_gpio_hwtype
!= hwtype
);
340 if (hwtype
== IMX31_GPIO
)
341 mxc_gpio_hwdata
= &imx31_gpio_hwdata
;
343 mxc_gpio_hwdata
= &imx1_imx21_gpio_hwdata
;
345 mxc_gpio_hwtype
= hwtype
;
348 static int mxc_gpio_to_irq(struct gpio_chip
*gc
, unsigned offset
)
350 struct bgpio_chip
*bgc
= to_bgpio_chip(gc
);
351 struct mxc_gpio_port
*port
=
352 container_of(bgc
, struct mxc_gpio_port
, bgc
);
354 return port
->virtual_irq_start
+ offset
;
357 static int __devinit
mxc_gpio_probe(struct platform_device
*pdev
)
359 struct device_node
*np
= pdev
->dev
.of_node
;
360 struct mxc_gpio_port
*port
;
361 struct resource
*iores
;
364 mxc_gpio_get_hw(pdev
);
366 port
= kzalloc(sizeof(struct mxc_gpio_port
), GFP_KERNEL
);
370 iores
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
376 if (!request_mem_region(iores
->start
, resource_size(iores
),
382 port
->base
= ioremap(iores
->start
, resource_size(iores
));
385 goto out_release_mem
;
388 port
->irq_high
= platform_get_irq(pdev
, 1);
389 port
->irq
= platform_get_irq(pdev
, 0);
395 /* disable the interrupt and clear the status */
396 writel(0, port
->base
+ GPIO_IMR
);
397 writel(~0, port
->base
+ GPIO_ISR
);
399 if (mxc_gpio_hwtype
== IMX21_GPIO
) {
400 /* setup one handler for all GPIO interrupts */
402 irq_set_chained_handler(port
->irq
,
403 mx2_gpio_irq_handler
);
405 /* setup one handler for each entry */
406 irq_set_chained_handler(port
->irq
, mx3_gpio_irq_handler
);
407 irq_set_handler_data(port
->irq
, port
);
408 if (port
->irq_high
> 0) {
409 /* setup handler for GPIO 16 to 31 */
410 irq_set_chained_handler(port
->irq_high
,
411 mx3_gpio_irq_handler
);
412 irq_set_handler_data(port
->irq_high
, port
);
416 err
= bgpio_init(&port
->bgc
, &pdev
->dev
, 4,
417 port
->base
+ GPIO_PSR
,
418 port
->base
+ GPIO_DR
, NULL
,
419 port
->base
+ GPIO_GDIR
, NULL
, false);
423 port
->bgc
.gc
.to_irq
= mxc_gpio_to_irq
;
424 port
->bgc
.gc
.base
= pdev
->id
* 32;
425 port
->bgc
.dir
= port
->bgc
.read_reg(port
->bgc
.reg_dir
);
426 port
->bgc
.data
= port
->bgc
.read_reg(port
->bgc
.reg_set
);
428 err
= gpiochip_add(&port
->bgc
.gc
);
430 goto out_bgpio_remove
;
433 * In dt case, we use gpio number range dynamically
434 * allocated by gpio core.
436 port
->virtual_irq_start
= MXC_GPIO_IRQ_START
+ (np
? port
->bgc
.gc
.base
:
439 /* gpio-mxc can be a generic irq chip */
440 mxc_gpio_init_gc(port
);
442 list_add_tail(&port
->node
, &mxc_gpio_ports
);
447 bgpio_remove(&port
->bgc
);
451 release_mem_region(iores
->start
, resource_size(iores
));
454 dev_info(&pdev
->dev
, "%s failed with errno %d\n", __func__
, err
);
458 static struct platform_driver mxc_gpio_driver
= {
461 .owner
= THIS_MODULE
,
462 .of_match_table
= mxc_gpio_dt_ids
,
464 .probe
= mxc_gpio_probe
,
465 .id_table
= mxc_gpio_devtype
,
468 static int __init
gpio_mxc_init(void)
470 return platform_driver_register(&mxc_gpio_driver
);
472 postcore_initcall(gpio_mxc_init
);
474 MODULE_AUTHOR("Freescale Semiconductor, "
475 "Daniel Mack <danielncaiaq.de>, "
476 "Juergen Beisert <kernel@pengutronix.de>");
477 MODULE_DESCRIPTION("Freescale MXC GPIO");
478 MODULE_LICENSE("GPL");