drivers/net/sfc/net_driver.h

   1 /****************************************************************************
   2  * Driver for Solarflare Solarstorm network controllers and boards
   3  * Copyright 2005-2006 Fen Systems Ltd.
   4  * Copyright 2005-2008 Solarflare Communications Inc.
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation, incorporated herein by reference.
   9  */
  10
  11 /* Common definitions for all Efx net driver code */
  12
  13 #ifndef EFX_NET_DRIVER_H
  14 #define EFX_NET_DRIVER_H
  15
  16 #include <linux/version.h>
  17 #include <linux/netdevice.h>
  18 #include <linux/etherdevice.h>
  19 #include <linux/ethtool.h>
  20 #include <linux/if_vlan.h>
  21 #include <linux/timer.h>
  22 #include <linux/mdio.h>
  23 #include <linux/list.h>
  24 #include <linux/pci.h>
  25 #include <linux/device.h>
  26 #include <linux/highmem.h>
  27 #include <linux/workqueue.h>
  28 #include <linux/i2c.h>
  29
  30 #include "enum.h"
  31 #include "bitfield.h"
  32
  33 /**************************************************************************
  34  *
  35  * Build definitions
  36  *
  37  **************************************************************************/
  38 #ifndef EFX_DRIVER_NAME
  39 #define EFX_DRIVER_NAME "sfc"
  40 #endif
  41 #define EFX_DRIVER_VERSION      "2.3"
  42
  43 #ifdef EFX_ENABLE_DEBUG
  44 #define EFX_BUG_ON_PARANOID(x) BUG_ON(x)
  45 #define EFX_WARN_ON_PARANOID(x) WARN_ON(x)
  46 #else
  47 #define EFX_BUG_ON_PARANOID(x) do {} while (0)
  48 #define EFX_WARN_ON_PARANOID(x) do {} while (0)
  49 #endif
  50
  51 /* Un-rate-limited logging */
  52 #define EFX_ERR(efx, fmt, args...) \
  53 dev_err(&((efx)->pci_dev->dev), "ERR: %s " fmt, efx_dev_name(efx), ##args)
  54
  55 #define EFX_INFO(efx, fmt, args...) \
  56 dev_info(&((efx)->pci_dev->dev), "INFO: %s " fmt, efx_dev_name(efx), ##args)
  57
  58 #ifdef EFX_ENABLE_DEBUG
  59 #define EFX_LOG(efx, fmt, args...) \
  60 dev_info(&((efx)->pci_dev->dev), "DBG: %s " fmt, efx_dev_name(efx), ##args)
  61 #else
  62 #define EFX_LOG(efx, fmt, args...) \
  63 dev_dbg(&((efx)->pci_dev->dev), "DBG: %s " fmt, efx_dev_name(efx), ##args)
  64 #endif
  65
  66 #define EFX_TRACE(efx, fmt, args...) do {} while (0)
  67
  68 #define EFX_REGDUMP(efx, fmt, args...) do {} while (0)
  69
  70 /* Rate-limited logging */
  71 #define EFX_ERR_RL(efx, fmt, args...) \
  72 do {if (net_ratelimit()) EFX_ERR(efx, fmt, ##args); } while (0)
  73
  74 #define EFX_INFO_RL(efx, fmt, args...) \
  75 do {if (net_ratelimit()) EFX_INFO(efx, fmt, ##args); } while (0)
  76
  77 #define EFX_LOG_RL(efx, fmt, args...) \
  78 do {if (net_ratelimit()) EFX_LOG(efx, fmt, ##args); } while (0)
  79
  80 /**************************************************************************
  81  *
  82  * Efx data structures
  83  *
  84  **************************************************************************/
  85
  86 #define EFX_MAX_CHANNELS 32
  87 #define EFX_MAX_RX_QUEUES EFX_MAX_CHANNELS
  88
  89 #define EFX_TX_QUEUE_OFFLOAD_CSUM       0
  90 #define EFX_TX_QUEUE_NO_CSUM            1
  91 #define EFX_TX_QUEUE_COUNT              2
  92
  93 /**
  94  * struct efx_special_buffer - An Efx special buffer
  95  * @addr: CPU base address of the buffer
  96  * @dma_addr: DMA base address of the buffer
  97  * @len: Buffer length, in bytes
  98  * @index: Buffer index within controller;s buffer table
  99  * @entries: Number of buffer table entries
 100  *
 101  * Special buffers are used for the event queues and the TX and RX
 102  * descriptor queues for each channel.  They are *not* used for the
 103  * actual transmit and receive buffers.
 104  *
 105  * Note that for Falcon, TX and RX descriptor queues live in host memory.
 106  * Allocation and freeing procedures must take this into account.
 107  */
 108 struct efx_special_buffer {
 109         void *addr;
 110         dma_addr_t dma_addr;
 111         unsigned int len;
 112         int index;
 113         int entries;
 114 };
 115
 116 /**
 117  * struct efx_tx_buffer - An Efx TX buffer
 118  * @skb: The associated socket buffer.
 119  *      Set only on the final fragment of a packet; %NULL for all other
 120  *      fragments.  When this fragment completes, then we can free this
 121  *      skb.
 122  * @tsoh: The associated TSO header structure, or %NULL if this
 123  *      buffer is not a TSO header.
 124  * @dma_addr: DMA address of the fragment.
 125  * @len: Length of this fragment.
 126  *      This field is zero when the queue slot is empty.
 127  * @continuation: True if this fragment is not the end of a packet.
 128  * @unmap_single: True if pci_unmap_single should be used.
 129  * @unmap_len: Length of this fragment to unmap
 130  */
 131 struct efx_tx_buffer {
 132         const struct sk_buff *skb;
 133         struct efx_tso_header *tsoh;
 134         dma_addr_t dma_addr;
 135         unsigned short len;
 136         bool continuation;
 137         bool unmap_single;
 138         unsigned short unmap_len;
 139 };
 140
 141 /**
 142  * struct efx_tx_queue - An Efx TX queue
 143  *
 144  * This is a ring buffer of TX fragments.
 145  * Since the TX completion path always executes on the same
 146  * CPU and the xmit path can operate on different CPUs,
 147  * performance is increased by ensuring that the completion
 148  * path and the xmit path operate on different cache lines.
 149  * This is particularly important if the xmit path is always
 150  * executing on one CPU which is different from the completion
 151  * path.  There is also a cache line for members which are
 152  * read but not written on the fast path.
 153  *
 154  * @efx: The associated Efx NIC
 155  * @queue: DMA queue number
 156  * @channel: The associated channel
 157  * @buffer: The software buffer ring
 158  * @txd: The hardware descriptor ring
 159  * @flushed: Used when handling queue flushing
 160  * @read_count: Current read pointer.
 161  *      This is the number of buffers that have been removed from both rings.
 162  * @stopped: Stopped count.
 163  *      Set if this TX queue is currently stopping its port.
 164  * @insert_count: Current insert pointer
 165  *      This is the number of buffers that have been added to the
 166  *      software ring.
 167  * @write_count: Current write pointer
 168  *      This is the number of buffers that have been added to the
 169  *      hardware ring.
 170  * @old_read_count: The value of read_count when last checked.
 171  *      This is here for performance reasons.  The xmit path will
 172  *      only get the up-to-date value of read_count if this
 173  *      variable indicates that the queue is full.  This is to
 174  *      avoid cache-line ping-pong between the xmit path and the
 175  *      completion path.
 176  * @tso_headers_free: A list of TSO headers allocated for this TX queue
 177  *      that are not in use, and so available for new TSO sends. The list
 178  *      is protected by the TX queue lock.
 179  * @tso_bursts: Number of times TSO xmit invoked by kernel
 180  * @tso_long_headers: Number of packets with headers too long for standard
 181  *      blocks
 182  * @tso_packets: Number of packets via the TSO xmit path
 183  */
 184 struct efx_tx_queue {
 185         /* Members which don't change on the fast path */
 186         struct efx_nic *efx ____cacheline_aligned_in_smp;
 187         int queue;
 188         struct efx_channel *channel;
 189         struct efx_nic *nic;
 190         struct efx_tx_buffer *buffer;
 191         struct efx_special_buffer txd;
 192         bool flushed;
 193
 194         /* Members used mainly on the completion path */
 195         unsigned int read_count ____cacheline_aligned_in_smp;
 196         int stopped;
 197
 198         /* Members used only on the xmit path */
 199         unsigned int insert_count ____cacheline_aligned_in_smp;
 200         unsigned int write_count;
 201         unsigned int old_read_count;
 202         struct efx_tso_header *tso_headers_free;
 203         unsigned int tso_bursts;
 204         unsigned int tso_long_headers;
 205         unsigned int tso_packets;
 206 };
 207
 208 /**
 209  * struct efx_rx_buffer - An Efx RX data buffer
 210  * @dma_addr: DMA base address of the buffer
 211  * @skb: The associated socket buffer, if any.
 212  *      If both this and page are %NULL, the buffer slot is currently free.
 213  * @page: The associated page buffer, if any.
 214  *      If both this and skb are %NULL, the buffer slot is currently free.
 215  * @data: Pointer to ethernet header
 216  * @len: Buffer length, in bytes.
 217  * @unmap_addr: DMA address to unmap
 218  */
 219 struct efx_rx_buffer {
 220         dma_addr_t dma_addr;
 221         struct sk_buff *skb;
 222         struct page *page;
 223         char *data;
 224         unsigned int len;
 225         dma_addr_t unmap_addr;
 226 };
 227
 228 /**
 229  * struct efx_rx_queue - An Efx RX queue
 230  * @efx: The associated Efx NIC
 231  * @queue: DMA queue number
 232  * @channel: The associated channel
 233  * @buffer: The software buffer ring
 234  * @rxd: The hardware descriptor ring
 235  * @added_count: Number of buffers added to the receive queue.
 236  * @notified_count: Number of buffers given to NIC (<= @added_count).
 237  * @removed_count: Number of buffers removed from the receive queue.
 238  * @add_lock: Receive queue descriptor add spin lock.
 239  *      This lock must be held in order to add buffers to the RX
 240  *      descriptor ring (rxd and buffer) and to update added_count (but
 241  *      not removed_count).
 242  * @max_fill: RX descriptor maximum fill level (<= ring size)
 243  * @fast_fill_trigger: RX descriptor fill level that will trigger a fast fill
 244  *      (<= @max_fill)
 245  * @fast_fill_limit: The level to which a fast fill will fill
 246  *      (@fast_fill_trigger <= @fast_fill_limit <= @max_fill)
 247  * @min_fill: RX descriptor minimum non-zero fill level.
 248  *      This records the minimum fill level observed when a ring
 249  *      refill was triggered.
 250  * @min_overfill: RX descriptor minimum overflow fill level.
 251  *      This records the minimum fill level at which RX queue
 252  *      overflow was observed.  It should never be set.
 253  * @alloc_page_count: RX allocation strategy counter.
 254  * @alloc_skb_count: RX allocation strategy counter.
 255  * @work: Descriptor push work thread
 256  * @buf_page: Page for next RX buffer.
 257  *      We can use a single page for multiple RX buffers. This tracks
 258  *      the remaining space in the allocation.
 259  * @buf_dma_addr: Page's DMA address.
 260  * @buf_data: Page's host address.
 261  * @flushed: Use when handling queue flushing
 262  */
 263 struct efx_rx_queue {
 264         struct efx_nic *efx;
 265         int queue;
 266         struct efx_channel *channel;
 267         struct efx_rx_buffer *buffer;
 268         struct efx_special_buffer rxd;
 269
 270         int added_count;
 271         int notified_count;
 272         int removed_count;
 273         spinlock_t add_lock;
 274         unsigned int max_fill;
 275         unsigned int fast_fill_trigger;
 276         unsigned int fast_fill_limit;
 277         unsigned int min_fill;
 278         unsigned int min_overfill;
 279         unsigned int alloc_page_count;
 280         unsigned int alloc_skb_count;
 281         struct delayed_work work;
 282         unsigned int slow_fill_count;
 283
 284         struct page *buf_page;
 285         dma_addr_t buf_dma_addr;
 286         char *buf_data;
 287         bool flushed;
 288 };
 289
 290 /**
 291  * struct efx_buffer - An Efx general-purpose buffer
 292  * @addr: host base address of the buffer
 293  * @dma_addr: DMA base address of the buffer
 294  * @len: Buffer length, in bytes
 295  *
 296  * Falcon uses these buffers for its interrupt status registers and
 297  * MAC stats dumps.
 298  */
 299 struct efx_buffer {
 300         void *addr;
 301         dma_addr_t dma_addr;
 302         unsigned int len;
 303 };
 304
 305
 306 /* Flags for channel->used_flags */
 307 #define EFX_USED_BY_RX 1
 308 #define EFX_USED_BY_TX 2
 309 #define EFX_USED_BY_RX_TX (EFX_USED_BY_RX | EFX_USED_BY_TX)
 310
 311 enum efx_rx_alloc_method {
 312         RX_ALLOC_METHOD_AUTO = 0,
 313         RX_ALLOC_METHOD_SKB = 1,
 314         RX_ALLOC_METHOD_PAGE = 2,
 315 };
 316
 317 /**
 318  * struct efx_channel - An Efx channel
 319  *
 320  * A channel comprises an event queue, at least one TX queue, at least
 321  * one RX queue, and an associated tasklet for processing the event
 322  * queue.
 323  *
 324  * @efx: Associated Efx NIC
 325  * @channel: Channel instance number
 326  * @name: Name for channel and IRQ
 327  * @used_flags: Channel is used by net driver
 328  * @enabled: Channel enabled indicator
 329  * @irq: IRQ number (MSI and MSI-X only)
 330  * @irq_moderation: IRQ moderation value (in hardware ticks)
 331  * @napi_dev: Net device used with NAPI
 332  * @napi_str: NAPI control structure
 333  * @reset_work: Scheduled reset work thread
 334  * @work_pending: Is work pending via NAPI?
 335  * @eventq: Event queue buffer
 336  * @eventq_read_ptr: Event queue read pointer
 337  * @last_eventq_read_ptr: Last event queue read pointer value.
 338  * @eventq_magic: Event queue magic value for driver-generated test events
 339  * @irq_count: Number of IRQs since last adaptive moderation decision
 340  * @irq_mod_score: IRQ moderation score
 341  * @rx_alloc_level: Watermark based heuristic counter for pushing descriptors
 342  *      and diagnostic counters
 343  * @rx_alloc_push_pages: RX allocation method currently in use for pushing
 344  *      descriptors
 345  * @n_rx_tobe_disc: Count of RX_TOBE_DISC errors
 346  * @n_rx_ip_frag_err: Count of RX IP fragment errors
 347  * @n_rx_ip_hdr_chksum_err: Count of RX IP header checksum errors
 348  * @n_rx_tcp_udp_chksum_err: Count of RX TCP and UDP checksum errors
 349  * @n_rx_frm_trunc: Count of RX_FRM_TRUNC errors
 350  * @n_rx_overlength: Count of RX_OVERLENGTH errors
 351  * @n_skbuff_leaks: Count of skbuffs leaked due to RX overrun
 352  */
 353 struct efx_channel {
 354         struct efx_nic *efx;
 355         int channel;
 356         char name[IFNAMSIZ + 6];
 357         int used_flags;
 358         bool enabled;
 359         int irq;
 360         unsigned int irq_moderation;
 361         struct net_device *napi_dev;
 362         struct napi_struct napi_str;
 363         bool work_pending;
 364         struct efx_special_buffer eventq;
 365         unsigned int eventq_read_ptr;
 366         unsigned int last_eventq_read_ptr;
 367         unsigned int eventq_magic;
 368
 369         unsigned int irq_count;
 370         unsigned int irq_mod_score;
 371
 372         int rx_alloc_level;
 373         int rx_alloc_push_pages;
 374
 375         unsigned n_rx_tobe_disc;
 376         unsigned n_rx_ip_frag_err;
 377         unsigned n_rx_ip_hdr_chksum_err;
 378         unsigned n_rx_tcp_udp_chksum_err;
 379         unsigned n_rx_frm_trunc;
 380         unsigned n_rx_overlength;
 381         unsigned n_skbuff_leaks;
 382
 383         /* Used to pipeline received packets in order to optimise memory
 384          * access with prefetches.
 385          */
 386         struct efx_rx_buffer *rx_pkt;
 387         bool rx_pkt_csummed;
 388
 389 };
 390
 391 enum efx_led_mode {
 392         EFX_LED_OFF     = 0,
 393         EFX_LED_ON      = 1,
 394         EFX_LED_DEFAULT = 2
 395 };
 396
 397 /**
 398  * struct efx_board - board information
 399  * @type: Board model type
 400  * @major: Major rev. ('A', 'B' ...)
 401  * @minor: Minor rev. (0, 1, ...)
 402  * @init: Initialisation function
 403  * @init_leds: Sets up board LEDs. May be called repeatedly.
 404  * @set_id_led: Set state of identifying LED or revert to automatic function
 405  * @monitor: Board-specific health check function
 406  * @fini: Cleanup function
 407  * @hwmon_client: I2C client for hardware monitor
 408  * @ioexp_client: I2C client for power/port control
 409  */
 410 struct efx_board {
 411         int type;
 412         int major;
 413         int minor;
 414         int (*init) (struct efx_nic *nic);
 415         /* As the LEDs are typically attached to the PHY, LEDs
 416          * have a separate init callback that happens later than
 417          * board init. */
 418         void (*init_leds)(struct efx_nic *efx);
 419         void (*set_id_led) (struct efx_nic *efx, enum efx_led_mode mode);
 420         int (*monitor) (struct efx_nic *nic);
 421         void (*fini) (struct efx_nic *nic);
 422         struct i2c_client *hwmon_client, *ioexp_client;
 423 };
 424
 425 #define STRING_TABLE_LOOKUP(val, member)        \
 426         member ## _names[val]
 427
 428 enum efx_int_mode {
 429         /* Be careful if altering to correct macro below */
 430         EFX_INT_MODE_MSIX = 0,
 431         EFX_INT_MODE_MSI = 1,
 432         EFX_INT_MODE_LEGACY = 2,
 433         EFX_INT_MODE_MAX        /* Insert any new items before this */
 434 };
 435 #define EFX_INT_MODE_USE_MSI(x) (((x)->interrupt_mode) <= EFX_INT_MODE_MSI)
 436
 437 enum phy_type {
 438         PHY_TYPE_NONE = 0,
 439         PHY_TYPE_TXC43128 = 1,
 440         PHY_TYPE_88E1111 = 2,
 441         PHY_TYPE_SFX7101 = 3,
 442         PHY_TYPE_QT2022C2 = 4,
 443         PHY_TYPE_PM8358 = 6,
 444         PHY_TYPE_SFT9001A = 8,
 445         PHY_TYPE_QT2025C = 9,
 446         PHY_TYPE_SFT9001B = 10,
 447         PHY_TYPE_MAX    /* Insert any new items before this */
 448 };
 449
 450 #define EFX_IS10G(efx) ((efx)->link_speed == 10000)
 451
 452 enum nic_state {
 453         STATE_INIT = 0,
 454         STATE_RUNNING = 1,
 455         STATE_FINI = 2,
 456         STATE_DISABLED = 3,
 457         STATE_MAX,
 458 };
 459
 460 /*
 461  * Alignment of page-allocated RX buffers
 462  *
 463  * Controls the number of bytes inserted at the start of an RX buffer.
 464  * This is the equivalent of NET_IP_ALIGN [which controls the alignment
 465  * of the skb->head for hardware DMA].
 466  */
 467 #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
 468 #define EFX_PAGE_IP_ALIGN 0
 469 #else
 470 #define EFX_PAGE_IP_ALIGN NET_IP_ALIGN
 471 #endif
 472
 473 /*
 474  * Alignment of the skb->head which wraps a page-allocated RX buffer
 475  *
 476  * The skb allocated to wrap an rx_buffer can have this alignment. Since
 477  * the data is memcpy'd from the rx_buf, it does not need to be equal to
 478  * EFX_PAGE_IP_ALIGN.
 479  */
 480 #define EFX_PAGE_SKB_ALIGN 2
 481
 482 /* Forward declaration */
 483 struct efx_nic;
 484
 485 /* Pseudo bit-mask flow control field */
 486 enum efx_fc_type {
 487         EFX_FC_RX = FLOW_CTRL_RX,
 488         EFX_FC_TX = FLOW_CTRL_TX,
 489         EFX_FC_AUTO = 4,
 490 };
 491
 492 /* Supported MAC bit-mask */
 493 enum efx_mac_type {
 494         EFX_GMAC = 1,
 495         EFX_XMAC = 2,
 496 };
 497
 498 /**
 499  * struct efx_mac_operations - Efx MAC operations table
 500  * @reconfigure: Reconfigure MAC. Serialised by the mac_lock
 501  * @update_stats: Update statistics
 502  * @irq: Hardware MAC event callback. Serialised by the mac_lock
 503  * @poll: Poll for hardware state. Serialised by the mac_lock
 504  */
 505 struct efx_mac_operations {
 506         void (*reconfigure) (struct efx_nic *efx);
 507         void (*update_stats) (struct efx_nic *efx);
 508         void (*irq) (struct efx_nic *efx);
 509         void (*poll) (struct efx_nic *efx);
 510 };
 511
 512 /**
 513  * struct efx_phy_operations - Efx PHY operations table
 514  * @init: Initialise PHY
 515  * @fini: Shut down PHY
 516  * @reconfigure: Reconfigure PHY (e.g. for new link parameters)
 517  * @clear_interrupt: Clear down interrupt
 518  * @poll: Poll for hardware state. Serialised by the mac_lock.
 519  * @get_settings: Get ethtool settings. Serialised by the mac_lock.
 520  * @set_settings: Set ethtool settings. Serialised by the mac_lock.
 521  * @set_npage_adv: Set abilities advertised in (Extended) Next Page
 522  *      (only needed where AN bit is set in mmds)
 523  * @num_tests: Number of PHY-specific tests/results
 524  * @test_names: Names of the tests/results
 525  * @run_tests: Run tests and record results as appropriate.
 526  *      Flags are the ethtool tests flags.
 527  * @mmds: MMD presence mask
 528  * @loopbacks: Supported loopback modes mask
 529  */
 530 struct efx_phy_operations {
 531         enum efx_mac_type macs;
 532         int (*init) (struct efx_nic *efx);
 533         void (*fini) (struct efx_nic *efx);
 534         void (*reconfigure) (struct efx_nic *efx);
 535         void (*clear_interrupt) (struct efx_nic *efx);
 536         void (*poll) (struct efx_nic *efx);
 537         void (*get_settings) (struct efx_nic *efx,
 538                               struct ethtool_cmd *ecmd);
 539         int (*set_settings) (struct efx_nic *efx,
 540                              struct ethtool_cmd *ecmd);
 541         void (*set_npage_adv) (struct efx_nic *efx, u32);
 542         u32 num_tests;
 543         const char *const *test_names;
 544         int (*run_tests) (struct efx_nic *efx, int *results, unsigned flags);
 545         int mmds;
 546         unsigned loopbacks;
 547 };
 548
 549 /**
 550  * @enum efx_phy_mode - PHY operating mode flags
 551  * @PHY_MODE_NORMAL: on and should pass traffic
 552  * @PHY_MODE_TX_DISABLED: on with TX disabled
 553  * @PHY_MODE_LOW_POWER: set to low power through MDIO
 554  * @PHY_MODE_OFF: switched off through external control
 555  * @PHY_MODE_SPECIAL: on but will not pass traffic
 556  */
 557 enum efx_phy_mode {
 558         PHY_MODE_NORMAL         = 0,
 559         PHY_MODE_TX_DISABLED    = 1,
 560         PHY_MODE_LOW_POWER      = 2,
 561         PHY_MODE_OFF            = 4,
 562         PHY_MODE_SPECIAL        = 8,
 563 };
 564
 565 static inline bool efx_phy_mode_disabled(enum efx_phy_mode mode)
 566 {
 567         return !!(mode & ~PHY_MODE_TX_DISABLED);
 568 }
 569
 570 /*
 571  * Efx extended statistics
 572  *
 573  * Not all statistics are provided by all supported MACs.  The purpose
 574  * is this structure is to contain the raw statistics provided by each
 575  * MAC.
 576  */
 577 struct efx_mac_stats {
 578         u64 tx_bytes;
 579         u64 tx_good_bytes;
 580         u64 tx_bad_bytes;
 581         unsigned long tx_packets;
 582         unsigned long tx_bad;
 583         unsigned long tx_pause;
 584         unsigned long tx_control;
 585         unsigned long tx_unicast;
 586         unsigned long tx_multicast;
 587         unsigned long tx_broadcast;
 588         unsigned long tx_lt64;
 589         unsigned long tx_64;
 590         unsigned long tx_65_to_127;
 591         unsigned long tx_128_to_255;
 592         unsigned long tx_256_to_511;
 593         unsigned long tx_512_to_1023;
 594         unsigned long tx_1024_to_15xx;
 595         unsigned long tx_15xx_to_jumbo;
 596         unsigned long tx_gtjumbo;
 597         unsigned long tx_collision;
 598         unsigned long tx_single_collision;
 599         unsigned long tx_multiple_collision;
 600         unsigned long tx_excessive_collision;
 601         unsigned long tx_deferred;
 602         unsigned long tx_late_collision;
 603         unsigned long tx_excessive_deferred;
 604         unsigned long tx_non_tcpudp;
 605         unsigned long tx_mac_src_error;
 606         unsigned long tx_ip_src_error;
 607         u64 rx_bytes;
 608         u64 rx_good_bytes;
 609         u64 rx_bad_bytes;
 610         unsigned long rx_packets;
 611         unsigned long rx_good;
 612         unsigned long rx_bad;
 613         unsigned long rx_pause;
 614         unsigned long rx_control;
 615         unsigned long rx_unicast;
 616         unsigned long rx_multicast;
 617         unsigned long rx_broadcast;
 618         unsigned long rx_lt64;
 619         unsigned long rx_64;
 620         unsigned long rx_65_to_127;
 621         unsigned long rx_128_to_255;
 622         unsigned long rx_256_to_511;
 623         unsigned long rx_512_to_1023;
 624         unsigned long rx_1024_to_15xx;
 625         unsigned long rx_15xx_to_jumbo;
 626         unsigned long rx_gtjumbo;
 627         unsigned long rx_bad_lt64;
 628         unsigned long rx_bad_64_to_15xx;
 629         unsigned long rx_bad_15xx_to_jumbo;
 630         unsigned long rx_bad_gtjumbo;
 631         unsigned long rx_overflow;
 632         unsigned long rx_missed;
 633         unsigned long rx_false_carrier;
 634         unsigned long rx_symbol_error;
 635         unsigned long rx_align_error;
 636         unsigned long rx_length_error;
 637         unsigned long rx_internal_error;
 638         unsigned long rx_good_lt64;
 639 };
 640
 641 /* Number of bits used in a multicast filter hash address */
 642 #define EFX_MCAST_HASH_BITS 8
 643
 644 /* Number of (single-bit) entries in a multicast filter hash */
 645 #define EFX_MCAST_HASH_ENTRIES (1 << EFX_MCAST_HASH_BITS)
 646
 647 /* An Efx multicast filter hash */
 648 union efx_multicast_hash {
 649         u8 byte[EFX_MCAST_HASH_ENTRIES / 8];
 650         efx_oword_t oword[EFX_MCAST_HASH_ENTRIES / sizeof(efx_oword_t) / 8];
 651 };
 652
 653 /**
 654  * struct efx_nic - an Efx NIC
 655  * @name: Device name (net device name or bus id before net device registered)
 656  * @pci_dev: The PCI device
 657  * @type: Controller type attributes
 658  * @legacy_irq: IRQ number
 659  * @workqueue: Workqueue for port reconfigures and the HW monitor.
 660  *      Work items do not hold and must not acquire RTNL.
 661  * @workqueue_name: Name of workqueue
 662  * @reset_work: Scheduled reset workitem
 663  * @monitor_work: Hardware monitor workitem
 664  * @membase_phys: Memory BAR value as physical address
 665  * @membase: Memory BAR value
 666  * @biu_lock: BIU (bus interface unit) lock
 667  * @interrupt_mode: Interrupt mode
 668  * @irq_rx_adaptive: Adaptive IRQ moderation enabled for RX event queues
 669  * @irq_rx_moderation: IRQ moderation time for RX event queues
 670  * @i2c_adap: I2C adapter
 671  * @board_info: Board-level information
 672  * @state: Device state flag. Serialised by the rtnl_lock.
 673  * @reset_pending: Pending reset method (normally RESET_TYPE_NONE)
 674  * @tx_queue: TX DMA queues
 675  * @rx_queue: RX DMA queues
 676  * @channel: Channels
 677  * @next_buffer_table: First available buffer table id
 678  * @n_rx_queues: Number of RX queues
 679  * @n_channels: Number of channels in use
 680  * @rx_buffer_len: RX buffer length
 681  * @rx_buffer_order: Order (log2) of number of pages for each RX buffer
 682  * @int_error_count: Number of internal errors seen recently
 683  * @int_error_expire: Time at which error count will be expired
 684  * @irq_status: Interrupt status buffer
 685  * @last_irq_cpu: Last CPU to handle interrupt.
 686  *      This register is written with the SMP processor ID whenever an
 687  *      interrupt is handled.  It is used by falcon_test_interrupt()
 688  *      to verify that an interrupt has occurred.
 689  * @spi_flash: SPI flash device
 690  *      This field will be %NULL if no flash device is present.
 691  * @spi_eeprom: SPI EEPROM device
 692  *      This field will be %NULL if no EEPROM device is present.
 693  * @spi_lock: SPI bus lock
 694  * @n_rx_nodesc_drop_cnt: RX no descriptor drop count
 695  * @nic_data: Hardware dependant state
 696  * @mac_lock: MAC access lock. Protects @port_enabled, @phy_mode,
 697  *      @port_inhibited, efx_monitor() and efx_reconfigure_port()
 698  * @port_enabled: Port enabled indicator.
 699  *      Serialises efx_stop_all(), efx_start_all(), efx_monitor(),
 700  *      efx_phy_work(), and efx_mac_work() with kernel interfaces. Safe to read
 701  *      under any one of the rtnl_lock, mac_lock, or netif_tx_lock, but all
 702  *      three must be held to modify it.
 703  * @port_inhibited: If set, the netif_carrier is always off. Hold the mac_lock
 704  * @port_initialized: Port initialized?
 705  * @net_dev: Operating system network device. Consider holding the rtnl lock
 706  * @rx_checksum_enabled: RX checksumming enabled
 707  * @netif_stop_count: Port stop count
 708  * @netif_stop_lock: Port stop lock
 709  * @mac_stats: MAC statistics. These include all statistics the MACs
 710  *      can provide.  Generic code converts these into a standard
 711  *      &struct net_device_stats.
 712  * @stats_buffer: DMA buffer for statistics
 713  * @stats_lock: Statistics update lock. Serialises statistics fetches
 714  * @stats_disable_count: Nest count for disabling statistics fetches
 715  * @mac_op: MAC interface
 716  * @mac_address: Permanent MAC address
 717  * @phy_type: PHY type
 718  * @phy_lock: PHY access lock
 719  * @phy_op: PHY interface
 720  * @phy_data: PHY private data (including PHY-specific stats)
 721  * @mdio: PHY MDIO interface
 722  * @phy_mode: PHY operating mode. Serialised by @mac_lock.
 723  * @mac_up: MAC link state
 724  * @link_up: Link status
 725  * @link_fd: Link is full duplex
 726  * @link_fc: Actualy flow control flags
 727  * @link_speed: Link speed (Mbps)
 728  * @n_link_state_changes: Number of times the link has changed state
 729  * @promiscuous: Promiscuous flag. Protected by netif_tx_lock.
 730  * @multicast_hash: Multicast hash table
 731  * @wanted_fc: Wanted flow control flags
 732  * @phy_work: work item for dealing with PHY events
 733  * @mac_work: work item for dealing with MAC events
 734  * @loopback_mode: Loopback status
 735  * @loopback_modes: Supported loopback mode bitmask
 736  * @loopback_selftest: Offline self-test private state
 737  *
 738  * The @priv field of the corresponding &struct net_device points to
 739  * this.
 740  */
 741 struct efx_nic {
 742         char name[IFNAMSIZ];
 743         struct pci_dev *pci_dev;
 744         const struct efx_nic_type *type;
 745         int legacy_irq;
 746         struct workqueue_struct *workqueue;
 747         char workqueue_name[16];
 748         struct work_struct reset_work;
 749         struct delayed_work monitor_work;
 750         resource_size_t membase_phys;
 751         void __iomem *membase;
 752         spinlock_t biu_lock;
 753         enum efx_int_mode interrupt_mode;
 754         bool irq_rx_adaptive;
 755         unsigned int irq_rx_moderation;
 756
 757         struct i2c_adapter i2c_adap;
 758         struct efx_board board_info;
 759
 760         enum nic_state state;
 761         enum reset_type reset_pending;
 762
 763         struct efx_tx_queue tx_queue[EFX_TX_QUEUE_COUNT];
 764         struct efx_rx_queue rx_queue[EFX_MAX_RX_QUEUES];
 765         struct efx_channel channel[EFX_MAX_CHANNELS];
 766
 767         unsigned next_buffer_table;
 768         int n_rx_queues;
 769         int n_channels;
 770         unsigned int rx_buffer_len;
 771         unsigned int rx_buffer_order;
 772
 773         unsigned int_error_count;
 774         unsigned long int_error_expire;
 775
 776         struct efx_buffer irq_status;
 777         volatile signed int last_irq_cpu;
 778
 779         struct efx_spi_device *spi_flash;
 780         struct efx_spi_device *spi_eeprom;
 781         struct mutex spi_lock;
 782
 783         unsigned n_rx_nodesc_drop_cnt;
 784
 785         struct falcon_nic_data *nic_data;
 786
 787         struct mutex mac_lock;
 788         struct work_struct mac_work;
 789         bool port_enabled;
 790         bool port_inhibited;
 791
 792         bool port_initialized;
 793         struct net_device *net_dev;
 794         bool rx_checksum_enabled;
 795
 796         atomic_t netif_stop_count;
 797         spinlock_t netif_stop_lock;
 798
 799         struct efx_mac_stats mac_stats;
 800         struct efx_buffer stats_buffer;
 801         spinlock_t stats_lock;
 802         unsigned int stats_disable_count;
 803
 804         struct efx_mac_operations *mac_op;
 805         unsigned char mac_address[ETH_ALEN];
 806
 807         enum phy_type phy_type;
 808         spinlock_t phy_lock;
 809         struct work_struct phy_work;
 810         struct efx_phy_operations *phy_op;
 811         void *phy_data;
 812         struct mdio_if_info mdio;
 813         enum efx_phy_mode phy_mode;
 814
 815         bool mac_up;
 816         bool link_up;
 817         bool link_fd;
 818         enum efx_fc_type link_fc;
 819         unsigned int link_speed;
 820         unsigned int n_link_state_changes;
 821
 822         bool promiscuous;
 823         union efx_multicast_hash multicast_hash;
 824         enum efx_fc_type wanted_fc;
 825
 826         atomic_t rx_reset;
 827         enum efx_loopback_mode loopback_mode;
 828         unsigned int loopback_modes;
 829
 830         void *loopback_selftest;
 831 };
 832
 833 static inline int efx_dev_registered(struct efx_nic *efx)
 834 {
 835         return efx->net_dev->reg_state == NETREG_REGISTERED;
 836 }
 837
 838 /* Net device name, for inclusion in log messages if it has been registered.
 839  * Use efx->name not efx->net_dev->name so that races with (un)registration
 840  * are harmless.
 841  */
 842 static inline const char *efx_dev_name(struct efx_nic *efx)
 843 {
 844         return efx_dev_registered(efx) ? efx->name : "";
 845 }
 846
 847 /**
 848  * struct efx_nic_type - Efx device type definition
 849  * @mem_map_size: Memory BAR mapped size
 850  * @txd_ptr_tbl_base: TX descriptor ring base address
 851  * @rxd_ptr_tbl_base: RX descriptor ring base address
 852  * @buf_tbl_base: Buffer table base address
 853  * @evq_ptr_tbl_base: Event queue pointer table base address
 854  * @evq_rptr_tbl_base: Event queue read-pointer table base address
 855  * @max_dma_mask: Maximum possible DMA mask
 856  * @rx_buffer_padding: Padding added to each RX buffer
 857  * @max_interrupt_mode: Highest capability interrupt mode supported
 858  *      from &enum efx_init_mode.
 859  * @phys_addr_channels: Number of channels with physically addressed
 860  *      descriptors
 861  */
 862 struct efx_nic_type {
 863         unsigned int mem_map_size;
 864         unsigned int txd_ptr_tbl_base;
 865         unsigned int rxd_ptr_tbl_base;
 866         unsigned int buf_tbl_base;
 867         unsigned int evq_ptr_tbl_base;
 868         unsigned int evq_rptr_tbl_base;
 869
 870         u64 max_dma_mask;
 871
 872         unsigned int rx_buffer_padding;
 873         unsigned int max_interrupt_mode;
 874         unsigned int phys_addr_channels;
 875 };
 876
 877 /**************************************************************************
 878  *
 879  * Prototypes and inline functions
 880  *
 881  *************************************************************************/
 882
 883 /* Iterate over all used channels */
 884 #define efx_for_each_channel(_channel, _efx)                            \
 885         for (_channel = &_efx->channel[0];                              \
 886              _channel < &_efx->channel[EFX_MAX_CHANNELS];               \
 887              _channel++)                                                \
 888                 if (!_channel->used_flags)                              \
 889                         continue;                                       \
 890                 else
 891
 892 /* Iterate over all used TX queues */
 893 #define efx_for_each_tx_queue(_tx_queue, _efx)                          \
 894         for (_tx_queue = &_efx->tx_queue[0];                            \
 895              _tx_queue < &_efx->tx_queue[EFX_TX_QUEUE_COUNT];           \
 896              _tx_queue++)
 897
 898 /* Iterate over all TX queues belonging to a channel */
 899 #define efx_for_each_channel_tx_queue(_tx_queue, _channel)              \
 900         for (_tx_queue = &_channel->efx->tx_queue[0];                   \
 901              _tx_queue < &_channel->efx->tx_queue[EFX_TX_QUEUE_COUNT];  \
 902              _tx_queue++)                                               \
 903                 if (_tx_queue->channel != _channel)                     \
 904                         continue;                                       \
 905                 else
 906
 907 /* Iterate over all used RX queues */
 908 #define efx_for_each_rx_queue(_rx_queue, _efx)                          \
 909         for (_rx_queue = &_efx->rx_queue[0];                            \
 910              _rx_queue < &_efx->rx_queue[_efx->n_rx_queues];            \
 911              _rx_queue++)
 912
 913 /* Iterate over all RX queues belonging to a channel */
 914 #define efx_for_each_channel_rx_queue(_rx_queue, _channel)              \
 915         for (_rx_queue = &_channel->efx->rx_queue[_channel->channel];   \
 916              _rx_queue;                                                 \
 917              _rx_queue = NULL)                                          \
 918                 if (_rx_queue->channel != _channel)                     \
 919                         continue;                                       \
 920                 else
 921
 922 /* Returns a pointer to the specified receive buffer in the RX
 923  * descriptor queue.
 924  */
 925 static inline struct efx_rx_buffer *efx_rx_buffer(struct efx_rx_queue *rx_queue,
 926                                                   unsigned int index)
 927 {
 928         return (&rx_queue->buffer[index]);
 929 }
 930
 931 /* Set bit in a little-endian bitfield */
 932 static inline void set_bit_le(unsigned nr, unsigned char *addr)
 933 {
 934         addr[nr / 8] |= (1 << (nr % 8));
 935 }
 936
 937 /* Clear bit in a little-endian bitfield */
 938 static inline void clear_bit_le(unsigned nr, unsigned char *addr)
 939 {
 940         addr[nr / 8] &= ~(1 << (nr % 8));
 941 }
 942
 943
 944 /**
 945  * EFX_MAX_FRAME_LEN - calculate maximum frame length
 946  *
 947  * This calculates the maximum frame length that will be used for a
 948  * given MTU.  The frame length will be equal to the MTU plus a
 949  * constant amount of header space and padding.  This is the quantity
 950  * that the net driver will program into the MAC as the maximum frame
 951  * length.
 952  *
 953  * The 10G MAC used in Falcon requires 8-byte alignment on the frame
 954  * length, so we round up to the nearest 8.
 955  *
 956  * Re-clocking by the XGXS on RX can reduce an IPG to 32 bits (half an
 957  * XGMII cycle).  If the frame length reaches the maximum value in the
 958  * same cycle, the XMAC can miss the IPG altogether.  We work around
 959  * this by adding a further 16 bytes.
 960  */
 961 #define EFX_MAX_FRAME_LEN(mtu) \
 962         ((((mtu) + ETH_HLEN + VLAN_HLEN + 4/* FCS */ + 7) & ~7) + 16)
 963
 964
 965 #endif /* EFX_NET_DRIVER_H */