2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
33 #include "drm_crtc_helper.h"
34 #include "intel_drv.h"
37 #include "drm_dp_helper.h"
40 #define DP_LINK_STATUS_SIZE 6
41 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
43 #define DP_LINK_CONFIGURATION_SIZE 9
45 #define IS_eDP(i) ((i)->base.type == INTEL_OUTPUT_EDP)
46 #define IS_PCH_eDP(i) ((i)->is_pch_edp)
49 struct intel_encoder base
;
52 uint8_t link_configuration
[DP_LINK_CONFIGURATION_SIZE
];
58 struct i2c_adapter adapter
;
59 struct i2c_algo_dp_aux_data algo
;
62 uint8_t link_status
[DP_LINK_STATUS_SIZE
];
65 static struct intel_dp
*enc_to_intel_dp(struct drm_encoder
*encoder
)
67 return container_of(enc_to_intel_encoder(encoder
), struct intel_dp
, base
);
70 static void intel_dp_start_link_train(struct intel_dp
*intel_dp
);
71 static void intel_dp_complete_link_train(struct intel_dp
*intel_dp
);
72 static void intel_dp_link_down(struct intel_dp
*intel_dp
);
75 intel_edp_link_config (struct intel_encoder
*intel_encoder
,
76 int *lane_num
, int *link_bw
)
78 struct intel_dp
*intel_dp
= container_of(intel_encoder
, struct intel_dp
, base
);
80 *lane_num
= intel_dp
->lane_count
;
81 if (intel_dp
->link_bw
== DP_LINK_BW_1_62
)
83 else if (intel_dp
->link_bw
== DP_LINK_BW_2_7
)
88 intel_dp_max_lane_count(struct intel_dp
*intel_dp
)
90 int max_lane_count
= 4;
92 if (intel_dp
->dpcd
[0] >= 0x11) {
93 max_lane_count
= intel_dp
->dpcd
[2] & 0x1f;
94 switch (max_lane_count
) {
95 case 1: case 2: case 4:
101 return max_lane_count
;
105 intel_dp_max_link_bw(struct intel_dp
*intel_dp
)
107 int max_link_bw
= intel_dp
->dpcd
[1];
109 switch (max_link_bw
) {
110 case DP_LINK_BW_1_62
:
114 max_link_bw
= DP_LINK_BW_1_62
;
121 intel_dp_link_clock(uint8_t link_bw
)
123 if (link_bw
== DP_LINK_BW_2_7
)
129 /* I think this is a fiction */
131 intel_dp_link_required(struct drm_device
*dev
, struct intel_dp
*intel_dp
, int pixel_clock
)
133 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
135 if (IS_eDP(intel_dp
) || IS_PCH_eDP(intel_dp
))
136 return (pixel_clock
* dev_priv
->edp_bpp
) / 8;
138 return pixel_clock
* 3;
142 intel_dp_max_data_rate(int max_link_clock
, int max_lanes
)
144 return (max_link_clock
* max_lanes
* 8) / 10;
148 intel_dp_mode_valid(struct drm_connector
*connector
,
149 struct drm_display_mode
*mode
)
151 struct drm_encoder
*encoder
= intel_attached_encoder(connector
);
152 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
153 struct drm_device
*dev
= connector
->dev
;
154 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
155 int max_link_clock
= intel_dp_link_clock(intel_dp_max_link_bw(intel_dp
));
156 int max_lanes
= intel_dp_max_lane_count(intel_dp
);
158 if ((IS_eDP(intel_dp
) || IS_PCH_eDP(intel_dp
)) &&
159 dev_priv
->panel_fixed_mode
) {
160 if (mode
->hdisplay
> dev_priv
->panel_fixed_mode
->hdisplay
)
163 if (mode
->vdisplay
> dev_priv
->panel_fixed_mode
->vdisplay
)
167 /* only refuse the mode on non eDP since we have seen some wierd eDP panels
168 which are outside spec tolerances but somehow work by magic */
169 if (!IS_eDP(intel_dp
) &&
170 (intel_dp_link_required(connector
->dev
, intel_dp
, mode
->clock
)
171 > intel_dp_max_data_rate(max_link_clock
, max_lanes
)))
172 return MODE_CLOCK_HIGH
;
174 if (mode
->clock
< 10000)
175 return MODE_CLOCK_LOW
;
181 pack_aux(uint8_t *src
, int src_bytes
)
188 for (i
= 0; i
< src_bytes
; i
++)
189 v
|= ((uint32_t) src
[i
]) << ((3-i
) * 8);
194 unpack_aux(uint32_t src
, uint8_t *dst
, int dst_bytes
)
199 for (i
= 0; i
< dst_bytes
; i
++)
200 dst
[i
] = src
>> ((3-i
) * 8);
203 /* hrawclock is 1/4 the FSB frequency */
205 intel_hrawclk(struct drm_device
*dev
)
207 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
210 clkcfg
= I915_READ(CLKCFG
);
211 switch (clkcfg
& CLKCFG_FSB_MASK
) {
220 case CLKCFG_FSB_1067
:
222 case CLKCFG_FSB_1333
:
224 /* these two are just a guess; one of them might be right */
225 case CLKCFG_FSB_1600
:
226 case CLKCFG_FSB_1600_ALT
:
234 intel_dp_aux_ch(struct intel_dp
*intel_dp
,
235 uint8_t *send
, int send_bytes
,
236 uint8_t *recv
, int recv_size
)
238 uint32_t output_reg
= intel_dp
->output_reg
;
239 struct drm_device
*dev
= intel_dp
->base
.enc
.dev
;
240 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
241 uint32_t ch_ctl
= output_reg
+ 0x10;
242 uint32_t ch_data
= ch_ctl
+ 4;
246 uint32_t aux_clock_divider
;
249 /* The clock divider is based off the hrawclk,
250 * and would like to run at 2MHz. So, take the
251 * hrawclk value and divide by 2 and use that
253 * Note that PCH attached eDP panels should use a 125MHz input
256 if (IS_eDP(intel_dp
) && !IS_PCH_eDP(intel_dp
)) {
258 aux_clock_divider
= 200; /* SNB eDP input clock at 400Mhz */
260 aux_clock_divider
= 225; /* eDP input clock at 450Mhz */
261 } else if (HAS_PCH_SPLIT(dev
))
262 aux_clock_divider
= 62; /* IRL input clock fixed at 125Mhz */
264 aux_clock_divider
= intel_hrawclk(dev
) / 2;
271 if (I915_READ(ch_ctl
) & DP_AUX_CH_CTL_SEND_BUSY
) {
272 DRM_ERROR("dp_aux_ch not started status 0x%08x\n",
277 /* Must try at least 3 times according to DP spec */
278 for (try = 0; try < 5; try++) {
279 /* Load the send data into the aux channel data registers */
280 for (i
= 0; i
< send_bytes
; i
+= 4)
281 I915_WRITE(ch_data
+ i
,
282 pack_aux(send
+ i
, send_bytes
- i
));
284 /* Send the command and wait for it to complete */
286 DP_AUX_CH_CTL_SEND_BUSY
|
287 DP_AUX_CH_CTL_TIME_OUT_400us
|
288 (send_bytes
<< DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
) |
289 (precharge
<< DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT
) |
290 (aux_clock_divider
<< DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT
) |
292 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
293 DP_AUX_CH_CTL_RECEIVE_ERROR
);
295 status
= I915_READ(ch_ctl
);
296 if ((status
& DP_AUX_CH_CTL_SEND_BUSY
) == 0)
301 /* Clear done status and any errors */
305 DP_AUX_CH_CTL_TIME_OUT_ERROR
|
306 DP_AUX_CH_CTL_RECEIVE_ERROR
);
307 if (status
& DP_AUX_CH_CTL_DONE
)
311 if ((status
& DP_AUX_CH_CTL_DONE
) == 0) {
312 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status
);
316 /* Check for timeout or receive error.
317 * Timeouts occur when the sink is not connected
319 if (status
& DP_AUX_CH_CTL_RECEIVE_ERROR
) {
320 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status
);
324 /* Timeouts occur when the device isn't connected, so they're
325 * "normal" -- don't fill the kernel log with these */
326 if (status
& DP_AUX_CH_CTL_TIME_OUT_ERROR
) {
327 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status
);
331 /* Unload any bytes sent back from the other side */
332 recv_bytes
= ((status
& DP_AUX_CH_CTL_MESSAGE_SIZE_MASK
) >>
333 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT
);
334 if (recv_bytes
> recv_size
)
335 recv_bytes
= recv_size
;
337 for (i
= 0; i
< recv_bytes
; i
+= 4)
338 unpack_aux(I915_READ(ch_data
+ i
),
339 recv
+ i
, recv_bytes
- i
);
344 /* Write data to the aux channel in native mode */
346 intel_dp_aux_native_write(struct intel_dp
*intel_dp
,
347 uint16_t address
, uint8_t *send
, int send_bytes
)
356 msg
[0] = AUX_NATIVE_WRITE
<< 4;
357 msg
[1] = address
>> 8;
358 msg
[2] = address
& 0xff;
359 msg
[3] = send_bytes
- 1;
360 memcpy(&msg
[4], send
, send_bytes
);
361 msg_bytes
= send_bytes
+ 4;
363 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
, &ack
, 1);
366 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
)
368 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
376 /* Write a single byte to the aux channel in native mode */
378 intel_dp_aux_native_write_1(struct intel_dp
*intel_dp
,
379 uint16_t address
, uint8_t byte
)
381 return intel_dp_aux_native_write(intel_dp
, address
, &byte
, 1);
384 /* read bytes from a native aux channel */
386 intel_dp_aux_native_read(struct intel_dp
*intel_dp
,
387 uint16_t address
, uint8_t *recv
, int recv_bytes
)
396 msg
[0] = AUX_NATIVE_READ
<< 4;
397 msg
[1] = address
>> 8;
398 msg
[2] = address
& 0xff;
399 msg
[3] = recv_bytes
- 1;
402 reply_bytes
= recv_bytes
+ 1;
405 ret
= intel_dp_aux_ch(intel_dp
, msg
, msg_bytes
,
412 if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_ACK
) {
413 memcpy(recv
, reply
+ 1, ret
- 1);
416 else if ((ack
& AUX_NATIVE_REPLY_MASK
) == AUX_NATIVE_REPLY_DEFER
)
424 intel_dp_i2c_aux_ch(struct i2c_adapter
*adapter
, int mode
,
425 uint8_t write_byte
, uint8_t *read_byte
)
427 struct i2c_algo_dp_aux_data
*algo_data
= adapter
->algo_data
;
428 struct intel_dp
*intel_dp
= container_of(adapter
,
431 uint16_t address
= algo_data
->address
;
438 /* Set up the command byte */
439 if (mode
& MODE_I2C_READ
)
440 msg
[0] = AUX_I2C_READ
<< 4;
442 msg
[0] = AUX_I2C_WRITE
<< 4;
444 if (!(mode
& MODE_I2C_STOP
))
445 msg
[0] |= AUX_I2C_MOT
<< 4;
447 msg
[1] = address
>> 8;
469 ret
= intel_dp_aux_ch(intel_dp
,
473 DRM_DEBUG_KMS("aux_ch failed %d\n", ret
);
476 switch (reply
[0] & AUX_I2C_REPLY_MASK
) {
477 case AUX_I2C_REPLY_ACK
:
478 if (mode
== MODE_I2C_READ
) {
479 *read_byte
= reply
[1];
481 return reply_bytes
- 1;
482 case AUX_I2C_REPLY_NACK
:
483 DRM_DEBUG_KMS("aux_ch nack\n");
485 case AUX_I2C_REPLY_DEFER
:
486 DRM_DEBUG_KMS("aux_ch defer\n");
490 DRM_ERROR("aux_ch invalid reply 0x%02x\n", reply
[0]);
497 intel_dp_i2c_init(struct intel_dp
*intel_dp
,
498 struct intel_connector
*intel_connector
, const char *name
)
500 DRM_DEBUG_KMS("i2c_init %s\n", name
);
501 intel_dp
->algo
.running
= false;
502 intel_dp
->algo
.address
= 0;
503 intel_dp
->algo
.aux_ch
= intel_dp_i2c_aux_ch
;
505 memset(&intel_dp
->adapter
, '\0', sizeof (intel_dp
->adapter
));
506 intel_dp
->adapter
.owner
= THIS_MODULE
;
507 intel_dp
->adapter
.class = I2C_CLASS_DDC
;
508 strncpy (intel_dp
->adapter
.name
, name
, sizeof(intel_dp
->adapter
.name
) - 1);
509 intel_dp
->adapter
.name
[sizeof(intel_dp
->adapter
.name
) - 1] = '\0';
510 intel_dp
->adapter
.algo_data
= &intel_dp
->algo
;
511 intel_dp
->adapter
.dev
.parent
= &intel_connector
->base
.kdev
;
513 return i2c_dp_aux_add_bus(&intel_dp
->adapter
);
517 intel_dp_mode_fixup(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
,
518 struct drm_display_mode
*adjusted_mode
)
520 struct drm_device
*dev
= encoder
->dev
;
521 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
522 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
523 int lane_count
, clock
;
524 int max_lane_count
= intel_dp_max_lane_count(intel_dp
);
525 int max_clock
= intel_dp_max_link_bw(intel_dp
) == DP_LINK_BW_2_7
? 1 : 0;
526 static int bws
[2] = { DP_LINK_BW_1_62
, DP_LINK_BW_2_7
};
528 if ((IS_eDP(intel_dp
) || IS_PCH_eDP(intel_dp
)) &&
529 dev_priv
->panel_fixed_mode
) {
530 intel_fixed_panel_mode(dev_priv
->panel_fixed_mode
, adjusted_mode
);
531 intel_pch_panel_fitting(dev
, DRM_MODE_SCALE_FULLSCREEN
,
532 mode
, adjusted_mode
);
534 * the mode->clock is used to calculate the Data&Link M/N
535 * of the pipe. For the eDP the fixed clock should be used.
537 mode
->clock
= dev_priv
->panel_fixed_mode
->clock
;
540 for (lane_count
= 1; lane_count
<= max_lane_count
; lane_count
<<= 1) {
541 for (clock
= 0; clock
<= max_clock
; clock
++) {
542 int link_avail
= intel_dp_max_data_rate(intel_dp_link_clock(bws
[clock
]), lane_count
);
544 if (intel_dp_link_required(encoder
->dev
, intel_dp
, mode
->clock
)
546 intel_dp
->link_bw
= bws
[clock
];
547 intel_dp
->lane_count
= lane_count
;
548 adjusted_mode
->clock
= intel_dp_link_clock(intel_dp
->link_bw
);
549 DRM_DEBUG_KMS("Display port link bw %02x lane "
550 "count %d clock %d\n",
551 intel_dp
->link_bw
, intel_dp
->lane_count
,
552 adjusted_mode
->clock
);
558 if (IS_eDP(intel_dp
) || IS_PCH_eDP(intel_dp
)) {
559 /* okay we failed just pick the highest */
560 intel_dp
->lane_count
= max_lane_count
;
561 intel_dp
->link_bw
= bws
[max_clock
];
562 adjusted_mode
->clock
= intel_dp_link_clock(intel_dp
->link_bw
);
563 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
564 "count %d clock %d\n",
565 intel_dp
->link_bw
, intel_dp
->lane_count
,
566 adjusted_mode
->clock
);
574 struct intel_dp_m_n
{
583 intel_reduce_ratio(uint32_t *num
, uint32_t *den
)
585 while (*num
> 0xffffff || *den
> 0xffffff) {
592 intel_dp_compute_m_n(int bpp
,
596 struct intel_dp_m_n
*m_n
)
599 m_n
->gmch_m
= (pixel_clock
* bpp
) >> 3;
600 m_n
->gmch_n
= link_clock
* nlanes
;
601 intel_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
602 m_n
->link_m
= pixel_clock
;
603 m_n
->link_n
= link_clock
;
604 intel_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
607 bool intel_pch_has_edp(struct drm_crtc
*crtc
)
609 struct drm_device
*dev
= crtc
->dev
;
610 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
611 struct drm_encoder
*encoder
;
613 list_for_each_entry(encoder
, &mode_config
->encoder_list
, head
) {
614 struct intel_dp
*intel_dp
;
616 if (encoder
->crtc
!= crtc
)
619 intel_dp
= enc_to_intel_dp(encoder
);
620 if (intel_dp
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
)
621 return intel_dp
->is_pch_edp
;
627 intel_dp_set_m_n(struct drm_crtc
*crtc
, struct drm_display_mode
*mode
,
628 struct drm_display_mode
*adjusted_mode
)
630 struct drm_device
*dev
= crtc
->dev
;
631 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
632 struct drm_encoder
*encoder
;
633 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
634 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
635 int lane_count
= 4, bpp
= 24;
636 struct intel_dp_m_n m_n
;
639 * Find the lane count in the intel_encoder private
641 list_for_each_entry(encoder
, &mode_config
->encoder_list
, head
) {
642 struct intel_dp
*intel_dp
;
644 if (encoder
->crtc
!= crtc
)
647 intel_dp
= enc_to_intel_dp(encoder
);
648 if (intel_dp
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
) {
649 lane_count
= intel_dp
->lane_count
;
650 if (IS_PCH_eDP(intel_dp
))
651 bpp
= dev_priv
->edp_bpp
;
657 * Compute the GMCH and Link ratios. The '3' here is
658 * the number of bytes_per_pixel post-LUT, which we always
659 * set up for 8-bits of R/G/B, or 3 bytes total.
661 intel_dp_compute_m_n(bpp
, lane_count
,
662 mode
->clock
, adjusted_mode
->clock
, &m_n
);
664 if (HAS_PCH_SPLIT(dev
)) {
665 if (intel_crtc
->pipe
== 0) {
666 I915_WRITE(TRANSA_DATA_M1
,
667 ((m_n
.tu
- 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT
) |
669 I915_WRITE(TRANSA_DATA_N1
, m_n
.gmch_n
);
670 I915_WRITE(TRANSA_DP_LINK_M1
, m_n
.link_m
);
671 I915_WRITE(TRANSA_DP_LINK_N1
, m_n
.link_n
);
673 I915_WRITE(TRANSB_DATA_M1
,
674 ((m_n
.tu
- 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT
) |
676 I915_WRITE(TRANSB_DATA_N1
, m_n
.gmch_n
);
677 I915_WRITE(TRANSB_DP_LINK_M1
, m_n
.link_m
);
678 I915_WRITE(TRANSB_DP_LINK_N1
, m_n
.link_n
);
681 if (intel_crtc
->pipe
== 0) {
682 I915_WRITE(PIPEA_GMCH_DATA_M
,
683 ((m_n
.tu
- 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT
) |
685 I915_WRITE(PIPEA_GMCH_DATA_N
,
687 I915_WRITE(PIPEA_DP_LINK_M
, m_n
.link_m
);
688 I915_WRITE(PIPEA_DP_LINK_N
, m_n
.link_n
);
690 I915_WRITE(PIPEB_GMCH_DATA_M
,
691 ((m_n
.tu
- 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT
) |
693 I915_WRITE(PIPEB_GMCH_DATA_N
,
695 I915_WRITE(PIPEB_DP_LINK_M
, m_n
.link_m
);
696 I915_WRITE(PIPEB_DP_LINK_N
, m_n
.link_n
);
702 intel_dp_mode_set(struct drm_encoder
*encoder
, struct drm_display_mode
*mode
,
703 struct drm_display_mode
*adjusted_mode
)
705 struct drm_device
*dev
= encoder
->dev
;
706 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
707 struct drm_crtc
*crtc
= intel_dp
->base
.enc
.crtc
;
708 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
710 intel_dp
->DP
= (DP_VOLTAGE_0_4
|
713 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PHSYNC
)
714 intel_dp
->DP
|= DP_SYNC_HS_HIGH
;
715 if (adjusted_mode
->flags
& DRM_MODE_FLAG_PVSYNC
)
716 intel_dp
->DP
|= DP_SYNC_VS_HIGH
;
718 if (HAS_PCH_CPT(dev
) && !IS_eDP(intel_dp
))
719 intel_dp
->DP
|= DP_LINK_TRAIN_OFF_CPT
;
721 intel_dp
->DP
|= DP_LINK_TRAIN_OFF
;
723 switch (intel_dp
->lane_count
) {
725 intel_dp
->DP
|= DP_PORT_WIDTH_1
;
728 intel_dp
->DP
|= DP_PORT_WIDTH_2
;
731 intel_dp
->DP
|= DP_PORT_WIDTH_4
;
734 if (intel_dp
->has_audio
)
735 intel_dp
->DP
|= DP_AUDIO_OUTPUT_ENABLE
;
737 memset(intel_dp
->link_configuration
, 0, DP_LINK_CONFIGURATION_SIZE
);
738 intel_dp
->link_configuration
[0] = intel_dp
->link_bw
;
739 intel_dp
->link_configuration
[1] = intel_dp
->lane_count
;
742 * Check for DPCD version > 1.1 and enhanced framing support
744 if (intel_dp
->dpcd
[0] >= 0x11 && (intel_dp
->dpcd
[2] & DP_ENHANCED_FRAME_CAP
)) {
745 intel_dp
->link_configuration
[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN
;
746 intel_dp
->DP
|= DP_ENHANCED_FRAMING
;
749 /* CPT DP's pipe select is decided in TRANS_DP_CTL */
750 if (intel_crtc
->pipe
== 1 && !HAS_PCH_CPT(dev
))
751 intel_dp
->DP
|= DP_PIPEB_SELECT
;
753 if (IS_eDP(intel_dp
)) {
754 /* don't miss out required setting for eDP */
755 intel_dp
->DP
|= DP_PLL_ENABLE
;
756 if (adjusted_mode
->clock
< 200000)
757 intel_dp
->DP
|= DP_PLL_FREQ_160MHZ
;
759 intel_dp
->DP
|= DP_PLL_FREQ_270MHZ
;
763 /* Returns true if the panel was already on when called */
764 static bool ironlake_edp_panel_on (struct drm_device
*dev
)
766 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
769 if (I915_READ(PCH_PP_STATUS
) & PP_ON
)
772 pp
= I915_READ(PCH_PP_CONTROL
);
774 /* ILK workaround: disable reset around power sequence */
775 pp
&= ~PANEL_POWER_RESET
;
776 I915_WRITE(PCH_PP_CONTROL
, pp
);
777 POSTING_READ(PCH_PP_CONTROL
);
779 pp
|= PANEL_UNLOCK_REGS
| POWER_TARGET_ON
;
780 I915_WRITE(PCH_PP_CONTROL
, pp
);
782 if (wait_for(I915_READ(PCH_PP_STATUS
) & PP_ON
, 5000))
783 DRM_ERROR("panel on wait timed out: 0x%08x\n",
784 I915_READ(PCH_PP_STATUS
));
786 pp
&= ~(PANEL_UNLOCK_REGS
);
787 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
788 I915_WRITE(PCH_PP_CONTROL
, pp
);
789 POSTING_READ(PCH_PP_CONTROL
);
794 static void ironlake_edp_panel_off (struct drm_device
*dev
)
796 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
799 pp
= I915_READ(PCH_PP_CONTROL
);
801 /* ILK workaround: disable reset around power sequence */
802 pp
&= ~PANEL_POWER_RESET
;
803 I915_WRITE(PCH_PP_CONTROL
, pp
);
804 POSTING_READ(PCH_PP_CONTROL
);
806 pp
&= ~POWER_TARGET_ON
;
807 I915_WRITE(PCH_PP_CONTROL
, pp
);
809 if (wait_for((I915_READ(PCH_PP_STATUS
) & PP_ON
) == 0, 5000))
810 DRM_ERROR("panel off wait timed out: 0x%08x\n",
811 I915_READ(PCH_PP_STATUS
));
813 /* Make sure VDD is enabled so DP AUX will work */
814 pp
|= PANEL_POWER_RESET
; /* restore panel reset bit */
815 I915_WRITE(PCH_PP_CONTROL
, pp
);
816 POSTING_READ(PCH_PP_CONTROL
);
819 static void ironlake_edp_panel_vdd_on(struct drm_device
*dev
)
821 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
824 pp
= I915_READ(PCH_PP_CONTROL
);
826 I915_WRITE(PCH_PP_CONTROL
, pp
);
827 POSTING_READ(PCH_PP_CONTROL
);
830 static void ironlake_edp_panel_vdd_off(struct drm_device
*dev
)
832 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
835 pp
= I915_READ(PCH_PP_CONTROL
);
836 pp
&= ~EDP_FORCE_VDD
;
837 I915_WRITE(PCH_PP_CONTROL
, pp
);
838 POSTING_READ(PCH_PP_CONTROL
);
841 static void ironlake_edp_backlight_on (struct drm_device
*dev
)
843 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
847 pp
= I915_READ(PCH_PP_CONTROL
);
848 pp
|= EDP_BLC_ENABLE
;
849 I915_WRITE(PCH_PP_CONTROL
, pp
);
852 static void ironlake_edp_backlight_off (struct drm_device
*dev
)
854 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
858 pp
= I915_READ(PCH_PP_CONTROL
);
859 pp
&= ~EDP_BLC_ENABLE
;
860 I915_WRITE(PCH_PP_CONTROL
, pp
);
863 static void ironlake_edp_pll_on(struct drm_encoder
*encoder
)
865 struct drm_device
*dev
= encoder
->dev
;
866 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
870 dpa_ctl
= I915_READ(DP_A
);
871 dpa_ctl
&= ~DP_PLL_ENABLE
;
872 I915_WRITE(DP_A
, dpa_ctl
);
875 static void ironlake_edp_pll_off(struct drm_encoder
*encoder
)
877 struct drm_device
*dev
= encoder
->dev
;
878 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
881 dpa_ctl
= I915_READ(DP_A
);
882 dpa_ctl
|= DP_PLL_ENABLE
;
883 I915_WRITE(DP_A
, dpa_ctl
);
887 static void intel_dp_prepare(struct drm_encoder
*encoder
)
889 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
890 struct drm_device
*dev
= encoder
->dev
;
891 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
892 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
894 if (IS_eDP(intel_dp
) || IS_PCH_eDP(intel_dp
)) {
895 ironlake_edp_backlight_off(dev
);
896 ironlake_edp_panel_vdd_on(dev
);
897 ironlake_edp_pll_on(encoder
);
899 if (dp_reg
& DP_PORT_EN
)
900 intel_dp_link_down(intel_dp
);
903 static void intel_dp_commit(struct drm_encoder
*encoder
)
905 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
906 struct drm_device
*dev
= encoder
->dev
;
908 intel_dp_start_link_train(intel_dp
);
910 if (IS_eDP(intel_dp
) || IS_PCH_eDP(intel_dp
))
911 ironlake_edp_panel_on(dev
);
913 intel_dp_complete_link_train(intel_dp
);
915 if (IS_eDP(intel_dp
) || IS_PCH_eDP(intel_dp
))
916 ironlake_edp_backlight_on(dev
);
920 intel_dp_dpms(struct drm_encoder
*encoder
, int mode
)
922 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
923 struct drm_device
*dev
= encoder
->dev
;
924 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
925 uint32_t dp_reg
= I915_READ(intel_dp
->output_reg
);
927 if (mode
!= DRM_MODE_DPMS_ON
) {
928 if (IS_eDP(intel_dp
) || IS_PCH_eDP(intel_dp
)) {
929 ironlake_edp_backlight_off(dev
);
930 ironlake_edp_panel_off(dev
);
932 if (dp_reg
& DP_PORT_EN
)
933 intel_dp_link_down(intel_dp
);
934 if (IS_eDP(intel_dp
) || IS_PCH_eDP(intel_dp
))
935 ironlake_edp_pll_off(encoder
);
937 if (!(dp_reg
& DP_PORT_EN
)) {
938 intel_dp_start_link_train(intel_dp
);
939 if (IS_eDP(intel_dp
) || IS_PCH_eDP(intel_dp
))
940 ironlake_edp_panel_on(dev
);
941 intel_dp_complete_link_train(intel_dp
);
942 if (IS_eDP(intel_dp
) || IS_PCH_eDP(intel_dp
))
943 ironlake_edp_backlight_on(dev
);
946 intel_dp
->dpms_mode
= mode
;
950 * Fetch AUX CH registers 0x202 - 0x207 which contain
951 * link status information
954 intel_dp_get_link_status(struct intel_dp
*intel_dp
)
958 ret
= intel_dp_aux_native_read(intel_dp
,
960 intel_dp
->link_status
, DP_LINK_STATUS_SIZE
);
961 if (ret
!= DP_LINK_STATUS_SIZE
)
967 intel_dp_link_status(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
970 return link_status
[r
- DP_LANE0_1_STATUS
];
974 intel_get_adjust_request_voltage(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
977 int i
= DP_ADJUST_REQUEST_LANE0_1
+ (lane
>> 1);
978 int s
= ((lane
& 1) ?
979 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT
:
980 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT
);
981 uint8_t l
= intel_dp_link_status(link_status
, i
);
983 return ((l
>> s
) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT
;
987 intel_get_adjust_request_pre_emphasis(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
990 int i
= DP_ADJUST_REQUEST_LANE0_1
+ (lane
>> 1);
991 int s
= ((lane
& 1) ?
992 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT
:
993 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT
);
994 uint8_t l
= intel_dp_link_status(link_status
, i
);
996 return ((l
>> s
) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT
;
1001 static char *voltage_names
[] = {
1002 "0.4V", "0.6V", "0.8V", "1.2V"
1004 static char *pre_emph_names
[] = {
1005 "0dB", "3.5dB", "6dB", "9.5dB"
1007 static char *link_train_names
[] = {
1008 "pattern 1", "pattern 2", "idle", "off"
1013 * These are source-specific values; current Intel hardware supports
1014 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1016 #define I830_DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_800
1019 intel_dp_pre_emphasis_max(uint8_t voltage_swing
)
1021 switch (voltage_swing
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1022 case DP_TRAIN_VOLTAGE_SWING_400
:
1023 return DP_TRAIN_PRE_EMPHASIS_6
;
1024 case DP_TRAIN_VOLTAGE_SWING_600
:
1025 return DP_TRAIN_PRE_EMPHASIS_6
;
1026 case DP_TRAIN_VOLTAGE_SWING_800
:
1027 return DP_TRAIN_PRE_EMPHASIS_3_5
;
1028 case DP_TRAIN_VOLTAGE_SWING_1200
:
1030 return DP_TRAIN_PRE_EMPHASIS_0
;
1035 intel_get_adjust_train(struct intel_dp
*intel_dp
)
1041 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
1042 uint8_t this_v
= intel_get_adjust_request_voltage(intel_dp
->link_status
, lane
);
1043 uint8_t this_p
= intel_get_adjust_request_pre_emphasis(intel_dp
->link_status
, lane
);
1051 if (v
>= I830_DP_VOLTAGE_MAX
)
1052 v
= I830_DP_VOLTAGE_MAX
| DP_TRAIN_MAX_SWING_REACHED
;
1054 if (p
>= intel_dp_pre_emphasis_max(v
))
1055 p
= intel_dp_pre_emphasis_max(v
) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED
;
1057 for (lane
= 0; lane
< 4; lane
++)
1058 intel_dp
->train_set
[lane
] = v
| p
;
1062 intel_dp_signal_levels(uint8_t train_set
, int lane_count
)
1064 uint32_t signal_levels
= 0;
1066 switch (train_set
& DP_TRAIN_VOLTAGE_SWING_MASK
) {
1067 case DP_TRAIN_VOLTAGE_SWING_400
:
1069 signal_levels
|= DP_VOLTAGE_0_4
;
1071 case DP_TRAIN_VOLTAGE_SWING_600
:
1072 signal_levels
|= DP_VOLTAGE_0_6
;
1074 case DP_TRAIN_VOLTAGE_SWING_800
:
1075 signal_levels
|= DP_VOLTAGE_0_8
;
1077 case DP_TRAIN_VOLTAGE_SWING_1200
:
1078 signal_levels
|= DP_VOLTAGE_1_2
;
1081 switch (train_set
& DP_TRAIN_PRE_EMPHASIS_MASK
) {
1082 case DP_TRAIN_PRE_EMPHASIS_0
:
1084 signal_levels
|= DP_PRE_EMPHASIS_0
;
1086 case DP_TRAIN_PRE_EMPHASIS_3_5
:
1087 signal_levels
|= DP_PRE_EMPHASIS_3_5
;
1089 case DP_TRAIN_PRE_EMPHASIS_6
:
1090 signal_levels
|= DP_PRE_EMPHASIS_6
;
1092 case DP_TRAIN_PRE_EMPHASIS_9_5
:
1093 signal_levels
|= DP_PRE_EMPHASIS_9_5
;
1096 return signal_levels
;
1099 /* Gen6's DP voltage swing and pre-emphasis control */
1101 intel_gen6_edp_signal_levels(uint8_t train_set
)
1103 switch (train_set
& (DP_TRAIN_VOLTAGE_SWING_MASK
|DP_TRAIN_PRE_EMPHASIS_MASK
)) {
1104 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_0
:
1105 return EDP_LINK_TRAIN_400MV_0DB_SNB_B
;
1106 case DP_TRAIN_VOLTAGE_SWING_400
| DP_TRAIN_PRE_EMPHASIS_6
:
1107 return EDP_LINK_TRAIN_400MV_6DB_SNB_B
;
1108 case DP_TRAIN_VOLTAGE_SWING_600
| DP_TRAIN_PRE_EMPHASIS_3_5
:
1109 return EDP_LINK_TRAIN_600MV_3_5DB_SNB_B
;
1110 case DP_TRAIN_VOLTAGE_SWING_800
| DP_TRAIN_PRE_EMPHASIS_0
:
1111 return EDP_LINK_TRAIN_800MV_0DB_SNB_B
;
1113 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level\n");
1114 return EDP_LINK_TRAIN_400MV_0DB_SNB_B
;
1119 intel_get_lane_status(uint8_t link_status
[DP_LINK_STATUS_SIZE
],
1122 int i
= DP_LANE0_1_STATUS
+ (lane
>> 1);
1123 int s
= (lane
& 1) * 4;
1124 uint8_t l
= intel_dp_link_status(link_status
, i
);
1126 return (l
>> s
) & 0xf;
1129 /* Check for clock recovery is done on all channels */
1131 intel_clock_recovery_ok(uint8_t link_status
[DP_LINK_STATUS_SIZE
], int lane_count
)
1134 uint8_t lane_status
;
1136 for (lane
= 0; lane
< lane_count
; lane
++) {
1137 lane_status
= intel_get_lane_status(link_status
, lane
);
1138 if ((lane_status
& DP_LANE_CR_DONE
) == 0)
1144 /* Check to see if channel eq is done on all channels */
1145 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1146 DP_LANE_CHANNEL_EQ_DONE|\
1147 DP_LANE_SYMBOL_LOCKED)
1149 intel_channel_eq_ok(struct intel_dp
*intel_dp
)
1152 uint8_t lane_status
;
1155 lane_align
= intel_dp_link_status(intel_dp
->link_status
,
1156 DP_LANE_ALIGN_STATUS_UPDATED
);
1157 if ((lane_align
& DP_INTERLANE_ALIGN_DONE
) == 0)
1159 for (lane
= 0; lane
< intel_dp
->lane_count
; lane
++) {
1160 lane_status
= intel_get_lane_status(intel_dp
->link_status
, lane
);
1161 if ((lane_status
& CHANNEL_EQ_BITS
) != CHANNEL_EQ_BITS
)
1168 intel_dp_set_link_train(struct intel_dp
*intel_dp
,
1169 uint32_t dp_reg_value
,
1170 uint8_t dp_train_pat
,
1173 struct drm_device
*dev
= intel_dp
->base
.enc
.dev
;
1174 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1175 struct intel_crtc
*intel_crtc
= to_intel_crtc(intel_dp
->base
.enc
.crtc
);
1178 I915_WRITE(intel_dp
->output_reg
, dp_reg_value
);
1179 POSTING_READ(intel_dp
->output_reg
);
1181 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
1183 intel_dp_aux_native_write_1(intel_dp
,
1184 DP_TRAINING_PATTERN_SET
,
1187 ret
= intel_dp_aux_native_write(intel_dp
,
1188 DP_TRAINING_LANE0_SET
, intel_dp
->train_set
, 4);
1195 /* Enable corresponding port and start training pattern 1 */
1197 intel_dp_start_link_train(struct intel_dp
*intel_dp
)
1199 struct drm_device
*dev
= intel_dp
->base
.enc
.dev
;
1202 bool clock_recovery
= false;
1206 uint32_t DP
= intel_dp
->DP
;
1208 /* Write the link configuration data */
1209 intel_dp_aux_native_write(intel_dp
, DP_LINK_BW_SET
,
1210 intel_dp
->link_configuration
,
1211 DP_LINK_CONFIGURATION_SIZE
);
1214 if (HAS_PCH_CPT(dev
) && !IS_eDP(intel_dp
))
1215 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
1217 DP
&= ~DP_LINK_TRAIN_MASK
;
1218 memset(intel_dp
->train_set
, 0, 4);
1221 clock_recovery
= false;
1223 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1224 uint32_t signal_levels
;
1225 if (IS_GEN6(dev
) && IS_eDP(intel_dp
)) {
1226 signal_levels
= intel_gen6_edp_signal_levels(intel_dp
->train_set
[0]);
1227 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
) | signal_levels
;
1229 signal_levels
= intel_dp_signal_levels(intel_dp
->train_set
[0], intel_dp
->lane_count
);
1230 DP
= (DP
& ~(DP_VOLTAGE_MASK
|DP_PRE_EMPHASIS_MASK
)) | signal_levels
;
1233 if (HAS_PCH_CPT(dev
) && !IS_eDP(intel_dp
))
1234 reg
= DP
| DP_LINK_TRAIN_PAT_1_CPT
;
1236 reg
= DP
| DP_LINK_TRAIN_PAT_1
;
1238 if (!intel_dp_set_link_train(intel_dp
, reg
,
1239 DP_TRAINING_PATTERN_1
, first
))
1242 /* Set training pattern 1 */
1245 if (!intel_dp_get_link_status(intel_dp
))
1248 if (intel_clock_recovery_ok(intel_dp
->link_status
, intel_dp
->lane_count
)) {
1249 clock_recovery
= true;
1253 /* Check to see if we've tried the max voltage */
1254 for (i
= 0; i
< intel_dp
->lane_count
; i
++)
1255 if ((intel_dp
->train_set
[i
] & DP_TRAIN_MAX_SWING_REACHED
) == 0)
1257 if (i
== intel_dp
->lane_count
)
1260 /* Check to see if we've tried the same voltage 5 times */
1261 if ((intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
) == voltage
) {
1267 voltage
= intel_dp
->train_set
[0] & DP_TRAIN_VOLTAGE_SWING_MASK
;
1269 /* Compute new intel_dp->train_set as requested by target */
1270 intel_get_adjust_train(intel_dp
);
1277 intel_dp_complete_link_train(struct intel_dp
*intel_dp
)
1279 struct drm_device
*dev
= intel_dp
->base
.enc
.dev
;
1280 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1281 bool channel_eq
= false;
1284 uint32_t DP
= intel_dp
->DP
;
1286 /* channel equalization */
1290 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1291 uint32_t signal_levels
;
1293 if (IS_GEN6(dev
) && IS_eDP(intel_dp
)) {
1294 signal_levels
= intel_gen6_edp_signal_levels(intel_dp
->train_set
[0]);
1295 DP
= (DP
& ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB
) | signal_levels
;
1297 signal_levels
= intel_dp_signal_levels(intel_dp
->train_set
[0], intel_dp
->lane_count
);
1298 DP
= (DP
& ~(DP_VOLTAGE_MASK
|DP_PRE_EMPHASIS_MASK
)) | signal_levels
;
1301 if (HAS_PCH_CPT(dev
) && !IS_eDP(intel_dp
))
1302 reg
= DP
| DP_LINK_TRAIN_PAT_2_CPT
;
1304 reg
= DP
| DP_LINK_TRAIN_PAT_2
;
1306 /* channel eq pattern */
1307 if (!intel_dp_set_link_train(intel_dp
, reg
,
1308 DP_TRAINING_PATTERN_2
,
1313 if (!intel_dp_get_link_status(intel_dp
))
1316 if (intel_channel_eq_ok(intel_dp
)) {
1325 /* Compute new intel_dp->train_set as requested by target */
1326 intel_get_adjust_train(intel_dp
);
1330 if (HAS_PCH_CPT(dev
) && !IS_eDP(intel_dp
))
1331 reg
= DP
| DP_LINK_TRAIN_OFF_CPT
;
1333 reg
= DP
| DP_LINK_TRAIN_OFF
;
1335 I915_WRITE(intel_dp
->output_reg
, reg
);
1336 POSTING_READ(intel_dp
->output_reg
);
1337 intel_dp_aux_native_write_1(intel_dp
,
1338 DP_TRAINING_PATTERN_SET
, DP_TRAINING_PATTERN_DISABLE
);
1342 intel_dp_link_down(struct intel_dp
*intel_dp
)
1344 struct drm_device
*dev
= intel_dp
->base
.enc
.dev
;
1345 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1346 uint32_t DP
= intel_dp
->DP
;
1348 DRM_DEBUG_KMS("\n");
1350 if (IS_eDP(intel_dp
)) {
1351 DP
&= ~DP_PLL_ENABLE
;
1352 I915_WRITE(intel_dp
->output_reg
, DP
);
1353 POSTING_READ(intel_dp
->output_reg
);
1357 if (HAS_PCH_CPT(dev
) && !IS_eDP(intel_dp
)) {
1358 DP
&= ~DP_LINK_TRAIN_MASK_CPT
;
1359 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE_CPT
);
1360 POSTING_READ(intel_dp
->output_reg
);
1362 DP
&= ~DP_LINK_TRAIN_MASK
;
1363 I915_WRITE(intel_dp
->output_reg
, DP
| DP_LINK_TRAIN_PAT_IDLE
);
1364 POSTING_READ(intel_dp
->output_reg
);
1369 if (IS_eDP(intel_dp
))
1370 DP
|= DP_LINK_TRAIN_OFF
;
1371 I915_WRITE(intel_dp
->output_reg
, DP
& ~DP_PORT_EN
);
1372 POSTING_READ(intel_dp
->output_reg
);
1376 * According to DP spec
1379 * 2. Configure link according to Receiver Capabilities
1380 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
1381 * 4. Check link status on receipt of hot-plug interrupt
1385 intel_dp_check_link_status(struct intel_dp
*intel_dp
)
1387 if (!intel_dp
->base
.enc
.crtc
)
1390 if (!intel_dp_get_link_status(intel_dp
)) {
1391 intel_dp_link_down(intel_dp
);
1395 if (!intel_channel_eq_ok(intel_dp
)) {
1396 intel_dp_start_link_train(intel_dp
);
1397 intel_dp_complete_link_train(intel_dp
);
1401 static enum drm_connector_status
1402 ironlake_dp_detect(struct drm_connector
*connector
)
1404 struct drm_encoder
*encoder
= intel_attached_encoder(connector
);
1405 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1406 enum drm_connector_status status
;
1408 /* Panel needs power for AUX to work */
1409 if (IS_eDP(intel_dp
) || IS_PCH_eDP(intel_dp
))
1410 ironlake_edp_panel_vdd_on(connector
->dev
);
1411 status
= connector_status_disconnected
;
1412 if (intel_dp_aux_native_read(intel_dp
,
1413 0x000, intel_dp
->dpcd
,
1414 sizeof (intel_dp
->dpcd
)) == sizeof (intel_dp
->dpcd
))
1416 if (intel_dp
->dpcd
[0] != 0)
1417 status
= connector_status_connected
;
1419 DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp
->dpcd
[0],
1420 intel_dp
->dpcd
[1], intel_dp
->dpcd
[2], intel_dp
->dpcd
[3]);
1421 if (IS_eDP(intel_dp
) || IS_PCH_eDP(intel_dp
))
1422 ironlake_edp_panel_vdd_off(connector
->dev
);
1427 * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1429 * \return true if DP port is connected.
1430 * \return false if DP port is disconnected.
1432 static enum drm_connector_status
1433 intel_dp_detect(struct drm_connector
*connector
)
1435 struct drm_encoder
*encoder
= intel_attached_encoder(connector
);
1436 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1437 struct drm_device
*dev
= intel_dp
->base
.enc
.dev
;
1438 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1440 enum drm_connector_status status
;
1442 intel_dp
->has_audio
= false;
1444 if (HAS_PCH_SPLIT(dev
))
1445 return ironlake_dp_detect(connector
);
1447 switch (intel_dp
->output_reg
) {
1449 bit
= DPB_HOTPLUG_INT_STATUS
;
1452 bit
= DPC_HOTPLUG_INT_STATUS
;
1455 bit
= DPD_HOTPLUG_INT_STATUS
;
1458 return connector_status_unknown
;
1461 temp
= I915_READ(PORT_HOTPLUG_STAT
);
1463 if ((temp
& bit
) == 0)
1464 return connector_status_disconnected
;
1466 status
= connector_status_disconnected
;
1467 if (intel_dp_aux_native_read(intel_dp
,
1468 0x000, intel_dp
->dpcd
,
1469 sizeof (intel_dp
->dpcd
)) == sizeof (intel_dp
->dpcd
))
1471 if (intel_dp
->dpcd
[0] != 0)
1472 status
= connector_status_connected
;
1477 static int intel_dp_get_modes(struct drm_connector
*connector
)
1479 struct drm_encoder
*encoder
= intel_attached_encoder(connector
);
1480 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1481 struct drm_device
*dev
= intel_dp
->base
.enc
.dev
;
1482 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1485 /* We should parse the EDID data and find out if it has an audio sink
1488 ret
= intel_ddc_get_modes(connector
, intel_dp
->base
.ddc_bus
);
1490 if ((IS_eDP(intel_dp
) || IS_PCH_eDP(intel_dp
)) &&
1491 !dev_priv
->panel_fixed_mode
) {
1492 struct drm_display_mode
*newmode
;
1493 list_for_each_entry(newmode
, &connector
->probed_modes
,
1495 if (newmode
->type
& DRM_MODE_TYPE_PREFERRED
) {
1496 dev_priv
->panel_fixed_mode
=
1497 drm_mode_duplicate(dev
, newmode
);
1506 /* if eDP has no EDID, try to use fixed panel mode from VBT */
1507 if (IS_eDP(intel_dp
) || IS_PCH_eDP(intel_dp
)) {
1508 if (dev_priv
->panel_fixed_mode
!= NULL
) {
1509 struct drm_display_mode
*mode
;
1510 mode
= drm_mode_duplicate(dev
, dev_priv
->panel_fixed_mode
);
1511 drm_mode_probed_add(connector
, mode
);
1519 intel_dp_destroy (struct drm_connector
*connector
)
1521 drm_sysfs_connector_remove(connector
);
1522 drm_connector_cleanup(connector
);
1526 static void intel_dp_encoder_destroy(struct drm_encoder
*encoder
)
1528 struct intel_dp
*intel_dp
= enc_to_intel_dp(encoder
);
1530 i2c_del_adapter(&intel_dp
->adapter
);
1531 drm_encoder_cleanup(encoder
);
1535 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs
= {
1536 .dpms
= intel_dp_dpms
,
1537 .mode_fixup
= intel_dp_mode_fixup
,
1538 .prepare
= intel_dp_prepare
,
1539 .mode_set
= intel_dp_mode_set
,
1540 .commit
= intel_dp_commit
,
1543 static const struct drm_connector_funcs intel_dp_connector_funcs
= {
1544 .dpms
= drm_helper_connector_dpms
,
1545 .detect
= intel_dp_detect
,
1546 .fill_modes
= drm_helper_probe_single_connector_modes
,
1547 .destroy
= intel_dp_destroy
,
1550 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs
= {
1551 .get_modes
= intel_dp_get_modes
,
1552 .mode_valid
= intel_dp_mode_valid
,
1553 .best_encoder
= intel_attached_encoder
,
1556 static const struct drm_encoder_funcs intel_dp_enc_funcs
= {
1557 .destroy
= intel_dp_encoder_destroy
,
1561 intel_dp_hot_plug(struct intel_encoder
*intel_encoder
)
1563 struct intel_dp
*intel_dp
= container_of(intel_encoder
, struct intel_dp
, base
);
1565 if (intel_dp
->dpms_mode
== DRM_MODE_DPMS_ON
)
1566 intel_dp_check_link_status(intel_dp
);
1569 /* Return which DP Port should be selected for Transcoder DP control */
1571 intel_trans_dp_port_sel (struct drm_crtc
*crtc
)
1573 struct drm_device
*dev
= crtc
->dev
;
1574 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
1575 struct drm_encoder
*encoder
;
1577 list_for_each_entry(encoder
, &mode_config
->encoder_list
, head
) {
1578 struct intel_dp
*intel_dp
;
1580 if (encoder
->crtc
!= crtc
)
1583 intel_dp
= enc_to_intel_dp(encoder
);
1584 if (intel_dp
->base
.type
== INTEL_OUTPUT_DISPLAYPORT
)
1585 return intel_dp
->output_reg
;
1591 /* check the VBT to see whether the eDP is on DP-D port */
1592 bool intel_dpd_is_edp(struct drm_device
*dev
)
1594 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1595 struct child_device_config
*p_child
;
1598 if (!dev_priv
->child_dev_num
)
1601 for (i
= 0; i
< dev_priv
->child_dev_num
; i
++) {
1602 p_child
= dev_priv
->child_dev
+ i
;
1604 if (p_child
->dvo_port
== PORT_IDPD
&&
1605 p_child
->device_type
== DEVICE_TYPE_eDP
)
1612 intel_dp_init(struct drm_device
*dev
, int output_reg
)
1614 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1615 struct drm_connector
*connector
;
1616 struct intel_dp
*intel_dp
;
1617 struct intel_encoder
*intel_encoder
;
1618 struct intel_connector
*intel_connector
;
1619 const char *name
= NULL
;
1622 intel_dp
= kzalloc(sizeof(struct intel_dp
), GFP_KERNEL
);
1626 intel_connector
= kzalloc(sizeof(struct intel_connector
), GFP_KERNEL
);
1627 if (!intel_connector
) {
1631 intel_encoder
= &intel_dp
->base
;
1633 if (HAS_PCH_SPLIT(dev
) && output_reg
== PCH_DP_D
)
1634 if (intel_dpd_is_edp(dev
))
1635 intel_dp
->is_pch_edp
= true;
1637 if (output_reg
== DP_A
|| IS_PCH_eDP(intel_dp
)) {
1638 type
= DRM_MODE_CONNECTOR_eDP
;
1639 intel_encoder
->type
= INTEL_OUTPUT_EDP
;
1641 type
= DRM_MODE_CONNECTOR_DisplayPort
;
1642 intel_encoder
->type
= INTEL_OUTPUT_DISPLAYPORT
;
1645 connector
= &intel_connector
->base
;
1646 drm_connector_init(dev
, connector
, &intel_dp_connector_funcs
, type
);
1647 drm_connector_helper_add(connector
, &intel_dp_connector_helper_funcs
);
1649 connector
->polled
= DRM_CONNECTOR_POLL_HPD
;
1651 if (output_reg
== DP_B
|| output_reg
== PCH_DP_B
)
1652 intel_encoder
->clone_mask
= (1 << INTEL_DP_B_CLONE_BIT
);
1653 else if (output_reg
== DP_C
|| output_reg
== PCH_DP_C
)
1654 intel_encoder
->clone_mask
= (1 << INTEL_DP_C_CLONE_BIT
);
1655 else if (output_reg
== DP_D
|| output_reg
== PCH_DP_D
)
1656 intel_encoder
->clone_mask
= (1 << INTEL_DP_D_CLONE_BIT
);
1658 if (IS_eDP(intel_dp
))
1659 intel_encoder
->clone_mask
= (1 << INTEL_EDP_CLONE_BIT
);
1661 intel_encoder
->crtc_mask
= (1 << 0) | (1 << 1);
1662 connector
->interlace_allowed
= true;
1663 connector
->doublescan_allowed
= 0;
1665 intel_dp
->output_reg
= output_reg
;
1666 intel_dp
->has_audio
= false;
1667 intel_dp
->dpms_mode
= DRM_MODE_DPMS_ON
;
1669 drm_encoder_init(dev
, &intel_encoder
->enc
, &intel_dp_enc_funcs
,
1670 DRM_MODE_ENCODER_TMDS
);
1671 drm_encoder_helper_add(&intel_encoder
->enc
, &intel_dp_helper_funcs
);
1673 drm_mode_connector_attach_encoder(&intel_connector
->base
,
1674 &intel_encoder
->enc
);
1675 drm_sysfs_connector_add(connector
);
1677 /* Set up the DDC bus. */
1678 switch (output_reg
) {
1684 dev_priv
->hotplug_supported_mask
|=
1685 HDMIB_HOTPLUG_INT_STATUS
;
1690 dev_priv
->hotplug_supported_mask
|=
1691 HDMIC_HOTPLUG_INT_STATUS
;
1696 dev_priv
->hotplug_supported_mask
|=
1697 HDMID_HOTPLUG_INT_STATUS
;
1702 intel_dp_i2c_init(intel_dp
, intel_connector
, name
);
1704 intel_encoder
->ddc_bus
= &intel_dp
->adapter
;
1705 intel_encoder
->hot_plug
= intel_dp_hot_plug
;
1707 if (output_reg
== DP_A
|| IS_PCH_eDP(intel_dp
)) {
1708 /* initialize panel mode from VBT if available for eDP */
1709 if (dev_priv
->lfp_lvds_vbt_mode
) {
1710 dev_priv
->panel_fixed_mode
=
1711 drm_mode_duplicate(dev
, dev_priv
->lfp_lvds_vbt_mode
);
1712 if (dev_priv
->panel_fixed_mode
) {
1713 dev_priv
->panel_fixed_mode
->type
|=
1714 DRM_MODE_TYPE_PREFERRED
;
1719 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1720 * 0xd. Failure to do so will result in spurious interrupts being
1721 * generated on the port when a cable is not attached.
1723 if (IS_G4X(dev
) && !IS_GM45(dev
)) {
1724 u32 temp
= I915_READ(PEG_BAND_GAP_DATA
);
1725 I915_WRITE(PEG_BAND_GAP_DATA
, (temp
& ~0xf) | 0xd);