?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
[PATCH] pcnet32: break receive routine into two pieces.
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / pcnet32.c
blobbf72aa80ccb6d91e9bf6aef7b13ae251f2c84b4a
1 /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
2 /*
3 * Copyright 1996-1999 Thomas Bogendoerfer
4 *
5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
6 *
7 * Copyright 1993 United States Government as represented by the
8 * Director, National Security Agency.
9 *
10 * This software may be used and distributed according to the terms
11 * of the GNU General Public License, incorporated herein by reference.
12 *
13 * This driver is for PCnet32 and PCnetPCI based ethercards
14 */
15 /**************************************************************************
16 * 23 Oct, 2000.
17 * Fixed a few bugs, related to running the controller in 32bit mode.
18 *
19 * Carsten Langgaard, carstenl@mips.com
20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
21 *
22 *************************************************************************/
23
24 #define DRV_NAME "pcnet32"
25 #define DRV_VERSION "1.32"
26 #define DRV_RELDATE "18.Mar.2006"
27 #define PFX DRV_NAME ": "
28
29 static const char *const version =
30 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n";
31
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/string.h>
35 #include <linux/errno.h>
36 #include <linux/ioport.h>
37 #include <linux/slab.h>
38 #include <linux/interrupt.h>
39 #include <linux/pci.h>
40 #include <linux/delay.h>
41 #include <linux/init.h>
42 #include <linux/ethtool.h>
43 #include <linux/mii.h>
44 #include <linux/crc32.h>
45 #include <linux/netdevice.h>
46 #include <linux/etherdevice.h>
47 #include <linux/skbuff.h>
48 #include <linux/spinlock.h>
49 #include <linux/moduleparam.h>
50 #include <linux/bitops.h>
51
52 #include <asm/dma.h>
53 #include <asm/io.h>
54 #include <asm/uaccess.h>
55 #include <asm/irq.h>
56
57 /*
58 * PCI device identifiers for "new style" Linux PCI Device Drivers
59 */
60 static struct pci_device_id pcnet32_pci_tbl[] = {
61 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), },
62 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), },
63
64 /*
65 * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
66 * the incorrect vendor id.
67 */
68 { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE),
69 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, },
70
71 { } /* terminate list */
72 };
73
74 MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl);
75
76 static int cards_found;
77
78 /*
79 * VLB I/O addresses
80 */
81 static unsigned int pcnet32_portlist[] __initdata =
82 { 0x300, 0x320, 0x340, 0x360, 0 };
83
84 static int pcnet32_debug = 0;
85 static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
86 static int pcnet32vlb; /* check for VLB cards ? */
87
88 static struct net_device *pcnet32_dev;
89
90 static int max_interrupt_work = 2;
91 static int rx_copybreak = 200;
92
93 #define PCNET32_PORT_AUI 0x00
94 #define PCNET32_PORT_10BT 0x01
95 #define PCNET32_PORT_GPSI 0x02
96 #define PCNET32_PORT_MII 0x03
97
98 #define PCNET32_PORT_PORTSEL 0x03
99 #define PCNET32_PORT_ASEL 0x04
100 #define PCNET32_PORT_100 0x40
101 #define PCNET32_PORT_FD 0x80
102
103 #define PCNET32_DMA_MASK 0xffffffff
104
105 #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
106 #define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4))
107
108 /*
109 * table to translate option values from tulip
110 * to internal options
111 */
112 static const unsigned char options_mapping[] = {
113 PCNET32_PORT_ASEL, /* 0 Auto-select */
114 PCNET32_PORT_AUI, /* 1 BNC/AUI */
115 PCNET32_PORT_AUI, /* 2 AUI/BNC */
116 PCNET32_PORT_ASEL, /* 3 not supported */
117 PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */
118 PCNET32_PORT_ASEL, /* 5 not supported */
119 PCNET32_PORT_ASEL, /* 6 not supported */
120 PCNET32_PORT_ASEL, /* 7 not supported */
121 PCNET32_PORT_ASEL, /* 8 not supported */
122 PCNET32_PORT_MII, /* 9 MII 10baseT */
123 PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */
124 PCNET32_PORT_MII, /* 11 MII (autosel) */
125 PCNET32_PORT_10BT, /* 12 10BaseT */
126 PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */
127 /* 14 MII 100BaseTx-FD */
128 PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD,
129 PCNET32_PORT_ASEL /* 15 not supported */
130 };
131
132 static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = {
133 "Loopback test (offline)"
134 };
135
136 #define PCNET32_TEST_LEN (sizeof(pcnet32_gstrings_test) / ETH_GSTRING_LEN)
137
138 #define PCNET32_NUM_REGS 136
139
140 #define MAX_UNITS 8 /* More are supported, limit only on options */
141 static int options[MAX_UNITS];
142 static int full_duplex[MAX_UNITS];
143 static int homepna[MAX_UNITS];
144
145 /*
146 * Theory of Operation
147 *
148 * This driver uses the same software structure as the normal lance
149 * driver. So look for a verbose description in lance.c. The differences
150 * to the normal lance driver is the use of the 32bit mode of PCnet32
151 * and PCnetPCI chips. Because these chips are 32bit chips, there is no
152 * 16MB limitation and we don't need bounce buffers.
153 */
154
155 /*
156 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
157 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
158 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
159 */
160 #ifndef PCNET32_LOG_TX_BUFFERS
161 #define PCNET32_LOG_TX_BUFFERS 4
162 #define PCNET32_LOG_RX_BUFFERS 5
163 #define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */
164 #define PCNET32_LOG_MAX_RX_BUFFERS 9
165 #endif
166
167 #define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
168 #define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
169
170 #define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
171 #define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
172
173 #define PKT_BUF_SZ 1544
174
175 /* Offsets from base I/O address. */
176 #define PCNET32_WIO_RDP 0x10
177 #define PCNET32_WIO_RAP 0x12
178 #define PCNET32_WIO_RESET 0x14
179 #define PCNET32_WIO_BDP 0x16
180
181 #define PCNET32_DWIO_RDP 0x10
182 #define PCNET32_DWIO_RAP 0x14
183 #define PCNET32_DWIO_RESET 0x18
184 #define PCNET32_DWIO_BDP 0x1C
185
186 #define PCNET32_TOTAL_SIZE 0x20
187
188 #define CSR0 0
189 #define CSR0_INIT 0x1
190 #define CSR0_START 0x2
191 #define CSR0_STOP 0x4
192 #define CSR0_TXPOLL 0x8
193 #define CSR0_INTEN 0x40
194 #define CSR0_IDON 0x0100
195 #define CSR0_NORMAL (CSR0_START | CSR0_INTEN)
196 #define PCNET32_INIT_LOW 1
197 #define PCNET32_INIT_HIGH 2
198 #define CSR3 3
199 #define CSR4 4
200 #define CSR5 5
201 #define CSR5_SUSPEND 0x0001
202 #define CSR15 15
203 #define PCNET32_MC_FILTER 8
204
205 #define PCNET32_79C970A 0x2621
206
207 /* The PCNET32 Rx and Tx ring descriptors. */
208 struct pcnet32_rx_head {
209 u32 base;
210 s16 buf_length; /* two`s complement of length */
211 s16 status;
212 u32 msg_length;
213 u32 reserved;
214 };
215
216 struct pcnet32_tx_head {
217 u32 base;
218 s16 length; /* two`s complement of length */
219 s16 status;
220 u32 misc;
221 u32 reserved;
222 };
223
224 /* The PCNET32 32-Bit initialization block, described in databook. */
225 struct pcnet32_init_block {
226 u16 mode;
227 u16 tlen_rlen;
228 u8 phys_addr[6];
229 u16 reserved;
230 u32 filter[2];
231 /* Receive and transmit ring base, along with extra bits. */
232 u32 rx_ring;
233 u32 tx_ring;
234 };
235
236 /* PCnet32 access functions */
237 struct pcnet32_access {
238 u16 (*read_csr) (unsigned long, int);
239 void (*write_csr) (unsigned long, int, u16);
240 u16 (*read_bcr) (unsigned long, int);
241 void (*write_bcr) (unsigned long, int, u16);
242 u16 (*read_rap) (unsigned long);
243 void (*write_rap) (unsigned long, u16);
244 void (*reset) (unsigned long);
245 };
246
247 /*
248 * The first field of pcnet32_private is read by the ethernet device
249 * so the structure should be allocated using pci_alloc_consistent().
250 */
251 struct pcnet32_private {
252 struct pcnet32_init_block init_block;
253 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
254 struct pcnet32_rx_head *rx_ring;
255 struct pcnet32_tx_head *tx_ring;
256 dma_addr_t dma_addr;/* DMA address of beginning of this
257 object, returned by pci_alloc_consistent */
258 struct pci_dev *pci_dev;
259 const char *name;
260 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
261 struct sk_buff **tx_skbuff;
262 struct sk_buff **rx_skbuff;
263 dma_addr_t *tx_dma_addr;
264 dma_addr_t *rx_dma_addr;
265 struct pcnet32_access a;
266 spinlock_t lock; /* Guard lock */
267 unsigned int cur_rx, cur_tx; /* The next free ring entry */
268 unsigned int rx_ring_size; /* current rx ring size */
269 unsigned int tx_ring_size; /* current tx ring size */
270 unsigned int rx_mod_mask; /* rx ring modular mask */
271 unsigned int tx_mod_mask; /* tx ring modular mask */
272 unsigned short rx_len_bits;
273 unsigned short tx_len_bits;
274 dma_addr_t rx_ring_dma_addr;
275 dma_addr_t tx_ring_dma_addr;
276 unsigned int dirty_rx, /* ring entries to be freed. */
277 dirty_tx;
278
279 struct net_device_stats stats;
280 char tx_full;
281 char phycount; /* number of phys found */
282 int options;
283 unsigned int shared_irq:1, /* shared irq possible */
284 dxsuflo:1, /* disable transmit stop on uflo */
285 mii:1; /* mii port available */
286 struct net_device *next;
287 struct mii_if_info mii_if;
288 struct timer_list watchdog_timer;
289 struct timer_list blink_timer;
290 u32 msg_enable; /* debug message level */
291
292 /* each bit indicates an available PHY */
293 u32 phymask;
294 unsigned short chip_version; /* which variant this is */
295 };
296
297 static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
298 static int pcnet32_probe1(unsigned long, int, struct pci_dev *);
299 static int pcnet32_open(struct net_device *);
300 static int pcnet32_init_ring(struct net_device *);
301 static int pcnet32_start_xmit(struct sk_buff *, struct net_device *);
302 static void pcnet32_tx_timeout(struct net_device *dev);
303 static irqreturn_t pcnet32_interrupt(int, void *, struct pt_regs *);
304 static int pcnet32_close(struct net_device *);
305 static struct net_device_stats *pcnet32_get_stats(struct net_device *);
306 static void pcnet32_load_multicast(struct net_device *dev);
307 static void pcnet32_set_multicast_list(struct net_device *);
308 static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
309 static void pcnet32_watchdog(struct net_device *);
310 static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
311 static void mdio_write(struct net_device *dev, int phy_id, int reg_num,
312 int val);
313 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits);
314 static void pcnet32_ethtool_test(struct net_device *dev,
315 struct ethtool_test *eth_test, u64 * data);
316 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1);
317 static int pcnet32_phys_id(struct net_device *dev, u32 data);
318 static void pcnet32_led_blink_callback(struct net_device *dev);
319 static int pcnet32_get_regs_len(struct net_device *dev);
320 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
321 void *ptr);
322 static void pcnet32_purge_tx_ring(struct net_device *dev);
323 static int pcnet32_alloc_ring(struct net_device *dev, char *name);
324 static void pcnet32_free_ring(struct net_device *dev);
325 static void pcnet32_check_media(struct net_device *dev, int verbose);
326
327 static u16 pcnet32_wio_read_csr(unsigned long addr, int index)
328 {
329 outw(index, addr + PCNET32_WIO_RAP);
330 return inw(addr + PCNET32_WIO_RDP);
331 }
332
333 static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val)
334 {
335 outw(index, addr + PCNET32_WIO_RAP);
336 outw(val, addr + PCNET32_WIO_RDP);
337 }
338
339 static u16 pcnet32_wio_read_bcr(unsigned long addr, int index)
340 {
341 outw(index, addr + PCNET32_WIO_RAP);
342 return inw(addr + PCNET32_WIO_BDP);
343 }
344
345 static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val)
346 {
347 outw(index, addr + PCNET32_WIO_RAP);
348 outw(val, addr + PCNET32_WIO_BDP);
349 }
350
351 static u16 pcnet32_wio_read_rap(unsigned long addr)
352 {
353 return inw(addr + PCNET32_WIO_RAP);
354 }
355
356 static void pcnet32_wio_write_rap(unsigned long addr, u16 val)
357 {
358 outw(val, addr + PCNET32_WIO_RAP);
359 }
360
361 static void pcnet32_wio_reset(unsigned long addr)
362 {
363 inw(addr + PCNET32_WIO_RESET);
364 }
365
366 static int pcnet32_wio_check(unsigned long addr)
367 {
368 outw(88, addr + PCNET32_WIO_RAP);
369 return (inw(addr + PCNET32_WIO_RAP) == 88);
370 }
371
372 static struct pcnet32_access pcnet32_wio = {
373 .read_csr = pcnet32_wio_read_csr,
374 .write_csr = pcnet32_wio_write_csr,
375 .read_bcr = pcnet32_wio_read_bcr,
376 .write_bcr = pcnet32_wio_write_bcr,
377 .read_rap = pcnet32_wio_read_rap,
378 .write_rap = pcnet32_wio_write_rap,
379 .reset = pcnet32_wio_reset
380 };
381
382 static u16 pcnet32_dwio_read_csr(unsigned long addr, int index)
383 {
384 outl(index, addr + PCNET32_DWIO_RAP);
385 return (inl(addr + PCNET32_DWIO_RDP) & 0xffff);
386 }
387
388 static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val)
389 {
390 outl(index, addr + PCNET32_DWIO_RAP);
391 outl(val, addr + PCNET32_DWIO_RDP);
392 }
393
394 static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index)
395 {
396 outl(index, addr + PCNET32_DWIO_RAP);
397 return (inl(addr + PCNET32_DWIO_BDP) & 0xffff);
398 }
399
400 static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val)
401 {
402 outl(index, addr + PCNET32_DWIO_RAP);
403 outl(val, addr + PCNET32_DWIO_BDP);
404 }
405
406 static u16 pcnet32_dwio_read_rap(unsigned long addr)
407 {
408 return (inl(addr + PCNET32_DWIO_RAP) & 0xffff);
409 }
410
411 static void pcnet32_dwio_write_rap(unsigned long addr, u16 val)
412 {
413 outl(val, addr + PCNET32_DWIO_RAP);
414 }
415
416 static void pcnet32_dwio_reset(unsigned long addr)
417 {
418 inl(addr + PCNET32_DWIO_RESET);
419 }
420
421 static int pcnet32_dwio_check(unsigned long addr)
422 {
423 outl(88, addr + PCNET32_DWIO_RAP);
424 return ((inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88);
425 }
426
427 static struct pcnet32_access pcnet32_dwio = {
428 .read_csr = pcnet32_dwio_read_csr,
429 .write_csr = pcnet32_dwio_write_csr,
430 .read_bcr = pcnet32_dwio_read_bcr,
431 .write_bcr = pcnet32_dwio_write_bcr,
432 .read_rap = pcnet32_dwio_read_rap,
433 .write_rap = pcnet32_dwio_write_rap,
434 .reset = pcnet32_dwio_reset
435 };
436
437 static void pcnet32_netif_stop(struct net_device *dev)
438 {
439 dev->trans_start = jiffies;
440 netif_poll_disable(dev);
441 netif_tx_disable(dev);
442 }
443
444 static void pcnet32_netif_start(struct net_device *dev)
445 {
446 netif_wake_queue(dev);
447 netif_poll_enable(dev);
448 }
449
450 /*
451 * Allocate space for the new sized tx ring.
452 * Free old resources
453 * Save new resources.
454 * Any failure keeps old resources.
455 * Must be called with lp->lock held.
456 */
457 static void pcnet32_realloc_tx_ring(struct net_device *dev,
458 struct pcnet32_private *lp,
459 unsigned int size)
460 {
461 dma_addr_t new_ring_dma_addr;
462 dma_addr_t *new_dma_addr_list;
463 struct pcnet32_tx_head *new_tx_ring;
464 struct sk_buff **new_skb_list;
465
466 pcnet32_purge_tx_ring(dev);
467
468 new_tx_ring = pci_alloc_consistent(lp->pci_dev,
469 sizeof(struct pcnet32_tx_head) *
470 (1 << size),
471 &new_ring_dma_addr);
472 if (new_tx_ring == NULL) {
473 if (netif_msg_drv(lp))
474 printk("\n" KERN_ERR
475 "%s: Consistent memory allocation failed.\n",
476 dev->name);
477 return;
478 }
479 memset(new_tx_ring, 0, sizeof(struct pcnet32_tx_head) * (1 << size));
480
481 new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
482 GFP_ATOMIC);
483 if (!new_dma_addr_list) {
484 if (netif_msg_drv(lp))
485 printk("\n" KERN_ERR
486 "%s: Memory allocation failed.\n", dev->name);
487 goto free_new_tx_ring;
488 }
489
490 new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
491 GFP_ATOMIC);
492 if (!new_skb_list) {
493 if (netif_msg_drv(lp))
494 printk("\n" KERN_ERR
495 "%s: Memory allocation failed.\n", dev->name);
496 goto free_new_lists;
497 }
498
499 kfree(lp->tx_skbuff);
500 kfree(lp->tx_dma_addr);
501 pci_free_consistent(lp->pci_dev,
502 sizeof(struct pcnet32_tx_head) *
503 lp->tx_ring_size, lp->tx_ring,
504 lp->tx_ring_dma_addr);
505
506 lp->tx_ring_size = (1 << size);
507 lp->tx_mod_mask = lp->tx_ring_size - 1;
508 lp->tx_len_bits = (size << 12);
509 lp->tx_ring = new_tx_ring;
510 lp->tx_ring_dma_addr = new_ring_dma_addr;
511 lp->tx_dma_addr = new_dma_addr_list;
512 lp->tx_skbuff = new_skb_list;
513 return;
514
515 free_new_lists:
516 kfree(new_dma_addr_list);
517 free_new_tx_ring:
518 pci_free_consistent(lp->pci_dev,
519 sizeof(struct pcnet32_tx_head) *
520 (1 << size),
521 new_tx_ring,
522 new_ring_dma_addr);
523 return;
524 }
525
526 /*
527 * Allocate space for the new sized rx ring.
528 * Re-use old receive buffers.
529 * alloc extra buffers
530 * free unneeded buffers
531 * free unneeded buffers
532 * Save new resources.
533 * Any failure keeps old resources.
534 * Must be called with lp->lock held.
535 */
536 static void pcnet32_realloc_rx_ring(struct net_device *dev,
537 struct pcnet32_private *lp,
538 unsigned int size)
539 {
540 dma_addr_t new_ring_dma_addr;
541 dma_addr_t *new_dma_addr_list;
542 struct pcnet32_rx_head *new_rx_ring;
543 struct sk_buff **new_skb_list;
544 int new, overlap;
545
546 new_rx_ring = pci_alloc_consistent(lp->pci_dev,
547 sizeof(struct pcnet32_rx_head) *
548 (1 << size),
549 &new_ring_dma_addr);
550 if (new_rx_ring == NULL) {
551 if (netif_msg_drv(lp))
552 printk("\n" KERN_ERR
553 "%s: Consistent memory allocation failed.\n",
554 dev->name);
555 return;
556 }
557 memset(new_rx_ring, 0, sizeof(struct pcnet32_rx_head) * (1 << size));
558
559 new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
560 GFP_ATOMIC);
561 if (!new_dma_addr_list) {
562 if (netif_msg_drv(lp))
563 printk("\n" KERN_ERR
564 "%s: Memory allocation failed.\n", dev->name);
565 goto free_new_rx_ring;
566 }
567
568 new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
569 GFP_ATOMIC);
570 if (!new_skb_list) {
571 if (netif_msg_drv(lp))
572 printk("\n" KERN_ERR
573 "%s: Memory allocation failed.\n", dev->name);
574 goto free_new_lists;
575 }
576
577 /* first copy the current receive buffers */
578 overlap = min(size, lp->rx_ring_size);
579 for (new = 0; new < overlap; new++) {
580 new_rx_ring[new] = lp->rx_ring[new];
581 new_dma_addr_list[new] = lp->rx_dma_addr[new];
582 new_skb_list[new] = lp->rx_skbuff[new];
583 }
584 /* now allocate any new buffers needed */
585 for (; new < size; new++ ) {
586 struct sk_buff *rx_skbuff;
587 new_skb_list[new] = dev_alloc_skb(PKT_BUF_SZ);
588 if (!(rx_skbuff = new_skb_list[new])) {
589 /* keep the original lists and buffers */
590 if (netif_msg_drv(lp))
591 printk(KERN_ERR
592 "%s: pcnet32_realloc_rx_ring dev_alloc_skb failed.\n",
593 dev->name);
594 goto free_all_new;
595 }
596 skb_reserve(rx_skbuff, 2);
597
598 new_dma_addr_list[new] =
599 pci_map_single(lp->pci_dev, rx_skbuff->data,
600 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
601 new_rx_ring[new].base = (u32) le32_to_cpu(new_dma_addr_list[new]);
602 new_rx_ring[new].buf_length = le16_to_cpu(2 - PKT_BUF_SZ);
603 new_rx_ring[new].status = le16_to_cpu(0x8000);
604 }
605 /* and free any unneeded buffers */
606 for (; new < lp->rx_ring_size; new++) {
607 if (lp->rx_skbuff[new]) {
608 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[new],
609 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
610 dev_kfree_skb(lp->rx_skbuff[new]);
611 }
612 }
613
614 kfree(lp->rx_skbuff);
615 kfree(lp->rx_dma_addr);
616 pci_free_consistent(lp->pci_dev,
617 sizeof(struct pcnet32_rx_head) *
618 lp->rx_ring_size, lp->rx_ring,
619 lp->rx_ring_dma_addr);
620
621 lp->rx_ring_size = (1 << size);
622 lp->rx_mod_mask = lp->rx_ring_size - 1;
623 lp->rx_len_bits = (size << 4);
624 lp->rx_ring = new_rx_ring;
625 lp->rx_ring_dma_addr = new_ring_dma_addr;
626 lp->rx_dma_addr = new_dma_addr_list;
627 lp->rx_skbuff = new_skb_list;
628 return;
629
630 free_all_new:
631 for (; --new >= lp->rx_ring_size; ) {
632 if (new_skb_list[new]) {
633 pci_unmap_single(lp->pci_dev, new_dma_addr_list[new],
634 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
635 dev_kfree_skb(new_skb_list[new]);
636 }
637 }
638 kfree(new_skb_list);
639 free_new_lists:
640 kfree(new_dma_addr_list);
641 free_new_rx_ring:
642 pci_free_consistent(lp->pci_dev,
643 sizeof(struct pcnet32_rx_head) *
644 (1 << size),
645 new_rx_ring,
646 new_ring_dma_addr);
647 return;
648 }
649
650 static void pcnet32_purge_rx_ring(struct net_device *dev)
651 {
652 struct pcnet32_private *lp = dev->priv;
653 int i;
654
655 /* free all allocated skbuffs */
656 for (i = 0; i < lp->rx_ring_size; i++) {
657 lp->rx_ring[i].status = 0; /* CPU owns buffer */
658 wmb(); /* Make sure adapter sees owner change */
659 if (lp->rx_skbuff[i]) {
660 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i],
661 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
662 dev_kfree_skb_any(lp->rx_skbuff[i]);
663 }
664 lp->rx_skbuff[i] = NULL;
665 lp->rx_dma_addr[i] = 0;
666 }
667 }
668
669 #ifdef CONFIG_NET_POLL_CONTROLLER
670 static void pcnet32_poll_controller(struct net_device *dev)
671 {
672 disable_irq(dev->irq);
673 pcnet32_interrupt(0, dev, NULL);
674 enable_irq(dev->irq);
675 }
676 #endif
677
678 static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
679 {
680 struct pcnet32_private *lp = dev->priv;
681 unsigned long flags;
682 int r = -EOPNOTSUPP;
683
684 if (lp->mii) {
685 spin_lock_irqsave(&lp->lock, flags);
686 mii_ethtool_gset(&lp->mii_if, cmd);
687 spin_unlock_irqrestore(&lp->lock, flags);
688 r = 0;
689 }
690 return r;
691 }
692
693 static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
694 {
695 struct pcnet32_private *lp = dev->priv;
696 unsigned long flags;
697 int r = -EOPNOTSUPP;
698
699 if (lp->mii) {
700 spin_lock_irqsave(&lp->lock, flags);
701 r = mii_ethtool_sset(&lp->mii_if, cmd);
702 spin_unlock_irqrestore(&lp->lock, flags);
703 }
704 return r;
705 }
706
707 static void pcnet32_get_drvinfo(struct net_device *dev,
708 struct ethtool_drvinfo *info)
709 {
710 struct pcnet32_private *lp = dev->priv;
711
712 strcpy(info->driver, DRV_NAME);
713 strcpy(info->version, DRV_VERSION);
714 if (lp->pci_dev)
715 strcpy(info->bus_info, pci_name(lp->pci_dev));
716 else
717 sprintf(info->bus_info, "VLB 0x%lx", dev->base_addr);
718 }
719
720 static u32 pcnet32_get_link(struct net_device *dev)
721 {
722 struct pcnet32_private *lp = dev->priv;
723 unsigned long flags;
724 int r;
725
726 spin_lock_irqsave(&lp->lock, flags);
727 if (lp->mii) {
728 r = mii_link_ok(&lp->mii_if);
729 } else if (lp->chip_version >= PCNET32_79C970A) {
730 ulong ioaddr = dev->base_addr; /* card base I/O address */
731 r = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
732 } else { /* can not detect link on really old chips */
733 r = 1;
734 }
735 spin_unlock_irqrestore(&lp->lock, flags);
736
737 return r;
738 }
739
740 static u32 pcnet32_get_msglevel(struct net_device *dev)
741 {
742 struct pcnet32_private *lp = dev->priv;
743 return lp->msg_enable;
744 }
745
746 static void pcnet32_set_msglevel(struct net_device *dev, u32 value)
747 {
748 struct pcnet32_private *lp = dev->priv;
749 lp->msg_enable = value;
750 }
751
752 static int pcnet32_nway_reset(struct net_device *dev)
753 {
754 struct pcnet32_private *lp = dev->priv;
755 unsigned long flags;
756 int r = -EOPNOTSUPP;
757
758 if (lp->mii) {
759 spin_lock_irqsave(&lp->lock, flags);
760 r = mii_nway_restart(&lp->mii_if);
761 spin_unlock_irqrestore(&lp->lock, flags);
762 }
763 return r;
764 }
765
766 static void pcnet32_get_ringparam(struct net_device *dev,
767 struct ethtool_ringparam *ering)
768 {
769 struct pcnet32_private *lp = dev->priv;
770
771 ering->tx_max_pending = TX_MAX_RING_SIZE;
772 ering->tx_pending = lp->tx_ring_size;
773 ering->rx_max_pending = RX_MAX_RING_SIZE;
774 ering->rx_pending = lp->rx_ring_size;
775 }
776
777 static int pcnet32_set_ringparam(struct net_device *dev,
778 struct ethtool_ringparam *ering)
779 {
780 struct pcnet32_private *lp = dev->priv;
781 unsigned long flags;
782 unsigned int size;
783 ulong ioaddr = dev->base_addr;
784 int i;
785
786 if (ering->rx_mini_pending || ering->rx_jumbo_pending)
787 return -EINVAL;
788
789 if (netif_running(dev))
790 pcnet32_netif_stop(dev);
791
792 spin_lock_irqsave(&lp->lock, flags);
793 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
794
795 size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE);
796
797 /* set the minimum ring size to 4, to allow the loopback test to work
798 * unchanged.
799 */
800 for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) {
801 if (size <= (1 << i))
802 break;
803 }
804 if ((1 << i) != lp->tx_ring_size)
805 pcnet32_realloc_tx_ring(dev, lp, i);
806
807 size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE);
808 for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) {
809 if (size <= (1 << i))
810 break;
811 }
812 if ((1 << i) != lp->rx_ring_size)
813 pcnet32_realloc_rx_ring(dev, lp, i);
814
815 dev->weight = lp->rx_ring_size / 2;
816
817 if (netif_running(dev)) {
818 pcnet32_netif_start(dev);
819 pcnet32_restart(dev, CSR0_NORMAL);
820 }
821
822 spin_unlock_irqrestore(&lp->lock, flags);
823
824 if (netif_msg_drv(lp))
825 printk(KERN_INFO
826 "%s: Ring Param Settings: RX: %d, TX: %d\n", dev->name,
827 lp->rx_ring_size, lp->tx_ring_size);
828
829 return 0;
830 }
831
832 static void pcnet32_get_strings(struct net_device *dev, u32 stringset,
833 u8 * data)
834 {
835 memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test));
836 }
837
838 static int pcnet32_self_test_count(struct net_device *dev)
839 {
840 return PCNET32_TEST_LEN;
841 }
842
843 static void pcnet32_ethtool_test(struct net_device *dev,
844 struct ethtool_test *test, u64 * data)
845 {
846 struct pcnet32_private *lp = dev->priv;
847 int rc;
848
849 if (test->flags == ETH_TEST_FL_OFFLINE) {
850 rc = pcnet32_loopback_test(dev, data);
851 if (rc) {
852 if (netif_msg_hw(lp))
853 printk(KERN_DEBUG "%s: Loopback test failed.\n",
854 dev->name);
855 test->flags |= ETH_TEST_FL_FAILED;
856 } else if (netif_msg_hw(lp))
857 printk(KERN_DEBUG "%s: Loopback test passed.\n",
858 dev->name);
859 } else if (netif_msg_hw(lp))
860 printk(KERN_DEBUG
861 "%s: No tests to run (specify 'Offline' on ethtool).",
862 dev->name);
863 } /* end pcnet32_ethtool_test */
864
865 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
866 {
867 struct pcnet32_private *lp = dev->priv;
868 struct pcnet32_access *a = &lp->a; /* access to registers */
869 ulong ioaddr = dev->base_addr; /* card base I/O address */
870 struct sk_buff *skb; /* sk buff */
871 int x, i; /* counters */
872 int numbuffs = 4; /* number of TX/RX buffers and descs */
873 u16 status = 0x8300; /* TX ring status */
874 u16 teststatus; /* test of ring status */
875 int rc; /* return code */
876 int size; /* size of packets */
877 unsigned char *packet; /* source packet data */
878 static const int data_len = 60; /* length of source packets */
879 unsigned long flags;
880 unsigned long ticks;
881
882 rc = 1; /* default to fail */
883
884 if (netif_running(dev))
885 pcnet32_close(dev);
886
887 spin_lock_irqsave(&lp->lock, flags);
888 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
889
890 numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size));
891
892 /* Reset the PCNET32 */
893 lp->a.reset(ioaddr);
894 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
895
896 /* switch pcnet32 to 32bit mode */
897 lp->a.write_bcr(ioaddr, 20, 2);
898
899 /* purge & init rings but don't actually restart */
900 pcnet32_restart(dev, 0x0000);
901
902 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
903
904 /* Initialize Transmit buffers. */
905 size = data_len + 15;
906 for (x = 0; x < numbuffs; x++) {
907 if (!(skb = dev_alloc_skb(size))) {
908 if (netif_msg_hw(lp))
909 printk(KERN_DEBUG
910 "%s: Cannot allocate skb at line: %d!\n",
911 dev->name, __LINE__);
912 goto clean_up;
913 } else {
914 packet = skb->data;
915 skb_put(skb, size); /* create space for data */
916 lp->tx_skbuff[x] = skb;
917 lp->tx_ring[x].length = le16_to_cpu(-skb->len);
918 lp->tx_ring[x].misc = 0;
919
920 /* put DA and SA into the skb */
921 for (i = 0; i < 6; i++)
922 *packet++ = dev->dev_addr[i];
923 for (i = 0; i < 6; i++)
924 *packet++ = dev->dev_addr[i];
925 /* type */
926 *packet++ = 0x08;
927 *packet++ = 0x06;
928 /* packet number */
929 *packet++ = x;
930 /* fill packet with data */
931 for (i = 0; i < data_len; i++)
932 *packet++ = i;
933
934 lp->tx_dma_addr[x] =
935 pci_map_single(lp->pci_dev, skb->data, skb->len,
936 PCI_DMA_TODEVICE);
937 lp->tx_ring[x].base =
938 (u32) le32_to_cpu(lp->tx_dma_addr[x]);
939 wmb(); /* Make sure owner changes after all others are visible */
940 lp->tx_ring[x].status = le16_to_cpu(status);
941 }
942 }
943
944 x = a->read_bcr(ioaddr, 32); /* set internal loopback in BCR32 */
945 a->write_bcr(ioaddr, 32, x | 0x0002);
946
947 /* set int loopback in CSR15 */
948 x = a->read_csr(ioaddr, CSR15) & 0xfffc;
949 lp->a.write_csr(ioaddr, CSR15, x | 0x0044);
950
951 teststatus = le16_to_cpu(0x8000);
952 lp->a.write_csr(ioaddr, CSR0, CSR0_START); /* Set STRT bit */
953
954 /* Check status of descriptors */
955 for (x = 0; x < numbuffs; x++) {
956 ticks = 0;
957 rmb();
958 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {
959 spin_unlock_irqrestore(&lp->lock, flags);
960 msleep(1);
961 spin_lock_irqsave(&lp->lock, flags);
962 rmb();
963 ticks++;
964 }
965 if (ticks == 200) {
966 if (netif_msg_hw(lp))
967 printk("%s: Desc %d failed to reset!\n",
968 dev->name, x);
969 break;
970 }
971 }
972
973 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
974 wmb();
975 if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {
976 printk(KERN_DEBUG "%s: RX loopback packets:\n", dev->name);
977
978 for (x = 0; x < numbuffs; x++) {
979 printk(KERN_DEBUG "%s: Packet %d:\n", dev->name, x);
980 skb = lp->rx_skbuff[x];
981 for (i = 0; i < size; i++) {
982 printk("%02x ", *(skb->data + i));
983 }
984 printk("\n");
985 }
986 }
987
988 x = 0;
989 rc = 0;
990 while (x < numbuffs && !rc) {
991 skb = lp->rx_skbuff[x];
992 packet = lp->tx_skbuff[x]->data;
993 for (i = 0; i < size; i++) {
994 if (*(skb->data + i) != packet[i]) {
995 if (netif_msg_hw(lp))
996 printk(KERN_DEBUG
997 "%s: Error in compare! %2x - %02x %02x\n",
998 dev->name, i, *(skb->data + i),
999 packet[i]);
1000 rc = 1;
1001 break;
1002 }
1003 }
1004 x++;
1005 }
1006
1007 clean_up:
1008 *data1 = rc;
1009 pcnet32_purge_tx_ring(dev);
1010
1011 x = a->read_csr(ioaddr, CSR15);
1012 a->write_csr(ioaddr, CSR15, (x & ~0x0044)); /* reset bits 6 and 2 */
1013
1014 x = a->read_bcr(ioaddr, 32); /* reset internal loopback */
1015 a->write_bcr(ioaddr, 32, (x & ~0x0002));
1016
1017 if (netif_running(dev)) {
1018 spin_unlock_irqrestore(&lp->lock, flags);
1019 pcnet32_open(dev);
1020 } else {
1021 pcnet32_purge_rx_ring(dev);
1022 lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
1023 spin_unlock_irqrestore(&lp->lock, flags);
1024 }
1025
1026 return (rc);
1027 } /* end pcnet32_loopback_test */
1028
1029 static void pcnet32_led_blink_callback(struct net_device *dev)
1030 {
1031 struct pcnet32_private *lp = dev->priv;
1032 struct pcnet32_access *a = &lp->a;
1033 ulong ioaddr = dev->base_addr;
1034 unsigned long flags;
1035 int i;
1036
1037 spin_lock_irqsave(&lp->lock, flags);
1038 for (i = 4; i < 8; i++) {
1039 a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000);
1040 }
1041 spin_unlock_irqrestore(&lp->lock, flags);
1042
1043 mod_timer(&lp->blink_timer, PCNET32_BLINK_TIMEOUT);
1044 }
1045
1046 static int pcnet32_phys_id(struct net_device *dev, u32 data)
1047 {
1048 struct pcnet32_private *lp = dev->priv;
1049 struct pcnet32_access *a = &lp->a;
1050 ulong ioaddr = dev->base_addr;
1051 unsigned long flags;
1052 int i, regs[4];
1053
1054 if (!lp->blink_timer.function) {
1055 init_timer(&lp->blink_timer);
1056 lp->blink_timer.function = (void *)pcnet32_led_blink_callback;
1057 lp->blink_timer.data = (unsigned long)dev;
1058 }
1059
1060 /* Save the current value of the bcrs */
1061 spin_lock_irqsave(&lp->lock, flags);
1062 for (i = 4; i < 8; i++) {
1063 regs[i - 4] = a->read_bcr(ioaddr, i);
1064 }
1065 spin_unlock_irqrestore(&lp->lock, flags);
1066
1067 mod_timer(&lp->blink_timer, jiffies);
1068 set_current_state(TASK_INTERRUPTIBLE);
1069
1070 if ((!data) || (data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ)))
1071 data = (u32) (MAX_SCHEDULE_TIMEOUT / HZ);
1072
1073 msleep_interruptible(data * 1000);
1074 del_timer_sync(&lp->blink_timer);
1075
1076 /* Restore the original value of the bcrs */
1077 spin_lock_irqsave(&lp->lock, flags);
1078 for (i = 4; i < 8; i++) {
1079 a->write_bcr(ioaddr, i, regs[i - 4]);
1080 }
1081 spin_unlock_irqrestore(&lp->lock, flags);
1082
1083 return 0;
1084 }
1085
1086 /*
1087 * lp->lock must be held.
1088 */
1089 static int pcnet32_suspend(struct net_device *dev, unsigned long *flags,
1090 int can_sleep)
1091 {
1092 int csr5;
1093 struct pcnet32_private *lp = dev->priv;
1094 struct pcnet32_access *a = &lp->a;
1095 ulong ioaddr = dev->base_addr;
1096 int ticks;
1097
1098 /* really old chips have to be stopped. */
1099 if (lp->chip_version < PCNET32_79C970A)
1100 return 0;
1101
1102 /* set SUSPEND (SPND) - CSR5 bit 0 */
1103 csr5 = a->read_csr(ioaddr, CSR5);
1104 a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
1105
1106 /* poll waiting for bit to be set */
1107 ticks = 0;
1108 while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) {
1109 spin_unlock_irqrestore(&lp->lock, *flags);
1110 if (can_sleep)
1111 msleep(1);
1112 else
1113 mdelay(1);
1114 spin_lock_irqsave(&lp->lock, *flags);
1115 ticks++;
1116 if (ticks > 200) {
1117 if (netif_msg_hw(lp))
1118 printk(KERN_DEBUG
1119 "%s: Error getting into suspend!\n",
1120 dev->name);
1121 return 0;
1122 }
1123 }
1124 return 1;
1125 }
1126
1127 /*
1128 * process one receive descriptor entry
1129 */
1130
1131 static void pcnet32_rx_entry(struct net_device *dev,
1132 struct pcnet32_private *lp,
1133 struct pcnet32_rx_head *rxp,
1134 int entry)
1135 {
1136 int status = (short)le16_to_cpu(rxp->status) >> 8;
1137 int rx_in_place = 0;
1138 struct sk_buff *skb;
1139 short pkt_len;
1140
1141 if (status != 0x03) { /* There was an error. */
1142 /*
1143 * There is a tricky error noted by John Murphy,
1144 * <murf@perftech.com> to Russ Nelson: Even with full-sized
1145 * buffers it's possible for a jabber packet to use two
1146 * buffers, with only the last correctly noting the error.
1147 */
1148 if (status & 0x01) /* Only count a general error at the */
1149 lp->stats.rx_errors++; /* end of a packet. */
1150 if (status & 0x20)
1151 lp->stats.rx_frame_errors++;
1152 if (status & 0x10)
1153 lp->stats.rx_over_errors++;
1154 if (status & 0x08)
1155 lp->stats.rx_crc_errors++;
1156 if (status & 0x04)
1157 lp->stats.rx_fifo_errors++;
1158 return;
1159 }
1160
1161 pkt_len = (le32_to_cpu(rxp->msg_length) & 0xfff) - 4;
1162
1163 /* Discard oversize frames. */
1164 if (unlikely(pkt_len > PKT_BUF_SZ - 2)) {
1165 if (netif_msg_drv(lp))
1166 printk(KERN_ERR "%s: Impossible packet size %d!\n",
1167 dev->name, pkt_len);
1168 lp->stats.rx_errors++;
1169 return;
1170 }
1171 if (pkt_len < 60) {
1172 if (netif_msg_rx_err(lp))
1173 printk(KERN_ERR "%s: Runt packet!\n", dev->name);
1174 lp->stats.rx_errors++;
1175 return;
1176 }
1177
1178 if (pkt_len > rx_copybreak) {
1179 struct sk_buff *newskb;
1180
1181 if ((newskb = dev_alloc_skb(PKT_BUF_SZ))) {
1182 skb_reserve(newskb, 2);
1183 skb = lp->rx_skbuff[entry];
1184 pci_unmap_single(lp->pci_dev,
1185 lp->rx_dma_addr[entry],
1186 PKT_BUF_SZ - 2,
1187 PCI_DMA_FROMDEVICE);
1188 skb_put(skb, pkt_len);
1189 lp->rx_skbuff[entry] = newskb;
1190 newskb->dev = dev;
1191 lp->rx_dma_addr[entry] =
1192 pci_map_single(lp->pci_dev,
1193 newskb->data,
1194 PKT_BUF_SZ - 2,
1195 PCI_DMA_FROMDEVICE);
1196 rxp->base = le32_to_cpu(lp->rx_dma_addr[entry]);
1197 rx_in_place = 1;
1198 } else
1199 skb = NULL;
1200 } else {
1201 skb = dev_alloc_skb(pkt_len + 2);
1202 }
1203
1204 if (skb == NULL) {
1205 if (netif_msg_drv(lp))
1206 printk(KERN_ERR
1207 "%s: Memory squeeze, dropping packet.\n",
1208 dev->name);
1209 lp->stats.rx_dropped++;
1210 return;
1211 }
1212 skb->dev = dev;
1213 if (!rx_in_place) {
1214 skb_reserve(skb, 2); /* 16 byte align */
1215 skb_put(skb, pkt_len); /* Make room */
1216 pci_dma_sync_single_for_cpu(lp->pci_dev,
1217 lp->rx_dma_addr[entry],
1218 PKT_BUF_SZ - 2,
1219 PCI_DMA_FROMDEVICE);
1220 eth_copy_and_sum(skb,
1221 (unsigned char *)(lp->rx_skbuff[entry]->data),
1222 pkt_len, 0);
1223 pci_dma_sync_single_for_device(lp->pci_dev,
1224 lp->rx_dma_addr[entry],
1225 PKT_BUF_SZ - 2,
1226 PCI_DMA_FROMDEVICE);
1227 }
1228 lp->stats.rx_bytes += skb->len;
1229 skb->protocol = eth_type_trans(skb, dev);
1230 netif_rx(skb);
1231 dev->last_rx = jiffies;
1232 lp->stats.rx_packets++;
1233 return;
1234 }
1235
1236
1237 static void pcnet32_rx(struct net_device *dev)
1238 {
1239 struct pcnet32_private *lp = dev->priv;
1240 int entry = lp->cur_rx & lp->rx_mod_mask;
1241 struct pcnet32_rx_head *rxp = &lp->rx_ring[entry];
1242 int npackets = 0;
1243 int boguscnt = lp->rx_ring_size / 2;
1244
1245 /* If we own the next entry, it's a new packet. Send it up. */
1246 while (boguscnt > npackets && (short)le16_to_cpu(rxp->status) >= 0) {
1247 pcnet32_rx_entry(dev, lp, rxp, entry);
1248 npackets += 1;
1249 /*
1250 * The docs say that the buffer length isn't touched, but Andrew
1251 * Boyd of QNX reports that some revs of the 79C965 clear it.
1252 */
1253 rxp->buf_length = le16_to_cpu(2 - PKT_BUF_SZ);
1254 wmb(); /* Make sure owner changes after others are visible */
1255 rxp->status = le16_to_cpu(0x8000);
1256 entry = (++lp->cur_rx) & lp->rx_mod_mask;
1257 rxp = &lp->rx_ring[entry];
1258 }
1259
1260 return;
1261 }
1262
1263 static int pcnet32_tx(struct net_device *dev, u16 csr0)
1264 {
1265 struct pcnet32_private *lp = dev->priv;
1266 unsigned int dirty_tx = lp->dirty_tx;
1267 int delta;
1268 int must_restart = 0;
1269
1270 while (dirty_tx != lp->cur_tx) {
1271 int entry = dirty_tx & lp->tx_mod_mask;
1272 int status = (short)le16_to_cpu(lp->tx_ring[entry].status);
1273
1274 if (status < 0)
1275 break; /* It still hasn't been Txed */
1276
1277 lp->tx_ring[entry].base = 0;
1278
1279 if (status & 0x4000) {
1280 /* There was a major error, log it. */
1281 int err_status = le32_to_cpu(lp->tx_ring[entry].misc);
1282 lp->stats.tx_errors++;
1283 if (netif_msg_tx_err(lp))
1284 printk(KERN_ERR
1285 "%s: Tx error status=%04x err_status=%08x\n",
1286 dev->name, status,
1287 err_status);
1288 if (err_status & 0x04000000)
1289 lp->stats.tx_aborted_errors++;
1290 if (err_status & 0x08000000)
1291 lp->stats.tx_carrier_errors++;
1292 if (err_status & 0x10000000)
1293 lp->stats.tx_window_errors++;
1294 #ifndef DO_DXSUFLO
1295 if (err_status & 0x40000000) {
1296 lp->stats.tx_fifo_errors++;
1297 /* Ackk! On FIFO errors the Tx unit is turned off! */
1298 /* Remove this verbosity later! */
1299 if (netif_msg_tx_err(lp))
1300 printk(KERN_ERR
1301 "%s: Tx FIFO error! CSR0=%4.4x\n",
1302 dev->name, csr0);
1303 must_restart = 1;
1304 }
1305 #else
1306 if (err_status & 0x40000000) {
1307 lp->stats.tx_fifo_errors++;
1308 if (!lp->dxsuflo) { /* If controller doesn't recover ... */
1309 /* Ackk! On FIFO errors the Tx unit is turned off! */
1310 /* Remove this verbosity later! */
1311 if (netif_msg_tx_err(lp))
1312 printk(KERN_ERR
1313 "%s: Tx FIFO error! CSR0=%4.4x\n",
1314 dev->name, csr0);
1315 must_restart = 1;
1316 }
1317 }
1318 #endif
1319 } else {
1320 if (status & 0x1800)
1321 lp->stats.collisions++;
1322 lp->stats.tx_packets++;
1323 }
1324
1325 /* We must free the original skb */
1326 if (lp->tx_skbuff[entry]) {
1327 pci_unmap_single(lp->pci_dev,
1328 lp->tx_dma_addr[entry],
1329 lp->tx_skbuff[entry]->
1330 len, PCI_DMA_TODEVICE);
1331 dev_kfree_skb_any(lp->tx_skbuff[entry]);
1332 lp->tx_skbuff[entry] = NULL;
1333 lp->tx_dma_addr[entry] = 0;
1334 }
1335 dirty_tx++;
1336 }
1337
1338 delta = (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + lp->tx_ring_size);
1339 if (delta > lp->tx_ring_size) {
1340 if (netif_msg_drv(lp))
1341 printk(KERN_ERR
1342 "%s: out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1343 dev->name, dirty_tx, lp->cur_tx,
1344 lp->tx_full);
1345 dirty_tx += lp->tx_ring_size;
1346 delta -= lp->tx_ring_size;
1347 }
1348
1349 if (lp->tx_full &&
1350 netif_queue_stopped(dev) &&
1351 delta < lp->tx_ring_size - 2) {
1352 /* The ring is no longer full, clear tbusy. */
1353 lp->tx_full = 0;
1354 netif_wake_queue(dev);
1355 }
1356 lp->dirty_tx = dirty_tx;
1357
1358 return must_restart;
1359 }
1360
1361 #define PCNET32_REGS_PER_PHY 32
1362 #define PCNET32_MAX_PHYS 32
1363 static int pcnet32_get_regs_len(struct net_device *dev)
1364 {
1365 struct pcnet32_private *lp = dev->priv;
1366 int j = lp->phycount * PCNET32_REGS_PER_PHY;
1367
1368 return ((PCNET32_NUM_REGS + j) * sizeof(u16));
1369 }
1370
1371 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1372 void *ptr)
1373 {
1374 int i, csr0;
1375 u16 *buff = ptr;
1376 struct pcnet32_private *lp = dev->priv;
1377 struct pcnet32_access *a = &lp->a;
1378 ulong ioaddr = dev->base_addr;
1379 unsigned long flags;
1380
1381 spin_lock_irqsave(&lp->lock, flags);
1382
1383 csr0 = a->read_csr(ioaddr, CSR0);
1384 if (!(csr0 & CSR0_STOP)) /* If not stopped */
1385 pcnet32_suspend(dev, &flags, 1);
1386
1387 /* read address PROM */
1388 for (i = 0; i < 16; i += 2)
1389 *buff++ = inw(ioaddr + i);
1390
1391 /* read control and status registers */
1392 for (i = 0; i < 90; i++) {
1393 *buff++ = a->read_csr(ioaddr, i);
1394 }
1395
1396 *buff++ = a->read_csr(ioaddr, 112);
1397 *buff++ = a->read_csr(ioaddr, 114);
1398
1399 /* read bus configuration registers */
1400 for (i = 0; i < 30; i++) {
1401 *buff++ = a->read_bcr(ioaddr, i);
1402 }
1403 *buff++ = 0; /* skip bcr30 so as not to hang 79C976 */
1404 for (i = 31; i < 36; i++) {
1405 *buff++ = a->read_bcr(ioaddr, i);
1406 }
1407
1408 /* read mii phy registers */
1409 if (lp->mii) {
1410 int j;
1411 for (j = 0; j < PCNET32_MAX_PHYS; j++) {
1412 if (lp->phymask & (1 << j)) {
1413 for (i = 0; i < PCNET32_REGS_PER_PHY; i++) {
1414 lp->a.write_bcr(ioaddr, 33,
1415 (j << 5) | i);
1416 *buff++ = lp->a.read_bcr(ioaddr, 34);
1417 }
1418 }
1419 }
1420 }
1421
1422 if (!(csr0 & CSR0_STOP)) { /* If not stopped */
1423 int csr5;
1424
1425 /* clear SUSPEND (SPND) - CSR5 bit 0 */
1426 csr5 = a->read_csr(ioaddr, CSR5);
1427 a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
1428 }
1429
1430 spin_unlock_irqrestore(&lp->lock, flags);
1431 }
1432
1433 static struct ethtool_ops pcnet32_ethtool_ops = {
1434 .get_settings = pcnet32_get_settings,
1435 .set_settings = pcnet32_set_settings,
1436 .get_drvinfo = pcnet32_get_drvinfo,
1437 .get_msglevel = pcnet32_get_msglevel,
1438 .set_msglevel = pcnet32_set_msglevel,
1439 .nway_reset = pcnet32_nway_reset,
1440 .get_link = pcnet32_get_link,
1441 .get_ringparam = pcnet32_get_ringparam,
1442 .set_ringparam = pcnet32_set_ringparam,
1443 .get_tx_csum = ethtool_op_get_tx_csum,
1444 .get_sg = ethtool_op_get_sg,
1445 .get_tso = ethtool_op_get_tso,
1446 .get_strings = pcnet32_get_strings,
1447 .self_test_count = pcnet32_self_test_count,
1448 .self_test = pcnet32_ethtool_test,
1449 .phys_id = pcnet32_phys_id,
1450 .get_regs_len = pcnet32_get_regs_len,
1451 .get_regs = pcnet32_get_regs,
1452 .get_perm_addr = ethtool_op_get_perm_addr,
1453 };
1454
1455 /* only probes for non-PCI devices, the rest are handled by
1456 * pci_register_driver via pcnet32_probe_pci */
1457
1458 static void __devinit pcnet32_probe_vlbus(unsigned int *pcnet32_portlist)
1459 {
1460 unsigned int *port, ioaddr;
1461
1462 /* search for PCnet32 VLB cards at known addresses */
1463 for (port = pcnet32_portlist; (ioaddr = *port); port++) {
1464 if (request_region
1465 (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {
1466 /* check if there is really a pcnet chip on that ioaddr */
1467 if ((inb(ioaddr + 14) == 0x57)
1468 && (inb(ioaddr + 15) == 0x57)) {
1469 pcnet32_probe1(ioaddr, 0, NULL);
1470 } else {
1471 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1472 }
1473 }
1474 }
1475 }
1476
1477 static int __devinit
1478 pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
1479 {
1480 unsigned long ioaddr;
1481 int err;
1482
1483 err = pci_enable_device(pdev);
1484 if (err < 0) {
1485 if (pcnet32_debug & NETIF_MSG_PROBE)
1486 printk(KERN_ERR PFX
1487 "failed to enable device -- err=%d\n", err);
1488 return err;
1489 }
1490 pci_set_master(pdev);
1491
1492 ioaddr = pci_resource_start(pdev, 0);
1493 if (!ioaddr) {
1494 if (pcnet32_debug & NETIF_MSG_PROBE)
1495 printk(KERN_ERR PFX
1496 "card has no PCI IO resources, aborting\n");
1497 return -ENODEV;
1498 }
1499
1500 if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) {
1501 if (pcnet32_debug & NETIF_MSG_PROBE)
1502 printk(KERN_ERR PFX
1503 "architecture does not support 32bit PCI busmaster DMA\n");
1504 return -ENODEV;
1505 }
1506 if (request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci") ==
1507 NULL) {
1508 if (pcnet32_debug & NETIF_MSG_PROBE)
1509 printk(KERN_ERR PFX
1510 "io address range already allocated\n");
1511 return -EBUSY;
1512 }
1513
1514 err = pcnet32_probe1(ioaddr, 1, pdev);
1515 if (err < 0) {
1516 pci_disable_device(pdev);
1517 }
1518 return err;
1519 }
1520
1521 /* pcnet32_probe1
1522 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
1523 * pdev will be NULL when called from pcnet32_probe_vlbus.
1524 */
1525 static int __devinit
1526 pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
1527 {
1528 struct pcnet32_private *lp;
1529 dma_addr_t lp_dma_addr;
1530 int i, media;
1531 int fdx, mii, fset, dxsuflo;
1532 int chip_version;
1533 char *chipname;
1534 struct net_device *dev;
1535 struct pcnet32_access *a = NULL;
1536 u8 promaddr[6];
1537 int ret = -ENODEV;
1538
1539 /* reset the chip */
1540 pcnet32_wio_reset(ioaddr);
1541
1542 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
1543 if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
1544 a = &pcnet32_wio;
1545 } else {
1546 pcnet32_dwio_reset(ioaddr);
1547 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4
1548 && pcnet32_dwio_check(ioaddr)) {
1549 a = &pcnet32_dwio;
1550 } else
1551 goto err_release_region;
1552 }
1553
1554 chip_version =
1555 a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16);
1556 if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW))
1557 printk(KERN_INFO " PCnet chip version is %#x.\n",
1558 chip_version);
1559 if ((chip_version & 0xfff) != 0x003) {
1560 if (pcnet32_debug & NETIF_MSG_PROBE)
1561 printk(KERN_INFO PFX "Unsupported chip version.\n");
1562 goto err_release_region;
1563 }
1564
1565 /* initialize variables */
1566 fdx = mii = fset = dxsuflo = 0;
1567 chip_version = (chip_version >> 12) & 0xffff;
1568
1569 switch (chip_version) {
1570 case 0x2420:
1571 chipname = "PCnet/PCI 79C970"; /* PCI */
1572 break;
1573 case 0x2430:
1574 if (shared)
1575 chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
1576 else
1577 chipname = "PCnet/32 79C965"; /* 486/VL bus */
1578 break;
1579 case 0x2621:
1580 chipname = "PCnet/PCI II 79C970A"; /* PCI */
1581 fdx = 1;
1582 break;
1583 case 0x2623:
1584 chipname = "PCnet/FAST 79C971"; /* PCI */
1585 fdx = 1;
1586 mii = 1;
1587 fset = 1;
1588 break;
1589 case 0x2624:
1590 chipname = "PCnet/FAST+ 79C972"; /* PCI */
1591 fdx = 1;
1592 mii = 1;
1593 fset = 1;
1594 break;
1595 case 0x2625:
1596 chipname = "PCnet/FAST III 79C973"; /* PCI */
1597 fdx = 1;
1598 mii = 1;
1599 break;
1600 case 0x2626:
1601 chipname = "PCnet/Home 79C978"; /* PCI */
1602 fdx = 1;
1603 /*
1604 * This is based on specs published at www.amd.com. This section
1605 * assumes that a card with a 79C978 wants to go into standard
1606 * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode,
1607 * and the module option homepna=1 can select this instead.
1608 */
1609 media = a->read_bcr(ioaddr, 49);
1610 media &= ~3; /* default to 10Mb ethernet */
1611 if (cards_found < MAX_UNITS && homepna[cards_found])
1612 media |= 1; /* switch to home wiring mode */
1613 if (pcnet32_debug & NETIF_MSG_PROBE)
1614 printk(KERN_DEBUG PFX "media set to %sMbit mode.\n",
1615 (media & 1) ? "1" : "10");
1616 a->write_bcr(ioaddr, 49, media);
1617 break;
1618 case 0x2627:
1619 chipname = "PCnet/FAST III 79C975"; /* PCI */
1620 fdx = 1;
1621 mii = 1;
1622 break;
1623 case 0x2628:
1624 chipname = "PCnet/PRO 79C976";
1625 fdx = 1;
1626 mii = 1;
1627 break;
1628 default:
1629 if (pcnet32_debug & NETIF_MSG_PROBE)
1630 printk(KERN_INFO PFX
1631 "PCnet version %#x, no PCnet32 chip.\n",
1632 chip_version);
1633 goto err_release_region;
1634 }
1635
1636 /*
1637 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1638 * starting until the packet is loaded. Strike one for reliability, lose
1639 * one for latency - although on PCI this isnt a big loss. Older chips
1640 * have FIFO's smaller than a packet, so you can't do this.
1641 * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1642 */
1643
1644 if (fset) {
1645 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860));
1646 a->write_csr(ioaddr, 80,
1647 (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
1648 dxsuflo = 1;
1649 }
1650
1651 dev = alloc_etherdev(0);
1652 if (!dev) {
1653 if (pcnet32_debug & NETIF_MSG_PROBE)
1654 printk(KERN_ERR PFX "Memory allocation failed.\n");
1655 ret = -ENOMEM;
1656 goto err_release_region;
1657 }
1658 SET_NETDEV_DEV(dev, &pdev->dev);
1659
1660 if (pcnet32_debug & NETIF_MSG_PROBE)
1661 printk(KERN_INFO PFX "%s at %#3lx,", chipname, ioaddr);
1662
1663 /* In most chips, after a chip reset, the ethernet address is read from the
1664 * station address PROM at the base address and programmed into the
1665 * "Physical Address Registers" CSR12-14.
1666 * As a precautionary measure, we read the PROM values and complain if
1667 * they disagree with the CSRs. If they miscompare, and the PROM addr
1668 * is valid, then the PROM addr is used.
1669 */
1670 for (i = 0; i < 3; i++) {
1671 unsigned int val;
1672 val = a->read_csr(ioaddr, i + 12) & 0x0ffff;
1673 /* There may be endianness issues here. */
1674 dev->dev_addr[2 * i] = val & 0x0ff;
1675 dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff;
1676 }
1677
1678 /* read PROM address and compare with CSR address */
1679 for (i = 0; i < 6; i++)
1680 promaddr[i] = inb(ioaddr + i);
1681
1682 if (memcmp(promaddr, dev->dev_addr, 6)
1683 || !is_valid_ether_addr(dev->dev_addr)) {
1684 if (is_valid_ether_addr(promaddr)) {
1685 if (pcnet32_debug & NETIF_MSG_PROBE) {
1686 printk(" warning: CSR address invalid,\n");
1687 printk(KERN_INFO
1688 " using instead PROM address of");
1689 }
1690 memcpy(dev->dev_addr, promaddr, 6);
1691 }
1692 }
1693 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1694
1695 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
1696 if (!is_valid_ether_addr(dev->perm_addr))
1697 memset(dev->dev_addr, 0, sizeof(dev->dev_addr));
1698
1699 if (pcnet32_debug & NETIF_MSG_PROBE) {
1700 for (i = 0; i < 6; i++)
1701 printk(" %2.2x", dev->dev_addr[i]);
1702
1703 /* Version 0x2623 and 0x2624 */
1704 if (((chip_version + 1) & 0xfffe) == 0x2624) {
1705 i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */
1706 printk("\n" KERN_INFO " tx_start_pt(0x%04x):", i);
1707 switch (i >> 10) {
1708 case 0:
1709 printk(" 20 bytes,");
1710 break;
1711 case 1:
1712 printk(" 64 bytes,");
1713 break;
1714 case 2:
1715 printk(" 128 bytes,");
1716 break;
1717 case 3:
1718 printk("~220 bytes,");
1719 break;
1720 }
1721 i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */
1722 printk(" BCR18(%x):", i & 0xffff);
1723 if (i & (1 << 5))
1724 printk("BurstWrEn ");
1725 if (i & (1 << 6))
1726 printk("BurstRdEn ");
1727 if (i & (1 << 7))
1728 printk("DWordIO ");
1729 if (i & (1 << 11))
1730 printk("NoUFlow ");
1731 i = a->read_bcr(ioaddr, 25);
1732 printk("\n" KERN_INFO " SRAMSIZE=0x%04x,", i << 8);
1733 i = a->read_bcr(ioaddr, 26);
1734 printk(" SRAM_BND=0x%04x,", i << 8);
1735 i = a->read_bcr(ioaddr, 27);
1736 if (i & (1 << 14))
1737 printk("LowLatRx");
1738 }
1739 }
1740
1741 dev->base_addr = ioaddr;
1742 /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
1743 if ((lp =
1744 pci_alloc_consistent(pdev, sizeof(*lp), &lp_dma_addr)) == NULL) {
1745 if (pcnet32_debug & NETIF_MSG_PROBE)
1746 printk(KERN_ERR PFX
1747 "Consistent memory allocation failed.\n");
1748 ret = -ENOMEM;
1749 goto err_free_netdev;
1750 }
1751
1752 memset(lp, 0, sizeof(*lp));
1753 lp->dma_addr = lp_dma_addr;
1754 lp->pci_dev = pdev;
1755
1756 spin_lock_init(&lp->lock);
1757
1758 SET_MODULE_OWNER(dev);
1759 SET_NETDEV_DEV(dev, &pdev->dev);
1760 dev->priv = lp;
1761 lp->name = chipname;
1762 lp->shared_irq = shared;
1763 lp->tx_ring_size = TX_RING_SIZE; /* default tx ring size */
1764 lp->rx_ring_size = RX_RING_SIZE; /* default rx ring size */
1765 lp->tx_mod_mask = lp->tx_ring_size - 1;
1766 lp->rx_mod_mask = lp->rx_ring_size - 1;
1767 lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12);
1768 lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4);
1769 lp->mii_if.full_duplex = fdx;
1770 lp->mii_if.phy_id_mask = 0x1f;
1771 lp->mii_if.reg_num_mask = 0x1f;
1772 lp->dxsuflo = dxsuflo;
1773 lp->mii = mii;
1774 lp->chip_version = chip_version;
1775 lp->msg_enable = pcnet32_debug;
1776 if ((cards_found >= MAX_UNITS)
1777 || (options[cards_found] > sizeof(options_mapping)))
1778 lp->options = PCNET32_PORT_ASEL;
1779 else
1780 lp->options = options_mapping[options[cards_found]];
1781 lp->mii_if.dev = dev;
1782 lp->mii_if.mdio_read = mdio_read;
1783 lp->mii_if.mdio_write = mdio_write;
1784
1785 if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
1786 ((cards_found >= MAX_UNITS) || full_duplex[cards_found]))
1787 lp->options |= PCNET32_PORT_FD;
1788
1789 if (!a) {
1790 if (pcnet32_debug & NETIF_MSG_PROBE)
1791 printk(KERN_ERR PFX "No access methods\n");
1792 ret = -ENODEV;
1793 goto err_free_consistent;
1794 }
1795 lp->a = *a;
1796
1797 /* prior to register_netdev, dev->name is not yet correct */
1798 if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) {
1799 ret = -ENOMEM;
1800 goto err_free_ring;
1801 }
1802 /* detect special T1/E1 WAN card by checking for MAC address */
1803 if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0
1804 && dev->dev_addr[2] == 0x75)
1805 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
1806
1807 lp->init_block.mode = le16_to_cpu(0x0003); /* Disable Rx and Tx. */
1808 lp->init_block.tlen_rlen =
1809 le16_to_cpu(lp->tx_len_bits | lp->rx_len_bits);
1810 for (i = 0; i < 6; i++)
1811 lp->init_block.phys_addr[i] = dev->dev_addr[i];
1812 lp->init_block.filter[0] = 0x00000000;
1813 lp->init_block.filter[1] = 0x00000000;
1814 lp->init_block.rx_ring = (u32) le32_to_cpu(lp->rx_ring_dma_addr);
1815 lp->init_block.tx_ring = (u32) le32_to_cpu(lp->tx_ring_dma_addr);
1816
1817 /* switch pcnet32 to 32bit mode */
1818 a->write_bcr(ioaddr, 20, 2);
1819
1820 a->write_csr(ioaddr, 1, (lp->dma_addr + offsetof(struct pcnet32_private,
1821 init_block)) & 0xffff);
1822 a->write_csr(ioaddr, 2, (lp->dma_addr + offsetof(struct pcnet32_private,
1823 init_block)) >> 16);
1824
1825 if (pdev) { /* use the IRQ provided by PCI */
1826 dev->irq = pdev->irq;
1827 if (pcnet32_debug & NETIF_MSG_PROBE)
1828 printk(" assigned IRQ %d.\n", dev->irq);
1829 } else {
1830 unsigned long irq_mask = probe_irq_on();
1831
1832 /*
1833 * To auto-IRQ we enable the initialization-done and DMA error
1834 * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1835 * boards will work.
1836 */
1837 /* Trigger an initialization just for the interrupt. */
1838 a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT);
1839 mdelay(1);
1840
1841 dev->irq = probe_irq_off(irq_mask);
1842 if (!dev->irq) {
1843 if (pcnet32_debug & NETIF_MSG_PROBE)
1844 printk(", failed to detect IRQ line.\n");
1845 ret = -ENODEV;
1846 goto err_free_ring;
1847 }
1848 if (pcnet32_debug & NETIF_MSG_PROBE)
1849 printk(", probed IRQ %d.\n", dev->irq);
1850 }
1851
1852 /* Set the mii phy_id so that we can query the link state */
1853 if (lp->mii) {
1854 /* lp->phycount and lp->phymask are set to 0 by memset above */
1855
1856 lp->mii_if.phy_id = ((lp->a.read_bcr(ioaddr, 33)) >> 5) & 0x1f;
1857 /* scan for PHYs */
1858 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
1859 unsigned short id1, id2;
1860
1861 id1 = mdio_read(dev, i, MII_PHYSID1);
1862 if (id1 == 0xffff)
1863 continue;
1864 id2 = mdio_read(dev, i, MII_PHYSID2);
1865 if (id2 == 0xffff)
1866 continue;
1867 if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624)
1868 continue; /* 79C971 & 79C972 have phantom phy at id 31 */
1869 lp->phycount++;
1870 lp->phymask |= (1 << i);
1871 lp->mii_if.phy_id = i;
1872 if (pcnet32_debug & NETIF_MSG_PROBE)
1873 printk(KERN_INFO PFX
1874 "Found PHY %04x:%04x at address %d.\n",
1875 id1, id2, i);
1876 }
1877 lp->a.write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5);
1878 if (lp->phycount > 1) {
1879 lp->options |= PCNET32_PORT_MII;
1880 }
1881 }
1882
1883 init_timer(&lp->watchdog_timer);
1884 lp->watchdog_timer.data = (unsigned long)dev;
1885 lp->watchdog_timer.function = (void *)&pcnet32_watchdog;
1886
1887 /* The PCNET32-specific entries in the device structure. */
1888 dev->open = &pcnet32_open;
1889 dev->hard_start_xmit = &pcnet32_start_xmit;
1890 dev->stop = &pcnet32_close;
1891 dev->get_stats = &pcnet32_get_stats;
1892 dev->set_multicast_list = &pcnet32_set_multicast_list;
1893 dev->do_ioctl = &pcnet32_ioctl;
1894 dev->ethtool_ops = &pcnet32_ethtool_ops;
1895 dev->tx_timeout = pcnet32_tx_timeout;
1896 dev->watchdog_timeo = (5 * HZ);
1897
1898 #ifdef CONFIG_NET_POLL_CONTROLLER
1899 dev->poll_controller = pcnet32_poll_controller;
1900 #endif
1901
1902 /* Fill in the generic fields of the device structure. */
1903 if (register_netdev(dev))
1904 goto err_free_ring;
1905
1906 if (pdev) {
1907 pci_set_drvdata(pdev, dev);
1908 } else {
1909 lp->next = pcnet32_dev;
1910 pcnet32_dev = dev;
1911 }
1912
1913 if (pcnet32_debug & NETIF_MSG_PROBE)
1914 printk(KERN_INFO "%s: registered as %s\n", dev->name, lp->name);
1915 cards_found++;
1916
1917 /* enable LED writes */
1918 a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000);
1919
1920 return 0;
1921
1922 err_free_ring:
1923 pcnet32_free_ring(dev);
1924 err_free_consistent:
1925 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
1926 err_free_netdev:
1927 free_netdev(dev);
1928 err_release_region:
1929 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1930 return ret;
1931 }
1932
1933 /* if any allocation fails, caller must also call pcnet32_free_ring */
1934 static int pcnet32_alloc_ring(struct net_device *dev, char *name)
1935 {
1936 struct pcnet32_private *lp = dev->priv;
1937
1938 lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
1939 sizeof(struct pcnet32_tx_head) *
1940 lp->tx_ring_size,
1941 &lp->tx_ring_dma_addr);
1942 if (lp->tx_ring == NULL) {
1943 if (netif_msg_drv(lp))
1944 printk("\n" KERN_ERR PFX
1945 "%s: Consistent memory allocation failed.\n",
1946 name);
1947 return -ENOMEM;
1948 }
1949
1950 lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
1951 sizeof(struct pcnet32_rx_head) *
1952 lp->rx_ring_size,
1953 &lp->rx_ring_dma_addr);
1954 if (lp->rx_ring == NULL) {
1955 if (netif_msg_drv(lp))
1956 printk("\n" KERN_ERR PFX
1957 "%s: Consistent memory allocation failed.\n",
1958 name);
1959 return -ENOMEM;
1960 }
1961
1962 lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t),
1963 GFP_ATOMIC);
1964 if (!lp->tx_dma_addr) {
1965 if (netif_msg_drv(lp))
1966 printk("\n" KERN_ERR PFX
1967 "%s: Memory allocation failed.\n", name);
1968 return -ENOMEM;
1969 }
1970
1971 lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t),
1972 GFP_ATOMIC);
1973 if (!lp->rx_dma_addr) {
1974 if (netif_msg_drv(lp))
1975 printk("\n" KERN_ERR PFX
1976 "%s: Memory allocation failed.\n", name);
1977 return -ENOMEM;
1978 }
1979
1980 lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *),
1981 GFP_ATOMIC);
1982 if (!lp->tx_skbuff) {
1983 if (netif_msg_drv(lp))
1984 printk("\n" KERN_ERR PFX
1985 "%s: Memory allocation failed.\n", name);
1986 return -ENOMEM;
1987 }
1988
1989 lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *),
1990 GFP_ATOMIC);
1991 if (!lp->rx_skbuff) {
1992 if (netif_msg_drv(lp))
1993 printk("\n" KERN_ERR PFX
1994 "%s: Memory allocation failed.\n", name);
1995 return -ENOMEM;
1996 }
1997
1998 return 0;
1999 }
2000
2001 static void pcnet32_free_ring(struct net_device *dev)
2002 {
2003 struct pcnet32_private *lp = dev->priv;
2004
2005 kfree(lp->tx_skbuff);
2006 lp->tx_skbuff = NULL;
2007
2008 kfree(lp->rx_skbuff);
2009 lp->rx_skbuff = NULL;
2010
2011 kfree(lp->tx_dma_addr);
2012 lp->tx_dma_addr = NULL;
2013
2014 kfree(lp->rx_dma_addr);
2015 lp->rx_dma_addr = NULL;
2016
2017 if (lp->tx_ring) {
2018 pci_free_consistent(lp->pci_dev,
2019 sizeof(struct pcnet32_tx_head) *
2020 lp->tx_ring_size, lp->tx_ring,
2021 lp->tx_ring_dma_addr);
2022 lp->tx_ring = NULL;
2023 }
2024
2025 if (lp->rx_ring) {
2026 pci_free_consistent(lp->pci_dev,
2027 sizeof(struct pcnet32_rx_head) *
2028 lp->rx_ring_size, lp->rx_ring,
2029 lp->rx_ring_dma_addr);
2030 lp->rx_ring = NULL;
2031 }
2032 }
2033
2034 static int pcnet32_open(struct net_device *dev)
2035 {
2036 struct pcnet32_private *lp = dev->priv;
2037 unsigned long ioaddr = dev->base_addr;
2038 u16 val;
2039 int i;
2040 int rc;
2041 unsigned long flags;
2042
2043 if (request_irq(dev->irq, &pcnet32_interrupt,
2044 lp->shared_irq ? IRQF_SHARED : 0, dev->name,
2045 (void *)dev)) {
2046 return -EAGAIN;
2047 }
2048
2049 spin_lock_irqsave(&lp->lock, flags);
2050 /* Check for a valid station address */
2051 if (!is_valid_ether_addr(dev->dev_addr)) {
2052 rc = -EINVAL;
2053 goto err_free_irq;
2054 }
2055
2056 /* Reset the PCNET32 */
2057 lp->a.reset(ioaddr);
2058
2059 /* switch pcnet32 to 32bit mode */
2060 lp->a.write_bcr(ioaddr, 20, 2);
2061
2062 if (netif_msg_ifup(lp))
2063 printk(KERN_DEBUG
2064 "%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n",
2065 dev->name, dev->irq, (u32) (lp->tx_ring_dma_addr),
2066 (u32) (lp->rx_ring_dma_addr),
2067 (u32) (lp->dma_addr +
2068 offsetof(struct pcnet32_private, init_block)));
2069
2070 /* set/reset autoselect bit */
2071 val = lp->a.read_bcr(ioaddr, 2) & ~2;
2072 if (lp->options & PCNET32_PORT_ASEL)
2073 val |= 2;
2074 lp->a.write_bcr(ioaddr, 2, val);
2075
2076 /* handle full duplex setting */
2077 if (lp->mii_if.full_duplex) {
2078 val = lp->a.read_bcr(ioaddr, 9) & ~3;
2079 if (lp->options & PCNET32_PORT_FD) {
2080 val |= 1;
2081 if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
2082 val |= 2;
2083 } else if (lp->options & PCNET32_PORT_ASEL) {
2084 /* workaround of xSeries250, turn on for 79C975 only */
2085 if (lp->chip_version == 0x2627)
2086 val |= 3;
2087 }
2088 lp->a.write_bcr(ioaddr, 9, val);
2089 }
2090
2091 /* set/reset GPSI bit in test register */
2092 val = lp->a.read_csr(ioaddr, 124) & ~0x10;
2093 if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
2094 val |= 0x10;
2095 lp->a.write_csr(ioaddr, 124, val);
2096
2097 /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
2098 if (lp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_AT &&
2099 (lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
2100 lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
2101 if (lp->options & PCNET32_PORT_ASEL) {
2102 lp->options = PCNET32_PORT_FD | PCNET32_PORT_100;
2103 if (netif_msg_link(lp))
2104 printk(KERN_DEBUG
2105 "%s: Setting 100Mb-Full Duplex.\n",
2106 dev->name);
2107 }
2108 }
2109 if (lp->phycount < 2) {
2110 /*
2111 * 24 Jun 2004 according AMD, in order to change the PHY,
2112 * DANAS (or DISPM for 79C976) must be set; then select the speed,
2113 * duplex, and/or enable auto negotiation, and clear DANAS
2114 */
2115 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
2116 lp->a.write_bcr(ioaddr, 32,
2117 lp->a.read_bcr(ioaddr, 32) | 0x0080);
2118 /* disable Auto Negotiation, set 10Mpbs, HD */
2119 val = lp->a.read_bcr(ioaddr, 32) & ~0xb8;
2120 if (lp->options & PCNET32_PORT_FD)
2121 val |= 0x10;
2122 if (lp->options & PCNET32_PORT_100)
2123 val |= 0x08;
2124 lp->a.write_bcr(ioaddr, 32, val);
2125 } else {
2126 if (lp->options & PCNET32_PORT_ASEL) {
2127 lp->a.write_bcr(ioaddr, 32,
2128 lp->a.read_bcr(ioaddr,
2129 32) | 0x0080);
2130 /* enable auto negotiate, setup, disable fd */
2131 val = lp->a.read_bcr(ioaddr, 32) & ~0x98;
2132 val |= 0x20;
2133 lp->a.write_bcr(ioaddr, 32, val);
2134 }
2135 }
2136 } else {
2137 int first_phy = -1;
2138 u16 bmcr;
2139 u32 bcr9;
2140 struct ethtool_cmd ecmd;
2141
2142 /*
2143 * There is really no good other way to handle multiple PHYs
2144 * other than turning off all automatics
2145 */
2146 val = lp->a.read_bcr(ioaddr, 2);
2147 lp->a.write_bcr(ioaddr, 2, val & ~2);
2148 val = lp->a.read_bcr(ioaddr, 32);
2149 lp->a.write_bcr(ioaddr, 32, val & ~(1 << 7)); /* stop MII manager */
2150
2151 if (!(lp->options & PCNET32_PORT_ASEL)) {
2152 /* setup ecmd */
2153 ecmd.port = PORT_MII;
2154 ecmd.transceiver = XCVR_INTERNAL;
2155 ecmd.autoneg = AUTONEG_DISABLE;
2156 ecmd.speed =
2157 lp->
2158 options & PCNET32_PORT_100 ? SPEED_100 : SPEED_10;
2159 bcr9 = lp->a.read_bcr(ioaddr, 9);
2160
2161 if (lp->options & PCNET32_PORT_FD) {
2162 ecmd.duplex = DUPLEX_FULL;
2163 bcr9 |= (1 << 0);
2164 } else {
2165 ecmd.duplex = DUPLEX_HALF;
2166 bcr9 |= ~(1 << 0);
2167 }
2168 lp->a.write_bcr(ioaddr, 9, bcr9);
2169 }
2170
2171 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2172 if (lp->phymask & (1 << i)) {
2173 /* isolate all but the first PHY */
2174 bmcr = mdio_read(dev, i, MII_BMCR);
2175 if (first_phy == -1) {
2176 first_phy = i;
2177 mdio_write(dev, i, MII_BMCR,
2178 bmcr & ~BMCR_ISOLATE);
2179 } else {
2180 mdio_write(dev, i, MII_BMCR,
2181 bmcr | BMCR_ISOLATE);
2182 }
2183 /* use mii_ethtool_sset to setup PHY */
2184 lp->mii_if.phy_id = i;
2185 ecmd.phy_address = i;
2186 if (lp->options & PCNET32_PORT_ASEL) {
2187 mii_ethtool_gset(&lp->mii_if, &ecmd);
2188 ecmd.autoneg = AUTONEG_ENABLE;
2189 }
2190 mii_ethtool_sset(&lp->mii_if, &ecmd);
2191 }
2192 }
2193 lp->mii_if.phy_id = first_phy;
2194 if (netif_msg_link(lp))
2195 printk(KERN_INFO "%s: Using PHY number %d.\n",
2196 dev->name, first_phy);
2197 }
2198
2199 #ifdef DO_DXSUFLO
2200 if (lp->dxsuflo) { /* Disable transmit stop on underflow */
2201 val = lp->a.read_csr(ioaddr, CSR3);
2202 val |= 0x40;
2203 lp->a.write_csr(ioaddr, CSR3, val);
2204 }
2205 #endif
2206
2207 lp->init_block.mode =
2208 le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
2209 pcnet32_load_multicast(dev);
2210
2211 if (pcnet32_init_ring(dev)) {
2212 rc = -ENOMEM;
2213 goto err_free_ring;
2214 }
2215
2216 /* Re-initialize the PCNET32, and start it when done. */
2217 lp->a.write_csr(ioaddr, 1, (lp->dma_addr +
2218 offsetof(struct pcnet32_private,
2219 init_block)) & 0xffff);
2220 lp->a.write_csr(ioaddr, 2,
2221 (lp->dma_addr +
2222 offsetof(struct pcnet32_private, init_block)) >> 16);
2223
2224 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
2225 lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
2226
2227 netif_start_queue(dev);
2228
2229 if (lp->chip_version >= PCNET32_79C970A) {
2230 /* Print the link status and start the watchdog */
2231 pcnet32_check_media(dev, 1);
2232 mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
2233 }
2234
2235 i = 0;
2236 while (i++ < 100)
2237 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
2238 break;
2239 /*
2240 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
2241 * reports that doing so triggers a bug in the '974.
2242 */
2243 lp->a.write_csr(ioaddr, CSR0, CSR0_NORMAL);
2244
2245 if (netif_msg_ifup(lp))
2246 printk(KERN_DEBUG
2247 "%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n",
2248 dev->name, i,
2249 (u32) (lp->dma_addr +
2250 offsetof(struct pcnet32_private, init_block)),
2251 lp->a.read_csr(ioaddr, CSR0));
2252
2253 spin_unlock_irqrestore(&lp->lock, flags);
2254
2255 return 0; /* Always succeed */
2256
2257 err_free_ring:
2258 /* free any allocated skbuffs */
2259 pcnet32_purge_rx_ring(dev);
2260
2261 /*
2262 * Switch back to 16bit mode to avoid problems with dumb
2263 * DOS packet driver after a warm reboot
2264 */
2265 lp->a.write_bcr(ioaddr, 20, 4);
2266
2267 err_free_irq:
2268 spin_unlock_irqrestore(&lp->lock, flags);
2269 free_irq(dev->irq, dev);
2270 return rc;
2271 }
2272
2273 /*
2274 * The LANCE has been halted for one reason or another (busmaster memory
2275 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
2276 * etc.). Modern LANCE variants always reload their ring-buffer
2277 * configuration when restarted, so we must reinitialize our ring
2278 * context before restarting. As part of this reinitialization,
2279 * find all packets still on the Tx ring and pretend that they had been
2280 * sent (in effect, drop the packets on the floor) - the higher-level
2281 * protocols will time out and retransmit. It'd be better to shuffle
2282 * these skbs to a temp list and then actually re-Tx them after
2283 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com
2284 */
2285
2286 static void pcnet32_purge_tx_ring(struct net_device *dev)
2287 {
2288 struct pcnet32_private *lp = dev->priv;
2289 int i;
2290
2291 for (i = 0; i < lp->tx_ring_size; i++) {
2292 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2293 wmb(); /* Make sure adapter sees owner change */
2294 if (lp->tx_skbuff[i]) {
2295 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i],
2296 lp->tx_skbuff[i]->len,
2297 PCI_DMA_TODEVICE);
2298 dev_kfree_skb_any(lp->tx_skbuff[i]);
2299 }
2300 lp->tx_skbuff[i] = NULL;
2301 lp->tx_dma_addr[i] = 0;
2302 }
2303 }
2304
2305 /* Initialize the PCNET32 Rx and Tx rings. */
2306 static int pcnet32_init_ring(struct net_device *dev)
2307 {
2308 struct pcnet32_private *lp = dev->priv;
2309 int i;
2310
2311 lp->tx_full = 0;
2312 lp->cur_rx = lp->cur_tx = 0;
2313 lp->dirty_rx = lp->dirty_tx = 0;
2314
2315 for (i = 0; i < lp->rx_ring_size; i++) {
2316 struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
2317 if (rx_skbuff == NULL) {
2318 if (!
2319 (rx_skbuff = lp->rx_skbuff[i] =
2320 dev_alloc_skb(PKT_BUF_SZ))) {
2321 /* there is not much, we can do at this point */
2322 if (netif_msg_drv(lp))
2323 printk(KERN_ERR
2324 "%s: pcnet32_init_ring dev_alloc_skb failed.\n",
2325 dev->name);
2326 return -1;
2327 }
2328 skb_reserve(rx_skbuff, 2);
2329 }
2330
2331 rmb();
2332 if (lp->rx_dma_addr[i] == 0)
2333 lp->rx_dma_addr[i] =
2334 pci_map_single(lp->pci_dev, rx_skbuff->data,
2335 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
2336 lp->rx_ring[i].base = (u32) le32_to_cpu(lp->rx_dma_addr[i]);
2337 lp->rx_ring[i].buf_length = le16_to_cpu(2 - PKT_BUF_SZ);
2338 wmb(); /* Make sure owner changes after all others are visible */
2339 lp->rx_ring[i].status = le16_to_cpu(0x8000);
2340 }
2341 /* The Tx buffer address is filled in as needed, but we do need to clear
2342 * the upper ownership bit. */
2343 for (i = 0; i < lp->tx_ring_size; i++) {
2344 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2345 wmb(); /* Make sure adapter sees owner change */
2346 lp->tx_ring[i].base = 0;
2347 lp->tx_dma_addr[i] = 0;
2348 }
2349
2350 lp->init_block.tlen_rlen =
2351 le16_to_cpu(lp->tx_len_bits | lp->rx_len_bits);
2352 for (i = 0; i < 6; i++)
2353 lp->init_block.phys_addr[i] = dev->dev_addr[i];
2354 lp->init_block.rx_ring = (u32) le32_to_cpu(lp->rx_ring_dma_addr);
2355 lp->init_block.tx_ring = (u32) le32_to_cpu(lp->tx_ring_dma_addr);
2356 wmb(); /* Make sure all changes are visible */
2357 return 0;
2358 }
2359
2360 /* the pcnet32 has been issued a stop or reset. Wait for the stop bit
2361 * then flush the pending transmit operations, re-initialize the ring,
2362 * and tell the chip to initialize.
2363 */
2364 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
2365 {
2366 struct pcnet32_private *lp = dev->priv;
2367 unsigned long ioaddr = dev->base_addr;
2368 int i;
2369
2370 /* wait for stop */
2371 for (i = 0; i < 100; i++)
2372 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_STOP)
2373 break;
2374
2375 if (i >= 100 && netif_msg_drv(lp))
2376 printk(KERN_ERR
2377 "%s: pcnet32_restart timed out waiting for stop.\n",
2378 dev->name);
2379
2380 pcnet32_purge_tx_ring(dev);
2381 if (pcnet32_init_ring(dev))
2382 return;
2383
2384 /* ReInit Ring */
2385 lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
2386 i = 0;
2387 while (i++ < 1000)
2388 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
2389 break;
2390
2391 lp->a.write_csr(ioaddr, CSR0, csr0_bits);
2392 }
2393
2394 static void pcnet32_tx_timeout(struct net_device *dev)
2395 {
2396 struct pcnet32_private *lp = dev->priv;
2397 unsigned long ioaddr = dev->base_addr, flags;
2398
2399 spin_lock_irqsave(&lp->lock, flags);
2400 /* Transmitter timeout, serious problems. */
2401 if (pcnet32_debug & NETIF_MSG_DRV)
2402 printk(KERN_ERR
2403 "%s: transmit timed out, status %4.4x, resetting.\n",
2404 dev->name, lp->a.read_csr(ioaddr, CSR0));
2405 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2406 lp->stats.tx_errors++;
2407 if (netif_msg_tx_err(lp)) {
2408 int i;
2409 printk(KERN_DEBUG
2410 " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
2411 lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
2412 lp->cur_rx);
2413 for (i = 0; i < lp->rx_ring_size; i++)
2414 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2415 le32_to_cpu(lp->rx_ring[i].base),
2416 (-le16_to_cpu(lp->rx_ring[i].buf_length)) &
2417 0xffff, le32_to_cpu(lp->rx_ring[i].msg_length),
2418 le16_to_cpu(lp->rx_ring[i].status));
2419 for (i = 0; i < lp->tx_ring_size; i++)
2420 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2421 le32_to_cpu(lp->tx_ring[i].base),
2422 (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff,
2423 le32_to_cpu(lp->tx_ring[i].misc),
2424 le16_to_cpu(lp->tx_ring[i].status));
2425 printk("\n");
2426 }
2427 pcnet32_restart(dev, CSR0_NORMAL);
2428
2429 dev->trans_start = jiffies;
2430 netif_wake_queue(dev);
2431
2432 spin_unlock_irqrestore(&lp->lock, flags);
2433 }
2434
2435 static int pcnet32_start_xmit(struct sk_buff *skb, struct net_device *dev)
2436 {
2437 struct pcnet32_private *lp = dev->priv;
2438 unsigned long ioaddr = dev->base_addr;
2439 u16 status;
2440 int entry;
2441 unsigned long flags;
2442
2443 spin_lock_irqsave(&lp->lock, flags);
2444
2445 if (netif_msg_tx_queued(lp)) {
2446 printk(KERN_DEBUG
2447 "%s: pcnet32_start_xmit() called, csr0 %4.4x.\n",
2448 dev->name, lp->a.read_csr(ioaddr, CSR0));
2449 }
2450
2451 /* Default status -- will not enable Successful-TxDone
2452 * interrupt when that option is available to us.
2453 */
2454 status = 0x8300;
2455
2456 /* Fill in a Tx ring entry */
2457
2458 /* Mask to ring buffer boundary. */
2459 entry = lp->cur_tx & lp->tx_mod_mask;
2460
2461 /* Caution: the write order is important here, set the status
2462 * with the "ownership" bits last. */
2463
2464 lp->tx_ring[entry].length = le16_to_cpu(-skb->len);
2465
2466 lp->tx_ring[entry].misc = 0x00000000;
2467
2468 lp->tx_skbuff[entry] = skb;
2469 lp->tx_dma_addr[entry] =
2470 pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
2471 lp->tx_ring[entry].base = (u32) le32_to_cpu(lp->tx_dma_addr[entry]);
2472 wmb(); /* Make sure owner changes after all others are visible */
2473 lp->tx_ring[entry].status = le16_to_cpu(status);
2474
2475 lp->cur_tx++;
2476 lp->stats.tx_bytes += skb->len;
2477
2478 /* Trigger an immediate send poll. */
2479 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL);
2480
2481 dev->trans_start = jiffies;
2482
2483 if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) {
2484 lp->tx_full = 1;
2485 netif_stop_queue(dev);
2486 }
2487 spin_unlock_irqrestore(&lp->lock, flags);
2488 return 0;
2489 }
2490
2491 /* The PCNET32 interrupt handler. */
2492 static irqreturn_t
2493 pcnet32_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2494 {
2495 struct net_device *dev = dev_id;
2496 struct pcnet32_private *lp;
2497 unsigned long ioaddr;
2498 u16 csr0;
2499 int boguscnt = max_interrupt_work;
2500 int must_restart;
2501
2502 if (!dev) {
2503 if (pcnet32_debug & NETIF_MSG_INTR)
2504 printk(KERN_DEBUG "%s(): irq %d for unknown device\n",
2505 __FUNCTION__, irq);
2506 return IRQ_NONE;
2507 }
2508
2509 ioaddr = dev->base_addr;
2510 lp = dev->priv;
2511
2512 spin_lock(&lp->lock);
2513
2514 csr0 = lp->a.read_csr(ioaddr, CSR0);
2515 while ((csr0 & 0x8f00) && --boguscnt >= 0) {
2516 if (csr0 == 0xffff) {
2517 break; /* PCMCIA remove happened */
2518 }
2519 /* Acknowledge all of the current interrupt sources ASAP. */
2520 lp->a.write_csr(ioaddr, CSR0, csr0 & ~0x004f);
2521
2522 must_restart = 0;
2523
2524 if (netif_msg_intr(lp))
2525 printk(KERN_DEBUG
2526 "%s: interrupt csr0=%#2.2x new csr=%#2.2x.\n",
2527 dev->name, csr0, lp->a.read_csr(ioaddr, CSR0));
2528
2529 if (csr0 & 0x0400) /* Rx interrupt */
2530 pcnet32_rx(dev);
2531
2532 if (csr0 & 0x0200) { /* Tx-done interrupt */
2533 must_restart = pcnet32_tx(dev, csr0);
2534 }
2535
2536 /* Log misc errors. */
2537 if (csr0 & 0x4000)
2538 lp->stats.tx_errors++; /* Tx babble. */
2539 if (csr0 & 0x1000) {
2540 /*
2541 * This happens when our receive ring is full. This
2542 * shouldn't be a problem as we will see normal rx
2543 * interrupts for the frames in the receive ring. But
2544 * there are some PCI chipsets (I can reproduce this
2545 * on SP3G with Intel saturn chipset) which have
2546 * sometimes problems and will fill up the receive
2547 * ring with error descriptors. In this situation we
2548 * don't get a rx interrupt, but a missed frame
2549 * interrupt sooner or later. So we try to clean up
2550 * our receive ring here.
2551 */
2552 pcnet32_rx(dev);
2553 lp->stats.rx_errors++; /* Missed a Rx frame. */
2554 }
2555 if (csr0 & 0x0800) {
2556 if (netif_msg_drv(lp))
2557 printk(KERN_ERR
2558 "%s: Bus master arbitration failure, status %4.4x.\n",
2559 dev->name, csr0);
2560 /* unlike for the lance, there is no restart needed */
2561 }
2562
2563 if (must_restart) {
2564 /* reset the chip to clear the error condition, then restart */
2565 lp->a.reset(ioaddr);
2566 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
2567 pcnet32_restart(dev, CSR0_START);
2568 netif_wake_queue(dev);
2569 }
2570 csr0 = lp->a.read_csr(ioaddr, CSR0);
2571 }
2572
2573 /* Set interrupt enable. */
2574 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN);
2575
2576 if (netif_msg_intr(lp))
2577 printk(KERN_DEBUG "%s: exiting interrupt, csr0=%#4.4x.\n",
2578 dev->name, lp->a.read_csr(ioaddr, CSR0));
2579
2580 spin_unlock(&lp->lock);
2581
2582 return IRQ_HANDLED;
2583 }
2584
2585 static int pcnet32_close(struct net_device *dev)
2586 {
2587 unsigned long ioaddr = dev->base_addr;
2588 struct pcnet32_private *lp = dev->priv;
2589 unsigned long flags;
2590
2591 del_timer_sync(&lp->watchdog_timer);
2592
2593 netif_stop_queue(dev);
2594
2595 spin_lock_irqsave(&lp->lock, flags);
2596
2597 lp->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
2598
2599 if (netif_msg_ifdown(lp))
2600 printk(KERN_DEBUG
2601 "%s: Shutting down ethercard, status was %2.2x.\n",
2602 dev->name, lp->a.read_csr(ioaddr, CSR0));
2603
2604 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
2605 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2606
2607 /*
2608 * Switch back to 16bit mode to avoid problems with dumb
2609 * DOS packet driver after a warm reboot
2610 */
2611 lp->a.write_bcr(ioaddr, 20, 4);
2612
2613 spin_unlock_irqrestore(&lp->lock, flags);
2614
2615 free_irq(dev->irq, dev);
2616
2617 spin_lock_irqsave(&lp->lock, flags);
2618
2619 pcnet32_purge_rx_ring(dev);
2620 pcnet32_purge_tx_ring(dev);
2621
2622 spin_unlock_irqrestore(&lp->lock, flags);
2623
2624 return 0;
2625 }
2626
2627 static struct net_device_stats *pcnet32_get_stats(struct net_device *dev)
2628 {
2629 struct pcnet32_private *lp = dev->priv;
2630 unsigned long ioaddr = dev->base_addr;
2631 unsigned long flags;
2632
2633 spin_lock_irqsave(&lp->lock, flags);
2634 lp->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
2635 spin_unlock_irqrestore(&lp->lock, flags);
2636
2637 return &lp->stats;
2638 }
2639
2640 /* taken from the sunlance driver, which it took from the depca driver */
2641 static void pcnet32_load_multicast(struct net_device *dev)
2642 {
2643 struct pcnet32_private *lp = dev->priv;
2644 volatile struct pcnet32_init_block *ib = &lp->init_block;
2645 volatile u16 *mcast_table = (u16 *) & ib->filter;
2646 struct dev_mc_list *dmi = dev->mc_list;
2647 unsigned long ioaddr = dev->base_addr;
2648 char *addrs;
2649 int i;
2650 u32 crc;
2651
2652 /* set all multicast bits */
2653 if (dev->flags & IFF_ALLMULTI) {
2654 ib->filter[0] = 0xffffffff;
2655 ib->filter[1] = 0xffffffff;
2656 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff);
2657 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff);
2658 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff);
2659 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff);
2660 return;
2661 }
2662 /* clear the multicast filter */
2663 ib->filter[0] = 0;
2664 ib->filter[1] = 0;
2665
2666 /* Add addresses */
2667 for (i = 0; i < dev->mc_count; i++) {
2668 addrs = dmi->dmi_addr;
2669 dmi = dmi->next;
2670
2671 /* multicast address? */
2672 if (!(*addrs & 1))
2673 continue;
2674
2675 crc = ether_crc_le(6, addrs);
2676 crc = crc >> 26;
2677 mcast_table[crc >> 4] =
2678 le16_to_cpu(le16_to_cpu(mcast_table[crc >> 4]) |
2679 (1 << (crc & 0xf)));
2680 }
2681 for (i = 0; i < 4; i++)
2682 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER + i,
2683 le16_to_cpu(mcast_table[i]));
2684 return;
2685 }
2686
2687 /*
2688 * Set or clear the multicast filter for this adaptor.
2689 */
2690 static void pcnet32_set_multicast_list(struct net_device *dev)
2691 {
2692 unsigned long ioaddr = dev->base_addr, flags;
2693 struct pcnet32_private *lp = dev->priv;
2694 int csr15, suspended;
2695
2696 spin_lock_irqsave(&lp->lock, flags);
2697 suspended = pcnet32_suspend(dev, &flags, 0);
2698 csr15 = lp->a.read_csr(ioaddr, CSR15);
2699 if (dev->flags & IFF_PROMISC) {
2700 /* Log any net taps. */
2701 if (netif_msg_hw(lp))
2702 printk(KERN_INFO "%s: Promiscuous mode enabled.\n",
2703 dev->name);
2704 lp->init_block.mode =
2705 le16_to_cpu(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) <<
2706 7);
2707 lp->a.write_csr(ioaddr, CSR15, csr15 | 0x8000);
2708 } else {
2709 lp->init_block.mode =
2710 le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
2711 lp->a.write_csr(ioaddr, CSR15, csr15 & 0x7fff);
2712 pcnet32_load_multicast(dev);
2713 }
2714
2715 if (suspended) {
2716 int csr5;
2717 /* clear SUSPEND (SPND) - CSR5 bit 0 */
2718 csr5 = lp->a.read_csr(ioaddr, CSR5);
2719 lp->a.write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
2720 } else {
2721 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2722 pcnet32_restart(dev, CSR0_NORMAL);
2723 netif_wake_queue(dev);
2724 }
2725
2726 spin_unlock_irqrestore(&lp->lock, flags);
2727 }
2728
2729 /* This routine assumes that the lp->lock is held */
2730 static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
2731 {
2732 struct pcnet32_private *lp = dev->priv;
2733 unsigned long ioaddr = dev->base_addr;
2734 u16 val_out;
2735
2736 if (!lp->mii)
2737 return 0;
2738
2739 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2740 val_out = lp->a.read_bcr(ioaddr, 34);
2741
2742 return val_out;
2743 }
2744
2745 /* This routine assumes that the lp->lock is held */
2746 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
2747 {
2748 struct pcnet32_private *lp = dev->priv;
2749 unsigned long ioaddr = dev->base_addr;
2750
2751 if (!lp->mii)
2752 return;
2753
2754 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2755 lp->a.write_bcr(ioaddr, 34, val);
2756 }
2757
2758 static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2759 {
2760 struct pcnet32_private *lp = dev->priv;
2761 int rc;
2762 unsigned long flags;
2763
2764 /* SIOC[GS]MIIxxx ioctls */
2765 if (lp->mii) {
2766 spin_lock_irqsave(&lp->lock, flags);
2767 rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL);
2768 spin_unlock_irqrestore(&lp->lock, flags);
2769 } else {
2770 rc = -EOPNOTSUPP;
2771 }
2772
2773 return rc;
2774 }
2775
2776 static int pcnet32_check_otherphy(struct net_device *dev)
2777 {
2778 struct pcnet32_private *lp = dev->priv;
2779 struct mii_if_info mii = lp->mii_if;
2780 u16 bmcr;
2781 int i;
2782
2783 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2784 if (i == lp->mii_if.phy_id)
2785 continue; /* skip active phy */
2786 if (lp->phymask & (1 << i)) {
2787 mii.phy_id = i;
2788 if (mii_link_ok(&mii)) {
2789 /* found PHY with active link */
2790 if (netif_msg_link(lp))
2791 printk(KERN_INFO
2792 "%s: Using PHY number %d.\n",
2793 dev->name, i);
2794
2795 /* isolate inactive phy */
2796 bmcr =
2797 mdio_read(dev, lp->mii_if.phy_id, MII_BMCR);
2798 mdio_write(dev, lp->mii_if.phy_id, MII_BMCR,
2799 bmcr | BMCR_ISOLATE);
2800
2801 /* de-isolate new phy */
2802 bmcr = mdio_read(dev, i, MII_BMCR);
2803 mdio_write(dev, i, MII_BMCR,
2804 bmcr & ~BMCR_ISOLATE);
2805
2806 /* set new phy address */
2807 lp->mii_if.phy_id = i;
2808 return 1;
2809 }
2810 }
2811 }
2812 return 0;
2813 }
2814
2815 /*
2816 * Show the status of the media. Similar to mii_check_media however it
2817 * correctly shows the link speed for all (tested) pcnet32 variants.
2818 * Devices with no mii just report link state without speed.
2819 *
2820 * Caller is assumed to hold and release the lp->lock.
2821 */
2822
2823 static void pcnet32_check_media(struct net_device *dev, int verbose)
2824 {
2825 struct pcnet32_private *lp = dev->priv;
2826 int curr_link;
2827 int prev_link = netif_carrier_ok(dev) ? 1 : 0;
2828 u32 bcr9;
2829
2830 if (lp->mii) {
2831 curr_link = mii_link_ok(&lp->mii_if);
2832 } else {
2833 ulong ioaddr = dev->base_addr; /* card base I/O address */
2834 curr_link = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
2835 }
2836 if (!curr_link) {
2837 if (prev_link || verbose) {
2838 netif_carrier_off(dev);
2839 if (netif_msg_link(lp))
2840 printk(KERN_INFO "%s: link down\n", dev->name);
2841 }
2842 if (lp->phycount > 1) {
2843 curr_link = pcnet32_check_otherphy(dev);
2844 prev_link = 0;
2845 }
2846 } else if (verbose || !prev_link) {
2847 netif_carrier_on(dev);
2848 if (lp->mii) {
2849 if (netif_msg_link(lp)) {
2850 struct ethtool_cmd ecmd;
2851 mii_ethtool_gset(&lp->mii_if, &ecmd);
2852 printk(KERN_INFO
2853 "%s: link up, %sMbps, %s-duplex\n",
2854 dev->name,
2855 (ecmd.speed == SPEED_100) ? "100" : "10",
2856 (ecmd.duplex ==
2857 DUPLEX_FULL) ? "full" : "half");
2858 }
2859 bcr9 = lp->a.read_bcr(dev->base_addr, 9);
2860 if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) {
2861 if (lp->mii_if.full_duplex)
2862 bcr9 |= (1 << 0);
2863 else
2864 bcr9 &= ~(1 << 0);
2865 lp->a.write_bcr(dev->base_addr, 9, bcr9);
2866 }
2867 } else {
2868 if (netif_msg_link(lp))
2869 printk(KERN_INFO "%s: link up\n", dev->name);
2870 }
2871 }
2872 }
2873
2874 /*
2875 * Check for loss of link and link establishment.
2876 * Can not use mii_check_media because it does nothing if mode is forced.
2877 */
2878
2879 static void pcnet32_watchdog(struct net_device *dev)
2880 {
2881 struct pcnet32_private *lp = dev->priv;
2882 unsigned long flags;
2883
2884 /* Print the link status if it has changed */
2885 spin_lock_irqsave(&lp->lock, flags);
2886 pcnet32_check_media(dev, 0);
2887 spin_unlock_irqrestore(&lp->lock, flags);
2888
2889 mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
2890 }
2891
2892 static void __devexit pcnet32_remove_one(struct pci_dev *pdev)
2893 {
2894 struct net_device *dev = pci_get_drvdata(pdev);
2895
2896 if (dev) {
2897 struct pcnet32_private *lp = dev->priv;
2898
2899 unregister_netdev(dev);
2900 pcnet32_free_ring(dev);
2901 release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
2902 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
2903 free_netdev(dev);
2904 pci_disable_device(pdev);
2905 pci_set_drvdata(pdev, NULL);
2906 }
2907 }
2908
2909 static struct pci_driver pcnet32_driver = {
2910 .name = DRV_NAME,
2911 .probe = pcnet32_probe_pci,
2912 .remove = __devexit_p(pcnet32_remove_one),
2913 .id_table = pcnet32_pci_tbl,
2914 };
2915
2916 /* An additional parameter that may be passed in... */
2917 static int debug = -1;
2918 static int tx_start_pt = -1;
2919 static int pcnet32_have_pci;
2920
2921 module_param(debug, int, 0);
2922 MODULE_PARM_DESC(debug, DRV_NAME " debug level");
2923 module_param(max_interrupt_work, int, 0);
2924 MODULE_PARM_DESC(max_interrupt_work,
2925 DRV_NAME " maximum events handled per interrupt");
2926 module_param(rx_copybreak, int, 0);
2927 MODULE_PARM_DESC(rx_copybreak,
2928 DRV_NAME " copy breakpoint for copy-only-tiny-frames");
2929 module_param(tx_start_pt, int, 0);
2930 MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
2931 module_param(pcnet32vlb, int, 0);
2932 MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
2933 module_param_array(options, int, NULL, 0);
2934 MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
2935 module_param_array(full_duplex, int, NULL, 0);
2936 MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
2937 /* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
2938 module_param_array(homepna, int, NULL, 0);
2939 MODULE_PARM_DESC(homepna,
2940 DRV_NAME
2941 " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
2942
2943 MODULE_AUTHOR("Thomas Bogendoerfer");
2944 MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
2945 MODULE_LICENSE("GPL");
2946
2947 #define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
2948
2949 static int __init pcnet32_init_module(void)
2950 {
2951 printk(KERN_INFO "%s", version);
2952
2953 pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT);
2954
2955 if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
2956 tx_start = tx_start_pt;
2957
2958 /* find the PCI devices */
2959 if (!pci_register_driver(&pcnet32_driver))
2960 pcnet32_have_pci = 1;
2961
2962 /* should we find any remaining VLbus devices ? */
2963 if (pcnet32vlb)
2964 pcnet32_probe_vlbus(pcnet32_portlist);
2965
2966 if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))
2967 printk(KERN_INFO PFX "%d cards_found.\n", cards_found);
2968
2969 return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV;
2970 }
2971
2972 static void __exit pcnet32_cleanup_module(void)
2973 {
2974 struct net_device *next_dev;
2975
2976 while (pcnet32_dev) {
2977 struct pcnet32_private *lp = pcnet32_dev->priv;
2978 next_dev = lp->next;
2979 unregister_netdev(pcnet32_dev);
2980 pcnet32_free_ring(pcnet32_dev);
2981 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
2982 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
2983 free_netdev(pcnet32_dev);
2984 pcnet32_dev = next_dev;
2985 }
2986
2987 if (pcnet32_have_pci)
2988 pci_unregister_driver(&pcnet32_driver);
2989 }
2990
2991 module_init(pcnet32_init_module);
2992 module_exit(pcnet32_cleanup_module);
2993
2994 /*
2995 * Local variables:
2996 * c-indent-level: 4
2997 * tab-width: 8
2998 * End:
2999 */
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree