arch/arm/mach-ux500/ste-dma40-db8500.h

   1 /*
   2  * arch/arm/mach-ux500/ste_dma40_db8500.h
   3  * DB8500-SoC-specific configuration for DMA40
   4  *
   5  * Copyright (C) ST-Ericsson 2007-2010
   6  * License terms: GNU General Public License (GPL) version 2
   7  * Author: Per Friden <per.friden@stericsson.com>
   8  * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
   9  */
  10 #ifndef STE_DMA40_DB8500_H
  11 #define STE_DMA40_DB8500_H
  12
  13 #define STEDMA40_NR_DEV 64
  14
  15 enum dma_src_dev_type {
  16         STEDMA40_DEV_SPI0_RX = 0,
  17         STEDMA40_DEV_SD_MMC0_RX = 1,
  18         STEDMA40_DEV_SD_MMC1_RX = 2,
  19         STEDMA40_DEV_SD_MMC2_RX = 3,
  20         STEDMA40_DEV_I2C1_RX = 4,
  21         STEDMA40_DEV_I2C3_RX = 5,
  22         STEDMA40_DEV_I2C2_RX = 6,
  23         STEDMA40_DEV_I2C4_RX = 7, /* Only on V1 */
  24         STEDMA40_DEV_SSP0_RX = 8,
  25         STEDMA40_DEV_SSP1_RX = 9,
  26         STEDMA40_DEV_MCDE_RX = 10,
  27         STEDMA40_DEV_UART2_RX = 11,
  28         STEDMA40_DEV_UART1_RX = 12,
  29         STEDMA40_DEV_UART0_RX = 13,
  30         STEDMA40_DEV_MSP2_RX = 14,
  31         STEDMA40_DEV_I2C0_RX = 15,
  32         STEDMA40_DEV_USB_OTG_IEP_8 = 16,
  33         STEDMA40_DEV_USB_OTG_IEP_1_9 = 17,
  34         STEDMA40_DEV_USB_OTG_IEP_2_10 = 18,
  35         STEDMA40_DEV_USB_OTG_IEP_3_11 = 19,
  36         STEDMA40_DEV_SLIM0_CH0_RX_HSI_RX_CH0 = 20,
  37         STEDMA40_DEV_SLIM0_CH1_RX_HSI_RX_CH1 = 21,
  38         STEDMA40_DEV_SLIM0_CH2_RX_HSI_RX_CH2 = 22,
  39         STEDMA40_DEV_SLIM0_CH3_RX_HSI_RX_CH3 = 23,
  40         STEDMA40_DEV_SRC_SXA0_RX_TX = 24,
  41         STEDMA40_DEV_SRC_SXA1_RX_TX = 25,
  42         STEDMA40_DEV_SRC_SXA2_RX_TX = 26,
  43         STEDMA40_DEV_SRC_SXA3_RX_TX = 27,
  44         STEDMA40_DEV_SD_MM2_RX = 28,
  45         STEDMA40_DEV_SD_MM0_RX = 29,
  46         STEDMA40_DEV_MSP1_RX = 30,
  47         /*
  48          * This channel is either SlimBus or MSP,
  49          * never both at the same time.
  50          */
  51         STEDMA40_SLIM0_CH0_RX = 31,
  52         STEDMA40_DEV_MSP0_RX = 31,
  53         STEDMA40_DEV_SD_MM1_RX = 32,
  54         STEDMA40_DEV_SPI2_RX = 33,
  55         STEDMA40_DEV_I2C3_RX2 = 34,
  56         STEDMA40_DEV_SPI1_RX = 35,
  57         STEDMA40_DEV_USB_OTG_IEP_4_12 = 36,
  58         STEDMA40_DEV_USB_OTG_IEP_5_13 = 37,
  59         STEDMA40_DEV_USB_OTG_IEP_6_14 = 38,
  60         STEDMA40_DEV_USB_OTG_IEP_7_15 = 39,
  61         STEDMA40_DEV_SPI3_RX = 40,
  62         STEDMA40_DEV_SD_MM3_RX = 41,
  63         STEDMA40_DEV_SD_MM4_RX = 42,
  64         STEDMA40_DEV_SD_MM5_RX = 43,
  65         STEDMA40_DEV_SRC_SXA4_RX_TX = 44,
  66         STEDMA40_DEV_SRC_SXA5_RX_TX = 45,
  67         STEDMA40_DEV_SRC_SXA6_RX_TX = 46,
  68         STEDMA40_DEV_SRC_SXA7_RX_TX = 47,
  69         STEDMA40_DEV_CAC1_RX = 48,
  70         /* RX channels 49 and 50 are unused */
  71         STEDMA40_DEV_MSHC_RX = 51,
  72         STEDMA40_DEV_SLIM1_CH0_RX_HSI_RX_CH4 = 52,
  73         STEDMA40_DEV_SLIM1_CH1_RX_HSI_RX_CH5 = 53,
  74         STEDMA40_DEV_SLIM1_CH2_RX_HSI_RX_CH6 = 54,
  75         STEDMA40_DEV_SLIM1_CH3_RX_HSI_RX_CH7 = 55,
  76         /* RX channels 56 thru 60 are unused */
  77         STEDMA40_DEV_CAC0_RX = 61,
  78         /* RX channels 62 and 63 are unused */
  79 };
  80
  81 enum dma_dest_dev_type {
  82         STEDMA40_DEV_SPI0_TX = 0,
  83         STEDMA40_DEV_SD_MMC0_TX = 1,
  84         STEDMA40_DEV_SD_MMC1_TX = 2,
  85         STEDMA40_DEV_SD_MMC2_TX = 3,
  86         STEDMA40_DEV_I2C1_TX = 4,
  87         STEDMA40_DEV_I2C3_TX = 5,
  88         STEDMA40_DEV_I2C2_TX = 6,
  89         STEDMA50_DEV_I2C4_TX = 7, /* Only on V1 */
  90         STEDMA40_DEV_SSP0_TX = 8,
  91         STEDMA40_DEV_SSP1_TX = 9,
  92         /* TX channel 10 is unused */
  93         STEDMA40_DEV_UART2_TX = 11,
  94         STEDMA40_DEV_UART1_TX = 12,
  95         STEDMA40_DEV_UART0_TX= 13,
  96         STEDMA40_DEV_MSP2_TX = 14,
  97         STEDMA40_DEV_I2C0_TX = 15,
  98         STEDMA40_DEV_USB_OTG_OEP_8 = 16,
  99         STEDMA40_DEV_USB_OTG_OEP_1_9 = 17,
 100         STEDMA40_DEV_USB_OTG_OEP_2_10= 18,
 101         STEDMA40_DEV_USB_OTG_OEP_3_11 = 19,
 102         STEDMA40_DEV_SLIM0_CH0_TX_HSI_TX_CH0 = 20,
 103         STEDMA40_DEV_SLIM0_CH1_TX_HSI_TX_CH1 = 21,
 104         STEDMA40_DEV_SLIM0_CH2_TX_HSI_TX_CH2 = 22,
 105         STEDMA40_DEV_SLIM0_CH3_TX_HSI_TX_CH3 = 23,
 106         STEDMA40_DEV_DST_SXA0_RX_TX = 24,
 107         STEDMA40_DEV_DST_SXA1_RX_TX = 25,
 108         STEDMA40_DEV_DST_SXA2_RX_TX = 26,
 109         STEDMA40_DEV_DST_SXA3_RX_TX = 27,
 110         STEDMA40_DEV_SD_MM2_TX = 28,
 111         STEDMA40_DEV_SD_MM0_TX = 29,
 112         STEDMA40_DEV_MSP1_TX = 30,
 113         /*
 114          * This channel is either SlimBus or MSP,
 115          * never both at the same time.
 116          */
 117         STEDMA40_SLIM0_CH0_TX = 31,
 118         STEDMA40_DEV_MSP0_TX = 31,
 119         STEDMA40_DEV_SD_MM1_TX = 32,
 120         STEDMA40_DEV_SPI2_TX = 33,
 121         /* Secondary I2C3 channel */
 122         STEDMA40_DEV_I2C3_TX2 = 34,
 123         STEDMA40_DEV_SPI1_TX = 35,
 124         STEDMA40_DEV_USB_OTG_OEP_4_12 = 36,
 125         STEDMA40_DEV_USB_OTG_OEP_5_13 = 37,
 126         STEDMA40_DEV_USB_OTG_OEP_6_14 = 38,
 127         STEDMA40_DEV_USB_OTG_OEP_7_15 = 39,
 128         STEDMA40_DEV_SPI3_TX = 40,
 129         STEDMA40_DEV_SD_MM3_TX = 41,
 130         STEDMA40_DEV_SD_MM4_TX = 42,
 131         STEDMA40_DEV_SD_MM5_TX = 43,
 132         STEDMA40_DEV_DST_SXA4_RX_TX = 44,
 133         STEDMA40_DEV_DST_SXA5_RX_TX = 45,
 134         STEDMA40_DEV_DST_SXA6_RX_TX = 46,
 135         STEDMA40_DEV_DST_SXA7_RX_TX = 47,
 136         STEDMA40_DEV_CAC1_TX = 48,
 137         STEDMA40_DEV_CAC1_TX_HAC1_TX = 49,
 138         STEDMA40_DEV_HAC1_TX = 50,
 139         STEDMA40_MEMXCPY_TX_0 = 51,
 140         STEDMA40_DEV_SLIM1_CH0_TX_HSI_TX_CH4 = 52,
 141         STEDMA40_DEV_SLIM1_CH1_TX_HSI_TX_CH5 = 53,
 142         STEDMA40_DEV_SLIM1_CH2_TX_HSI_TX_CH6 = 54,
 143         STEDMA40_DEV_SLIM1_CH3_TX_HSI_TX_CH7 = 55,
 144         STEDMA40_MEMCPY_TX_1 = 56,
 145         STEDMA40_MEMCPY_TX_2 = 57,
 146         STEDMA40_MEMCPY_TX_3 = 58,
 147         STEDMA40_MEMCPY_TX_4 = 59,
 148         STEDMA40_MEMCPY_TX_5 = 60,
 149         STEDMA40_DEV_CAC0_TX = 61,
 150         STEDMA40_DEV_CAC0_TX_HAC0_TX = 62,
 151         STEDMA40_DEV_HAC0_TX = 63,
 152 };
 153
 154 #endif