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ARM: 6415/1: ux500: DB5500 mailbox driver
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / net / e1000e / 82571.c
blobd3d4a57e24505f9c36af9ef139bfc9133788a4bd
1 /*******************************************************************************
2
3 Intel PRO/1000 Linux driver
4 Copyright(c) 1999 - 2010 Intel Corporation.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
21
22 Contact Information:
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27 *******************************************************************************/
28
29 /*
30 * 82571EB Gigabit Ethernet Controller
31 * 82571EB Gigabit Ethernet Controller (Copper)
32 * 82571EB Gigabit Ethernet Controller (Fiber)
33 * 82571EB Dual Port Gigabit Mezzanine Adapter
34 * 82571EB Quad Port Gigabit Mezzanine Adapter
35 * 82571PT Gigabit PT Quad Port Server ExpressModule
36 * 82572EI Gigabit Ethernet Controller (Copper)
37 * 82572EI Gigabit Ethernet Controller (Fiber)
38 * 82572EI Gigabit Ethernet Controller
39 * 82573V Gigabit Ethernet Controller (Copper)
40 * 82573E Gigabit Ethernet Controller (Copper)
41 * 82573L Gigabit Ethernet Controller
42 * 82574L Gigabit Network Connection
43 * 82583V Gigabit Network Connection
44 */
45
46 #include "e1000.h"
47
48 #define ID_LED_RESERVED_F746 0xF746
49 #define ID_LED_DEFAULT_82573 ((ID_LED_DEF1_DEF2 << 12) | \
50 (ID_LED_OFF1_ON2 << 8) | \
51 (ID_LED_DEF1_DEF2 << 4) | \
52 (ID_LED_DEF1_DEF2))
53
54 #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000
55
56 #define E1000_NVM_INIT_CTRL2_MNGM 0x6000 /* Manageability Operation Mode mask */
57
58 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
59 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
60 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
61 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
62 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
63 u16 words, u16 *data);
64 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
65 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
66 static s32 e1000_setup_link_82571(struct e1000_hw *hw);
67 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
68 static void e1000_clear_vfta_82571(struct e1000_hw *hw);
69 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
70 static s32 e1000_led_on_82574(struct e1000_hw *hw);
71 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
72 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
73
74 /**
75 * e1000_init_phy_params_82571 - Init PHY func ptrs.
76 * @hw: pointer to the HW structure
77 **/
78 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
79 {
80 struct e1000_phy_info *phy = &hw->phy;
81 s32 ret_val;
82
83 if (hw->phy.media_type != e1000_media_type_copper) {
84 phy->type = e1000_phy_none;
85 return 0;
86 }
87
88 phy->addr = 1;
89 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
90 phy->reset_delay_us = 100;
91
92 phy->ops.power_up = e1000_power_up_phy_copper;
93 phy->ops.power_down = e1000_power_down_phy_copper_82571;
94
95 switch (hw->mac.type) {
96 case e1000_82571:
97 case e1000_82572:
98 phy->type = e1000_phy_igp_2;
99 break;
100 case e1000_82573:
101 phy->type = e1000_phy_m88;
102 break;
103 case e1000_82574:
104 case e1000_82583:
105 phy->type = e1000_phy_bm;
106 break;
107 default:
108 return -E1000_ERR_PHY;
109 break;
110 }
111
112 /* This can only be done after all function pointers are setup. */
113 ret_val = e1000_get_phy_id_82571(hw);
114
115 /* Verify phy id */
116 switch (hw->mac.type) {
117 case e1000_82571:
118 case e1000_82572:
119 if (phy->id != IGP01E1000_I_PHY_ID)
120 return -E1000_ERR_PHY;
121 break;
122 case e1000_82573:
123 if (phy->id != M88E1111_I_PHY_ID)
124 return -E1000_ERR_PHY;
125 break;
126 case e1000_82574:
127 case e1000_82583:
128 if (phy->id != BME1000_E_PHY_ID_R2)
129 return -E1000_ERR_PHY;
130 break;
131 default:
132 return -E1000_ERR_PHY;
133 break;
134 }
135
136 return 0;
137 }
138
139 /**
140 * e1000_init_nvm_params_82571 - Init NVM func ptrs.
141 * @hw: pointer to the HW structure
142 **/
143 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
144 {
145 struct e1000_nvm_info *nvm = &hw->nvm;
146 u32 eecd = er32(EECD);
147 u16 size;
148
149 nvm->opcode_bits = 8;
150 nvm->delay_usec = 1;
151 switch (nvm->override) {
152 case e1000_nvm_override_spi_large:
153 nvm->page_size = 32;
154 nvm->address_bits = 16;
155 break;
156 case e1000_nvm_override_spi_small:
157 nvm->page_size = 8;
158 nvm->address_bits = 8;
159 break;
160 default:
161 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
162 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
163 break;
164 }
165
166 switch (hw->mac.type) {
167 case e1000_82573:
168 case e1000_82574:
169 case e1000_82583:
170 if (((eecd >> 15) & 0x3) == 0x3) {
171 nvm->type = e1000_nvm_flash_hw;
172 nvm->word_size = 2048;
173 /*
174 * Autonomous Flash update bit must be cleared due
175 * to Flash update issue.
176 */
177 eecd &= ~E1000_EECD_AUPDEN;
178 ew32(EECD, eecd);
179 break;
180 }
181 /* Fall Through */
182 default:
183 nvm->type = e1000_nvm_eeprom_spi;
184 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
185 E1000_EECD_SIZE_EX_SHIFT);
186 /*
187 * Added to a constant, "size" becomes the left-shift value
188 * for setting word_size.
189 */
190 size += NVM_WORD_SIZE_BASE_SHIFT;
191
192 /* EEPROM access above 16k is unsupported */
193 if (size > 14)
194 size = 14;
195 nvm->word_size = 1 << size;
196 break;
197 }
198
199 return 0;
200 }
201
202 /**
203 * e1000_init_mac_params_82571 - Init MAC func ptrs.
204 * @hw: pointer to the HW structure
205 **/
206 static s32 e1000_init_mac_params_82571(struct e1000_adapter *adapter)
207 {
208 struct e1000_hw *hw = &adapter->hw;
209 struct e1000_mac_info *mac = &hw->mac;
210 struct e1000_mac_operations *func = &mac->ops;
211 u32 swsm = 0;
212 u32 swsm2 = 0;
213 bool force_clear_smbi = false;
214
215 /* Set media type */
216 switch (adapter->pdev->device) {
217 case E1000_DEV_ID_82571EB_FIBER:
218 case E1000_DEV_ID_82572EI_FIBER:
219 case E1000_DEV_ID_82571EB_QUAD_FIBER:
220 hw->phy.media_type = e1000_media_type_fiber;
221 break;
222 case E1000_DEV_ID_82571EB_SERDES:
223 case E1000_DEV_ID_82572EI_SERDES:
224 case E1000_DEV_ID_82571EB_SERDES_DUAL:
225 case E1000_DEV_ID_82571EB_SERDES_QUAD:
226 hw->phy.media_type = e1000_media_type_internal_serdes;
227 break;
228 default:
229 hw->phy.media_type = e1000_media_type_copper;
230 break;
231 }
232
233 /* Set mta register count */
234 mac->mta_reg_count = 128;
235 /* Set rar entry count */
236 mac->rar_entry_count = E1000_RAR_ENTRIES;
237 /* Adaptive IFS supported */
238 mac->adaptive_ifs = true;
239
240 /* check for link */
241 switch (hw->phy.media_type) {
242 case e1000_media_type_copper:
243 func->setup_physical_interface = e1000_setup_copper_link_82571;
244 func->check_for_link = e1000e_check_for_copper_link;
245 func->get_link_up_info = e1000e_get_speed_and_duplex_copper;
246 break;
247 case e1000_media_type_fiber:
248 func->setup_physical_interface =
249 e1000_setup_fiber_serdes_link_82571;
250 func->check_for_link = e1000e_check_for_fiber_link;
251 func->get_link_up_info =
252 e1000e_get_speed_and_duplex_fiber_serdes;
253 break;
254 case e1000_media_type_internal_serdes:
255 func->setup_physical_interface =
256 e1000_setup_fiber_serdes_link_82571;
257 func->check_for_link = e1000_check_for_serdes_link_82571;
258 func->get_link_up_info =
259 e1000e_get_speed_and_duplex_fiber_serdes;
260 break;
261 default:
262 return -E1000_ERR_CONFIG;
263 break;
264 }
265
266 switch (hw->mac.type) {
267 case e1000_82573:
268 func->set_lan_id = e1000_set_lan_id_single_port;
269 func->check_mng_mode = e1000e_check_mng_mode_generic;
270 func->led_on = e1000e_led_on_generic;
271
272 /* FWSM register */
273 mac->has_fwsm = true;
274 /*
275 * ARC supported; valid only if manageability features are
276 * enabled.
277 */
278 mac->arc_subsystem_valid =
279 (er32(FWSM) & E1000_FWSM_MODE_MASK)
280 ? true : false;
281 break;
282 case e1000_82574:
283 case e1000_82583:
284 func->set_lan_id = e1000_set_lan_id_single_port;
285 func->check_mng_mode = e1000_check_mng_mode_82574;
286 func->led_on = e1000_led_on_82574;
287 break;
288 default:
289 func->check_mng_mode = e1000e_check_mng_mode_generic;
290 func->led_on = e1000e_led_on_generic;
291
292 /* FWSM register */
293 mac->has_fwsm = true;
294 break;
295 }
296
297 /*
298 * Ensure that the inter-port SWSM.SMBI lock bit is clear before
299 * first NVM or PHY acess. This should be done for single-port
300 * devices, and for one port only on dual-port devices so that
301 * for those devices we can still use the SMBI lock to synchronize
302 * inter-port accesses to the PHY & NVM.
303 */
304 switch (hw->mac.type) {
305 case e1000_82571:
306 case e1000_82572:
307 swsm2 = er32(SWSM2);
308
309 if (!(swsm2 & E1000_SWSM2_LOCK)) {
310 /* Only do this for the first interface on this card */
311 ew32(SWSM2,
312 swsm2 | E1000_SWSM2_LOCK);
313 force_clear_smbi = true;
314 } else
315 force_clear_smbi = false;
316 break;
317 default:
318 force_clear_smbi = true;
319 break;
320 }
321
322 if (force_clear_smbi) {
323 /* Make sure SWSM.SMBI is clear */
324 swsm = er32(SWSM);
325 if (swsm & E1000_SWSM_SMBI) {
326 /* This bit should not be set on a first interface, and
327 * indicates that the bootagent or EFI code has
328 * improperly left this bit enabled
329 */
330 e_dbg("Please update your 82571 Bootagent\n");
331 }
332 ew32(SWSM, swsm & ~E1000_SWSM_SMBI);
333 }
334
335 /*
336 * Initialize device specific counter of SMBI acquisition
337 * timeouts.
338 */
339 hw->dev_spec.e82571.smb_counter = 0;
340
341 return 0;
342 }
343
344 static s32 e1000_get_variants_82571(struct e1000_adapter *adapter)
345 {
346 struct e1000_hw *hw = &adapter->hw;
347 static int global_quad_port_a; /* global port a indication */
348 struct pci_dev *pdev = adapter->pdev;
349 int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1;
350 s32 rc;
351
352 rc = e1000_init_mac_params_82571(adapter);
353 if (rc)
354 return rc;
355
356 rc = e1000_init_nvm_params_82571(hw);
357 if (rc)
358 return rc;
359
360 rc = e1000_init_phy_params_82571(hw);
361 if (rc)
362 return rc;
363
364 /* tag quad port adapters first, it's used below */
365 switch (pdev->device) {
366 case E1000_DEV_ID_82571EB_QUAD_COPPER:
367 case E1000_DEV_ID_82571EB_QUAD_FIBER:
368 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
369 case E1000_DEV_ID_82571PT_QUAD_COPPER:
370 adapter->flags |= FLAG_IS_QUAD_PORT;
371 /* mark the first port */
372 if (global_quad_port_a == 0)
373 adapter->flags |= FLAG_IS_QUAD_PORT_A;
374 /* Reset for multiple quad port adapters */
375 global_quad_port_a++;
376 if (global_quad_port_a == 4)
377 global_quad_port_a = 0;
378 break;
379 default:
380 break;
381 }
382
383 switch (adapter->hw.mac.type) {
384 case e1000_82571:
385 /* these dual ports don't have WoL on port B at all */
386 if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) ||
387 (pdev->device == E1000_DEV_ID_82571EB_SERDES) ||
388 (pdev->device == E1000_DEV_ID_82571EB_COPPER)) &&
389 (is_port_b))
390 adapter->flags &= ~FLAG_HAS_WOL;
391 /* quad ports only support WoL on port A */
392 if (adapter->flags & FLAG_IS_QUAD_PORT &&
393 (!(adapter->flags & FLAG_IS_QUAD_PORT_A)))
394 adapter->flags &= ~FLAG_HAS_WOL;
395 /* Does not support WoL on any port */
396 if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD)
397 adapter->flags &= ~FLAG_HAS_WOL;
398 break;
399 case e1000_82573:
400 case e1000_82574:
401 case e1000_82583:
402 /* Disable ASPM L0s due to hardware errata */
403 e1000e_disable_aspm(adapter->pdev, PCIE_LINK_STATE_L0S);
404
405 if (pdev->device == E1000_DEV_ID_82573L) {
406 adapter->flags |= FLAG_HAS_JUMBO_FRAMES;
407 adapter->max_hw_frame_size = DEFAULT_JUMBO;
408 }
409 break;
410 default:
411 break;
412 }
413
414 return 0;
415 }
416
417 /**
418 * e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
419 * @hw: pointer to the HW structure
420 *
421 * Reads the PHY registers and stores the PHY ID and possibly the PHY
422 * revision in the hardware structure.
423 **/
424 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
425 {
426 struct e1000_phy_info *phy = &hw->phy;
427 s32 ret_val;
428 u16 phy_id = 0;
429
430 switch (hw->mac.type) {
431 case e1000_82571:
432 case e1000_82572:
433 /*
434 * The 82571 firmware may still be configuring the PHY.
435 * In this case, we cannot access the PHY until the
436 * configuration is done. So we explicitly set the
437 * PHY ID.
438 */
439 phy->id = IGP01E1000_I_PHY_ID;
440 break;
441 case e1000_82573:
442 return e1000e_get_phy_id(hw);
443 break;
444 case e1000_82574:
445 case e1000_82583:
446 ret_val = e1e_rphy(hw, PHY_ID1, &phy_id);
447 if (ret_val)
448 return ret_val;
449
450 phy->id = (u32)(phy_id << 16);
451 udelay(20);
452 ret_val = e1e_rphy(hw, PHY_ID2, &phy_id);
453 if (ret_val)
454 return ret_val;
455
456 phy->id |= (u32)(phy_id);
457 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
458 break;
459 default:
460 return -E1000_ERR_PHY;
461 break;
462 }
463
464 return 0;
465 }
466
467 /**
468 * e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
469 * @hw: pointer to the HW structure
470 *
471 * Acquire the HW semaphore to access the PHY or NVM
472 **/
473 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
474 {
475 u32 swsm;
476 s32 sw_timeout = hw->nvm.word_size + 1;
477 s32 fw_timeout = hw->nvm.word_size + 1;
478 s32 i = 0;
479
480 /*
481 * If we have timedout 3 times on trying to acquire
482 * the inter-port SMBI semaphore, there is old code
483 * operating on the other port, and it is not
484 * releasing SMBI. Modify the number of times that
485 * we try for the semaphore to interwork with this
486 * older code.
487 */
488 if (hw->dev_spec.e82571.smb_counter > 2)
489 sw_timeout = 1;
490
491 /* Get the SW semaphore */
492 while (i < sw_timeout) {
493 swsm = er32(SWSM);
494 if (!(swsm & E1000_SWSM_SMBI))
495 break;
496
497 udelay(50);
498 i++;
499 }
500
501 if (i == sw_timeout) {
502 e_dbg("Driver can't access device - SMBI bit is set.\n");
503 hw->dev_spec.e82571.smb_counter++;
504 }
505 /* Get the FW semaphore. */
506 for (i = 0; i < fw_timeout; i++) {
507 swsm = er32(SWSM);
508 ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
509
510 /* Semaphore acquired if bit latched */
511 if (er32(SWSM) & E1000_SWSM_SWESMBI)
512 break;
513
514 udelay(50);
515 }
516
517 if (i == fw_timeout) {
518 /* Release semaphores */
519 e1000_put_hw_semaphore_82571(hw);
520 e_dbg("Driver can't access the NVM\n");
521 return -E1000_ERR_NVM;
522 }
523
524 return 0;
525 }
526
527 /**
528 * e1000_put_hw_semaphore_82571 - Release hardware semaphore
529 * @hw: pointer to the HW structure
530 *
531 * Release hardware semaphore used to access the PHY or NVM
532 **/
533 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
534 {
535 u32 swsm;
536
537 swsm = er32(SWSM);
538 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
539 ew32(SWSM, swsm);
540 }
541
542 /**
543 * e1000_acquire_nvm_82571 - Request for access to the EEPROM
544 * @hw: pointer to the HW structure
545 *
546 * To gain access to the EEPROM, first we must obtain a hardware semaphore.
547 * Then for non-82573 hardware, set the EEPROM access request bit and wait
548 * for EEPROM access grant bit. If the access grant bit is not set, release
549 * hardware semaphore.
550 **/
551 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
552 {
553 s32 ret_val;
554
555 ret_val = e1000_get_hw_semaphore_82571(hw);
556 if (ret_val)
557 return ret_val;
558
559 switch (hw->mac.type) {
560 case e1000_82573:
561 case e1000_82574:
562 case e1000_82583:
563 break;
564 default:
565 ret_val = e1000e_acquire_nvm(hw);
566 break;
567 }
568
569 if (ret_val)
570 e1000_put_hw_semaphore_82571(hw);
571
572 return ret_val;
573 }
574
575 /**
576 * e1000_release_nvm_82571 - Release exclusive access to EEPROM
577 * @hw: pointer to the HW structure
578 *
579 * Stop any current commands to the EEPROM and clear the EEPROM request bit.
580 **/
581 static void e1000_release_nvm_82571(struct e1000_hw *hw)
582 {
583 e1000e_release_nvm(hw);
584 e1000_put_hw_semaphore_82571(hw);
585 }
586
587 /**
588 * e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
589 * @hw: pointer to the HW structure
590 * @offset: offset within the EEPROM to be written to
591 * @words: number of words to write
592 * @data: 16 bit word(s) to be written to the EEPROM
593 *
594 * For non-82573 silicon, write data to EEPROM at offset using SPI interface.
595 *
596 * If e1000e_update_nvm_checksum is not called after this function, the
597 * EEPROM will most likely contain an invalid checksum.
598 **/
599 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
600 u16 *data)
601 {
602 s32 ret_val;
603
604 switch (hw->mac.type) {
605 case e1000_82573:
606 case e1000_82574:
607 case e1000_82583:
608 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
609 break;
610 case e1000_82571:
611 case e1000_82572:
612 ret_val = e1000e_write_nvm_spi(hw, offset, words, data);
613 break;
614 default:
615 ret_val = -E1000_ERR_NVM;
616 break;
617 }
618
619 return ret_val;
620 }
621
622 /**
623 * e1000_update_nvm_checksum_82571 - Update EEPROM checksum
624 * @hw: pointer to the HW structure
625 *
626 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
627 * up to the checksum. Then calculates the EEPROM checksum and writes the
628 * value to the EEPROM.
629 **/
630 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
631 {
632 u32 eecd;
633 s32 ret_val;
634 u16 i;
635
636 ret_val = e1000e_update_nvm_checksum_generic(hw);
637 if (ret_val)
638 return ret_val;
639
640 /*
641 * If our nvm is an EEPROM, then we're done
642 * otherwise, commit the checksum to the flash NVM.
643 */
644 if (hw->nvm.type != e1000_nvm_flash_hw)
645 return ret_val;
646
647 /* Check for pending operations. */
648 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
649 msleep(1);
650 if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
651 break;
652 }
653
654 if (i == E1000_FLASH_UPDATES)
655 return -E1000_ERR_NVM;
656
657 /* Reset the firmware if using STM opcode. */
658 if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {
659 /*
660 * The enabling of and the actual reset must be done
661 * in two write cycles.
662 */
663 ew32(HICR, E1000_HICR_FW_RESET_ENABLE);
664 e1e_flush();
665 ew32(HICR, E1000_HICR_FW_RESET);
666 }
667
668 /* Commit the write to flash */
669 eecd = er32(EECD) | E1000_EECD_FLUPD;
670 ew32(EECD, eecd);
671
672 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
673 msleep(1);
674 if ((er32(EECD) & E1000_EECD_FLUPD) == 0)
675 break;
676 }
677
678 if (i == E1000_FLASH_UPDATES)
679 return -E1000_ERR_NVM;
680
681 return 0;
682 }
683
684 /**
685 * e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
686 * @hw: pointer to the HW structure
687 *
688 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
689 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
690 **/
691 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
692 {
693 if (hw->nvm.type == e1000_nvm_flash_hw)
694 e1000_fix_nvm_checksum_82571(hw);
695
696 return e1000e_validate_nvm_checksum_generic(hw);
697 }
698
699 /**
700 * e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
701 * @hw: pointer to the HW structure
702 * @offset: offset within the EEPROM to be written to
703 * @words: number of words to write
704 * @data: 16 bit word(s) to be written to the EEPROM
705 *
706 * After checking for invalid values, poll the EEPROM to ensure the previous
707 * command has completed before trying to write the next word. After write
708 * poll for completion.
709 *
710 * If e1000e_update_nvm_checksum is not called after this function, the
711 * EEPROM will most likely contain an invalid checksum.
712 **/
713 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
714 u16 words, u16 *data)
715 {
716 struct e1000_nvm_info *nvm = &hw->nvm;
717 u32 i, eewr = 0;
718 s32 ret_val = 0;
719
720 /*
721 * A check for invalid values: offset too large, too many words,
722 * and not enough words.
723 */
724 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
725 (words == 0)) {
726 e_dbg("nvm parameter(s) out of bounds\n");
727 return -E1000_ERR_NVM;
728 }
729
730 for (i = 0; i < words; i++) {
731 eewr = (data[i] << E1000_NVM_RW_REG_DATA) |
732 ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
733 E1000_NVM_RW_REG_START;
734
735 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
736 if (ret_val)
737 break;
738
739 ew32(EEWR, eewr);
740
741 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
742 if (ret_val)
743 break;
744 }
745
746 return ret_val;
747 }
748
749 /**
750 * e1000_get_cfg_done_82571 - Poll for configuration done
751 * @hw: pointer to the HW structure
752 *
753 * Reads the management control register for the config done bit to be set.
754 **/
755 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
756 {
757 s32 timeout = PHY_CFG_TIMEOUT;
758
759 while (timeout) {
760 if (er32(EEMNGCTL) &
761 E1000_NVM_CFG_DONE_PORT_0)
762 break;
763 msleep(1);
764 timeout--;
765 }
766 if (!timeout) {
767 e_dbg("MNG configuration cycle has not completed.\n");
768 return -E1000_ERR_RESET;
769 }
770
771 return 0;
772 }
773
774 /**
775 * e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
776 * @hw: pointer to the HW structure
777 * @active: true to enable LPLU, false to disable
778 *
779 * Sets the LPLU D0 state according to the active flag. When activating LPLU
780 * this function also disables smart speed and vice versa. LPLU will not be
781 * activated unless the device autonegotiation advertisement meets standards
782 * of either 10 or 10/100 or 10/100/1000 at all duplexes. This is a function
783 * pointer entry point only called by PHY setup routines.
784 **/
785 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
786 {
787 struct e1000_phy_info *phy = &hw->phy;
788 s32 ret_val;
789 u16 data;
790
791 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
792 if (ret_val)
793 return ret_val;
794
795 if (active) {
796 data |= IGP02E1000_PM_D0_LPLU;
797 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
798 if (ret_val)
799 return ret_val;
800
801 /* When LPLU is enabled, we should disable SmartSpeed */
802 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
803 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
804 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
805 if (ret_val)
806 return ret_val;
807 } else {
808 data &= ~IGP02E1000_PM_D0_LPLU;
809 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
810 /*
811 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
812 * during Dx states where the power conservation is most
813 * important. During driver activity we should enable
814 * SmartSpeed, so performance is maintained.
815 */
816 if (phy->smart_speed == e1000_smart_speed_on) {
817 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
818 &data);
819 if (ret_val)
820 return ret_val;
821
822 data |= IGP01E1000_PSCFR_SMART_SPEED;
823 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
824 data);
825 if (ret_val)
826 return ret_val;
827 } else if (phy->smart_speed == e1000_smart_speed_off) {
828 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
829 &data);
830 if (ret_val)
831 return ret_val;
832
833 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
834 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
835 data);
836 if (ret_val)
837 return ret_val;
838 }
839 }
840
841 return 0;
842 }
843
844 /**
845 * e1000_reset_hw_82571 - Reset hardware
846 * @hw: pointer to the HW structure
847 *
848 * This resets the hardware into a known state.
849 **/
850 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
851 {
852 u32 ctrl, extcnf_ctrl, ctrl_ext, icr;
853 s32 ret_val;
854 u16 i = 0;
855
856 /*
857 * Prevent the PCI-E bus from sticking if there is no TLP connection
858 * on the last TLP read/write transaction when MAC is reset.
859 */
860 ret_val = e1000e_disable_pcie_master(hw);
861 if (ret_val)
862 e_dbg("PCI-E Master disable polling has failed.\n");
863
864 e_dbg("Masking off all interrupts\n");
865 ew32(IMC, 0xffffffff);
866
867 ew32(RCTL, 0);
868 ew32(TCTL, E1000_TCTL_PSP);
869 e1e_flush();
870
871 msleep(10);
872
873 /*
874 * Must acquire the MDIO ownership before MAC reset.
875 * Ownership defaults to firmware after a reset.
876 */
877 switch (hw->mac.type) {
878 case e1000_82573:
879 case e1000_82574:
880 case e1000_82583:
881 extcnf_ctrl = er32(EXTCNF_CTRL);
882 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
883
884 do {
885 ew32(EXTCNF_CTRL, extcnf_ctrl);
886 extcnf_ctrl = er32(EXTCNF_CTRL);
887
888 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
889 break;
890
891 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
892
893 msleep(2);
894 i++;
895 } while (i < MDIO_OWNERSHIP_TIMEOUT);
896 break;
897 default:
898 break;
899 }
900
901 ctrl = er32(CTRL);
902
903 e_dbg("Issuing a global reset to MAC\n");
904 ew32(CTRL, ctrl | E1000_CTRL_RST);
905
906 if (hw->nvm.type == e1000_nvm_flash_hw) {
907 udelay(10);
908 ctrl_ext = er32(CTRL_EXT);
909 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
910 ew32(CTRL_EXT, ctrl_ext);
911 e1e_flush();
912 }
913
914 ret_val = e1000e_get_auto_rd_done(hw);
915 if (ret_val)
916 /* We don't want to continue accessing MAC registers. */
917 return ret_val;
918
919 /*
920 * Phy configuration from NVM just starts after EECD_AUTO_RD is set.
921 * Need to wait for Phy configuration completion before accessing
922 * NVM and Phy.
923 */
924
925 switch (hw->mac.type) {
926 case e1000_82573:
927 case e1000_82574:
928 case e1000_82583:
929 msleep(25);
930 break;
931 default:
932 break;
933 }
934
935 /* Clear any pending interrupt events. */
936 ew32(IMC, 0xffffffff);
937 icr = er32(ICR);
938
939 if (hw->mac.type == e1000_82571) {
940 /* Install any alternate MAC address into RAR0 */
941 ret_val = e1000_check_alt_mac_addr_generic(hw);
942 if (ret_val)
943 return ret_val;
944
945 e1000e_set_laa_state_82571(hw, true);
946 }
947
948 /* Reinitialize the 82571 serdes link state machine */
949 if (hw->phy.media_type == e1000_media_type_internal_serdes)
950 hw->mac.serdes_link_state = e1000_serdes_link_down;
951
952 return 0;
953 }
954
955 /**
956 * e1000_init_hw_82571 - Initialize hardware
957 * @hw: pointer to the HW structure
958 *
959 * This inits the hardware readying it for operation.
960 **/
961 static s32 e1000_init_hw_82571(struct e1000_hw *hw)
962 {
963 struct e1000_mac_info *mac = &hw->mac;
964 u32 reg_data;
965 s32 ret_val;
966 u16 i, rar_count = mac->rar_entry_count;
967
968 e1000_initialize_hw_bits_82571(hw);
969
970 /* Initialize identification LED */
971 ret_val = e1000e_id_led_init(hw);
972 if (ret_val)
973 e_dbg("Error initializing identification LED\n");
974 /* This is not fatal and we should not stop init due to this */
975
976 /* Disabling VLAN filtering */
977 e_dbg("Initializing the IEEE VLAN\n");
978 mac->ops.clear_vfta(hw);
979
980 /* Setup the receive address. */
981 /*
982 * If, however, a locally administered address was assigned to the
983 * 82571, we must reserve a RAR for it to work around an issue where
984 * resetting one port will reload the MAC on the other port.
985 */
986 if (e1000e_get_laa_state_82571(hw))
987 rar_count--;
988 e1000e_init_rx_addrs(hw, rar_count);
989
990 /* Zero out the Multicast HASH table */
991 e_dbg("Zeroing the MTA\n");
992 for (i = 0; i < mac->mta_reg_count; i++)
993 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
994
995 /* Setup link and flow control */
996 ret_val = e1000_setup_link_82571(hw);
997
998 /* Set the transmit descriptor write-back policy */
999 reg_data = er32(TXDCTL(0));
1000 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1001 E1000_TXDCTL_FULL_TX_DESC_WB |
1002 E1000_TXDCTL_COUNT_DESC;
1003 ew32(TXDCTL(0), reg_data);
1004
1005 /* ...for both queues. */
1006 switch (mac->type) {
1007 case e1000_82573:
1008 e1000e_enable_tx_pkt_filtering(hw);
1009 /* fall through */
1010 case e1000_82574:
1011 case e1000_82583:
1012 reg_data = er32(GCR);
1013 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1014 ew32(GCR, reg_data);
1015 break;
1016 default:
1017 reg_data = er32(TXDCTL(1));
1018 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
1019 E1000_TXDCTL_FULL_TX_DESC_WB |
1020 E1000_TXDCTL_COUNT_DESC;
1021 ew32(TXDCTL(1), reg_data);
1022 break;
1023 }
1024
1025 /*
1026 * Clear all of the statistics registers (clear on read). It is
1027 * important that we do this after we have tried to establish link
1028 * because the symbol error count will increment wildly if there
1029 * is no link.
1030 */
1031 e1000_clear_hw_cntrs_82571(hw);
1032
1033 return ret_val;
1034 }
1035
1036 /**
1037 * e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1038 * @hw: pointer to the HW structure
1039 *
1040 * Initializes required hardware-dependent bits needed for normal operation.
1041 **/
1042 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1043 {
1044 u32 reg;
1045
1046 /* Transmit Descriptor Control 0 */
1047 reg = er32(TXDCTL(0));
1048 reg |= (1 << 22);
1049 ew32(TXDCTL(0), reg);
1050
1051 /* Transmit Descriptor Control 1 */
1052 reg = er32(TXDCTL(1));
1053 reg |= (1 << 22);
1054 ew32(TXDCTL(1), reg);
1055
1056 /* Transmit Arbitration Control 0 */
1057 reg = er32(TARC(0));
1058 reg &= ~(0xF << 27); /* 30:27 */
1059 switch (hw->mac.type) {
1060 case e1000_82571:
1061 case e1000_82572:
1062 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1063 break;
1064 default:
1065 break;
1066 }
1067 ew32(TARC(0), reg);
1068
1069 /* Transmit Arbitration Control 1 */
1070 reg = er32(TARC(1));
1071 switch (hw->mac.type) {
1072 case e1000_82571:
1073 case e1000_82572:
1074 reg &= ~((1 << 29) | (1 << 30));
1075 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1076 if (er32(TCTL) & E1000_TCTL_MULR)
1077 reg &= ~(1 << 28);
1078 else
1079 reg |= (1 << 28);
1080 ew32(TARC(1), reg);
1081 break;
1082 default:
1083 break;
1084 }
1085
1086 /* Device Control */
1087 switch (hw->mac.type) {
1088 case e1000_82573:
1089 case e1000_82574:
1090 case e1000_82583:
1091 reg = er32(CTRL);
1092 reg &= ~(1 << 29);
1093 ew32(CTRL, reg);
1094 break;
1095 default:
1096 break;
1097 }
1098
1099 /* Extended Device Control */
1100 switch (hw->mac.type) {
1101 case e1000_82573:
1102 case e1000_82574:
1103 case e1000_82583:
1104 reg = er32(CTRL_EXT);
1105 reg &= ~(1 << 23);
1106 reg |= (1 << 22);
1107 ew32(CTRL_EXT, reg);
1108 break;
1109 default:
1110 break;
1111 }
1112
1113 if (hw->mac.type == e1000_82571) {
1114 reg = er32(PBA_ECC);
1115 reg |= E1000_PBA_ECC_CORR_EN;
1116 ew32(PBA_ECC, reg);
1117 }
1118 /*
1119 * Workaround for hardware errata.
1120 * Ensure that DMA Dynamic Clock gating is disabled on 82571 and 82572
1121 */
1122
1123 if ((hw->mac.type == e1000_82571) ||
1124 (hw->mac.type == e1000_82572)) {
1125 reg = er32(CTRL_EXT);
1126 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1127 ew32(CTRL_EXT, reg);
1128 }
1129
1130
1131 /* PCI-Ex Control Registers */
1132 switch (hw->mac.type) {
1133 case e1000_82574:
1134 case e1000_82583:
1135 reg = er32(GCR);
1136 reg |= (1 << 22);
1137 ew32(GCR, reg);
1138
1139 /*
1140 * Workaround for hardware errata.
1141 * apply workaround for hardware errata documented in errata
1142 * docs Fixes issue where some error prone or unreliable PCIe
1143 * completions are occurring, particularly with ASPM enabled.
1144 * Without fix, issue can cause tx timeouts.
1145 */
1146 reg = er32(GCR2);
1147 reg |= 1;
1148 ew32(GCR2, reg);
1149 break;
1150 default:
1151 break;
1152 }
1153 }
1154
1155 /**
1156 * e1000_clear_vfta_82571 - Clear VLAN filter table
1157 * @hw: pointer to the HW structure
1158 *
1159 * Clears the register array which contains the VLAN filter table by
1160 * setting all the values to 0.
1161 **/
1162 static void e1000_clear_vfta_82571(struct e1000_hw *hw)
1163 {
1164 u32 offset;
1165 u32 vfta_value = 0;
1166 u32 vfta_offset = 0;
1167 u32 vfta_bit_in_reg = 0;
1168
1169 switch (hw->mac.type) {
1170 case e1000_82573:
1171 case e1000_82574:
1172 case e1000_82583:
1173 if (hw->mng_cookie.vlan_id != 0) {
1174 /*
1175 * The VFTA is a 4096b bit-field, each identifying
1176 * a single VLAN ID. The following operations
1177 * determine which 32b entry (i.e. offset) into the
1178 * array we want to set the VLAN ID (i.e. bit) of
1179 * the manageability unit.
1180 */
1181 vfta_offset = (hw->mng_cookie.vlan_id >>
1182 E1000_VFTA_ENTRY_SHIFT) &
1183 E1000_VFTA_ENTRY_MASK;
1184 vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
1185 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1186 }
1187 break;
1188 default:
1189 break;
1190 }
1191 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1192 /*
1193 * If the offset we want to clear is the same offset of the
1194 * manageability VLAN ID, then clear all bits except that of
1195 * the manageability unit.
1196 */
1197 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1198 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1199 e1e_flush();
1200 }
1201 }
1202
1203 /**
1204 * e1000_check_mng_mode_82574 - Check manageability is enabled
1205 * @hw: pointer to the HW structure
1206 *
1207 * Reads the NVM Initialization Control Word 2 and returns true
1208 * (>0) if any manageability is enabled, else false (0).
1209 **/
1210 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1211 {
1212 u16 data;
1213
1214 e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1215 return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1216 }
1217
1218 /**
1219 * e1000_led_on_82574 - Turn LED on
1220 * @hw: pointer to the HW structure
1221 *
1222 * Turn LED on.
1223 **/
1224 static s32 e1000_led_on_82574(struct e1000_hw *hw)
1225 {
1226 u32 ctrl;
1227 u32 i;
1228
1229 ctrl = hw->mac.ledctl_mode2;
1230 if (!(E1000_STATUS_LU & er32(STATUS))) {
1231 /*
1232 * If no link, then turn LED on by setting the invert bit
1233 * for each LED that's "on" (0x0E) in ledctl_mode2.
1234 */
1235 for (i = 0; i < 4; i++)
1236 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1237 E1000_LEDCTL_MODE_LED_ON)
1238 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1239 }
1240 ew32(LEDCTL, ctrl);
1241
1242 return 0;
1243 }
1244
1245 /**
1246 * e1000_setup_link_82571 - Setup flow control and link settings
1247 * @hw: pointer to the HW structure
1248 *
1249 * Determines which flow control settings to use, then configures flow
1250 * control. Calls the appropriate media-specific link configuration
1251 * function. Assuming the adapter has a valid link partner, a valid link
1252 * should be established. Assumes the hardware has previously been reset
1253 * and the transmitter and receiver are not enabled.
1254 **/
1255 static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1256 {
1257 /*
1258 * 82573 does not have a word in the NVM to determine
1259 * the default flow control setting, so we explicitly
1260 * set it to full.
1261 */
1262 switch (hw->mac.type) {
1263 case e1000_82573:
1264 case e1000_82574:
1265 case e1000_82583:
1266 if (hw->fc.requested_mode == e1000_fc_default)
1267 hw->fc.requested_mode = e1000_fc_full;
1268 break;
1269 default:
1270 break;
1271 }
1272
1273 return e1000e_setup_link(hw);
1274 }
1275
1276 /**
1277 * e1000_setup_copper_link_82571 - Configure copper link settings
1278 * @hw: pointer to the HW structure
1279 *
1280 * Configures the link for auto-neg or forced speed and duplex. Then we check
1281 * for link, once link is established calls to configure collision distance
1282 * and flow control are called.
1283 **/
1284 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1285 {
1286 u32 ctrl;
1287 s32 ret_val;
1288
1289 ctrl = er32(CTRL);
1290 ctrl |= E1000_CTRL_SLU;
1291 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1292 ew32(CTRL, ctrl);
1293
1294 switch (hw->phy.type) {
1295 case e1000_phy_m88:
1296 case e1000_phy_bm:
1297 ret_val = e1000e_copper_link_setup_m88(hw);
1298 break;
1299 case e1000_phy_igp_2:
1300 ret_val = e1000e_copper_link_setup_igp(hw);
1301 break;
1302 default:
1303 return -E1000_ERR_PHY;
1304 break;
1305 }
1306
1307 if (ret_val)
1308 return ret_val;
1309
1310 ret_val = e1000e_setup_copper_link(hw);
1311
1312 return ret_val;
1313 }
1314
1315 /**
1316 * e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1317 * @hw: pointer to the HW structure
1318 *
1319 * Configures collision distance and flow control for fiber and serdes links.
1320 * Upon successful setup, poll for link.
1321 **/
1322 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1323 {
1324 switch (hw->mac.type) {
1325 case e1000_82571:
1326 case e1000_82572:
1327 /*
1328 * If SerDes loopback mode is entered, there is no form
1329 * of reset to take the adapter out of that mode. So we
1330 * have to explicitly take the adapter out of loopback
1331 * mode. This prevents drivers from twiddling their thumbs
1332 * if another tool failed to take it out of loopback mode.
1333 */
1334 ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1335 break;
1336 default:
1337 break;
1338 }
1339
1340 return e1000e_setup_fiber_serdes_link(hw);
1341 }
1342
1343 /**
1344 * e1000_check_for_serdes_link_82571 - Check for link (Serdes)
1345 * @hw: pointer to the HW structure
1346 *
1347 * Reports the link state as up or down.
1348 *
1349 * If autonegotiation is supported by the link partner, the link state is
1350 * determined by the result of autonegotiation. This is the most likely case.
1351 * If autonegotiation is not supported by the link partner, and the link
1352 * has a valid signal, force the link up.
1353 *
1354 * The link state is represented internally here by 4 states:
1355 *
1356 * 1) down
1357 * 2) autoneg_progress
1358 * 3) autoneg_complete (the link successfully autonegotiated)
1359 * 4) forced_up (the link has been forced up, it did not autonegotiate)
1360 *
1361 **/
1362 static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1363 {
1364 struct e1000_mac_info *mac = &hw->mac;
1365 u32 rxcw;
1366 u32 ctrl;
1367 u32 status;
1368 s32 ret_val = 0;
1369
1370 ctrl = er32(CTRL);
1371 status = er32(STATUS);
1372 rxcw = er32(RXCW);
1373
1374 if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1375
1376 /* Receiver is synchronized with no invalid bits. */
1377 switch (mac->serdes_link_state) {
1378 case e1000_serdes_link_autoneg_complete:
1379 if (!(status & E1000_STATUS_LU)) {
1380 /*
1381 * We have lost link, retry autoneg before
1382 * reporting link failure
1383 */
1384 mac->serdes_link_state =
1385 e1000_serdes_link_autoneg_progress;
1386 mac->serdes_has_link = false;
1387 e_dbg("AN_UP -> AN_PROG\n");
1388 }
1389 break;
1390
1391 case e1000_serdes_link_forced_up:
1392 /*
1393 * If we are receiving /C/ ordered sets, re-enable
1394 * auto-negotiation in the TXCW register and disable
1395 * forced link in the Device Control register in an
1396 * attempt to auto-negotiate with our link partner.
1397 */
1398 if (rxcw & E1000_RXCW_C) {
1399 /* Enable autoneg, and unforce link up */
1400 ew32(TXCW, mac->txcw);
1401 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
1402 mac->serdes_link_state =
1403 e1000_serdes_link_autoneg_progress;
1404 mac->serdes_has_link = false;
1405 e_dbg("FORCED_UP -> AN_PROG\n");
1406 }
1407 break;
1408
1409 case e1000_serdes_link_autoneg_progress:
1410 if (rxcw & E1000_RXCW_C) {
1411 /*
1412 * We received /C/ ordered sets, meaning the
1413 * link partner has autonegotiated, and we can
1414 * trust the Link Up (LU) status bit.
1415 */
1416 if (status & E1000_STATUS_LU) {
1417 mac->serdes_link_state =
1418 e1000_serdes_link_autoneg_complete;
1419 e_dbg("AN_PROG -> AN_UP\n");
1420 mac->serdes_has_link = true;
1421 } else {
1422 /* Autoneg completed, but failed. */
1423 mac->serdes_link_state =
1424 e1000_serdes_link_down;
1425 e_dbg("AN_PROG -> DOWN\n");
1426 }
1427 } else {
1428 /*
1429 * The link partner did not autoneg.
1430 * Force link up and full duplex, and change
1431 * state to forced.
1432 */
1433 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
1434 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1435 ew32(CTRL, ctrl);
1436
1437 /* Configure Flow Control after link up. */
1438 ret_val = e1000e_config_fc_after_link_up(hw);
1439 if (ret_val) {
1440 e_dbg("Error config flow control\n");
1441 break;
1442 }
1443 mac->serdes_link_state =
1444 e1000_serdes_link_forced_up;
1445 mac->serdes_has_link = true;
1446 e_dbg("AN_PROG -> FORCED_UP\n");
1447 }
1448 break;
1449
1450 case e1000_serdes_link_down:
1451 default:
1452 /*
1453 * The link was down but the receiver has now gained
1454 * valid sync, so lets see if we can bring the link
1455 * up.
1456 */
1457 ew32(TXCW, mac->txcw);
1458 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
1459 mac->serdes_link_state =
1460 e1000_serdes_link_autoneg_progress;
1461 e_dbg("DOWN -> AN_PROG\n");
1462 break;
1463 }
1464 } else {
1465 if (!(rxcw & E1000_RXCW_SYNCH)) {
1466 mac->serdes_has_link = false;
1467 mac->serdes_link_state = e1000_serdes_link_down;
1468 e_dbg("ANYSTATE -> DOWN\n");
1469 } else {
1470 /*
1471 * We have sync, and can tolerate one invalid (IV)
1472 * codeword before declaring link down, so reread
1473 * to look again.
1474 */
1475 udelay(10);
1476 rxcw = er32(RXCW);
1477 if (rxcw & E1000_RXCW_IV) {
1478 mac->serdes_link_state = e1000_serdes_link_down;
1479 mac->serdes_has_link = false;
1480 e_dbg("ANYSTATE -> DOWN\n");
1481 }
1482 }
1483 }
1484
1485 return ret_val;
1486 }
1487
1488 /**
1489 * e1000_valid_led_default_82571 - Verify a valid default LED config
1490 * @hw: pointer to the HW structure
1491 * @data: pointer to the NVM (EEPROM)
1492 *
1493 * Read the EEPROM for the current default LED configuration. If the
1494 * LED configuration is not valid, set to a valid LED configuration.
1495 **/
1496 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1497 {
1498 s32 ret_val;
1499
1500 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1501 if (ret_val) {
1502 e_dbg("NVM Read Error\n");
1503 return ret_val;
1504 }
1505
1506 switch (hw->mac.type) {
1507 case e1000_82573:
1508 case e1000_82574:
1509 case e1000_82583:
1510 if (*data == ID_LED_RESERVED_F746)
1511 *data = ID_LED_DEFAULT_82573;
1512 break;
1513 default:
1514 if (*data == ID_LED_RESERVED_0000 ||
1515 *data == ID_LED_RESERVED_FFFF)
1516 *data = ID_LED_DEFAULT;
1517 break;
1518 }
1519
1520 return 0;
1521 }
1522
1523 /**
1524 * e1000e_get_laa_state_82571 - Get locally administered address state
1525 * @hw: pointer to the HW structure
1526 *
1527 * Retrieve and return the current locally administered address state.
1528 **/
1529 bool e1000e_get_laa_state_82571(struct e1000_hw *hw)
1530 {
1531 if (hw->mac.type != e1000_82571)
1532 return false;
1533
1534 return hw->dev_spec.e82571.laa_is_present;
1535 }
1536
1537 /**
1538 * e1000e_set_laa_state_82571 - Set locally administered address state
1539 * @hw: pointer to the HW structure
1540 * @state: enable/disable locally administered address
1541 *
1542 * Enable/Disable the current locally administered address state.
1543 **/
1544 void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state)
1545 {
1546 if (hw->mac.type != e1000_82571)
1547 return;
1548
1549 hw->dev_spec.e82571.laa_is_present = state;
1550
1551 /* If workaround is activated... */
1552 if (state)
1553 /*
1554 * Hold a copy of the LAA in RAR[14] This is done so that
1555 * between the time RAR[0] gets clobbered and the time it
1556 * gets fixed, the actual LAA is in one of the RARs and no
1557 * incoming packets directed to this port are dropped.
1558 * Eventually the LAA will be in RAR[0] and RAR[14].
1559 */
1560 e1000e_rar_set(hw, hw->mac.addr, hw->mac.rar_entry_count - 1);
1561 }
1562
1563 /**
1564 * e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1565 * @hw: pointer to the HW structure
1566 *
1567 * Verifies that the EEPROM has completed the update. After updating the
1568 * EEPROM, we need to check bit 15 in work 0x23 for the checksum fix. If
1569 * the checksum fix is not implemented, we need to set the bit and update
1570 * the checksum. Otherwise, if bit 15 is set and the checksum is incorrect,
1571 * we need to return bad checksum.
1572 **/
1573 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1574 {
1575 struct e1000_nvm_info *nvm = &hw->nvm;
1576 s32 ret_val;
1577 u16 data;
1578
1579 if (nvm->type != e1000_nvm_flash_hw)
1580 return 0;
1581
1582 /*
1583 * Check bit 4 of word 10h. If it is 0, firmware is done updating
1584 * 10h-12h. Checksum may need to be fixed.
1585 */
1586 ret_val = e1000_read_nvm(hw, 0x10, 1, &data);
1587 if (ret_val)
1588 return ret_val;
1589
1590 if (!(data & 0x10)) {
1591 /*
1592 * Read 0x23 and check bit 15. This bit is a 1
1593 * when the checksum has already been fixed. If
1594 * the checksum is still wrong and this bit is a
1595 * 1, we need to return bad checksum. Otherwise,
1596 * we need to set this bit to a 1 and update the
1597 * checksum.
1598 */
1599 ret_val = e1000_read_nvm(hw, 0x23, 1, &data);
1600 if (ret_val)
1601 return ret_val;
1602
1603 if (!(data & 0x8000)) {
1604 data |= 0x8000;
1605 ret_val = e1000_write_nvm(hw, 0x23, 1, &data);
1606 if (ret_val)
1607 return ret_val;
1608 ret_val = e1000e_update_nvm_checksum(hw);
1609 }
1610 }
1611
1612 return 0;
1613 }
1614
1615 /**
1616 * e1000_read_mac_addr_82571 - Read device MAC address
1617 * @hw: pointer to the HW structure
1618 **/
1619 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1620 {
1621 s32 ret_val = 0;
1622
1623 if (hw->mac.type == e1000_82571) {
1624 /*
1625 * If there's an alternate MAC address place it in RAR0
1626 * so that it will override the Si installed default perm
1627 * address.
1628 */
1629 ret_val = e1000_check_alt_mac_addr_generic(hw);
1630 if (ret_val)
1631 goto out;
1632 }
1633
1634 ret_val = e1000_read_mac_addr_generic(hw);
1635
1636 out:
1637 return ret_val;
1638 }
1639
1640 /**
1641 * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
1642 * @hw: pointer to the HW structure
1643 *
1644 * In the case of a PHY power down to save power, or to turn off link during a
1645 * driver unload, or wake on lan is not enabled, remove the link.
1646 **/
1647 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1648 {
1649 struct e1000_phy_info *phy = &hw->phy;
1650 struct e1000_mac_info *mac = &hw->mac;
1651
1652 if (!(phy->ops.check_reset_block))
1653 return;
1654
1655 /* If the management interface is not enabled, then power down */
1656 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1657 e1000_power_down_phy_copper(hw);
1658 }
1659
1660 /**
1661 * e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1662 * @hw: pointer to the HW structure
1663 *
1664 * Clears the hardware counters by reading the counter registers.
1665 **/
1666 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1667 {
1668 e1000e_clear_hw_cntrs_base(hw);
1669
1670 er32(PRC64);
1671 er32(PRC127);
1672 er32(PRC255);
1673 er32(PRC511);
1674 er32(PRC1023);
1675 er32(PRC1522);
1676 er32(PTC64);
1677 er32(PTC127);
1678 er32(PTC255);
1679 er32(PTC511);
1680 er32(PTC1023);
1681 er32(PTC1522);
1682
1683 er32(ALGNERRC);
1684 er32(RXERRC);
1685 er32(TNCRS);
1686 er32(CEXTERR);
1687 er32(TSCTC);
1688 er32(TSCTFC);
1689
1690 er32(MGTPRC);
1691 er32(MGTPDC);
1692 er32(MGTPTC);
1693
1694 er32(IAC);
1695 er32(ICRXOC);
1696
1697 er32(ICRXPTC);
1698 er32(ICRXATC);
1699 er32(ICTXPTC);
1700 er32(ICTXATC);
1701 er32(ICTXQEC);
1702 er32(ICTXQMTC);
1703 er32(ICRXDMTC);
1704 }
1705
1706 static struct e1000_mac_operations e82571_mac_ops = {
1707 /* .check_mng_mode: mac type dependent */
1708 /* .check_for_link: media type dependent */
1709 .id_led_init = e1000e_id_led_init,
1710 .cleanup_led = e1000e_cleanup_led_generic,
1711 .clear_hw_cntrs = e1000_clear_hw_cntrs_82571,
1712 .get_bus_info = e1000e_get_bus_info_pcie,
1713 .set_lan_id = e1000_set_lan_id_multi_port_pcie,
1714 /* .get_link_up_info: media type dependent */
1715 /* .led_on: mac type dependent */
1716 .led_off = e1000e_led_off_generic,
1717 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
1718 .write_vfta = e1000_write_vfta_generic,
1719 .clear_vfta = e1000_clear_vfta_82571,
1720 .reset_hw = e1000_reset_hw_82571,
1721 .init_hw = e1000_init_hw_82571,
1722 .setup_link = e1000_setup_link_82571,
1723 /* .setup_physical_interface: media type dependent */
1724 .setup_led = e1000e_setup_led_generic,
1725 .read_mac_addr = e1000_read_mac_addr_82571,
1726 };
1727
1728 static struct e1000_phy_operations e82_phy_ops_igp = {
1729 .acquire = e1000_get_hw_semaphore_82571,
1730 .check_polarity = e1000_check_polarity_igp,
1731 .check_reset_block = e1000e_check_reset_block_generic,
1732 .commit = NULL,
1733 .force_speed_duplex = e1000e_phy_force_speed_duplex_igp,
1734 .get_cfg_done = e1000_get_cfg_done_82571,
1735 .get_cable_length = e1000e_get_cable_length_igp_2,
1736 .get_info = e1000e_get_phy_info_igp,
1737 .read_reg = e1000e_read_phy_reg_igp,
1738 .release = e1000_put_hw_semaphore_82571,
1739 .reset = e1000e_phy_hw_reset_generic,
1740 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
1741 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1742 .write_reg = e1000e_write_phy_reg_igp,
1743 .cfg_on_link_up = NULL,
1744 };
1745
1746 static struct e1000_phy_operations e82_phy_ops_m88 = {
1747 .acquire = e1000_get_hw_semaphore_82571,
1748 .check_polarity = e1000_check_polarity_m88,
1749 .check_reset_block = e1000e_check_reset_block_generic,
1750 .commit = e1000e_phy_sw_reset,
1751 .force_speed_duplex = e1000e_phy_force_speed_duplex_m88,
1752 .get_cfg_done = e1000e_get_cfg_done,
1753 .get_cable_length = e1000e_get_cable_length_m88,
1754 .get_info = e1000e_get_phy_info_m88,
1755 .read_reg = e1000e_read_phy_reg_m88,
1756 .release = e1000_put_hw_semaphore_82571,
1757 .reset = e1000e_phy_hw_reset_generic,
1758 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
1759 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1760 .write_reg = e1000e_write_phy_reg_m88,
1761 .cfg_on_link_up = NULL,
1762 };
1763
1764 static struct e1000_phy_operations e82_phy_ops_bm = {
1765 .acquire = e1000_get_hw_semaphore_82571,
1766 .check_polarity = e1000_check_polarity_m88,
1767 .check_reset_block = e1000e_check_reset_block_generic,
1768 .commit = e1000e_phy_sw_reset,
1769 .force_speed_duplex = e1000e_phy_force_speed_duplex_m88,
1770 .get_cfg_done = e1000e_get_cfg_done,
1771 .get_cable_length = e1000e_get_cable_length_m88,
1772 .get_info = e1000e_get_phy_info_m88,
1773 .read_reg = e1000e_read_phy_reg_bm2,
1774 .release = e1000_put_hw_semaphore_82571,
1775 .reset = e1000e_phy_hw_reset_generic,
1776 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
1777 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1778 .write_reg = e1000e_write_phy_reg_bm2,
1779 .cfg_on_link_up = NULL,
1780 };
1781
1782 static struct e1000_nvm_operations e82571_nvm_ops = {
1783 .acquire = e1000_acquire_nvm_82571,
1784 .read = e1000e_read_nvm_eerd,
1785 .release = e1000_release_nvm_82571,
1786 .update = e1000_update_nvm_checksum_82571,
1787 .valid_led_default = e1000_valid_led_default_82571,
1788 .validate = e1000_validate_nvm_checksum_82571,
1789 .write = e1000_write_nvm_82571,
1790 };
1791
1792 struct e1000_info e1000_82571_info = {
1793 .mac = e1000_82571,
1794 .flags = FLAG_HAS_HW_VLAN_FILTER
1795 | FLAG_HAS_JUMBO_FRAMES
1796 | FLAG_HAS_WOL
1797 | FLAG_APME_IN_CTRL3
1798 | FLAG_RX_CSUM_ENABLED
1799 | FLAG_HAS_CTRLEXT_ON_LOAD
1800 | FLAG_HAS_SMART_POWER_DOWN
1801 | FLAG_RESET_OVERWRITES_LAA /* errata */
1802 | FLAG_TARC_SPEED_MODE_BIT /* errata */
1803 | FLAG_APME_CHECK_PORT_B,
1804 .flags2 = FLAG2_DISABLE_ASPM_L1, /* errata 13 */
1805 .pba = 38,
1806 .max_hw_frame_size = DEFAULT_JUMBO,
1807 .get_variants = e1000_get_variants_82571,
1808 .mac_ops = &e82571_mac_ops,
1809 .phy_ops = &e82_phy_ops_igp,
1810 .nvm_ops = &e82571_nvm_ops,
1811 };
1812
1813 struct e1000_info e1000_82572_info = {
1814 .mac = e1000_82572,
1815 .flags = FLAG_HAS_HW_VLAN_FILTER
1816 | FLAG_HAS_JUMBO_FRAMES
1817 | FLAG_HAS_WOL
1818 | FLAG_APME_IN_CTRL3
1819 | FLAG_RX_CSUM_ENABLED
1820 | FLAG_HAS_CTRLEXT_ON_LOAD
1821 | FLAG_TARC_SPEED_MODE_BIT, /* errata */
1822 .flags2 = FLAG2_DISABLE_ASPM_L1, /* errata 13 */
1823 .pba = 38,
1824 .max_hw_frame_size = DEFAULT_JUMBO,
1825 .get_variants = e1000_get_variants_82571,
1826 .mac_ops = &e82571_mac_ops,
1827 .phy_ops = &e82_phy_ops_igp,
1828 .nvm_ops = &e82571_nvm_ops,
1829 };
1830
1831 struct e1000_info e1000_82573_info = {
1832 .mac = e1000_82573,
1833 .flags = FLAG_HAS_HW_VLAN_FILTER
1834 | FLAG_HAS_WOL
1835 | FLAG_APME_IN_CTRL3
1836 | FLAG_RX_CSUM_ENABLED
1837 | FLAG_HAS_SMART_POWER_DOWN
1838 | FLAG_HAS_AMT
1839 | FLAG_HAS_SWSM_ON_LOAD,
1840 .flags2 = FLAG2_DISABLE_ASPM_L1,
1841 .pba = 20,
1842 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
1843 .get_variants = e1000_get_variants_82571,
1844 .mac_ops = &e82571_mac_ops,
1845 .phy_ops = &e82_phy_ops_m88,
1846 .nvm_ops = &e82571_nvm_ops,
1847 };
1848
1849 struct e1000_info e1000_82574_info = {
1850 .mac = e1000_82574,
1851 .flags = FLAG_HAS_HW_VLAN_FILTER
1852 | FLAG_HAS_MSIX
1853 | FLAG_HAS_JUMBO_FRAMES
1854 | FLAG_HAS_WOL
1855 | FLAG_APME_IN_CTRL3
1856 | FLAG_RX_CSUM_ENABLED
1857 | FLAG_HAS_SMART_POWER_DOWN
1858 | FLAG_HAS_AMT
1859 | FLAG_HAS_CTRLEXT_ON_LOAD,
1860 .pba = 36,
1861 .max_hw_frame_size = DEFAULT_JUMBO,
1862 .get_variants = e1000_get_variants_82571,
1863 .mac_ops = &e82571_mac_ops,
1864 .phy_ops = &e82_phy_ops_bm,
1865 .nvm_ops = &e82571_nvm_ops,
1866 };
1867
1868 struct e1000_info e1000_82583_info = {
1869 .mac = e1000_82583,
1870 .flags = FLAG_HAS_HW_VLAN_FILTER
1871 | FLAG_HAS_WOL
1872 | FLAG_APME_IN_CTRL3
1873 | FLAG_RX_CSUM_ENABLED
1874 | FLAG_HAS_SMART_POWER_DOWN
1875 | FLAG_HAS_AMT
1876 | FLAG_HAS_CTRLEXT_ON_LOAD,
1877 .pba = 36,
1878 .max_hw_frame_size = ETH_FRAME_LEN + ETH_FCS_LEN,
1879 .get_variants = e1000_get_variants_82571,
1880 .mac_ops = &e82571_mac_ops,
1881 .phy_ops = &e82_phy_ops_bm,
1882 .nvm_ops = &e82571_nvm_ops,
1883 };
1884
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree