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davinci: Add NAND flash support for DA850/OMAP-L138
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / arm / mach-davinci / da850.c
blobdb4209413450959df5c06e1d057fc455c4b9d1f5
1 /*
2 * TI DA850/OMAP-L138 chip specific setup
3 *
4 * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * Derived from: arch/arm/mach-davinci/da830.c
7 * Original Copyrights follow:
8 *
9 * 2009 (c) MontaVista Software, Inc. This file is licensed under
10 * the terms of the GNU General Public License version 2. This program
11 * is licensed "as is" without any warranty of any kind, whether express
12 * or implied.
13 */
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/clk.h>
17 #include <linux/platform_device.h>
18
19 #include <asm/mach/map.h>
20
21 #include <mach/clock.h>
22 #include <mach/psc.h>
23 #include <mach/mux.h>
24 #include <mach/irqs.h>
25 #include <mach/cputype.h>
26 #include <mach/common.h>
27 #include <mach/time.h>
28 #include <mach/da8xx.h>
29
30 #include "clock.h"
31 #include "mux.h"
32
33 #define DA850_PLL1_BASE 0x01e1a000
34 #define DA850_TIMER64P2_BASE 0x01f0c000
35 #define DA850_TIMER64P3_BASE 0x01f0d000
36
37 #define DA850_REF_FREQ 24000000
38
39 static struct pll_data pll0_data = {
40 .num = 1,
41 .phys_base = DA8XX_PLL0_BASE,
42 .flags = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
43 };
44
45 static struct clk ref_clk = {
46 .name = "ref_clk",
47 .rate = DA850_REF_FREQ,
48 };
49
50 static struct clk pll0_clk = {
51 .name = "pll0",
52 .parent = &ref_clk,
53 .pll_data = &pll0_data,
54 .flags = CLK_PLL,
55 };
56
57 static struct clk pll0_aux_clk = {
58 .name = "pll0_aux_clk",
59 .parent = &pll0_clk,
60 .flags = CLK_PLL | PRE_PLL,
61 };
62
63 static struct clk pll0_sysclk2 = {
64 .name = "pll0_sysclk2",
65 .parent = &pll0_clk,
66 .flags = CLK_PLL,
67 .div_reg = PLLDIV2,
68 };
69
70 static struct clk pll0_sysclk3 = {
71 .name = "pll0_sysclk3",
72 .parent = &pll0_clk,
73 .flags = CLK_PLL,
74 .div_reg = PLLDIV3,
75 };
76
77 static struct clk pll0_sysclk4 = {
78 .name = "pll0_sysclk4",
79 .parent = &pll0_clk,
80 .flags = CLK_PLL,
81 .div_reg = PLLDIV4,
82 };
83
84 static struct clk pll0_sysclk5 = {
85 .name = "pll0_sysclk5",
86 .parent = &pll0_clk,
87 .flags = CLK_PLL,
88 .div_reg = PLLDIV5,
89 };
90
91 static struct clk pll0_sysclk6 = {
92 .name = "pll0_sysclk6",
93 .parent = &pll0_clk,
94 .flags = CLK_PLL,
95 .div_reg = PLLDIV6,
96 };
97
98 static struct clk pll0_sysclk7 = {
99 .name = "pll0_sysclk7",
100 .parent = &pll0_clk,
101 .flags = CLK_PLL,
102 .div_reg = PLLDIV7,
103 };
104
105 static struct pll_data pll1_data = {
106 .num = 2,
107 .phys_base = DA850_PLL1_BASE,
108 .flags = PLL_HAS_POSTDIV,
109 };
110
111 static struct clk pll1_clk = {
112 .name = "pll1",
113 .parent = &ref_clk,
114 .pll_data = &pll1_data,
115 .flags = CLK_PLL,
116 };
117
118 static struct clk pll1_aux_clk = {
119 .name = "pll1_aux_clk",
120 .parent = &pll1_clk,
121 .flags = CLK_PLL | PRE_PLL,
122 };
123
124 static struct clk pll1_sysclk2 = {
125 .name = "pll1_sysclk2",
126 .parent = &pll1_clk,
127 .flags = CLK_PLL,
128 .div_reg = PLLDIV2,
129 };
130
131 static struct clk pll1_sysclk3 = {
132 .name = "pll1_sysclk3",
133 .parent = &pll1_clk,
134 .flags = CLK_PLL,
135 .div_reg = PLLDIV3,
136 };
137
138 static struct clk pll1_sysclk4 = {
139 .name = "pll1_sysclk4",
140 .parent = &pll1_clk,
141 .flags = CLK_PLL,
142 .div_reg = PLLDIV4,
143 };
144
145 static struct clk pll1_sysclk5 = {
146 .name = "pll1_sysclk5",
147 .parent = &pll1_clk,
148 .flags = CLK_PLL,
149 .div_reg = PLLDIV5,
150 };
151
152 static struct clk pll1_sysclk6 = {
153 .name = "pll0_sysclk6",
154 .parent = &pll0_clk,
155 .flags = CLK_PLL,
156 .div_reg = PLLDIV6,
157 };
158
159 static struct clk pll1_sysclk7 = {
160 .name = "pll1_sysclk7",
161 .parent = &pll1_clk,
162 .flags = CLK_PLL,
163 .div_reg = PLLDIV7,
164 };
165
166 static struct clk i2c0_clk = {
167 .name = "i2c0",
168 .parent = &pll0_aux_clk,
169 };
170
171 static struct clk timerp64_0_clk = {
172 .name = "timer0",
173 .parent = &pll0_aux_clk,
174 };
175
176 static struct clk timerp64_1_clk = {
177 .name = "timer1",
178 .parent = &pll0_aux_clk,
179 };
180
181 static struct clk arm_rom_clk = {
182 .name = "arm_rom",
183 .parent = &pll0_sysclk2,
184 .lpsc = DA8XX_LPSC0_ARM_RAM_ROM,
185 .flags = ALWAYS_ENABLED,
186 };
187
188 static struct clk tpcc0_clk = {
189 .name = "tpcc0",
190 .parent = &pll0_sysclk2,
191 .lpsc = DA8XX_LPSC0_TPCC,
192 .flags = ALWAYS_ENABLED | CLK_PSC,
193 };
194
195 static struct clk tptc0_clk = {
196 .name = "tptc0",
197 .parent = &pll0_sysclk2,
198 .lpsc = DA8XX_LPSC0_TPTC0,
199 .flags = ALWAYS_ENABLED,
200 };
201
202 static struct clk tptc1_clk = {
203 .name = "tptc1",
204 .parent = &pll0_sysclk2,
205 .lpsc = DA8XX_LPSC0_TPTC1,
206 .flags = ALWAYS_ENABLED,
207 };
208
209 static struct clk tpcc1_clk = {
210 .name = "tpcc1",
211 .parent = &pll0_sysclk2,
212 .lpsc = DA850_LPSC1_TPCC1,
213 .flags = CLK_PSC | ALWAYS_ENABLED,
214 .psc_ctlr = 1,
215 };
216
217 static struct clk tptc2_clk = {
218 .name = "tptc2",
219 .parent = &pll0_sysclk2,
220 .lpsc = DA850_LPSC1_TPTC2,
221 .flags = ALWAYS_ENABLED,
222 .psc_ctlr = 1,
223 };
224
225 static struct clk uart0_clk = {
226 .name = "uart0",
227 .parent = &pll0_sysclk2,
228 .lpsc = DA8XX_LPSC0_UART0,
229 };
230
231 static struct clk uart1_clk = {
232 .name = "uart1",
233 .parent = &pll0_sysclk2,
234 .lpsc = DA8XX_LPSC1_UART1,
235 .psc_ctlr = 1,
236 };
237
238 static struct clk uart2_clk = {
239 .name = "uart2",
240 .parent = &pll0_sysclk2,
241 .lpsc = DA8XX_LPSC1_UART2,
242 .psc_ctlr = 1,
243 };
244
245 static struct clk aintc_clk = {
246 .name = "aintc",
247 .parent = &pll0_sysclk4,
248 .lpsc = DA8XX_LPSC0_AINTC,
249 .flags = ALWAYS_ENABLED,
250 };
251
252 static struct clk gpio_clk = {
253 .name = "gpio",
254 .parent = &pll0_sysclk4,
255 .lpsc = DA8XX_LPSC1_GPIO,
256 .psc_ctlr = 1,
257 };
258
259 static struct clk i2c1_clk = {
260 .name = "i2c1",
261 .parent = &pll0_sysclk4,
262 .lpsc = DA8XX_LPSC1_I2C,
263 .psc_ctlr = 1,
264 };
265
266 static struct clk emif3_clk = {
267 .name = "emif3",
268 .parent = &pll0_sysclk5,
269 .lpsc = DA8XX_LPSC1_EMIF3C,
270 .flags = ALWAYS_ENABLED,
271 .psc_ctlr = 1,
272 };
273
274 static struct clk arm_clk = {
275 .name = "arm",
276 .parent = &pll0_sysclk6,
277 .lpsc = DA8XX_LPSC0_ARM,
278 .flags = ALWAYS_ENABLED,
279 };
280
281 static struct clk rmii_clk = {
282 .name = "rmii",
283 .parent = &pll0_sysclk7,
284 };
285
286 static struct clk emac_clk = {
287 .name = "emac",
288 .parent = &pll0_sysclk4,
289 .lpsc = DA8XX_LPSC1_CPGMAC,
290 .psc_ctlr = 1,
291 };
292
293 static struct clk mcasp_clk = {
294 .name = "mcasp",
295 .parent = &pll0_sysclk2,
296 .lpsc = DA8XX_LPSC1_McASP0,
297 .psc_ctlr = 1,
298 };
299
300 static struct clk lcdc_clk = {
301 .name = "lcdc",
302 .parent = &pll0_sysclk2,
303 .lpsc = DA8XX_LPSC1_LCDC,
304 .psc_ctlr = 1,
305 };
306
307 static struct clk mmcsd_clk = {
308 .name = "mmcsd",
309 .parent = &pll0_sysclk2,
310 .lpsc = DA8XX_LPSC0_MMC_SD,
311 };
312
313 static struct clk aemif_clk = {
314 .name = "aemif",
315 .parent = &pll0_sysclk3,
316 .lpsc = DA8XX_LPSC0_EMIF25,
317 .flags = ALWAYS_ENABLED,
318 };
319
320 static struct davinci_clk da850_clks[] = {
321 CLK(NULL, "ref", &ref_clk),
322 CLK(NULL, "pll0", &pll0_clk),
323 CLK(NULL, "pll0_aux", &pll0_aux_clk),
324 CLK(NULL, "pll0_sysclk2", &pll0_sysclk2),
325 CLK(NULL, "pll0_sysclk3", &pll0_sysclk3),
326 CLK(NULL, "pll0_sysclk4", &pll0_sysclk4),
327 CLK(NULL, "pll0_sysclk5", &pll0_sysclk5),
328 CLK(NULL, "pll0_sysclk6", &pll0_sysclk6),
329 CLK(NULL, "pll0_sysclk7", &pll0_sysclk7),
330 CLK(NULL, "pll1", &pll1_clk),
331 CLK(NULL, "pll1_aux", &pll1_aux_clk),
332 CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
333 CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
334 CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
335 CLK(NULL, "pll1_sysclk5", &pll1_sysclk5),
336 CLK(NULL, "pll1_sysclk6", &pll1_sysclk6),
337 CLK(NULL, "pll1_sysclk7", &pll1_sysclk7),
338 CLK("i2c_davinci.1", NULL, &i2c0_clk),
339 CLK(NULL, "timer0", &timerp64_0_clk),
340 CLK("watchdog", NULL, &timerp64_1_clk),
341 CLK(NULL, "arm_rom", &arm_rom_clk),
342 CLK(NULL, "tpcc0", &tpcc0_clk),
343 CLK(NULL, "tptc0", &tptc0_clk),
344 CLK(NULL, "tptc1", &tptc1_clk),
345 CLK(NULL, "tpcc1", &tpcc1_clk),
346 CLK(NULL, "tptc2", &tptc2_clk),
347 CLK(NULL, "uart0", &uart0_clk),
348 CLK(NULL, "uart1", &uart1_clk),
349 CLK(NULL, "uart2", &uart2_clk),
350 CLK(NULL, "aintc", &aintc_clk),
351 CLK(NULL, "gpio", &gpio_clk),
352 CLK("i2c_davinci.2", NULL, &i2c1_clk),
353 CLK(NULL, "emif3", &emif3_clk),
354 CLK(NULL, "arm", &arm_clk),
355 CLK(NULL, "rmii", &rmii_clk),
356 CLK("davinci_emac.1", NULL, &emac_clk),
357 CLK("davinci-mcasp.0", NULL, &mcasp_clk),
358 CLK("da8xx_lcdc.0", NULL, &lcdc_clk),
359 CLK("davinci_mmc.0", NULL, &mmcsd_clk),
360 CLK(NULL, "aemif", &aemif_clk),
361 CLK(NULL, NULL, NULL),
362 };
363
364 /*
365 * Device specific mux setup
366 *
367 * soc description mux mode mode mux dbg
368 * reg offset mask mode
369 */
370 static const struct mux_config da850_pins[] = {
371 #ifdef CONFIG_DAVINCI_MUX
372 /* UART0 function */
373 MUX_CFG(DA850, NUART0_CTS, 3, 24, 15, 2, false)
374 MUX_CFG(DA850, NUART0_RTS, 3, 28, 15, 2, false)
375 MUX_CFG(DA850, UART0_RXD, 3, 16, 15, 2, false)
376 MUX_CFG(DA850, UART0_TXD, 3, 20, 15, 2, false)
377 /* UART1 function */
378 MUX_CFG(DA850, UART1_RXD, 4, 24, 15, 2, false)
379 MUX_CFG(DA850, UART1_TXD, 4, 28, 15, 2, false)
380 /* UART2 function */
381 MUX_CFG(DA850, UART2_RXD, 4, 16, 15, 2, false)
382 MUX_CFG(DA850, UART2_TXD, 4, 20, 15, 2, false)
383 /* I2C1 function */
384 MUX_CFG(DA850, I2C1_SCL, 4, 16, 15, 4, false)
385 MUX_CFG(DA850, I2C1_SDA, 4, 20, 15, 4, false)
386 /* I2C0 function */
387 MUX_CFG(DA850, I2C0_SDA, 4, 12, 15, 2, false)
388 MUX_CFG(DA850, I2C0_SCL, 4, 8, 15, 2, false)
389 /* EMAC function */
390 MUX_CFG(DA850, MII_TXEN, 2, 4, 15, 8, false)
391 MUX_CFG(DA850, MII_TXCLK, 2, 8, 15, 8, false)
392 MUX_CFG(DA850, MII_COL, 2, 12, 15, 8, false)
393 MUX_CFG(DA850, MII_TXD_3, 2, 16, 15, 8, false)
394 MUX_CFG(DA850, MII_TXD_2, 2, 20, 15, 8, false)
395 MUX_CFG(DA850, MII_TXD_1, 2, 24, 15, 8, false)
396 MUX_CFG(DA850, MII_TXD_0, 2, 28, 15, 8, false)
397 MUX_CFG(DA850, MII_RXCLK, 3, 0, 15, 8, false)
398 MUX_CFG(DA850, MII_RXDV, 3, 4, 15, 8, false)
399 MUX_CFG(DA850, MII_RXER, 3, 8, 15, 8, false)
400 MUX_CFG(DA850, MII_CRS, 3, 12, 15, 8, false)
401 MUX_CFG(DA850, MII_RXD_3, 3, 16, 15, 8, false)
402 MUX_CFG(DA850, MII_RXD_2, 3, 20, 15, 8, false)
403 MUX_CFG(DA850, MII_RXD_1, 3, 24, 15, 8, false)
404 MUX_CFG(DA850, MII_RXD_0, 3, 28, 15, 8, false)
405 MUX_CFG(DA850, MDIO_CLK, 4, 0, 15, 8, false)
406 MUX_CFG(DA850, MDIO_D, 4, 4, 15, 8, false)
407 /* McASP function */
408 MUX_CFG(DA850, ACLKR, 0, 0, 15, 1, false)
409 MUX_CFG(DA850, ACLKX, 0, 4, 15, 1, false)
410 MUX_CFG(DA850, AFSR, 0, 8, 15, 1, false)
411 MUX_CFG(DA850, AFSX, 0, 12, 15, 1, false)
412 MUX_CFG(DA850, AHCLKR, 0, 16, 15, 1, false)
413 MUX_CFG(DA850, AHCLKX, 0, 20, 15, 1, false)
414 MUX_CFG(DA850, AMUTE, 0, 24, 15, 1, false)
415 MUX_CFG(DA850, AXR_15, 1, 0, 15, 1, false)
416 MUX_CFG(DA850, AXR_14, 1, 4, 15, 1, false)
417 MUX_CFG(DA850, AXR_13, 1, 8, 15, 1, false)
418 MUX_CFG(DA850, AXR_12, 1, 12, 15, 1, false)
419 MUX_CFG(DA850, AXR_11, 1, 16, 15, 1, false)
420 MUX_CFG(DA850, AXR_10, 1, 20, 15, 1, false)
421 MUX_CFG(DA850, AXR_9, 1, 24, 15, 1, false)
422 MUX_CFG(DA850, AXR_8, 1, 28, 15, 1, false)
423 MUX_CFG(DA850, AXR_7, 2, 0, 15, 1, false)
424 MUX_CFG(DA850, AXR_6, 2, 4, 15, 1, false)
425 MUX_CFG(DA850, AXR_5, 2, 8, 15, 1, false)
426 MUX_CFG(DA850, AXR_4, 2, 12, 15, 1, false)
427 MUX_CFG(DA850, AXR_3, 2, 16, 15, 1, false)
428 MUX_CFG(DA850, AXR_2, 2, 20, 15, 1, false)
429 MUX_CFG(DA850, AXR_1, 2, 24, 15, 1, false)
430 MUX_CFG(DA850, AXR_0, 2, 28, 15, 1, false)
431 /* LCD function */
432 MUX_CFG(DA850, LCD_D_7, 16, 8, 15, 2, false)
433 MUX_CFG(DA850, LCD_D_6, 16, 12, 15, 2, false)
434 MUX_CFG(DA850, LCD_D_5, 16, 16, 15, 2, false)
435 MUX_CFG(DA850, LCD_D_4, 16, 20, 15, 2, false)
436 MUX_CFG(DA850, LCD_D_3, 16, 24, 15, 2, false)
437 MUX_CFG(DA850, LCD_D_2, 16, 28, 15, 2, false)
438 MUX_CFG(DA850, LCD_D_1, 17, 0, 15, 2, false)
439 MUX_CFG(DA850, LCD_D_0, 17, 4, 15, 2, false)
440 MUX_CFG(DA850, LCD_D_15, 17, 8, 15, 2, false)
441 MUX_CFG(DA850, LCD_D_14, 17, 12, 15, 2, false)
442 MUX_CFG(DA850, LCD_D_13, 17, 16, 15, 2, false)
443 MUX_CFG(DA850, LCD_D_12, 17, 20, 15, 2, false)
444 MUX_CFG(DA850, LCD_D_11, 17, 24, 15, 2, false)
445 MUX_CFG(DA850, LCD_D_10, 17, 28, 15, 2, false)
446 MUX_CFG(DA850, LCD_D_9, 18, 0, 15, 2, false)
447 MUX_CFG(DA850, LCD_D_8, 18, 4, 15, 2, false)
448 MUX_CFG(DA850, LCD_PCLK, 18, 24, 15, 2, false)
449 MUX_CFG(DA850, LCD_HSYNC, 19, 0, 15, 2, false)
450 MUX_CFG(DA850, LCD_VSYNC, 19, 4, 15, 2, false)
451 MUX_CFG(DA850, NLCD_AC_ENB_CS, 19, 24, 15, 2, false)
452 /* MMC/SD0 function */
453 MUX_CFG(DA850, MMCSD0_DAT_0, 10, 8, 15, 2, false)
454 MUX_CFG(DA850, MMCSD0_DAT_1, 10, 12, 15, 2, false)
455 MUX_CFG(DA850, MMCSD0_DAT_2, 10, 16, 15, 2, false)
456 MUX_CFG(DA850, MMCSD0_DAT_3, 10, 20, 15, 2, false)
457 MUX_CFG(DA850, MMCSD0_CLK, 10, 0, 15, 2, false)
458 MUX_CFG(DA850, MMCSD0_CMD, 10, 4, 15, 2, false)
459 /* EMIF2.5/EMIFA function */
460 MUX_CFG(DA850, EMA_D_7, 9, 0, 15, 1, false)
461 MUX_CFG(DA850, EMA_D_6, 9, 4, 15, 1, false)
462 MUX_CFG(DA850, EMA_D_5, 9, 8, 15, 1, false)
463 MUX_CFG(DA850, EMA_D_4, 9, 12, 15, 1, false)
464 MUX_CFG(DA850, EMA_D_3, 9, 16, 15, 1, false)
465 MUX_CFG(DA850, EMA_D_2, 9, 20, 15, 1, false)
466 MUX_CFG(DA850, EMA_D_1, 9, 24, 15, 1, false)
467 MUX_CFG(DA850, EMA_D_0, 9, 28, 15, 1, false)
468 MUX_CFG(DA850, EMA_A_1, 12, 24, 15, 1, false)
469 MUX_CFG(DA850, EMA_A_2, 12, 20, 15, 1, false)
470 MUX_CFG(DA850, NEMA_CS_3, 7, 4, 15, 1, false)
471 MUX_CFG(DA850, NEMA_CS_4, 7, 8, 15, 1, false)
472 MUX_CFG(DA850, NEMA_WE, 7, 16, 15, 1, false)
473 MUX_CFG(DA850, NEMA_OE, 7, 20, 15, 1, false)
474 /* GPIO function */
475 MUX_CFG(DA850, GPIO2_15, 5, 0, 15, 8, false)
476 MUX_CFG(DA850, GPIO8_10, 18, 28, 15, 8, false)
477 MUX_CFG(DA850, GPIO4_0, 10, 28, 15, 8, false)
478 MUX_CFG(DA850, GPIO4_1, 10, 24, 15, 8, false)
479 #endif
480 };
481
482 const short da850_uart0_pins[] __initdata = {
483 DA850_NUART0_CTS, DA850_NUART0_RTS, DA850_UART0_RXD, DA850_UART0_TXD,
484 -1
485 };
486
487 const short da850_uart1_pins[] __initdata = {
488 DA850_UART1_RXD, DA850_UART1_TXD,
489 -1
490 };
491
492 const short da850_uart2_pins[] __initdata = {
493 DA850_UART2_RXD, DA850_UART2_TXD,
494 -1
495 };
496
497 const short da850_i2c0_pins[] __initdata = {
498 DA850_I2C0_SDA, DA850_I2C0_SCL,
499 -1
500 };
501
502 const short da850_i2c1_pins[] __initdata = {
503 DA850_I2C1_SCL, DA850_I2C1_SDA,
504 -1
505 };
506
507 const short da850_cpgmac_pins[] __initdata = {
508 DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3,
509 DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER,
510 DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3,
511 DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK,
512 DA850_MDIO_D,
513 -1
514 };
515
516 const short da850_mcasp_pins[] __initdata = {
517 DA850_AHCLKX, DA850_ACLKX, DA850_AFSX,
518 DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, DA850_AMUTE,
519 DA850_AXR_11, DA850_AXR_12,
520 -1
521 };
522
523 const short da850_lcdcntl_pins[] __initdata = {
524 DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3, DA850_LCD_D_4,
525 DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7, DA850_LCD_D_8,
526 DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11, DA850_LCD_D_12,
527 DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15, DA850_LCD_PCLK,
528 DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS, DA850_GPIO2_15,
529 DA850_GPIO8_10,
530 -1
531 };
532
533 const short da850_mmcsd0_pins[] __initdata = {
534 DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2,
535 DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD,
536 DA850_GPIO4_0, DA850_GPIO4_1,
537 -1
538 };
539
540 const short da850_nand_pins[] __initdata = {
541 DA850_EMA_D_7, DA850_EMA_D_6, DA850_EMA_D_5, DA850_EMA_D_4,
542 DA850_EMA_D_3, DA850_EMA_D_2, DA850_EMA_D_1, DA850_EMA_D_0,
543 DA850_EMA_A_1, DA850_EMA_A_2, DA850_NEMA_CS_3, DA850_NEMA_CS_4,
544 DA850_NEMA_WE, DA850_NEMA_OE,
545 -1
546 };
547
548 /* FIQ are pri 0-1; otherwise 2-7, with 7 lowest priority */
549 static u8 da850_default_priorities[DA850_N_CP_INTC_IRQ] = {
550 [IRQ_DA8XX_COMMTX] = 7,
551 [IRQ_DA8XX_COMMRX] = 7,
552 [IRQ_DA8XX_NINT] = 7,
553 [IRQ_DA8XX_EVTOUT0] = 7,
554 [IRQ_DA8XX_EVTOUT1] = 7,
555 [IRQ_DA8XX_EVTOUT2] = 7,
556 [IRQ_DA8XX_EVTOUT3] = 7,
557 [IRQ_DA8XX_EVTOUT4] = 7,
558 [IRQ_DA8XX_EVTOUT5] = 7,
559 [IRQ_DA8XX_EVTOUT6] = 7,
560 [IRQ_DA8XX_EVTOUT6] = 7,
561 [IRQ_DA8XX_EVTOUT7] = 7,
562 [IRQ_DA8XX_CCINT0] = 7,
563 [IRQ_DA8XX_CCERRINT] = 7,
564 [IRQ_DA8XX_TCERRINT0] = 7,
565 [IRQ_DA8XX_AEMIFINT] = 7,
566 [IRQ_DA8XX_I2CINT0] = 7,
567 [IRQ_DA8XX_MMCSDINT0] = 7,
568 [IRQ_DA8XX_MMCSDINT1] = 7,
569 [IRQ_DA8XX_ALLINT0] = 7,
570 [IRQ_DA8XX_RTC] = 7,
571 [IRQ_DA8XX_SPINT0] = 7,
572 [IRQ_DA8XX_TINT12_0] = 7,
573 [IRQ_DA8XX_TINT34_0] = 7,
574 [IRQ_DA8XX_TINT12_1] = 7,
575 [IRQ_DA8XX_TINT34_1] = 7,
576 [IRQ_DA8XX_UARTINT0] = 7,
577 [IRQ_DA8XX_KEYMGRINT] = 7,
578 [IRQ_DA8XX_SECINT] = 7,
579 [IRQ_DA8XX_SECKEYERR] = 7,
580 [IRQ_DA850_MPUADDRERR0] = 7,
581 [IRQ_DA850_MPUPROTERR0] = 7,
582 [IRQ_DA850_IOPUADDRERR0] = 7,
583 [IRQ_DA850_IOPUPROTERR0] = 7,
584 [IRQ_DA850_IOPUADDRERR1] = 7,
585 [IRQ_DA850_IOPUPROTERR1] = 7,
586 [IRQ_DA850_IOPUADDRERR2] = 7,
587 [IRQ_DA850_IOPUPROTERR2] = 7,
588 [IRQ_DA850_BOOTCFG_ADDR_ERR] = 7,
589 [IRQ_DA850_BOOTCFG_PROT_ERR] = 7,
590 [IRQ_DA850_MPUADDRERR1] = 7,
591 [IRQ_DA850_MPUPROTERR1] = 7,
592 [IRQ_DA850_IOPUADDRERR3] = 7,
593 [IRQ_DA850_IOPUPROTERR3] = 7,
594 [IRQ_DA850_IOPUADDRERR4] = 7,
595 [IRQ_DA850_IOPUPROTERR4] = 7,
596 [IRQ_DA850_IOPUADDRERR5] = 7,
597 [IRQ_DA850_IOPUPROTERR5] = 7,
598 [IRQ_DA850_MIOPU_BOOTCFG_ERR] = 7,
599 [IRQ_DA8XX_CHIPINT0] = 7,
600 [IRQ_DA8XX_CHIPINT1] = 7,
601 [IRQ_DA8XX_CHIPINT2] = 7,
602 [IRQ_DA8XX_CHIPINT3] = 7,
603 [IRQ_DA8XX_TCERRINT1] = 7,
604 [IRQ_DA8XX_C0_RX_THRESH_PULSE] = 7,
605 [IRQ_DA8XX_C0_RX_PULSE] = 7,
606 [IRQ_DA8XX_C0_TX_PULSE] = 7,
607 [IRQ_DA8XX_C0_MISC_PULSE] = 7,
608 [IRQ_DA8XX_C1_RX_THRESH_PULSE] = 7,
609 [IRQ_DA8XX_C1_RX_PULSE] = 7,
610 [IRQ_DA8XX_C1_TX_PULSE] = 7,
611 [IRQ_DA8XX_C1_MISC_PULSE] = 7,
612 [IRQ_DA8XX_MEMERR] = 7,
613 [IRQ_DA8XX_GPIO0] = 7,
614 [IRQ_DA8XX_GPIO1] = 7,
615 [IRQ_DA8XX_GPIO2] = 7,
616 [IRQ_DA8XX_GPIO3] = 7,
617 [IRQ_DA8XX_GPIO4] = 7,
618 [IRQ_DA8XX_GPIO5] = 7,
619 [IRQ_DA8XX_GPIO6] = 7,
620 [IRQ_DA8XX_GPIO7] = 7,
621 [IRQ_DA8XX_GPIO8] = 7,
622 [IRQ_DA8XX_I2CINT1] = 7,
623 [IRQ_DA8XX_LCDINT] = 7,
624 [IRQ_DA8XX_UARTINT1] = 7,
625 [IRQ_DA8XX_MCASPINT] = 7,
626 [IRQ_DA8XX_ALLINT1] = 7,
627 [IRQ_DA8XX_SPINT1] = 7,
628 [IRQ_DA8XX_UHPI_INT1] = 7,
629 [IRQ_DA8XX_USB_INT] = 7,
630 [IRQ_DA8XX_IRQN] = 7,
631 [IRQ_DA8XX_RWAKEUP] = 7,
632 [IRQ_DA8XX_UARTINT2] = 7,
633 [IRQ_DA8XX_DFTSSINT] = 7,
634 [IRQ_DA8XX_EHRPWM0] = 7,
635 [IRQ_DA8XX_EHRPWM0TZ] = 7,
636 [IRQ_DA8XX_EHRPWM1] = 7,
637 [IRQ_DA8XX_EHRPWM1TZ] = 7,
638 [IRQ_DA850_SATAINT] = 7,
639 [IRQ_DA850_TINT12_2] = 7,
640 [IRQ_DA850_TINT34_2] = 7,
641 [IRQ_DA850_TINTALL_2] = 7,
642 [IRQ_DA8XX_ECAP0] = 7,
643 [IRQ_DA8XX_ECAP1] = 7,
644 [IRQ_DA8XX_ECAP2] = 7,
645 [IRQ_DA850_MMCSDINT0_1] = 7,
646 [IRQ_DA850_MMCSDINT1_1] = 7,
647 [IRQ_DA850_T12CMPINT0_2] = 7,
648 [IRQ_DA850_T12CMPINT1_2] = 7,
649 [IRQ_DA850_T12CMPINT2_2] = 7,
650 [IRQ_DA850_T12CMPINT3_2] = 7,
651 [IRQ_DA850_T12CMPINT4_2] = 7,
652 [IRQ_DA850_T12CMPINT5_2] = 7,
653 [IRQ_DA850_T12CMPINT6_2] = 7,
654 [IRQ_DA850_T12CMPINT7_2] = 7,
655 [IRQ_DA850_T12CMPINT0_3] = 7,
656 [IRQ_DA850_T12CMPINT1_3] = 7,
657 [IRQ_DA850_T12CMPINT2_3] = 7,
658 [IRQ_DA850_T12CMPINT3_3] = 7,
659 [IRQ_DA850_T12CMPINT4_3] = 7,
660 [IRQ_DA850_T12CMPINT5_3] = 7,
661 [IRQ_DA850_T12CMPINT6_3] = 7,
662 [IRQ_DA850_T12CMPINT7_3] = 7,
663 [IRQ_DA850_RPIINT] = 7,
664 [IRQ_DA850_VPIFINT] = 7,
665 [IRQ_DA850_CCINT1] = 7,
666 [IRQ_DA850_CCERRINT1] = 7,
667 [IRQ_DA850_TCERRINT2] = 7,
668 [IRQ_DA850_TINT12_3] = 7,
669 [IRQ_DA850_TINT34_3] = 7,
670 [IRQ_DA850_TINTALL_3] = 7,
671 [IRQ_DA850_MCBSP0RINT] = 7,
672 [IRQ_DA850_MCBSP0XINT] = 7,
673 [IRQ_DA850_MCBSP1RINT] = 7,
674 [IRQ_DA850_MCBSP1XINT] = 7,
675 [IRQ_DA8XX_ARMCLKSTOPREQ] = 7,
676 };
677
678 static struct map_desc da850_io_desc[] = {
679 {
680 .virtual = IO_VIRT,
681 .pfn = __phys_to_pfn(IO_PHYS),
682 .length = IO_SIZE,
683 .type = MT_DEVICE
684 },
685 {
686 .virtual = DA8XX_CP_INTC_VIRT,
687 .pfn = __phys_to_pfn(DA8XX_CP_INTC_BASE),
688 .length = DA8XX_CP_INTC_SIZE,
689 .type = MT_DEVICE
690 },
691 };
692
693 static void __iomem *da850_psc_bases[] = {
694 IO_ADDRESS(DA8XX_PSC0_BASE),
695 IO_ADDRESS(DA8XX_PSC1_BASE),
696 };
697
698 /* Contents of JTAG ID register used to identify exact cpu type */
699 static struct davinci_id da850_ids[] = {
700 {
701 .variant = 0x0,
702 .part_no = 0xb7d1,
703 .manufacturer = 0x017, /* 0x02f >> 1 */
704 .cpu_id = DAVINCI_CPU_ID_DA850,
705 .name = "da850/omap-l138",
706 },
707 };
708
709 static struct davinci_timer_instance da850_timer_instance[4] = {
710 {
711 .base = IO_ADDRESS(DA8XX_TIMER64P0_BASE),
712 .bottom_irq = IRQ_DA8XX_TINT12_0,
713 .top_irq = IRQ_DA8XX_TINT34_0,
714 },
715 {
716 .base = IO_ADDRESS(DA8XX_TIMER64P1_BASE),
717 .bottom_irq = IRQ_DA8XX_TINT12_1,
718 .top_irq = IRQ_DA8XX_TINT34_1,
719 },
720 {
721 .base = IO_ADDRESS(DA850_TIMER64P2_BASE),
722 .bottom_irq = IRQ_DA850_TINT12_2,
723 .top_irq = IRQ_DA850_TINT34_2,
724 },
725 {
726 .base = IO_ADDRESS(DA850_TIMER64P3_BASE),
727 .bottom_irq = IRQ_DA850_TINT12_3,
728 .top_irq = IRQ_DA850_TINT34_3,
729 },
730 };
731
732 /*
733 * T0_BOT: Timer 0, bottom : Used for clock_event
734 * T0_TOP: Timer 0, top : Used for clocksource
735 * T1_BOT, T1_TOP: Timer 1, bottom & top: Used for watchdog timer
736 */
737 static struct davinci_timer_info da850_timer_info = {
738 .timers = da850_timer_instance,
739 .clockevent_id = T0_BOT,
740 .clocksource_id = T0_TOP,
741 };
742
743 static struct davinci_soc_info davinci_soc_info_da850 = {
744 .io_desc = da850_io_desc,
745 .io_desc_num = ARRAY_SIZE(da850_io_desc),
746 .jtag_id_base = IO_ADDRESS(DA8XX_JTAG_ID_REG),
747 .ids = da850_ids,
748 .ids_num = ARRAY_SIZE(da850_ids),
749 .cpu_clks = da850_clks,
750 .psc_bases = da850_psc_bases,
751 .psc_bases_num = ARRAY_SIZE(da850_psc_bases),
752 .pinmux_base = IO_ADDRESS(DA8XX_BOOT_CFG_BASE + 0x120),
753 .pinmux_pins = da850_pins,
754 .pinmux_pins_num = ARRAY_SIZE(da850_pins),
755 .intc_base = (void __iomem *)DA8XX_CP_INTC_VIRT,
756 .intc_type = DAVINCI_INTC_TYPE_CP_INTC,
757 .intc_irq_prios = da850_default_priorities,
758 .intc_irq_num = DA850_N_CP_INTC_IRQ,
759 .timer_info = &da850_timer_info,
760 .gpio_base = IO_ADDRESS(DA8XX_GPIO_BASE),
761 .gpio_num = 144,
762 .gpio_irq = IRQ_DA8XX_GPIO0,
763 .serial_dev = &da8xx_serial_device,
764 .emac_pdata = &da8xx_emac_pdata,
765 };
766
767 void __init da850_init(void)
768 {
769 davinci_common_init(&davinci_soc_info_da850);
770 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree