[MIPS] replace __inline with inline
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / mips / philips / pnx8550 / jbs / board_setup.c
blobe550a3e12f654445178f2e494a315926405adfd9
1 /*
2 * JBS Specific board startup routines.
4 * Copyright 2005, Embedded Alley Solutions, Inc
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
11 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
14 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
15 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
16 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
17 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
18 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
19 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
20 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 675 Mass Ave, Cambridge, MA 02139, USA.
26 #include <linux/init.h>
27 #include <linux/sched.h>
28 #include <linux/ioport.h>
29 #include <linux/mm.h>
30 #include <linux/console.h>
31 #include <linux/mc146818rtc.h>
32 #include <linux/delay.h>
34 #include <asm/cpu.h>
35 #include <asm/bootinfo.h>
36 #include <asm/irq.h>
37 #include <asm/mipsregs.h>
38 #include <asm/reboot.h>
39 #include <asm/pgtable.h>
41 #include <glb.h>
43 /* CP0 hazard avoidance. */
44 #define BARRIER __asm__ __volatile__(".set noreorder\n\t" \
45 "nop; nop; nop; nop; nop; nop;\n\t" \
46 ".set reorder\n\t")
48 void __init board_setup(void)
50 unsigned long config0, configpr;
52 config0 = read_c0_config();
54 /* clear all three cache coherency fields */
55 config0 &= ~(0x7 | (7<<25) | (7<<28));
56 config0 |= (_page_cachable_default >> _CACHE_SHIFT) |
57 (CONF_CM_DEFAULT << 25) | (CONF_CM_DEFAULT << 28);
58 write_c0_config(config0);
59 BARRIER;
61 configpr = read_c0_config7();
62 configpr |= (1<<19); /* enable tlb */
63 write_c0_config7(configpr);
64 BARRIER;