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KVM: x86 emulator: move invlpg emulation into a function
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / x86 / kvm / emulate.c
blobc522b4e3dbb016870b101a8489e1a469b49f0936
1 /******************************************************************************
2 * emulate.c
3 *
4 * Generic x86 (32-bit and 64-bit) instruction decoder and emulator.
5 *
6 * Copyright (c) 2005 Keir Fraser
7 *
8 * Linux coding style, mod r/m decoder, segment base fixes, real-mode
9 * privileged instructions:
10 *
11 * Copyright (C) 2006 Qumranet
12 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
13 *
14 * Avi Kivity <avi@qumranet.com>
15 * Yaniv Kamay <yaniv@qumranet.com>
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 *
20 * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
21 */
22
23 #include <linux/kvm_host.h>
24 #include "kvm_cache_regs.h"
25 #include <linux/module.h>
26 #include <asm/kvm_emulate.h>
27
28 #include "x86.h"
29 #include "tss.h"
30
31 /*
32 * Opcode effective-address decode tables.
33 * Note that we only emulate instructions that have at least one memory
34 * operand (excluding implicit stack references). We assume that stack
35 * references and instruction fetches will never occur in special memory
36 * areas that require emulation. So, for example, 'mov <imm>,<reg>' need
37 * not be handled.
38 */
39
40 /* Operand sizes: 8-bit operands or specified/overridden size. */
41 #define ByteOp (1<<0) /* 8-bit operands. */
42 /* Destination operand type. */
43 #define ImplicitOps (1<<1) /* Implicit in opcode. No generic decode. */
44 #define DstReg (2<<1) /* Register operand. */
45 #define DstMem (3<<1) /* Memory operand. */
46 #define DstAcc (4<<1) /* Destination Accumulator */
47 #define DstDI (5<<1) /* Destination is in ES:(E)DI */
48 #define DstMem64 (6<<1) /* 64bit memory operand */
49 #define DstImmUByte (7<<1) /* 8-bit unsigned immediate operand */
50 #define DstMask (7<<1)
51 /* Source operand type. */
52 #define SrcNone (0<<4) /* No source operand. */
53 #define SrcReg (1<<4) /* Register operand. */
54 #define SrcMem (2<<4) /* Memory operand. */
55 #define SrcMem16 (3<<4) /* Memory operand (16-bit). */
56 #define SrcMem32 (4<<4) /* Memory operand (32-bit). */
57 #define SrcImm (5<<4) /* Immediate operand. */
58 #define SrcImmByte (6<<4) /* 8-bit sign-extended immediate operand. */
59 #define SrcOne (7<<4) /* Implied '1' */
60 #define SrcImmUByte (8<<4) /* 8-bit unsigned immediate operand. */
61 #define SrcImmU (9<<4) /* Immediate operand, unsigned */
62 #define SrcSI (0xa<<4) /* Source is in the DS:RSI */
63 #define SrcImmFAddr (0xb<<4) /* Source is immediate far address */
64 #define SrcMemFAddr (0xc<<4) /* Source is far address in memory */
65 #define SrcAcc (0xd<<4) /* Source Accumulator */
66 #define SrcImmU16 (0xe<<4) /* Immediate operand, unsigned, 16 bits */
67 #define SrcMask (0xf<<4)
68 /* Generic ModRM decode. */
69 #define ModRM (1<<8)
70 /* Destination is only written; never read. */
71 #define Mov (1<<9)
72 #define BitOp (1<<10)
73 #define MemAbs (1<<11) /* Memory operand is absolute displacement */
74 #define String (1<<12) /* String instruction (rep capable) */
75 #define Stack (1<<13) /* Stack instruction (push/pop) */
76 #define Group (1<<14) /* Bits 3:5 of modrm byte extend opcode */
77 #define GroupDual (1<<15) /* Alternate decoding of mod == 3 */
78 #define Prefix (1<<16) /* Instruction varies with 66/f2/f3 prefix */
79 #define Sse (1<<17) /* SSE Vector instruction */
80 #define RMExt (1<<18) /* Opcode extension in ModRM r/m if mod == 3 */
81 /* Misc flags */
82 #define Prot (1<<21) /* instruction generates #UD if not in prot-mode */
83 #define VendorSpecific (1<<22) /* Vendor specific instruction */
84 #define NoAccess (1<<23) /* Don't access memory (lea/invlpg/verr etc) */
85 #define Op3264 (1<<24) /* Operand is 64b in long mode, 32b otherwise */
86 #define Undefined (1<<25) /* No Such Instruction */
87 #define Lock (1<<26) /* lock prefix is allowed for the instruction */
88 #define Priv (1<<27) /* instruction generates #GP if current CPL != 0 */
89 #define No64 (1<<28)
90 /* Source 2 operand type */
91 #define Src2None (0<<29)
92 #define Src2CL (1<<29)
93 #define Src2ImmByte (2<<29)
94 #define Src2One (3<<29)
95 #define Src2Imm (4<<29)
96 #define Src2Mask (7<<29)
97
98 #define X2(x...) x, x
99 #define X3(x...) X2(x), x
100 #define X4(x...) X2(x), X2(x)
101 #define X5(x...) X4(x), x
102 #define X6(x...) X4(x), X2(x)
103 #define X7(x...) X4(x), X3(x)
104 #define X8(x...) X4(x), X4(x)
105 #define X16(x...) X8(x), X8(x)
106
107 struct opcode {
108 u32 flags;
109 u8 intercept;
110 union {
111 int (*execute)(struct x86_emulate_ctxt *ctxt);
112 struct opcode *group;
113 struct group_dual *gdual;
114 struct gprefix *gprefix;
115 } u;
116 int (*check_perm)(struct x86_emulate_ctxt *ctxt);
117 };
118
119 struct group_dual {
120 struct opcode mod012[8];
121 struct opcode mod3[8];
122 };
123
124 struct gprefix {
125 struct opcode pfx_no;
126 struct opcode pfx_66;
127 struct opcode pfx_f2;
128 struct opcode pfx_f3;
129 };
130
131 /* EFLAGS bit definitions. */
132 #define EFLG_ID (1<<21)
133 #define EFLG_VIP (1<<20)
134 #define EFLG_VIF (1<<19)
135 #define EFLG_AC (1<<18)
136 #define EFLG_VM (1<<17)
137 #define EFLG_RF (1<<16)
138 #define EFLG_IOPL (3<<12)
139 #define EFLG_NT (1<<14)
140 #define EFLG_OF (1<<11)
141 #define EFLG_DF (1<<10)
142 #define EFLG_IF (1<<9)
143 #define EFLG_TF (1<<8)
144 #define EFLG_SF (1<<7)
145 #define EFLG_ZF (1<<6)
146 #define EFLG_AF (1<<4)
147 #define EFLG_PF (1<<2)
148 #define EFLG_CF (1<<0)
149
150 #define EFLG_RESERVED_ZEROS_MASK 0xffc0802a
151 #define EFLG_RESERVED_ONE_MASK 2
152
153 /*
154 * Instruction emulation:
155 * Most instructions are emulated directly via a fragment of inline assembly
156 * code. This allows us to save/restore EFLAGS and thus very easily pick up
157 * any modified flags.
158 */
159
160 #if defined(CONFIG_X86_64)
161 #define _LO32 "k" /* force 32-bit operand */
162 #define _STK "%%rsp" /* stack pointer */
163 #elif defined(__i386__)
164 #define _LO32 "" /* force 32-bit operand */
165 #define _STK "%%esp" /* stack pointer */
166 #endif
167
168 /*
169 * These EFLAGS bits are restored from saved value during emulation, and
170 * any changes are written back to the saved value after emulation.
171 */
172 #define EFLAGS_MASK (EFLG_OF|EFLG_SF|EFLG_ZF|EFLG_AF|EFLG_PF|EFLG_CF)
173
174 /* Before executing instruction: restore necessary bits in EFLAGS. */
175 #define _PRE_EFLAGS(_sav, _msk, _tmp) \
176 /* EFLAGS = (_sav & _msk) | (EFLAGS & ~_msk); _sav &= ~_msk; */ \
177 "movl %"_sav",%"_LO32 _tmp"; " \
178 "push %"_tmp"; " \
179 "push %"_tmp"; " \
180 "movl %"_msk",%"_LO32 _tmp"; " \
181 "andl %"_LO32 _tmp",("_STK"); " \
182 "pushf; " \
183 "notl %"_LO32 _tmp"; " \
184 "andl %"_LO32 _tmp",("_STK"); " \
185 "andl %"_LO32 _tmp","__stringify(BITS_PER_LONG/4)"("_STK"); " \
186 "pop %"_tmp"; " \
187 "orl %"_LO32 _tmp",("_STK"); " \
188 "popf; " \
189 "pop %"_sav"; "
190
191 /* After executing instruction: write-back necessary bits in EFLAGS. */
192 #define _POST_EFLAGS(_sav, _msk, _tmp) \
193 /* _sav |= EFLAGS & _msk; */ \
194 "pushf; " \
195 "pop %"_tmp"; " \
196 "andl %"_msk",%"_LO32 _tmp"; " \
197 "orl %"_LO32 _tmp",%"_sav"; "
198
199 #ifdef CONFIG_X86_64
200 #define ON64(x) x
201 #else
202 #define ON64(x)
203 #endif
204
205 #define ____emulate_2op(_op, _src, _dst, _eflags, _x, _y, _suffix, _dsttype) \
206 do { \
207 __asm__ __volatile__ ( \
208 _PRE_EFLAGS("0", "4", "2") \
209 _op _suffix " %"_x"3,%1; " \
210 _POST_EFLAGS("0", "4", "2") \
211 : "=m" (_eflags), "+q" (*(_dsttype*)&(_dst).val),\
212 "=&r" (_tmp) \
213 : _y ((_src).val), "i" (EFLAGS_MASK)); \
214 } while (0)
215
216
217 /* Raw emulation: instruction has two explicit operands. */
218 #define __emulate_2op_nobyte(_op,_src,_dst,_eflags,_wx,_wy,_lx,_ly,_qx,_qy) \
219 do { \
220 unsigned long _tmp; \
221 \
222 switch ((_dst).bytes) { \
223 case 2: \
224 ____emulate_2op(_op,_src,_dst,_eflags,_wx,_wy,"w",u16);\
225 break; \
226 case 4: \
227 ____emulate_2op(_op,_src,_dst,_eflags,_lx,_ly,"l",u32);\
228 break; \
229 case 8: \
230 ON64(____emulate_2op(_op,_src,_dst,_eflags,_qx,_qy,"q",u64)); \
231 break; \
232 } \
233 } while (0)
234
235 #define __emulate_2op(_op,_src,_dst,_eflags,_bx,_by,_wx,_wy,_lx,_ly,_qx,_qy) \
236 do { \
237 unsigned long _tmp; \
238 switch ((_dst).bytes) { \
239 case 1: \
240 ____emulate_2op(_op,_src,_dst,_eflags,_bx,_by,"b",u8); \
241 break; \
242 default: \
243 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
244 _wx, _wy, _lx, _ly, _qx, _qy); \
245 break; \
246 } \
247 } while (0)
248
249 /* Source operand is byte-sized and may be restricted to just %cl. */
250 #define emulate_2op_SrcB(_op, _src, _dst, _eflags) \
251 __emulate_2op(_op, _src, _dst, _eflags, \
252 "b", "c", "b", "c", "b", "c", "b", "c")
253
254 /* Source operand is byte, word, long or quad sized. */
255 #define emulate_2op_SrcV(_op, _src, _dst, _eflags) \
256 __emulate_2op(_op, _src, _dst, _eflags, \
257 "b", "q", "w", "r", _LO32, "r", "", "r")
258
259 /* Source operand is word, long or quad sized. */
260 #define emulate_2op_SrcV_nobyte(_op, _src, _dst, _eflags) \
261 __emulate_2op_nobyte(_op, _src, _dst, _eflags, \
262 "w", "r", _LO32, "r", "", "r")
263
264 /* Instruction has three operands and one operand is stored in ECX register */
265 #define __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, _suffix, _type) \
266 do { \
267 unsigned long _tmp; \
268 _type _clv = (_cl).val; \
269 _type _srcv = (_src).val; \
270 _type _dstv = (_dst).val; \
271 \
272 __asm__ __volatile__ ( \
273 _PRE_EFLAGS("0", "5", "2") \
274 _op _suffix " %4,%1 \n" \
275 _POST_EFLAGS("0", "5", "2") \
276 : "=m" (_eflags), "+r" (_dstv), "=&r" (_tmp) \
277 : "c" (_clv) , "r" (_srcv), "i" (EFLAGS_MASK) \
278 ); \
279 \
280 (_cl).val = (unsigned long) _clv; \
281 (_src).val = (unsigned long) _srcv; \
282 (_dst).val = (unsigned long) _dstv; \
283 } while (0)
284
285 #define emulate_2op_cl(_op, _cl, _src, _dst, _eflags) \
286 do { \
287 switch ((_dst).bytes) { \
288 case 2: \
289 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
290 "w", unsigned short); \
291 break; \
292 case 4: \
293 __emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
294 "l", unsigned int); \
295 break; \
296 case 8: \
297 ON64(__emulate_2op_cl(_op, _cl, _src, _dst, _eflags, \
298 "q", unsigned long)); \
299 break; \
300 } \
301 } while (0)
302
303 #define __emulate_1op(_op, _dst, _eflags, _suffix) \
304 do { \
305 unsigned long _tmp; \
306 \
307 __asm__ __volatile__ ( \
308 _PRE_EFLAGS("0", "3", "2") \
309 _op _suffix " %1; " \
310 _POST_EFLAGS("0", "3", "2") \
311 : "=m" (_eflags), "+m" ((_dst).val), \
312 "=&r" (_tmp) \
313 : "i" (EFLAGS_MASK)); \
314 } while (0)
315
316 /* Instruction has only one explicit operand (no source operand). */
317 #define emulate_1op(_op, _dst, _eflags) \
318 do { \
319 switch ((_dst).bytes) { \
320 case 1: __emulate_1op(_op, _dst, _eflags, "b"); break; \
321 case 2: __emulate_1op(_op, _dst, _eflags, "w"); break; \
322 case 4: __emulate_1op(_op, _dst, _eflags, "l"); break; \
323 case 8: ON64(__emulate_1op(_op, _dst, _eflags, "q")); break; \
324 } \
325 } while (0)
326
327 #define __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, _suffix) \
328 do { \
329 unsigned long _tmp; \
330 \
331 __asm__ __volatile__ ( \
332 _PRE_EFLAGS("0", "4", "1") \
333 _op _suffix " %5; " \
334 _POST_EFLAGS("0", "4", "1") \
335 : "=m" (_eflags), "=&r" (_tmp), \
336 "+a" (_rax), "+d" (_rdx) \
337 : "i" (EFLAGS_MASK), "m" ((_src).val), \
338 "a" (_rax), "d" (_rdx)); \
339 } while (0)
340
341 #define __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _suffix, _ex) \
342 do { \
343 unsigned long _tmp; \
344 \
345 __asm__ __volatile__ ( \
346 _PRE_EFLAGS("0", "5", "1") \
347 "1: \n\t" \
348 _op _suffix " %6; " \
349 "2: \n\t" \
350 _POST_EFLAGS("0", "5", "1") \
351 ".pushsection .fixup,\"ax\" \n\t" \
352 "3: movb $1, %4 \n\t" \
353 "jmp 2b \n\t" \
354 ".popsection \n\t" \
355 _ASM_EXTABLE(1b, 3b) \
356 : "=m" (_eflags), "=&r" (_tmp), \
357 "+a" (_rax), "+d" (_rdx), "+qm"(_ex) \
358 : "i" (EFLAGS_MASK), "m" ((_src).val), \
359 "a" (_rax), "d" (_rdx)); \
360 } while (0)
361
362 /* instruction has only one source operand, destination is implicit (e.g. mul, div, imul, idiv) */
363 #define emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags) \
364 do { \
365 switch((_src).bytes) { \
366 case 1: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "b"); break; \
367 case 2: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "w"); break; \
368 case 4: __emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "l"); break; \
369 case 8: ON64(__emulate_1op_rax_rdx(_op, _src, _rax, _rdx, _eflags, "q")); break; \
370 } \
371 } while (0)
372
373 #define emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, _eflags, _ex) \
374 do { \
375 switch((_src).bytes) { \
376 case 1: \
377 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
378 _eflags, "b", _ex); \
379 break; \
380 case 2: \
381 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
382 _eflags, "w", _ex); \
383 break; \
384 case 4: \
385 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
386 _eflags, "l", _ex); \
387 break; \
388 case 8: ON64( \
389 __emulate_1op_rax_rdx_ex(_op, _src, _rax, _rdx, \
390 _eflags, "q", _ex)); \
391 break; \
392 } \
393 } while (0)
394
395 /* Fetch next part of the instruction being emulated. */
396 #define insn_fetch(_type, _size, _eip) \
397 ({ unsigned long _x; \
398 rc = do_insn_fetch(ctxt, ops, (_eip), &_x, (_size)); \
399 if (rc != X86EMUL_CONTINUE) \
400 goto done; \
401 (_eip) += (_size); \
402 (_type)_x; \
403 })
404
405 #define insn_fetch_arr(_arr, _size, _eip) \
406 ({ rc = do_insn_fetch(ctxt, ops, (_eip), _arr, (_size)); \
407 if (rc != X86EMUL_CONTINUE) \
408 goto done; \
409 (_eip) += (_size); \
410 })
411
412 static int emulator_check_intercept(struct x86_emulate_ctxt *ctxt,
413 enum x86_intercept intercept,
414 enum x86_intercept_stage stage)
415 {
416 struct x86_instruction_info info = {
417 .intercept = intercept,
418 .rep_prefix = ctxt->decode.rep_prefix,
419 .modrm_mod = ctxt->decode.modrm_mod,
420 .modrm_reg = ctxt->decode.modrm_reg,
421 .modrm_rm = ctxt->decode.modrm_rm,
422 .src_val = ctxt->decode.src.val64,
423 .src_bytes = ctxt->decode.src.bytes,
424 .dst_bytes = ctxt->decode.dst.bytes,
425 .ad_bytes = ctxt->decode.ad_bytes,
426 .next_rip = ctxt->eip,
427 };
428
429 return ctxt->ops->intercept(ctxt->vcpu, &info, stage);
430 }
431
432 static inline unsigned long ad_mask(struct decode_cache *c)
433 {
434 return (1UL << (c->ad_bytes << 3)) - 1;
435 }
436
437 /* Access/update address held in a register, based on addressing mode. */
438 static inline unsigned long
439 address_mask(struct decode_cache *c, unsigned long reg)
440 {
441 if (c->ad_bytes == sizeof(unsigned long))
442 return reg;
443 else
444 return reg & ad_mask(c);
445 }
446
447 static inline unsigned long
448 register_address(struct decode_cache *c, unsigned long reg)
449 {
450 return address_mask(c, reg);
451 }
452
453 static inline void
454 register_address_increment(struct decode_cache *c, unsigned long *reg, int inc)
455 {
456 if (c->ad_bytes == sizeof(unsigned long))
457 *reg += inc;
458 else
459 *reg = (*reg & ~ad_mask(c)) | ((*reg + inc) & ad_mask(c));
460 }
461
462 static inline void jmp_rel(struct decode_cache *c, int rel)
463 {
464 register_address_increment(c, &c->eip, rel);
465 }
466
467 static void set_seg_override(struct decode_cache *c, int seg)
468 {
469 c->has_seg_override = true;
470 c->seg_override = seg;
471 }
472
473 static unsigned long seg_base(struct x86_emulate_ctxt *ctxt,
474 struct x86_emulate_ops *ops, int seg)
475 {
476 if (ctxt->mode == X86EMUL_MODE_PROT64 && seg < VCPU_SREG_FS)
477 return 0;
478
479 return ops->get_cached_segment_base(seg, ctxt->vcpu);
480 }
481
482 static unsigned seg_override(struct x86_emulate_ctxt *ctxt,
483 struct x86_emulate_ops *ops,
484 struct decode_cache *c)
485 {
486 if (!c->has_seg_override)
487 return 0;
488
489 return c->seg_override;
490 }
491
492 static ulong linear(struct x86_emulate_ctxt *ctxt,
493 struct segmented_address addr)
494 {
495 struct decode_cache *c = &ctxt->decode;
496 ulong la;
497
498 la = seg_base(ctxt, ctxt->ops, addr.seg) + addr.ea;
499 if (c->ad_bytes != 8)
500 la &= (u32)-1;
501 return la;
502 }
503
504 static int emulate_exception(struct x86_emulate_ctxt *ctxt, int vec,
505 u32 error, bool valid)
506 {
507 ctxt->exception.vector = vec;
508 ctxt->exception.error_code = error;
509 ctxt->exception.error_code_valid = valid;
510 return X86EMUL_PROPAGATE_FAULT;
511 }
512
513 static int emulate_db(struct x86_emulate_ctxt *ctxt)
514 {
515 return emulate_exception(ctxt, DB_VECTOR, 0, false);
516 }
517
518 static int emulate_gp(struct x86_emulate_ctxt *ctxt, int err)
519 {
520 return emulate_exception(ctxt, GP_VECTOR, err, true);
521 }
522
523 static int emulate_ud(struct x86_emulate_ctxt *ctxt)
524 {
525 return emulate_exception(ctxt, UD_VECTOR, 0, false);
526 }
527
528 static int emulate_ts(struct x86_emulate_ctxt *ctxt, int err)
529 {
530 return emulate_exception(ctxt, TS_VECTOR, err, true);
531 }
532
533 static int emulate_de(struct x86_emulate_ctxt *ctxt)
534 {
535 return emulate_exception(ctxt, DE_VECTOR, 0, false);
536 }
537
538 static int emulate_nm(struct x86_emulate_ctxt *ctxt)
539 {
540 return emulate_exception(ctxt, NM_VECTOR, 0, false);
541 }
542
543 static int segmented_read_std(struct x86_emulate_ctxt *ctxt,
544 struct segmented_address addr,
545 void *data,
546 unsigned size)
547 {
548 return ctxt->ops->read_std(linear(ctxt, addr), data, size, ctxt->vcpu,
549 &ctxt->exception);
550 }
551
552 static int do_fetch_insn_byte(struct x86_emulate_ctxt *ctxt,
553 struct x86_emulate_ops *ops,
554 unsigned long eip, u8 *dest)
555 {
556 struct fetch_cache *fc = &ctxt->decode.fetch;
557 int rc;
558 int size, cur_size;
559
560 if (eip == fc->end) {
561 cur_size = fc->end - fc->start;
562 size = min(15UL - cur_size, PAGE_SIZE - offset_in_page(eip));
563 rc = ops->fetch(ctxt->cs_base + eip, fc->data + cur_size,
564 size, ctxt->vcpu, &ctxt->exception);
565 if (rc != X86EMUL_CONTINUE)
566 return rc;
567 fc->end += size;
568 }
569 *dest = fc->data[eip - fc->start];
570 return X86EMUL_CONTINUE;
571 }
572
573 static int do_insn_fetch(struct x86_emulate_ctxt *ctxt,
574 struct x86_emulate_ops *ops,
575 unsigned long eip, void *dest, unsigned size)
576 {
577 int rc;
578
579 /* x86 instructions are limited to 15 bytes. */
580 if (eip + size - ctxt->eip > 15)
581 return X86EMUL_UNHANDLEABLE;
582 while (size--) {
583 rc = do_fetch_insn_byte(ctxt, ops, eip++, dest++);
584 if (rc != X86EMUL_CONTINUE)
585 return rc;
586 }
587 return X86EMUL_CONTINUE;
588 }
589
590 /*
591 * Given the 'reg' portion of a ModRM byte, and a register block, return a
592 * pointer into the block that addresses the relevant register.
593 * @highbyte_regs specifies whether to decode AH,CH,DH,BH.
594 */
595 static void *decode_register(u8 modrm_reg, unsigned long *regs,
596 int highbyte_regs)
597 {
598 void *p;
599
600 p = &regs[modrm_reg];
601 if (highbyte_regs && modrm_reg >= 4 && modrm_reg < 8)
602 p = (unsigned char *)&regs[modrm_reg & 3] + 1;
603 return p;
604 }
605
606 static int read_descriptor(struct x86_emulate_ctxt *ctxt,
607 struct x86_emulate_ops *ops,
608 struct segmented_address addr,
609 u16 *size, unsigned long *address, int op_bytes)
610 {
611 int rc;
612
613 if (op_bytes == 2)
614 op_bytes = 3;
615 *address = 0;
616 rc = segmented_read_std(ctxt, addr, size, 2);
617 if (rc != X86EMUL_CONTINUE)
618 return rc;
619 addr.ea += 2;
620 rc = segmented_read_std(ctxt, addr, address, op_bytes);
621 return rc;
622 }
623
624 static int test_cc(unsigned int condition, unsigned int flags)
625 {
626 int rc = 0;
627
628 switch ((condition & 15) >> 1) {
629 case 0: /* o */
630 rc |= (flags & EFLG_OF);
631 break;
632 case 1: /* b/c/nae */
633 rc |= (flags & EFLG_CF);
634 break;
635 case 2: /* z/e */
636 rc |= (flags & EFLG_ZF);
637 break;
638 case 3: /* be/na */
639 rc |= (flags & (EFLG_CF|EFLG_ZF));
640 break;
641 case 4: /* s */
642 rc |= (flags & EFLG_SF);
643 break;
644 case 5: /* p/pe */
645 rc |= (flags & EFLG_PF);
646 break;
647 case 7: /* le/ng */
648 rc |= (flags & EFLG_ZF);
649 /* fall through */
650 case 6: /* l/nge */
651 rc |= (!(flags & EFLG_SF) != !(flags & EFLG_OF));
652 break;
653 }
654
655 /* Odd condition identifiers (lsb == 1) have inverted sense. */
656 return (!!rc ^ (condition & 1));
657 }
658
659 static void fetch_register_operand(struct operand *op)
660 {
661 switch (op->bytes) {
662 case 1:
663 op->val = *(u8 *)op->addr.reg;
664 break;
665 case 2:
666 op->val = *(u16 *)op->addr.reg;
667 break;
668 case 4:
669 op->val = *(u32 *)op->addr.reg;
670 break;
671 case 8:
672 op->val = *(u64 *)op->addr.reg;
673 break;
674 }
675 }
676
677 static void read_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data, int reg)
678 {
679 ctxt->ops->get_fpu(ctxt);
680 switch (reg) {
681 case 0: asm("movdqu %%xmm0, %0" : "=m"(*data)); break;
682 case 1: asm("movdqu %%xmm1, %0" : "=m"(*data)); break;
683 case 2: asm("movdqu %%xmm2, %0" : "=m"(*data)); break;
684 case 3: asm("movdqu %%xmm3, %0" : "=m"(*data)); break;
685 case 4: asm("movdqu %%xmm4, %0" : "=m"(*data)); break;
686 case 5: asm("movdqu %%xmm5, %0" : "=m"(*data)); break;
687 case 6: asm("movdqu %%xmm6, %0" : "=m"(*data)); break;
688 case 7: asm("movdqu %%xmm7, %0" : "=m"(*data)); break;
689 #ifdef CONFIG_X86_64
690 case 8: asm("movdqu %%xmm8, %0" : "=m"(*data)); break;
691 case 9: asm("movdqu %%xmm9, %0" : "=m"(*data)); break;
692 case 10: asm("movdqu %%xmm10, %0" : "=m"(*data)); break;
693 case 11: asm("movdqu %%xmm11, %0" : "=m"(*data)); break;
694 case 12: asm("movdqu %%xmm12, %0" : "=m"(*data)); break;
695 case 13: asm("movdqu %%xmm13, %0" : "=m"(*data)); break;
696 case 14: asm("movdqu %%xmm14, %0" : "=m"(*data)); break;
697 case 15: asm("movdqu %%xmm15, %0" : "=m"(*data)); break;
698 #endif
699 default: BUG();
700 }
701 ctxt->ops->put_fpu(ctxt);
702 }
703
704 static void write_sse_reg(struct x86_emulate_ctxt *ctxt, sse128_t *data,
705 int reg)
706 {
707 ctxt->ops->get_fpu(ctxt);
708 switch (reg) {
709 case 0: asm("movdqu %0, %%xmm0" : : "m"(*data)); break;
710 case 1: asm("movdqu %0, %%xmm1" : : "m"(*data)); break;
711 case 2: asm("movdqu %0, %%xmm2" : : "m"(*data)); break;
712 case 3: asm("movdqu %0, %%xmm3" : : "m"(*data)); break;
713 case 4: asm("movdqu %0, %%xmm4" : : "m"(*data)); break;
714 case 5: asm("movdqu %0, %%xmm5" : : "m"(*data)); break;
715 case 6: asm("movdqu %0, %%xmm6" : : "m"(*data)); break;
716 case 7: asm("movdqu %0, %%xmm7" : : "m"(*data)); break;
717 #ifdef CONFIG_X86_64
718 case 8: asm("movdqu %0, %%xmm8" : : "m"(*data)); break;
719 case 9: asm("movdqu %0, %%xmm9" : : "m"(*data)); break;
720 case 10: asm("movdqu %0, %%xmm10" : : "m"(*data)); break;
721 case 11: asm("movdqu %0, %%xmm11" : : "m"(*data)); break;
722 case 12: asm("movdqu %0, %%xmm12" : : "m"(*data)); break;
723 case 13: asm("movdqu %0, %%xmm13" : : "m"(*data)); break;
724 case 14: asm("movdqu %0, %%xmm14" : : "m"(*data)); break;
725 case 15: asm("movdqu %0, %%xmm15" : : "m"(*data)); break;
726 #endif
727 default: BUG();
728 }
729 ctxt->ops->put_fpu(ctxt);
730 }
731
732 static void decode_register_operand(struct x86_emulate_ctxt *ctxt,
733 struct operand *op,
734 struct decode_cache *c,
735 int inhibit_bytereg)
736 {
737 unsigned reg = c->modrm_reg;
738 int highbyte_regs = c->rex_prefix == 0;
739
740 if (!(c->d & ModRM))
741 reg = (c->b & 7) | ((c->rex_prefix & 1) << 3);
742
743 if (c->d & Sse) {
744 op->type = OP_XMM;
745 op->bytes = 16;
746 op->addr.xmm = reg;
747 read_sse_reg(ctxt, &op->vec_val, reg);
748 return;
749 }
750
751 op->type = OP_REG;
752 if ((c->d & ByteOp) && !inhibit_bytereg) {
753 op->addr.reg = decode_register(reg, c->regs, highbyte_regs);
754 op->bytes = 1;
755 } else {
756 op->addr.reg = decode_register(reg, c->regs, 0);
757 op->bytes = c->op_bytes;
758 }
759 fetch_register_operand(op);
760 op->orig_val = op->val;
761 }
762
763 static int decode_modrm(struct x86_emulate_ctxt *ctxt,
764 struct x86_emulate_ops *ops,
765 struct operand *op)
766 {
767 struct decode_cache *c = &ctxt->decode;
768 u8 sib;
769 int index_reg = 0, base_reg = 0, scale;
770 int rc = X86EMUL_CONTINUE;
771 ulong modrm_ea = 0;
772
773 if (c->rex_prefix) {
774 c->modrm_reg = (c->rex_prefix & 4) << 1; /* REX.R */
775 index_reg = (c->rex_prefix & 2) << 2; /* REX.X */
776 c->modrm_rm = base_reg = (c->rex_prefix & 1) << 3; /* REG.B */
777 }
778
779 c->modrm = insn_fetch(u8, 1, c->eip);
780 c->modrm_mod |= (c->modrm & 0xc0) >> 6;
781 c->modrm_reg |= (c->modrm & 0x38) >> 3;
782 c->modrm_rm |= (c->modrm & 0x07);
783 c->modrm_seg = VCPU_SREG_DS;
784
785 if (c->modrm_mod == 3) {
786 op->type = OP_REG;
787 op->bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
788 op->addr.reg = decode_register(c->modrm_rm,
789 c->regs, c->d & ByteOp);
790 if (c->d & Sse) {
791 op->type = OP_XMM;
792 op->bytes = 16;
793 op->addr.xmm = c->modrm_rm;
794 read_sse_reg(ctxt, &op->vec_val, c->modrm_rm);
795 return rc;
796 }
797 fetch_register_operand(op);
798 return rc;
799 }
800
801 op->type = OP_MEM;
802
803 if (c->ad_bytes == 2) {
804 unsigned bx = c->regs[VCPU_REGS_RBX];
805 unsigned bp = c->regs[VCPU_REGS_RBP];
806 unsigned si = c->regs[VCPU_REGS_RSI];
807 unsigned di = c->regs[VCPU_REGS_RDI];
808
809 /* 16-bit ModR/M decode. */
810 switch (c->modrm_mod) {
811 case 0:
812 if (c->modrm_rm == 6)
813 modrm_ea += insn_fetch(u16, 2, c->eip);
814 break;
815 case 1:
816 modrm_ea += insn_fetch(s8, 1, c->eip);
817 break;
818 case 2:
819 modrm_ea += insn_fetch(u16, 2, c->eip);
820 break;
821 }
822 switch (c->modrm_rm) {
823 case 0:
824 modrm_ea += bx + si;
825 break;
826 case 1:
827 modrm_ea += bx + di;
828 break;
829 case 2:
830 modrm_ea += bp + si;
831 break;
832 case 3:
833 modrm_ea += bp + di;
834 break;
835 case 4:
836 modrm_ea += si;
837 break;
838 case 5:
839 modrm_ea += di;
840 break;
841 case 6:
842 if (c->modrm_mod != 0)
843 modrm_ea += bp;
844 break;
845 case 7:
846 modrm_ea += bx;
847 break;
848 }
849 if (c->modrm_rm == 2 || c->modrm_rm == 3 ||
850 (c->modrm_rm == 6 && c->modrm_mod != 0))
851 c->modrm_seg = VCPU_SREG_SS;
852 modrm_ea = (u16)modrm_ea;
853 } else {
854 /* 32/64-bit ModR/M decode. */
855 if ((c->modrm_rm & 7) == 4) {
856 sib = insn_fetch(u8, 1, c->eip);
857 index_reg |= (sib >> 3) & 7;
858 base_reg |= sib & 7;
859 scale = sib >> 6;
860
861 if ((base_reg & 7) == 5 && c->modrm_mod == 0)
862 modrm_ea += insn_fetch(s32, 4, c->eip);
863 else
864 modrm_ea += c->regs[base_reg];
865 if (index_reg != 4)
866 modrm_ea += c->regs[index_reg] << scale;
867 } else if ((c->modrm_rm & 7) == 5 && c->modrm_mod == 0) {
868 if (ctxt->mode == X86EMUL_MODE_PROT64)
869 c->rip_relative = 1;
870 } else
871 modrm_ea += c->regs[c->modrm_rm];
872 switch (c->modrm_mod) {
873 case 0:
874 if (c->modrm_rm == 5)
875 modrm_ea += insn_fetch(s32, 4, c->eip);
876 break;
877 case 1:
878 modrm_ea += insn_fetch(s8, 1, c->eip);
879 break;
880 case 2:
881 modrm_ea += insn_fetch(s32, 4, c->eip);
882 break;
883 }
884 }
885 op->addr.mem.ea = modrm_ea;
886 done:
887 return rc;
888 }
889
890 static int decode_abs(struct x86_emulate_ctxt *ctxt,
891 struct x86_emulate_ops *ops,
892 struct operand *op)
893 {
894 struct decode_cache *c = &ctxt->decode;
895 int rc = X86EMUL_CONTINUE;
896
897 op->type = OP_MEM;
898 switch (c->ad_bytes) {
899 case 2:
900 op->addr.mem.ea = insn_fetch(u16, 2, c->eip);
901 break;
902 case 4:
903 op->addr.mem.ea = insn_fetch(u32, 4, c->eip);
904 break;
905 case 8:
906 op->addr.mem.ea = insn_fetch(u64, 8, c->eip);
907 break;
908 }
909 done:
910 return rc;
911 }
912
913 static void fetch_bit_operand(struct decode_cache *c)
914 {
915 long sv = 0, mask;
916
917 if (c->dst.type == OP_MEM && c->src.type == OP_REG) {
918 mask = ~(c->dst.bytes * 8 - 1);
919
920 if (c->src.bytes == 2)
921 sv = (s16)c->src.val & (s16)mask;
922 else if (c->src.bytes == 4)
923 sv = (s32)c->src.val & (s32)mask;
924
925 c->dst.addr.mem.ea += (sv >> 3);
926 }
927
928 /* only subword offset */
929 c->src.val &= (c->dst.bytes << 3) - 1;
930 }
931
932 static int read_emulated(struct x86_emulate_ctxt *ctxt,
933 struct x86_emulate_ops *ops,
934 unsigned long addr, void *dest, unsigned size)
935 {
936 int rc;
937 struct read_cache *mc = &ctxt->decode.mem_read;
938
939 while (size) {
940 int n = min(size, 8u);
941 size -= n;
942 if (mc->pos < mc->end)
943 goto read_cached;
944
945 rc = ops->read_emulated(addr, mc->data + mc->end, n,
946 &ctxt->exception, ctxt->vcpu);
947 if (rc != X86EMUL_CONTINUE)
948 return rc;
949 mc->end += n;
950
951 read_cached:
952 memcpy(dest, mc->data + mc->pos, n);
953 mc->pos += n;
954 dest += n;
955 addr += n;
956 }
957 return X86EMUL_CONTINUE;
958 }
959
960 static int segmented_read(struct x86_emulate_ctxt *ctxt,
961 struct segmented_address addr,
962 void *data,
963 unsigned size)
964 {
965 return read_emulated(ctxt, ctxt->ops, linear(ctxt, addr), data, size);
966 }
967
968 static int segmented_write(struct x86_emulate_ctxt *ctxt,
969 struct segmented_address addr,
970 const void *data,
971 unsigned size)
972 {
973 return ctxt->ops->write_emulated(linear(ctxt, addr), data, size,
974 &ctxt->exception, ctxt->vcpu);
975 }
976
977 static int segmented_cmpxchg(struct x86_emulate_ctxt *ctxt,
978 struct segmented_address addr,
979 const void *orig_data, const void *data,
980 unsigned size)
981 {
982 return ctxt->ops->cmpxchg_emulated(linear(ctxt, addr), orig_data, data,
983 size, &ctxt->exception, ctxt->vcpu);
984 }
985
986 static int pio_in_emulated(struct x86_emulate_ctxt *ctxt,
987 struct x86_emulate_ops *ops,
988 unsigned int size, unsigned short port,
989 void *dest)
990 {
991 struct read_cache *rc = &ctxt->decode.io_read;
992
993 if (rc->pos == rc->end) { /* refill pio read ahead */
994 struct decode_cache *c = &ctxt->decode;
995 unsigned int in_page, n;
996 unsigned int count = c->rep_prefix ?
997 address_mask(c, c->regs[VCPU_REGS_RCX]) : 1;
998 in_page = (ctxt->eflags & EFLG_DF) ?
999 offset_in_page(c->regs[VCPU_REGS_RDI]) :
1000 PAGE_SIZE - offset_in_page(c->regs[VCPU_REGS_RDI]);
1001 n = min(min(in_page, (unsigned int)sizeof(rc->data)) / size,
1002 count);
1003 if (n == 0)
1004 n = 1;
1005 rc->pos = rc->end = 0;
1006 if (!ops->pio_in_emulated(size, port, rc->data, n, ctxt->vcpu))
1007 return 0;
1008 rc->end = n * size;
1009 }
1010
1011 memcpy(dest, rc->data + rc->pos, size);
1012 rc->pos += size;
1013 return 1;
1014 }
1015
1016 static u32 desc_limit_scaled(struct desc_struct *desc)
1017 {
1018 u32 limit = get_desc_limit(desc);
1019
1020 return desc->g ? (limit << 12) | 0xfff : limit;
1021 }
1022
1023 static void get_descriptor_table_ptr(struct x86_emulate_ctxt *ctxt,
1024 struct x86_emulate_ops *ops,
1025 u16 selector, struct desc_ptr *dt)
1026 {
1027 if (selector & 1 << 2) {
1028 struct desc_struct desc;
1029 memset (dt, 0, sizeof *dt);
1030 if (!ops->get_cached_descriptor(&desc, NULL, VCPU_SREG_LDTR,
1031 ctxt->vcpu))
1032 return;
1033
1034 dt->size = desc_limit_scaled(&desc); /* what if limit > 65535? */
1035 dt->address = get_desc_base(&desc);
1036 } else
1037 ops->get_gdt(dt, ctxt->vcpu);
1038 }
1039
1040 /* allowed just for 8 bytes segments */
1041 static int read_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1042 struct x86_emulate_ops *ops,
1043 u16 selector, struct desc_struct *desc)
1044 {
1045 struct desc_ptr dt;
1046 u16 index = selector >> 3;
1047 int ret;
1048 ulong addr;
1049
1050 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1051
1052 if (dt.size < index * 8 + 7)
1053 return emulate_gp(ctxt, selector & 0xfffc);
1054 addr = dt.address + index * 8;
1055 ret = ops->read_std(addr, desc, sizeof *desc, ctxt->vcpu,
1056 &ctxt->exception);
1057
1058 return ret;
1059 }
1060
1061 /* allowed just for 8 bytes segments */
1062 static int write_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1063 struct x86_emulate_ops *ops,
1064 u16 selector, struct desc_struct *desc)
1065 {
1066 struct desc_ptr dt;
1067 u16 index = selector >> 3;
1068 ulong addr;
1069 int ret;
1070
1071 get_descriptor_table_ptr(ctxt, ops, selector, &dt);
1072
1073 if (dt.size < index * 8 + 7)
1074 return emulate_gp(ctxt, selector & 0xfffc);
1075
1076 addr = dt.address + index * 8;
1077 ret = ops->write_std(addr, desc, sizeof *desc, ctxt->vcpu,
1078 &ctxt->exception);
1079
1080 return ret;
1081 }
1082
1083 /* Does not support long mode */
1084 static int load_segment_descriptor(struct x86_emulate_ctxt *ctxt,
1085 struct x86_emulate_ops *ops,
1086 u16 selector, int seg)
1087 {
1088 struct desc_struct seg_desc;
1089 u8 dpl, rpl, cpl;
1090 unsigned err_vec = GP_VECTOR;
1091 u32 err_code = 0;
1092 bool null_selector = !(selector & ~0x3); /* 0000-0003 are null */
1093 int ret;
1094
1095 memset(&seg_desc, 0, sizeof seg_desc);
1096
1097 if ((seg <= VCPU_SREG_GS && ctxt->mode == X86EMUL_MODE_VM86)
1098 || ctxt->mode == X86EMUL_MODE_REAL) {
1099 /* set real mode segment descriptor */
1100 set_desc_base(&seg_desc, selector << 4);
1101 set_desc_limit(&seg_desc, 0xffff);
1102 seg_desc.type = 3;
1103 seg_desc.p = 1;
1104 seg_desc.s = 1;
1105 goto load;
1106 }
1107
1108 /* NULL selector is not valid for TR, CS and SS */
1109 if ((seg == VCPU_SREG_CS || seg == VCPU_SREG_SS || seg == VCPU_SREG_TR)
1110 && null_selector)
1111 goto exception;
1112
1113 /* TR should be in GDT only */
1114 if (seg == VCPU_SREG_TR && (selector & (1 << 2)))
1115 goto exception;
1116
1117 if (null_selector) /* for NULL selector skip all following checks */
1118 goto load;
1119
1120 ret = read_segment_descriptor(ctxt, ops, selector, &seg_desc);
1121 if (ret != X86EMUL_CONTINUE)
1122 return ret;
1123
1124 err_code = selector & 0xfffc;
1125 err_vec = GP_VECTOR;
1126
1127 /* can't load system descriptor into segment selecor */
1128 if (seg <= VCPU_SREG_GS && !seg_desc.s)
1129 goto exception;
1130
1131 if (!seg_desc.p) {
1132 err_vec = (seg == VCPU_SREG_SS) ? SS_VECTOR : NP_VECTOR;
1133 goto exception;
1134 }
1135
1136 rpl = selector & 3;
1137 dpl = seg_desc.dpl;
1138 cpl = ops->cpl(ctxt->vcpu);
1139
1140 switch (seg) {
1141 case VCPU_SREG_SS:
1142 /*
1143 * segment is not a writable data segment or segment
1144 * selector's RPL != CPL or segment selector's RPL != CPL
1145 */
1146 if (rpl != cpl || (seg_desc.type & 0xa) != 0x2 || dpl != cpl)
1147 goto exception;
1148 break;
1149 case VCPU_SREG_CS:
1150 if (!(seg_desc.type & 8))
1151 goto exception;
1152
1153 if (seg_desc.type & 4) {
1154 /* conforming */
1155 if (dpl > cpl)
1156 goto exception;
1157 } else {
1158 /* nonconforming */
1159 if (rpl > cpl || dpl != cpl)
1160 goto exception;
1161 }
1162 /* CS(RPL) <- CPL */
1163 selector = (selector & 0xfffc) | cpl;
1164 break;
1165 case VCPU_SREG_TR:
1166 if (seg_desc.s || (seg_desc.type != 1 && seg_desc.type != 9))
1167 goto exception;
1168 break;
1169 case VCPU_SREG_LDTR:
1170 if (seg_desc.s || seg_desc.type != 2)
1171 goto exception;
1172 break;
1173 default: /* DS, ES, FS, or GS */
1174 /*
1175 * segment is not a data or readable code segment or
1176 * ((segment is a data or nonconforming code segment)
1177 * and (both RPL and CPL > DPL))
1178 */
1179 if ((seg_desc.type & 0xa) == 0x8 ||
1180 (((seg_desc.type & 0xc) != 0xc) &&
1181 (rpl > dpl && cpl > dpl)))
1182 goto exception;
1183 break;
1184 }
1185
1186 if (seg_desc.s) {
1187 /* mark segment as accessed */
1188 seg_desc.type |= 1;
1189 ret = write_segment_descriptor(ctxt, ops, selector, &seg_desc);
1190 if (ret != X86EMUL_CONTINUE)
1191 return ret;
1192 }
1193 load:
1194 ops->set_segment_selector(selector, seg, ctxt->vcpu);
1195 ops->set_cached_descriptor(&seg_desc, 0, seg, ctxt->vcpu);
1196 return X86EMUL_CONTINUE;
1197 exception:
1198 emulate_exception(ctxt, err_vec, err_code, true);
1199 return X86EMUL_PROPAGATE_FAULT;
1200 }
1201
1202 static void write_register_operand(struct operand *op)
1203 {
1204 /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. */
1205 switch (op->bytes) {
1206 case 1:
1207 *(u8 *)op->addr.reg = (u8)op->val;
1208 break;
1209 case 2:
1210 *(u16 *)op->addr.reg = (u16)op->val;
1211 break;
1212 case 4:
1213 *op->addr.reg = (u32)op->val;
1214 break; /* 64b: zero-extend */
1215 case 8:
1216 *op->addr.reg = op->val;
1217 break;
1218 }
1219 }
1220
1221 static inline int writeback(struct x86_emulate_ctxt *ctxt,
1222 struct x86_emulate_ops *ops)
1223 {
1224 int rc;
1225 struct decode_cache *c = &ctxt->decode;
1226
1227 switch (c->dst.type) {
1228 case OP_REG:
1229 write_register_operand(&c->dst);
1230 break;
1231 case OP_MEM:
1232 if (c->lock_prefix)
1233 rc = segmented_cmpxchg(ctxt,
1234 c->dst.addr.mem,
1235 &c->dst.orig_val,
1236 &c->dst.val,
1237 c->dst.bytes);
1238 else
1239 rc = segmented_write(ctxt,
1240 c->dst.addr.mem,
1241 &c->dst.val,
1242 c->dst.bytes);
1243 if (rc != X86EMUL_CONTINUE)
1244 return rc;
1245 break;
1246 case OP_XMM:
1247 write_sse_reg(ctxt, &c->dst.vec_val, c->dst.addr.xmm);
1248 break;
1249 case OP_NONE:
1250 /* no writeback */
1251 break;
1252 default:
1253 break;
1254 }
1255 return X86EMUL_CONTINUE;
1256 }
1257
1258 static inline void emulate_push(struct x86_emulate_ctxt *ctxt,
1259 struct x86_emulate_ops *ops)
1260 {
1261 struct decode_cache *c = &ctxt->decode;
1262
1263 c->dst.type = OP_MEM;
1264 c->dst.bytes = c->op_bytes;
1265 c->dst.val = c->src.val;
1266 register_address_increment(c, &c->regs[VCPU_REGS_RSP], -c->op_bytes);
1267 c->dst.addr.mem.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
1268 c->dst.addr.mem.seg = VCPU_SREG_SS;
1269 }
1270
1271 static int emulate_pop(struct x86_emulate_ctxt *ctxt,
1272 struct x86_emulate_ops *ops,
1273 void *dest, int len)
1274 {
1275 struct decode_cache *c = &ctxt->decode;
1276 int rc;
1277 struct segmented_address addr;
1278
1279 addr.ea = register_address(c, c->regs[VCPU_REGS_RSP]);
1280 addr.seg = VCPU_SREG_SS;
1281 rc = segmented_read(ctxt, addr, dest, len);
1282 if (rc != X86EMUL_CONTINUE)
1283 return rc;
1284
1285 register_address_increment(c, &c->regs[VCPU_REGS_RSP], len);
1286 return rc;
1287 }
1288
1289 static int emulate_popf(struct x86_emulate_ctxt *ctxt,
1290 struct x86_emulate_ops *ops,
1291 void *dest, int len)
1292 {
1293 int rc;
1294 unsigned long val, change_mask;
1295 int iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1296 int cpl = ops->cpl(ctxt->vcpu);
1297
1298 rc = emulate_pop(ctxt, ops, &val, len);
1299 if (rc != X86EMUL_CONTINUE)
1300 return rc;
1301
1302 change_mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_OF
1303 | EFLG_TF | EFLG_DF | EFLG_NT | EFLG_RF | EFLG_AC | EFLG_ID;
1304
1305 switch(ctxt->mode) {
1306 case X86EMUL_MODE_PROT64:
1307 case X86EMUL_MODE_PROT32:
1308 case X86EMUL_MODE_PROT16:
1309 if (cpl == 0)
1310 change_mask |= EFLG_IOPL;
1311 if (cpl <= iopl)
1312 change_mask |= EFLG_IF;
1313 break;
1314 case X86EMUL_MODE_VM86:
1315 if (iopl < 3)
1316 return emulate_gp(ctxt, 0);
1317 change_mask |= EFLG_IF;
1318 break;
1319 default: /* real mode */
1320 change_mask |= (EFLG_IOPL | EFLG_IF);
1321 break;
1322 }
1323
1324 *(unsigned long *)dest =
1325 (ctxt->eflags & ~change_mask) | (val & change_mask);
1326
1327 return rc;
1328 }
1329
1330 static void emulate_push_sreg(struct x86_emulate_ctxt *ctxt,
1331 struct x86_emulate_ops *ops, int seg)
1332 {
1333 struct decode_cache *c = &ctxt->decode;
1334
1335 c->src.val = ops->get_segment_selector(seg, ctxt->vcpu);
1336
1337 emulate_push(ctxt, ops);
1338 }
1339
1340 static int emulate_pop_sreg(struct x86_emulate_ctxt *ctxt,
1341 struct x86_emulate_ops *ops, int seg)
1342 {
1343 struct decode_cache *c = &ctxt->decode;
1344 unsigned long selector;
1345 int rc;
1346
1347 rc = emulate_pop(ctxt, ops, &selector, c->op_bytes);
1348 if (rc != X86EMUL_CONTINUE)
1349 return rc;
1350
1351 rc = load_segment_descriptor(ctxt, ops, (u16)selector, seg);
1352 return rc;
1353 }
1354
1355 static int emulate_pusha(struct x86_emulate_ctxt *ctxt,
1356 struct x86_emulate_ops *ops)
1357 {
1358 struct decode_cache *c = &ctxt->decode;
1359 unsigned long old_esp = c->regs[VCPU_REGS_RSP];
1360 int rc = X86EMUL_CONTINUE;
1361 int reg = VCPU_REGS_RAX;
1362
1363 while (reg <= VCPU_REGS_RDI) {
1364 (reg == VCPU_REGS_RSP) ?
1365 (c->src.val = old_esp) : (c->src.val = c->regs[reg]);
1366
1367 emulate_push(ctxt, ops);
1368
1369 rc = writeback(ctxt, ops);
1370 if (rc != X86EMUL_CONTINUE)
1371 return rc;
1372
1373 ++reg;
1374 }
1375
1376 /* Disable writeback. */
1377 c->dst.type = OP_NONE;
1378
1379 return rc;
1380 }
1381
1382 static int emulate_popa(struct x86_emulate_ctxt *ctxt,
1383 struct x86_emulate_ops *ops)
1384 {
1385 struct decode_cache *c = &ctxt->decode;
1386 int rc = X86EMUL_CONTINUE;
1387 int reg = VCPU_REGS_RDI;
1388
1389 while (reg >= VCPU_REGS_RAX) {
1390 if (reg == VCPU_REGS_RSP) {
1391 register_address_increment(c, &c->regs[VCPU_REGS_RSP],
1392 c->op_bytes);
1393 --reg;
1394 }
1395
1396 rc = emulate_pop(ctxt, ops, &c->regs[reg], c->op_bytes);
1397 if (rc != X86EMUL_CONTINUE)
1398 break;
1399 --reg;
1400 }
1401 return rc;
1402 }
1403
1404 int emulate_int_real(struct x86_emulate_ctxt *ctxt,
1405 struct x86_emulate_ops *ops, int irq)
1406 {
1407 struct decode_cache *c = &ctxt->decode;
1408 int rc;
1409 struct desc_ptr dt;
1410 gva_t cs_addr;
1411 gva_t eip_addr;
1412 u16 cs, eip;
1413
1414 /* TODO: Add limit checks */
1415 c->src.val = ctxt->eflags;
1416 emulate_push(ctxt, ops);
1417 rc = writeback(ctxt, ops);
1418 if (rc != X86EMUL_CONTINUE)
1419 return rc;
1420
1421 ctxt->eflags &= ~(EFLG_IF | EFLG_TF | EFLG_AC);
1422
1423 c->src.val = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1424 emulate_push(ctxt, ops);
1425 rc = writeback(ctxt, ops);
1426 if (rc != X86EMUL_CONTINUE)
1427 return rc;
1428
1429 c->src.val = c->eip;
1430 emulate_push(ctxt, ops);
1431 rc = writeback(ctxt, ops);
1432 if (rc != X86EMUL_CONTINUE)
1433 return rc;
1434
1435 c->dst.type = OP_NONE;
1436
1437 ops->get_idt(&dt, ctxt->vcpu);
1438
1439 eip_addr = dt.address + (irq << 2);
1440 cs_addr = dt.address + (irq << 2) + 2;
1441
1442 rc = ops->read_std(cs_addr, &cs, 2, ctxt->vcpu, &ctxt->exception);
1443 if (rc != X86EMUL_CONTINUE)
1444 return rc;
1445
1446 rc = ops->read_std(eip_addr, &eip, 2, ctxt->vcpu, &ctxt->exception);
1447 if (rc != X86EMUL_CONTINUE)
1448 return rc;
1449
1450 rc = load_segment_descriptor(ctxt, ops, cs, VCPU_SREG_CS);
1451 if (rc != X86EMUL_CONTINUE)
1452 return rc;
1453
1454 c->eip = eip;
1455
1456 return rc;
1457 }
1458
1459 static int emulate_int(struct x86_emulate_ctxt *ctxt,
1460 struct x86_emulate_ops *ops, int irq)
1461 {
1462 switch(ctxt->mode) {
1463 case X86EMUL_MODE_REAL:
1464 return emulate_int_real(ctxt, ops, irq);
1465 case X86EMUL_MODE_VM86:
1466 case X86EMUL_MODE_PROT16:
1467 case X86EMUL_MODE_PROT32:
1468 case X86EMUL_MODE_PROT64:
1469 default:
1470 /* Protected mode interrupts unimplemented yet */
1471 return X86EMUL_UNHANDLEABLE;
1472 }
1473 }
1474
1475 static int emulate_iret_real(struct x86_emulate_ctxt *ctxt,
1476 struct x86_emulate_ops *ops)
1477 {
1478 struct decode_cache *c = &ctxt->decode;
1479 int rc = X86EMUL_CONTINUE;
1480 unsigned long temp_eip = 0;
1481 unsigned long temp_eflags = 0;
1482 unsigned long cs = 0;
1483 unsigned long mask = EFLG_CF | EFLG_PF | EFLG_AF | EFLG_ZF | EFLG_SF | EFLG_TF |
1484 EFLG_IF | EFLG_DF | EFLG_OF | EFLG_IOPL | EFLG_NT | EFLG_RF |
1485 EFLG_AC | EFLG_ID | (1 << 1); /* Last one is the reserved bit */
1486 unsigned long vm86_mask = EFLG_VM | EFLG_VIF | EFLG_VIP;
1487
1488 /* TODO: Add stack limit check */
1489
1490 rc = emulate_pop(ctxt, ops, &temp_eip, c->op_bytes);
1491
1492 if (rc != X86EMUL_CONTINUE)
1493 return rc;
1494
1495 if (temp_eip & ~0xffff)
1496 return emulate_gp(ctxt, 0);
1497
1498 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1499
1500 if (rc != X86EMUL_CONTINUE)
1501 return rc;
1502
1503 rc = emulate_pop(ctxt, ops, &temp_eflags, c->op_bytes);
1504
1505 if (rc != X86EMUL_CONTINUE)
1506 return rc;
1507
1508 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
1509
1510 if (rc != X86EMUL_CONTINUE)
1511 return rc;
1512
1513 c->eip = temp_eip;
1514
1515
1516 if (c->op_bytes == 4)
1517 ctxt->eflags = ((temp_eflags & mask) | (ctxt->eflags & vm86_mask));
1518 else if (c->op_bytes == 2) {
1519 ctxt->eflags &= ~0xffff;
1520 ctxt->eflags |= temp_eflags;
1521 }
1522
1523 ctxt->eflags &= ~EFLG_RESERVED_ZEROS_MASK; /* Clear reserved zeros */
1524 ctxt->eflags |= EFLG_RESERVED_ONE_MASK;
1525
1526 return rc;
1527 }
1528
1529 static inline int emulate_iret(struct x86_emulate_ctxt *ctxt,
1530 struct x86_emulate_ops* ops)
1531 {
1532 switch(ctxt->mode) {
1533 case X86EMUL_MODE_REAL:
1534 return emulate_iret_real(ctxt, ops);
1535 case X86EMUL_MODE_VM86:
1536 case X86EMUL_MODE_PROT16:
1537 case X86EMUL_MODE_PROT32:
1538 case X86EMUL_MODE_PROT64:
1539 default:
1540 /* iret from protected mode unimplemented yet */
1541 return X86EMUL_UNHANDLEABLE;
1542 }
1543 }
1544
1545 static inline int emulate_grp1a(struct x86_emulate_ctxt *ctxt,
1546 struct x86_emulate_ops *ops)
1547 {
1548 struct decode_cache *c = &ctxt->decode;
1549
1550 return emulate_pop(ctxt, ops, &c->dst.val, c->dst.bytes);
1551 }
1552
1553 static inline void emulate_grp2(struct x86_emulate_ctxt *ctxt)
1554 {
1555 struct decode_cache *c = &ctxt->decode;
1556 switch (c->modrm_reg) {
1557 case 0: /* rol */
1558 emulate_2op_SrcB("rol", c->src, c->dst, ctxt->eflags);
1559 break;
1560 case 1: /* ror */
1561 emulate_2op_SrcB("ror", c->src, c->dst, ctxt->eflags);
1562 break;
1563 case 2: /* rcl */
1564 emulate_2op_SrcB("rcl", c->src, c->dst, ctxt->eflags);
1565 break;
1566 case 3: /* rcr */
1567 emulate_2op_SrcB("rcr", c->src, c->dst, ctxt->eflags);
1568 break;
1569 case 4: /* sal/shl */
1570 case 6: /* sal/shl */
1571 emulate_2op_SrcB("sal", c->src, c->dst, ctxt->eflags);
1572 break;
1573 case 5: /* shr */
1574 emulate_2op_SrcB("shr", c->src, c->dst, ctxt->eflags);
1575 break;
1576 case 7: /* sar */
1577 emulate_2op_SrcB("sar", c->src, c->dst, ctxt->eflags);
1578 break;
1579 }
1580 }
1581
1582 static inline int emulate_grp3(struct x86_emulate_ctxt *ctxt,
1583 struct x86_emulate_ops *ops)
1584 {
1585 struct decode_cache *c = &ctxt->decode;
1586 unsigned long *rax = &c->regs[VCPU_REGS_RAX];
1587 unsigned long *rdx = &c->regs[VCPU_REGS_RDX];
1588 u8 de = 0;
1589
1590 switch (c->modrm_reg) {
1591 case 0 ... 1: /* test */
1592 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
1593 break;
1594 case 2: /* not */
1595 c->dst.val = ~c->dst.val;
1596 break;
1597 case 3: /* neg */
1598 emulate_1op("neg", c->dst, ctxt->eflags);
1599 break;
1600 case 4: /* mul */
1601 emulate_1op_rax_rdx("mul", c->src, *rax, *rdx, ctxt->eflags);
1602 break;
1603 case 5: /* imul */
1604 emulate_1op_rax_rdx("imul", c->src, *rax, *rdx, ctxt->eflags);
1605 break;
1606 case 6: /* div */
1607 emulate_1op_rax_rdx_ex("div", c->src, *rax, *rdx,
1608 ctxt->eflags, de);
1609 break;
1610 case 7: /* idiv */
1611 emulate_1op_rax_rdx_ex("idiv", c->src, *rax, *rdx,
1612 ctxt->eflags, de);
1613 break;
1614 default:
1615 return X86EMUL_UNHANDLEABLE;
1616 }
1617 if (de)
1618 return emulate_de(ctxt);
1619 return X86EMUL_CONTINUE;
1620 }
1621
1622 static inline int emulate_grp45(struct x86_emulate_ctxt *ctxt,
1623 struct x86_emulate_ops *ops)
1624 {
1625 struct decode_cache *c = &ctxt->decode;
1626
1627 switch (c->modrm_reg) {
1628 case 0: /* inc */
1629 emulate_1op("inc", c->dst, ctxt->eflags);
1630 break;
1631 case 1: /* dec */
1632 emulate_1op("dec", c->dst, ctxt->eflags);
1633 break;
1634 case 2: /* call near abs */ {
1635 long int old_eip;
1636 old_eip = c->eip;
1637 c->eip = c->src.val;
1638 c->src.val = old_eip;
1639 emulate_push(ctxt, ops);
1640 break;
1641 }
1642 case 4: /* jmp abs */
1643 c->eip = c->src.val;
1644 break;
1645 case 6: /* push */
1646 emulate_push(ctxt, ops);
1647 break;
1648 }
1649 return X86EMUL_CONTINUE;
1650 }
1651
1652 static inline int emulate_grp9(struct x86_emulate_ctxt *ctxt,
1653 struct x86_emulate_ops *ops)
1654 {
1655 struct decode_cache *c = &ctxt->decode;
1656 u64 old = c->dst.orig_val64;
1657
1658 if (((u32) (old >> 0) != (u32) c->regs[VCPU_REGS_RAX]) ||
1659 ((u32) (old >> 32) != (u32) c->regs[VCPU_REGS_RDX])) {
1660 c->regs[VCPU_REGS_RAX] = (u32) (old >> 0);
1661 c->regs[VCPU_REGS_RDX] = (u32) (old >> 32);
1662 ctxt->eflags &= ~EFLG_ZF;
1663 } else {
1664 c->dst.val64 = ((u64)c->regs[VCPU_REGS_RCX] << 32) |
1665 (u32) c->regs[VCPU_REGS_RBX];
1666
1667 ctxt->eflags |= EFLG_ZF;
1668 }
1669 return X86EMUL_CONTINUE;
1670 }
1671
1672 static int emulate_ret_far(struct x86_emulate_ctxt *ctxt,
1673 struct x86_emulate_ops *ops)
1674 {
1675 struct decode_cache *c = &ctxt->decode;
1676 int rc;
1677 unsigned long cs;
1678
1679 rc = emulate_pop(ctxt, ops, &c->eip, c->op_bytes);
1680 if (rc != X86EMUL_CONTINUE)
1681 return rc;
1682 if (c->op_bytes == 4)
1683 c->eip = (u32)c->eip;
1684 rc = emulate_pop(ctxt, ops, &cs, c->op_bytes);
1685 if (rc != X86EMUL_CONTINUE)
1686 return rc;
1687 rc = load_segment_descriptor(ctxt, ops, (u16)cs, VCPU_SREG_CS);
1688 return rc;
1689 }
1690
1691 static int emulate_load_segment(struct x86_emulate_ctxt *ctxt,
1692 struct x86_emulate_ops *ops, int seg)
1693 {
1694 struct decode_cache *c = &ctxt->decode;
1695 unsigned short sel;
1696 int rc;
1697
1698 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
1699
1700 rc = load_segment_descriptor(ctxt, ops, sel, seg);
1701 if (rc != X86EMUL_CONTINUE)
1702 return rc;
1703
1704 c->dst.val = c->src.val;
1705 return rc;
1706 }
1707
1708 static inline void
1709 setup_syscalls_segments(struct x86_emulate_ctxt *ctxt,
1710 struct x86_emulate_ops *ops, struct desc_struct *cs,
1711 struct desc_struct *ss)
1712 {
1713 memset(cs, 0, sizeof(struct desc_struct));
1714 ops->get_cached_descriptor(cs, NULL, VCPU_SREG_CS, ctxt->vcpu);
1715 memset(ss, 0, sizeof(struct desc_struct));
1716
1717 cs->l = 0; /* will be adjusted later */
1718 set_desc_base(cs, 0); /* flat segment */
1719 cs->g = 1; /* 4kb granularity */
1720 set_desc_limit(cs, 0xfffff); /* 4GB limit */
1721 cs->type = 0x0b; /* Read, Execute, Accessed */
1722 cs->s = 1;
1723 cs->dpl = 0; /* will be adjusted later */
1724 cs->p = 1;
1725 cs->d = 1;
1726
1727 set_desc_base(ss, 0); /* flat segment */
1728 set_desc_limit(ss, 0xfffff); /* 4GB limit */
1729 ss->g = 1; /* 4kb granularity */
1730 ss->s = 1;
1731 ss->type = 0x03; /* Read/Write, Accessed */
1732 ss->d = 1; /* 32bit stack segment */
1733 ss->dpl = 0;
1734 ss->p = 1;
1735 }
1736
1737 static int
1738 emulate_syscall(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1739 {
1740 struct decode_cache *c = &ctxt->decode;
1741 struct desc_struct cs, ss;
1742 u64 msr_data;
1743 u16 cs_sel, ss_sel;
1744
1745 /* syscall is not available in real mode */
1746 if (ctxt->mode == X86EMUL_MODE_REAL ||
1747 ctxt->mode == X86EMUL_MODE_VM86)
1748 return emulate_ud(ctxt);
1749
1750 setup_syscalls_segments(ctxt, ops, &cs, &ss);
1751
1752 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
1753 msr_data >>= 32;
1754 cs_sel = (u16)(msr_data & 0xfffc);
1755 ss_sel = (u16)(msr_data + 8);
1756
1757 if (is_long_mode(ctxt->vcpu)) {
1758 cs.d = 0;
1759 cs.l = 1;
1760 }
1761 ops->set_cached_descriptor(&cs, 0, VCPU_SREG_CS, ctxt->vcpu);
1762 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1763 ops->set_cached_descriptor(&ss, 0, VCPU_SREG_SS, ctxt->vcpu);
1764 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
1765
1766 c->regs[VCPU_REGS_RCX] = c->eip;
1767 if (is_long_mode(ctxt->vcpu)) {
1768 #ifdef CONFIG_X86_64
1769 c->regs[VCPU_REGS_R11] = ctxt->eflags & ~EFLG_RF;
1770
1771 ops->get_msr(ctxt->vcpu,
1772 ctxt->mode == X86EMUL_MODE_PROT64 ?
1773 MSR_LSTAR : MSR_CSTAR, &msr_data);
1774 c->eip = msr_data;
1775
1776 ops->get_msr(ctxt->vcpu, MSR_SYSCALL_MASK, &msr_data);
1777 ctxt->eflags &= ~(msr_data | EFLG_RF);
1778 #endif
1779 } else {
1780 /* legacy mode */
1781 ops->get_msr(ctxt->vcpu, MSR_STAR, &msr_data);
1782 c->eip = (u32)msr_data;
1783
1784 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1785 }
1786
1787 return X86EMUL_CONTINUE;
1788 }
1789
1790 static int
1791 emulate_sysenter(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1792 {
1793 struct decode_cache *c = &ctxt->decode;
1794 struct desc_struct cs, ss;
1795 u64 msr_data;
1796 u16 cs_sel, ss_sel;
1797
1798 /* inject #GP if in real mode */
1799 if (ctxt->mode == X86EMUL_MODE_REAL)
1800 return emulate_gp(ctxt, 0);
1801
1802 /* XXX sysenter/sysexit have not been tested in 64bit mode.
1803 * Therefore, we inject an #UD.
1804 */
1805 if (ctxt->mode == X86EMUL_MODE_PROT64)
1806 return emulate_ud(ctxt);
1807
1808 setup_syscalls_segments(ctxt, ops, &cs, &ss);
1809
1810 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
1811 switch (ctxt->mode) {
1812 case X86EMUL_MODE_PROT32:
1813 if ((msr_data & 0xfffc) == 0x0)
1814 return emulate_gp(ctxt, 0);
1815 break;
1816 case X86EMUL_MODE_PROT64:
1817 if (msr_data == 0x0)
1818 return emulate_gp(ctxt, 0);
1819 break;
1820 }
1821
1822 ctxt->eflags &= ~(EFLG_VM | EFLG_IF | EFLG_RF);
1823 cs_sel = (u16)msr_data;
1824 cs_sel &= ~SELECTOR_RPL_MASK;
1825 ss_sel = cs_sel + 8;
1826 ss_sel &= ~SELECTOR_RPL_MASK;
1827 if (ctxt->mode == X86EMUL_MODE_PROT64
1828 || is_long_mode(ctxt->vcpu)) {
1829 cs.d = 0;
1830 cs.l = 1;
1831 }
1832
1833 ops->set_cached_descriptor(&cs, 0, VCPU_SREG_CS, ctxt->vcpu);
1834 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1835 ops->set_cached_descriptor(&ss, 0, VCPU_SREG_SS, ctxt->vcpu);
1836 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
1837
1838 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_EIP, &msr_data);
1839 c->eip = msr_data;
1840
1841 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_ESP, &msr_data);
1842 c->regs[VCPU_REGS_RSP] = msr_data;
1843
1844 return X86EMUL_CONTINUE;
1845 }
1846
1847 static int
1848 emulate_sysexit(struct x86_emulate_ctxt *ctxt, struct x86_emulate_ops *ops)
1849 {
1850 struct decode_cache *c = &ctxt->decode;
1851 struct desc_struct cs, ss;
1852 u64 msr_data;
1853 int usermode;
1854 u16 cs_sel, ss_sel;
1855
1856 /* inject #GP if in real mode or Virtual 8086 mode */
1857 if (ctxt->mode == X86EMUL_MODE_REAL ||
1858 ctxt->mode == X86EMUL_MODE_VM86)
1859 return emulate_gp(ctxt, 0);
1860
1861 setup_syscalls_segments(ctxt, ops, &cs, &ss);
1862
1863 if ((c->rex_prefix & 0x8) != 0x0)
1864 usermode = X86EMUL_MODE_PROT64;
1865 else
1866 usermode = X86EMUL_MODE_PROT32;
1867
1868 cs.dpl = 3;
1869 ss.dpl = 3;
1870 ops->get_msr(ctxt->vcpu, MSR_IA32_SYSENTER_CS, &msr_data);
1871 switch (usermode) {
1872 case X86EMUL_MODE_PROT32:
1873 cs_sel = (u16)(msr_data + 16);
1874 if ((msr_data & 0xfffc) == 0x0)
1875 return emulate_gp(ctxt, 0);
1876 ss_sel = (u16)(msr_data + 24);
1877 break;
1878 case X86EMUL_MODE_PROT64:
1879 cs_sel = (u16)(msr_data + 32);
1880 if (msr_data == 0x0)
1881 return emulate_gp(ctxt, 0);
1882 ss_sel = cs_sel + 8;
1883 cs.d = 0;
1884 cs.l = 1;
1885 break;
1886 }
1887 cs_sel |= SELECTOR_RPL_MASK;
1888 ss_sel |= SELECTOR_RPL_MASK;
1889
1890 ops->set_cached_descriptor(&cs, 0, VCPU_SREG_CS, ctxt->vcpu);
1891 ops->set_segment_selector(cs_sel, VCPU_SREG_CS, ctxt->vcpu);
1892 ops->set_cached_descriptor(&ss, 0, VCPU_SREG_SS, ctxt->vcpu);
1893 ops->set_segment_selector(ss_sel, VCPU_SREG_SS, ctxt->vcpu);
1894
1895 c->eip = c->regs[VCPU_REGS_RDX];
1896 c->regs[VCPU_REGS_RSP] = c->regs[VCPU_REGS_RCX];
1897
1898 return X86EMUL_CONTINUE;
1899 }
1900
1901 static bool emulator_bad_iopl(struct x86_emulate_ctxt *ctxt,
1902 struct x86_emulate_ops *ops)
1903 {
1904 int iopl;
1905 if (ctxt->mode == X86EMUL_MODE_REAL)
1906 return false;
1907 if (ctxt->mode == X86EMUL_MODE_VM86)
1908 return true;
1909 iopl = (ctxt->eflags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1910 return ops->cpl(ctxt->vcpu) > iopl;
1911 }
1912
1913 static bool emulator_io_port_access_allowed(struct x86_emulate_ctxt *ctxt,
1914 struct x86_emulate_ops *ops,
1915 u16 port, u16 len)
1916 {
1917 struct desc_struct tr_seg;
1918 u32 base3;
1919 int r;
1920 u16 io_bitmap_ptr, perm, bit_idx = port & 0x7;
1921 unsigned mask = (1 << len) - 1;
1922 unsigned long base;
1923
1924 ops->get_cached_descriptor(&tr_seg, &base3, VCPU_SREG_TR, ctxt->vcpu);
1925 if (!tr_seg.p)
1926 return false;
1927 if (desc_limit_scaled(&tr_seg) < 103)
1928 return false;
1929 base = get_desc_base(&tr_seg);
1930 #ifdef CONFIG_X86_64
1931 base |= ((u64)base3) << 32;
1932 #endif
1933 r = ops->read_std(base + 102, &io_bitmap_ptr, 2, ctxt->vcpu, NULL);
1934 if (r != X86EMUL_CONTINUE)
1935 return false;
1936 if (io_bitmap_ptr + port/8 > desc_limit_scaled(&tr_seg))
1937 return false;
1938 r = ops->read_std(base + io_bitmap_ptr + port/8, &perm, 2, ctxt->vcpu,
1939 NULL);
1940 if (r != X86EMUL_CONTINUE)
1941 return false;
1942 if ((perm >> bit_idx) & mask)
1943 return false;
1944 return true;
1945 }
1946
1947 static bool emulator_io_permited(struct x86_emulate_ctxt *ctxt,
1948 struct x86_emulate_ops *ops,
1949 u16 port, u16 len)
1950 {
1951 if (ctxt->perm_ok)
1952 return true;
1953
1954 if (emulator_bad_iopl(ctxt, ops))
1955 if (!emulator_io_port_access_allowed(ctxt, ops, port, len))
1956 return false;
1957
1958 ctxt->perm_ok = true;
1959
1960 return true;
1961 }
1962
1963 static void save_state_to_tss16(struct x86_emulate_ctxt *ctxt,
1964 struct x86_emulate_ops *ops,
1965 struct tss_segment_16 *tss)
1966 {
1967 struct decode_cache *c = &ctxt->decode;
1968
1969 tss->ip = c->eip;
1970 tss->flag = ctxt->eflags;
1971 tss->ax = c->regs[VCPU_REGS_RAX];
1972 tss->cx = c->regs[VCPU_REGS_RCX];
1973 tss->dx = c->regs[VCPU_REGS_RDX];
1974 tss->bx = c->regs[VCPU_REGS_RBX];
1975 tss->sp = c->regs[VCPU_REGS_RSP];
1976 tss->bp = c->regs[VCPU_REGS_RBP];
1977 tss->si = c->regs[VCPU_REGS_RSI];
1978 tss->di = c->regs[VCPU_REGS_RDI];
1979
1980 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
1981 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
1982 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
1983 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
1984 tss->ldt = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
1985 }
1986
1987 static int load_state_from_tss16(struct x86_emulate_ctxt *ctxt,
1988 struct x86_emulate_ops *ops,
1989 struct tss_segment_16 *tss)
1990 {
1991 struct decode_cache *c = &ctxt->decode;
1992 int ret;
1993
1994 c->eip = tss->ip;
1995 ctxt->eflags = tss->flag | 2;
1996 c->regs[VCPU_REGS_RAX] = tss->ax;
1997 c->regs[VCPU_REGS_RCX] = tss->cx;
1998 c->regs[VCPU_REGS_RDX] = tss->dx;
1999 c->regs[VCPU_REGS_RBX] = tss->bx;
2000 c->regs[VCPU_REGS_RSP] = tss->sp;
2001 c->regs[VCPU_REGS_RBP] = tss->bp;
2002 c->regs[VCPU_REGS_RSI] = tss->si;
2003 c->regs[VCPU_REGS_RDI] = tss->di;
2004
2005 /*
2006 * SDM says that segment selectors are loaded before segment
2007 * descriptors
2008 */
2009 ops->set_segment_selector(tss->ldt, VCPU_SREG_LDTR, ctxt->vcpu);
2010 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2011 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2012 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2013 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2014
2015 /*
2016 * Now load segment descriptors. If fault happenes at this stage
2017 * it is handled in a context of new task
2018 */
2019 ret = load_segment_descriptor(ctxt, ops, tss->ldt, VCPU_SREG_LDTR);
2020 if (ret != X86EMUL_CONTINUE)
2021 return ret;
2022 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2023 if (ret != X86EMUL_CONTINUE)
2024 return ret;
2025 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2026 if (ret != X86EMUL_CONTINUE)
2027 return ret;
2028 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2029 if (ret != X86EMUL_CONTINUE)
2030 return ret;
2031 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2032 if (ret != X86EMUL_CONTINUE)
2033 return ret;
2034
2035 return X86EMUL_CONTINUE;
2036 }
2037
2038 static int task_switch_16(struct x86_emulate_ctxt *ctxt,
2039 struct x86_emulate_ops *ops,
2040 u16 tss_selector, u16 old_tss_sel,
2041 ulong old_tss_base, struct desc_struct *new_desc)
2042 {
2043 struct tss_segment_16 tss_seg;
2044 int ret;
2045 u32 new_tss_base = get_desc_base(new_desc);
2046
2047 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2048 &ctxt->exception);
2049 if (ret != X86EMUL_CONTINUE)
2050 /* FIXME: need to provide precise fault address */
2051 return ret;
2052
2053 save_state_to_tss16(ctxt, ops, &tss_seg);
2054
2055 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2056 &ctxt->exception);
2057 if (ret != X86EMUL_CONTINUE)
2058 /* FIXME: need to provide precise fault address */
2059 return ret;
2060
2061 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2062 &ctxt->exception);
2063 if (ret != X86EMUL_CONTINUE)
2064 /* FIXME: need to provide precise fault address */
2065 return ret;
2066
2067 if (old_tss_sel != 0xffff) {
2068 tss_seg.prev_task_link = old_tss_sel;
2069
2070 ret = ops->write_std(new_tss_base,
2071 &tss_seg.prev_task_link,
2072 sizeof tss_seg.prev_task_link,
2073 ctxt->vcpu, &ctxt->exception);
2074 if (ret != X86EMUL_CONTINUE)
2075 /* FIXME: need to provide precise fault address */
2076 return ret;
2077 }
2078
2079 return load_state_from_tss16(ctxt, ops, &tss_seg);
2080 }
2081
2082 static void save_state_to_tss32(struct x86_emulate_ctxt *ctxt,
2083 struct x86_emulate_ops *ops,
2084 struct tss_segment_32 *tss)
2085 {
2086 struct decode_cache *c = &ctxt->decode;
2087
2088 tss->cr3 = ops->get_cr(3, ctxt->vcpu);
2089 tss->eip = c->eip;
2090 tss->eflags = ctxt->eflags;
2091 tss->eax = c->regs[VCPU_REGS_RAX];
2092 tss->ecx = c->regs[VCPU_REGS_RCX];
2093 tss->edx = c->regs[VCPU_REGS_RDX];
2094 tss->ebx = c->regs[VCPU_REGS_RBX];
2095 tss->esp = c->regs[VCPU_REGS_RSP];
2096 tss->ebp = c->regs[VCPU_REGS_RBP];
2097 tss->esi = c->regs[VCPU_REGS_RSI];
2098 tss->edi = c->regs[VCPU_REGS_RDI];
2099
2100 tss->es = ops->get_segment_selector(VCPU_SREG_ES, ctxt->vcpu);
2101 tss->cs = ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2102 tss->ss = ops->get_segment_selector(VCPU_SREG_SS, ctxt->vcpu);
2103 tss->ds = ops->get_segment_selector(VCPU_SREG_DS, ctxt->vcpu);
2104 tss->fs = ops->get_segment_selector(VCPU_SREG_FS, ctxt->vcpu);
2105 tss->gs = ops->get_segment_selector(VCPU_SREG_GS, ctxt->vcpu);
2106 tss->ldt_selector = ops->get_segment_selector(VCPU_SREG_LDTR, ctxt->vcpu);
2107 }
2108
2109 static int load_state_from_tss32(struct x86_emulate_ctxt *ctxt,
2110 struct x86_emulate_ops *ops,
2111 struct tss_segment_32 *tss)
2112 {
2113 struct decode_cache *c = &ctxt->decode;
2114 int ret;
2115
2116 if (ops->set_cr(3, tss->cr3, ctxt->vcpu))
2117 return emulate_gp(ctxt, 0);
2118 c->eip = tss->eip;
2119 ctxt->eflags = tss->eflags | 2;
2120 c->regs[VCPU_REGS_RAX] = tss->eax;
2121 c->regs[VCPU_REGS_RCX] = tss->ecx;
2122 c->regs[VCPU_REGS_RDX] = tss->edx;
2123 c->regs[VCPU_REGS_RBX] = tss->ebx;
2124 c->regs[VCPU_REGS_RSP] = tss->esp;
2125 c->regs[VCPU_REGS_RBP] = tss->ebp;
2126 c->regs[VCPU_REGS_RSI] = tss->esi;
2127 c->regs[VCPU_REGS_RDI] = tss->edi;
2128
2129 /*
2130 * SDM says that segment selectors are loaded before segment
2131 * descriptors
2132 */
2133 ops->set_segment_selector(tss->ldt_selector, VCPU_SREG_LDTR, ctxt->vcpu);
2134 ops->set_segment_selector(tss->es, VCPU_SREG_ES, ctxt->vcpu);
2135 ops->set_segment_selector(tss->cs, VCPU_SREG_CS, ctxt->vcpu);
2136 ops->set_segment_selector(tss->ss, VCPU_SREG_SS, ctxt->vcpu);
2137 ops->set_segment_selector(tss->ds, VCPU_SREG_DS, ctxt->vcpu);
2138 ops->set_segment_selector(tss->fs, VCPU_SREG_FS, ctxt->vcpu);
2139 ops->set_segment_selector(tss->gs, VCPU_SREG_GS, ctxt->vcpu);
2140
2141 /*
2142 * Now load segment descriptors. If fault happenes at this stage
2143 * it is handled in a context of new task
2144 */
2145 ret = load_segment_descriptor(ctxt, ops, tss->ldt_selector, VCPU_SREG_LDTR);
2146 if (ret != X86EMUL_CONTINUE)
2147 return ret;
2148 ret = load_segment_descriptor(ctxt, ops, tss->es, VCPU_SREG_ES);
2149 if (ret != X86EMUL_CONTINUE)
2150 return ret;
2151 ret = load_segment_descriptor(ctxt, ops, tss->cs, VCPU_SREG_CS);
2152 if (ret != X86EMUL_CONTINUE)
2153 return ret;
2154 ret = load_segment_descriptor(ctxt, ops, tss->ss, VCPU_SREG_SS);
2155 if (ret != X86EMUL_CONTINUE)
2156 return ret;
2157 ret = load_segment_descriptor(ctxt, ops, tss->ds, VCPU_SREG_DS);
2158 if (ret != X86EMUL_CONTINUE)
2159 return ret;
2160 ret = load_segment_descriptor(ctxt, ops, tss->fs, VCPU_SREG_FS);
2161 if (ret != X86EMUL_CONTINUE)
2162 return ret;
2163 ret = load_segment_descriptor(ctxt, ops, tss->gs, VCPU_SREG_GS);
2164 if (ret != X86EMUL_CONTINUE)
2165 return ret;
2166
2167 return X86EMUL_CONTINUE;
2168 }
2169
2170 static int task_switch_32(struct x86_emulate_ctxt *ctxt,
2171 struct x86_emulate_ops *ops,
2172 u16 tss_selector, u16 old_tss_sel,
2173 ulong old_tss_base, struct desc_struct *new_desc)
2174 {
2175 struct tss_segment_32 tss_seg;
2176 int ret;
2177 u32 new_tss_base = get_desc_base(new_desc);
2178
2179 ret = ops->read_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2180 &ctxt->exception);
2181 if (ret != X86EMUL_CONTINUE)
2182 /* FIXME: need to provide precise fault address */
2183 return ret;
2184
2185 save_state_to_tss32(ctxt, ops, &tss_seg);
2186
2187 ret = ops->write_std(old_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2188 &ctxt->exception);
2189 if (ret != X86EMUL_CONTINUE)
2190 /* FIXME: need to provide precise fault address */
2191 return ret;
2192
2193 ret = ops->read_std(new_tss_base, &tss_seg, sizeof tss_seg, ctxt->vcpu,
2194 &ctxt->exception);
2195 if (ret != X86EMUL_CONTINUE)
2196 /* FIXME: need to provide precise fault address */
2197 return ret;
2198
2199 if (old_tss_sel != 0xffff) {
2200 tss_seg.prev_task_link = old_tss_sel;
2201
2202 ret = ops->write_std(new_tss_base,
2203 &tss_seg.prev_task_link,
2204 sizeof tss_seg.prev_task_link,
2205 ctxt->vcpu, &ctxt->exception);
2206 if (ret != X86EMUL_CONTINUE)
2207 /* FIXME: need to provide precise fault address */
2208 return ret;
2209 }
2210
2211 return load_state_from_tss32(ctxt, ops, &tss_seg);
2212 }
2213
2214 static int emulator_do_task_switch(struct x86_emulate_ctxt *ctxt,
2215 struct x86_emulate_ops *ops,
2216 u16 tss_selector, int reason,
2217 bool has_error_code, u32 error_code)
2218 {
2219 struct desc_struct curr_tss_desc, next_tss_desc;
2220 int ret;
2221 u16 old_tss_sel = ops->get_segment_selector(VCPU_SREG_TR, ctxt->vcpu);
2222 ulong old_tss_base =
2223 ops->get_cached_segment_base(VCPU_SREG_TR, ctxt->vcpu);
2224 u32 desc_limit;
2225
2226 /* FIXME: old_tss_base == ~0 ? */
2227
2228 ret = read_segment_descriptor(ctxt, ops, tss_selector, &next_tss_desc);
2229 if (ret != X86EMUL_CONTINUE)
2230 return ret;
2231 ret = read_segment_descriptor(ctxt, ops, old_tss_sel, &curr_tss_desc);
2232 if (ret != X86EMUL_CONTINUE)
2233 return ret;
2234
2235 /* FIXME: check that next_tss_desc is tss */
2236
2237 if (reason != TASK_SWITCH_IRET) {
2238 if ((tss_selector & 3) > next_tss_desc.dpl ||
2239 ops->cpl(ctxt->vcpu) > next_tss_desc.dpl)
2240 return emulate_gp(ctxt, 0);
2241 }
2242
2243 desc_limit = desc_limit_scaled(&next_tss_desc);
2244 if (!next_tss_desc.p ||
2245 ((desc_limit < 0x67 && (next_tss_desc.type & 8)) ||
2246 desc_limit < 0x2b)) {
2247 emulate_ts(ctxt, tss_selector & 0xfffc);
2248 return X86EMUL_PROPAGATE_FAULT;
2249 }
2250
2251 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
2252 curr_tss_desc.type &= ~(1 << 1); /* clear busy flag */
2253 write_segment_descriptor(ctxt, ops, old_tss_sel,
2254 &curr_tss_desc);
2255 }
2256
2257 if (reason == TASK_SWITCH_IRET)
2258 ctxt->eflags = ctxt->eflags & ~X86_EFLAGS_NT;
2259
2260 /* set back link to prev task only if NT bit is set in eflags
2261 note that old_tss_sel is not used afetr this point */
2262 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
2263 old_tss_sel = 0xffff;
2264
2265 if (next_tss_desc.type & 8)
2266 ret = task_switch_32(ctxt, ops, tss_selector, old_tss_sel,
2267 old_tss_base, &next_tss_desc);
2268 else
2269 ret = task_switch_16(ctxt, ops, tss_selector, old_tss_sel,
2270 old_tss_base, &next_tss_desc);
2271 if (ret != X86EMUL_CONTINUE)
2272 return ret;
2273
2274 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE)
2275 ctxt->eflags = ctxt->eflags | X86_EFLAGS_NT;
2276
2277 if (reason != TASK_SWITCH_IRET) {
2278 next_tss_desc.type |= (1 << 1); /* set busy flag */
2279 write_segment_descriptor(ctxt, ops, tss_selector,
2280 &next_tss_desc);
2281 }
2282
2283 ops->set_cr(0, ops->get_cr(0, ctxt->vcpu) | X86_CR0_TS, ctxt->vcpu);
2284 ops->set_cached_descriptor(&next_tss_desc, 0, VCPU_SREG_TR, ctxt->vcpu);
2285 ops->set_segment_selector(tss_selector, VCPU_SREG_TR, ctxt->vcpu);
2286
2287 if (has_error_code) {
2288 struct decode_cache *c = &ctxt->decode;
2289
2290 c->op_bytes = c->ad_bytes = (next_tss_desc.type & 8) ? 4 : 2;
2291 c->lock_prefix = 0;
2292 c->src.val = (unsigned long) error_code;
2293 emulate_push(ctxt, ops);
2294 }
2295
2296 return ret;
2297 }
2298
2299 int emulator_task_switch(struct x86_emulate_ctxt *ctxt,
2300 u16 tss_selector, int reason,
2301 bool has_error_code, u32 error_code)
2302 {
2303 struct x86_emulate_ops *ops = ctxt->ops;
2304 struct decode_cache *c = &ctxt->decode;
2305 int rc;
2306
2307 c->eip = ctxt->eip;
2308 c->dst.type = OP_NONE;
2309
2310 rc = emulator_do_task_switch(ctxt, ops, tss_selector, reason,
2311 has_error_code, error_code);
2312
2313 if (rc == X86EMUL_CONTINUE) {
2314 rc = writeback(ctxt, ops);
2315 if (rc == X86EMUL_CONTINUE)
2316 ctxt->eip = c->eip;
2317 }
2318
2319 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
2320 }
2321
2322 static void string_addr_inc(struct x86_emulate_ctxt *ctxt, unsigned seg,
2323 int reg, struct operand *op)
2324 {
2325 struct decode_cache *c = &ctxt->decode;
2326 int df = (ctxt->eflags & EFLG_DF) ? -1 : 1;
2327
2328 register_address_increment(c, &c->regs[reg], df * op->bytes);
2329 op->addr.mem.ea = register_address(c, c->regs[reg]);
2330 op->addr.mem.seg = seg;
2331 }
2332
2333 static int em_push(struct x86_emulate_ctxt *ctxt)
2334 {
2335 emulate_push(ctxt, ctxt->ops);
2336 return X86EMUL_CONTINUE;
2337 }
2338
2339 static int em_das(struct x86_emulate_ctxt *ctxt)
2340 {
2341 struct decode_cache *c = &ctxt->decode;
2342 u8 al, old_al;
2343 bool af, cf, old_cf;
2344
2345 cf = ctxt->eflags & X86_EFLAGS_CF;
2346 al = c->dst.val;
2347
2348 old_al = al;
2349 old_cf = cf;
2350 cf = false;
2351 af = ctxt->eflags & X86_EFLAGS_AF;
2352 if ((al & 0x0f) > 9 || af) {
2353 al -= 6;
2354 cf = old_cf | (al >= 250);
2355 af = true;
2356 } else {
2357 af = false;
2358 }
2359 if (old_al > 0x99 || old_cf) {
2360 al -= 0x60;
2361 cf = true;
2362 }
2363
2364 c->dst.val = al;
2365 /* Set PF, ZF, SF */
2366 c->src.type = OP_IMM;
2367 c->src.val = 0;
2368 c->src.bytes = 1;
2369 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
2370 ctxt->eflags &= ~(X86_EFLAGS_AF | X86_EFLAGS_CF);
2371 if (cf)
2372 ctxt->eflags |= X86_EFLAGS_CF;
2373 if (af)
2374 ctxt->eflags |= X86_EFLAGS_AF;
2375 return X86EMUL_CONTINUE;
2376 }
2377
2378 static int em_call_far(struct x86_emulate_ctxt *ctxt)
2379 {
2380 struct decode_cache *c = &ctxt->decode;
2381 u16 sel, old_cs;
2382 ulong old_eip;
2383 int rc;
2384
2385 old_cs = ctxt->ops->get_segment_selector(VCPU_SREG_CS, ctxt->vcpu);
2386 old_eip = c->eip;
2387
2388 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
2389 if (load_segment_descriptor(ctxt, ctxt->ops, sel, VCPU_SREG_CS))
2390 return X86EMUL_CONTINUE;
2391
2392 c->eip = 0;
2393 memcpy(&c->eip, c->src.valptr, c->op_bytes);
2394
2395 c->src.val = old_cs;
2396 emulate_push(ctxt, ctxt->ops);
2397 rc = writeback(ctxt, ctxt->ops);
2398 if (rc != X86EMUL_CONTINUE)
2399 return rc;
2400
2401 c->src.val = old_eip;
2402 emulate_push(ctxt, ctxt->ops);
2403 rc = writeback(ctxt, ctxt->ops);
2404 if (rc != X86EMUL_CONTINUE)
2405 return rc;
2406
2407 c->dst.type = OP_NONE;
2408
2409 return X86EMUL_CONTINUE;
2410 }
2411
2412 static int em_ret_near_imm(struct x86_emulate_ctxt *ctxt)
2413 {
2414 struct decode_cache *c = &ctxt->decode;
2415 int rc;
2416
2417 c->dst.type = OP_REG;
2418 c->dst.addr.reg = &c->eip;
2419 c->dst.bytes = c->op_bytes;
2420 rc = emulate_pop(ctxt, ctxt->ops, &c->dst.val, c->op_bytes);
2421 if (rc != X86EMUL_CONTINUE)
2422 return rc;
2423 register_address_increment(c, &c->regs[VCPU_REGS_RSP], c->src.val);
2424 return X86EMUL_CONTINUE;
2425 }
2426
2427 static int em_imul(struct x86_emulate_ctxt *ctxt)
2428 {
2429 struct decode_cache *c = &ctxt->decode;
2430
2431 emulate_2op_SrcV_nobyte("imul", c->src, c->dst, ctxt->eflags);
2432 return X86EMUL_CONTINUE;
2433 }
2434
2435 static int em_imul_3op(struct x86_emulate_ctxt *ctxt)
2436 {
2437 struct decode_cache *c = &ctxt->decode;
2438
2439 c->dst.val = c->src2.val;
2440 return em_imul(ctxt);
2441 }
2442
2443 static int em_cwd(struct x86_emulate_ctxt *ctxt)
2444 {
2445 struct decode_cache *c = &ctxt->decode;
2446
2447 c->dst.type = OP_REG;
2448 c->dst.bytes = c->src.bytes;
2449 c->dst.addr.reg = &c->regs[VCPU_REGS_RDX];
2450 c->dst.val = ~((c->src.val >> (c->src.bytes * 8 - 1)) - 1);
2451
2452 return X86EMUL_CONTINUE;
2453 }
2454
2455 static int em_rdtsc(struct x86_emulate_ctxt *ctxt)
2456 {
2457 struct decode_cache *c = &ctxt->decode;
2458 u64 tsc = 0;
2459
2460 ctxt->ops->get_msr(ctxt->vcpu, MSR_IA32_TSC, &tsc);
2461 c->regs[VCPU_REGS_RAX] = (u32)tsc;
2462 c->regs[VCPU_REGS_RDX] = tsc >> 32;
2463 return X86EMUL_CONTINUE;
2464 }
2465
2466 static int em_mov(struct x86_emulate_ctxt *ctxt)
2467 {
2468 struct decode_cache *c = &ctxt->decode;
2469 c->dst.val = c->src.val;
2470 return X86EMUL_CONTINUE;
2471 }
2472
2473 static int em_movdqu(struct x86_emulate_ctxt *ctxt)
2474 {
2475 struct decode_cache *c = &ctxt->decode;
2476 memcpy(&c->dst.vec_val, &c->src.vec_val, c->op_bytes);
2477 return X86EMUL_CONTINUE;
2478 }
2479
2480 static int em_invlpg(struct x86_emulate_ctxt *ctxt)
2481 {
2482 struct decode_cache *c = &ctxt->decode;
2483 emulate_invlpg(ctxt->vcpu, linear(ctxt, c->src.addr.mem));
2484 /* Disable writeback. */
2485 c->dst.type = OP_NONE;
2486 return X86EMUL_CONTINUE;
2487 }
2488
2489 static bool valid_cr(int nr)
2490 {
2491 switch (nr) {
2492 case 0:
2493 case 2 ... 4:
2494 case 8:
2495 return true;
2496 default:
2497 return false;
2498 }
2499 }
2500
2501 static int check_cr_read(struct x86_emulate_ctxt *ctxt)
2502 {
2503 struct decode_cache *c = &ctxt->decode;
2504
2505 if (!valid_cr(c->modrm_reg))
2506 return emulate_ud(ctxt);
2507
2508 return X86EMUL_CONTINUE;
2509 }
2510
2511 static int check_cr_write(struct x86_emulate_ctxt *ctxt)
2512 {
2513 struct decode_cache *c = &ctxt->decode;
2514 u64 new_val = c->src.val64;
2515 int cr = c->modrm_reg;
2516
2517 static u64 cr_reserved_bits[] = {
2518 0xffffffff00000000ULL,
2519 0, 0, 0, /* CR3 checked later */
2520 CR4_RESERVED_BITS,
2521 0, 0, 0,
2522 CR8_RESERVED_BITS,
2523 };
2524
2525 if (!valid_cr(cr))
2526 return emulate_ud(ctxt);
2527
2528 if (new_val & cr_reserved_bits[cr])
2529 return emulate_gp(ctxt, 0);
2530
2531 switch (cr) {
2532 case 0: {
2533 u64 cr4, efer;
2534 if (((new_val & X86_CR0_PG) && !(new_val & X86_CR0_PE)) ||
2535 ((new_val & X86_CR0_NW) && !(new_val & X86_CR0_CD)))
2536 return emulate_gp(ctxt, 0);
2537
2538 cr4 = ctxt->ops->get_cr(4, ctxt->vcpu);
2539 ctxt->ops->get_msr(ctxt->vcpu, MSR_EFER, &efer);
2540
2541 if ((new_val & X86_CR0_PG) && (efer & EFER_LME) &&
2542 !(cr4 & X86_CR4_PAE))
2543 return emulate_gp(ctxt, 0);
2544
2545 break;
2546 }
2547 case 3: {
2548 u64 rsvd = 0;
2549
2550 if (is_long_mode(ctxt->vcpu))
2551 rsvd = CR3_L_MODE_RESERVED_BITS;
2552 else if (is_pae(ctxt->vcpu))
2553 rsvd = CR3_PAE_RESERVED_BITS;
2554 else if (is_paging(ctxt->vcpu))
2555 rsvd = CR3_NONPAE_RESERVED_BITS;
2556
2557 if (new_val & rsvd)
2558 return emulate_gp(ctxt, 0);
2559
2560 break;
2561 }
2562 case 4: {
2563 u64 cr4, efer;
2564
2565 cr4 = ctxt->ops->get_cr(4, ctxt->vcpu);
2566 ctxt->ops->get_msr(ctxt->vcpu, MSR_EFER, &efer);
2567
2568 if ((efer & EFER_LMA) && !(new_val & X86_CR4_PAE))
2569 return emulate_gp(ctxt, 0);
2570
2571 break;
2572 }
2573 }
2574
2575 return X86EMUL_CONTINUE;
2576 }
2577
2578 static int check_dr7_gd(struct x86_emulate_ctxt *ctxt)
2579 {
2580 unsigned long dr7;
2581
2582 ctxt->ops->get_dr(7, &dr7, ctxt->vcpu);
2583
2584 /* Check if DR7.Global_Enable is set */
2585 return dr7 & (1 << 13);
2586 }
2587
2588 static int check_dr_read(struct x86_emulate_ctxt *ctxt)
2589 {
2590 struct decode_cache *c = &ctxt->decode;
2591 int dr = c->modrm_reg;
2592 u64 cr4;
2593
2594 if (dr > 7)
2595 return emulate_ud(ctxt);
2596
2597 cr4 = ctxt->ops->get_cr(4, ctxt->vcpu);
2598 if ((cr4 & X86_CR4_DE) && (dr == 4 || dr == 5))
2599 return emulate_ud(ctxt);
2600
2601 if (check_dr7_gd(ctxt))
2602 return emulate_db(ctxt);
2603
2604 return X86EMUL_CONTINUE;
2605 }
2606
2607 static int check_dr_write(struct x86_emulate_ctxt *ctxt)
2608 {
2609 struct decode_cache *c = &ctxt->decode;
2610 u64 new_val = c->src.val64;
2611 int dr = c->modrm_reg;
2612
2613 if ((dr == 6 || dr == 7) && (new_val & 0xffffffff00000000ULL))
2614 return emulate_gp(ctxt, 0);
2615
2616 return check_dr_read(ctxt);
2617 }
2618
2619 static int check_svme(struct x86_emulate_ctxt *ctxt)
2620 {
2621 u64 efer;
2622
2623 ctxt->ops->get_msr(ctxt->vcpu, MSR_EFER, &efer);
2624
2625 if (!(efer & EFER_SVME))
2626 return emulate_ud(ctxt);
2627
2628 return X86EMUL_CONTINUE;
2629 }
2630
2631 static int check_svme_pa(struct x86_emulate_ctxt *ctxt)
2632 {
2633 u64 rax = kvm_register_read(ctxt->vcpu, VCPU_REGS_RAX);
2634
2635 /* Valid physical address? */
2636 if (rax & 0xffff000000000000)
2637 return emulate_gp(ctxt, 0);
2638
2639 return check_svme(ctxt);
2640 }
2641
2642 static int check_rdtsc(struct x86_emulate_ctxt *ctxt)
2643 {
2644 u64 cr4 = ctxt->ops->get_cr(4, ctxt->vcpu);
2645
2646 if (cr4 & X86_CR4_TSD && ctxt->ops->cpl(ctxt->vcpu))
2647 return emulate_ud(ctxt);
2648
2649 return X86EMUL_CONTINUE;
2650 }
2651
2652 static int check_rdpmc(struct x86_emulate_ctxt *ctxt)
2653 {
2654 u64 cr4 = ctxt->ops->get_cr(4, ctxt->vcpu);
2655 u64 rcx = kvm_register_read(ctxt->vcpu, VCPU_REGS_RCX);
2656
2657 if ((!(cr4 & X86_CR4_PCE) && ctxt->ops->cpl(ctxt->vcpu)) ||
2658 (rcx > 3))
2659 return emulate_gp(ctxt, 0);
2660
2661 return X86EMUL_CONTINUE;
2662 }
2663
2664 static int check_perm_in(struct x86_emulate_ctxt *ctxt)
2665 {
2666 struct decode_cache *c = &ctxt->decode;
2667
2668 c->dst.bytes = min(c->dst.bytes, 4u);
2669 if (!emulator_io_permited(ctxt, ctxt->ops, c->src.val, c->dst.bytes))
2670 return emulate_gp(ctxt, 0);
2671
2672 return X86EMUL_CONTINUE;
2673 }
2674
2675 static int check_perm_out(struct x86_emulate_ctxt *ctxt)
2676 {
2677 struct decode_cache *c = &ctxt->decode;
2678
2679 c->src.bytes = min(c->src.bytes, 4u);
2680 if (!emulator_io_permited(ctxt, ctxt->ops, c->dst.val, c->src.bytes))
2681 return emulate_gp(ctxt, 0);
2682
2683 return X86EMUL_CONTINUE;
2684 }
2685
2686 #define D(_y) { .flags = (_y) }
2687 #define DI(_y, _i) { .flags = (_y), .intercept = x86_intercept_##_i }
2688 #define DIP(_y, _i, _p) { .flags = (_y), .intercept = x86_intercept_##_i, \
2689 .check_perm = (_p) }
2690 #define N D(0)
2691 #define EXT(_f, _e) { .flags = ((_f) | RMExt), .u.group = (_e) }
2692 #define G(_f, _g) { .flags = ((_f) | Group), .u.group = (_g) }
2693 #define GD(_f, _g) { .flags = ((_f) | Group | GroupDual), .u.gdual = (_g) }
2694 #define I(_f, _e) { .flags = (_f), .u.execute = (_e) }
2695 #define II(_f, _e, _i) \
2696 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i }
2697 #define IIP(_f, _e, _i, _p) \
2698 { .flags = (_f), .u.execute = (_e), .intercept = x86_intercept_##_i, \
2699 .check_perm = (_p) }
2700 #define GP(_f, _g) { .flags = ((_f) | Prefix), .u.gprefix = (_g) }
2701
2702 #define D2bv(_f) D((_f) | ByteOp), D(_f)
2703 #define D2bvIP(_f, _i, _p) DIP((_f) | ByteOp, _i, _p), DIP(_f, _i, _p)
2704 #define I2bv(_f, _e) I((_f) | ByteOp, _e), I(_f, _e)
2705
2706 #define D6ALU(_f) D2bv((_f) | DstMem | SrcReg | ModRM), \
2707 D2bv(((_f) | DstReg | SrcMem | ModRM) & ~Lock), \
2708 D2bv(((_f) & ~Lock) | DstAcc | SrcImm)
2709
2710 static struct opcode group7_rm1[] = {
2711 DI(SrcNone | ModRM | Priv, monitor),
2712 DI(SrcNone | ModRM | Priv, mwait),
2713 N, N, N, N, N, N,
2714 };
2715
2716 static struct opcode group7_rm3[] = {
2717 DIP(SrcNone | ModRM | Prot | Priv, vmrun, check_svme_pa),
2718 DI(SrcNone | ModRM | Prot | VendorSpecific, vmmcall),
2719 DIP(SrcNone | ModRM | Prot | Priv, vmload, check_svme_pa),
2720 DIP(SrcNone | ModRM | Prot | Priv, vmsave, check_svme_pa),
2721 DIP(SrcNone | ModRM | Prot | Priv, stgi, check_svme),
2722 DIP(SrcNone | ModRM | Prot | Priv, clgi, check_svme),
2723 DIP(SrcNone | ModRM | Prot | Priv, skinit, check_svme),
2724 DIP(SrcNone | ModRM | Prot | Priv, invlpga, check_svme),
2725 };
2726
2727 static struct opcode group7_rm7[] = {
2728 N,
2729 DIP(SrcNone | ModRM, rdtscp, check_rdtsc),
2730 N, N, N, N, N, N,
2731 };
2732 static struct opcode group1[] = {
2733 X7(D(Lock)), N
2734 };
2735
2736 static struct opcode group1A[] = {
2737 D(DstMem | SrcNone | ModRM | Mov | Stack), N, N, N, N, N, N, N,
2738 };
2739
2740 static struct opcode group3[] = {
2741 D(DstMem | SrcImm | ModRM), D(DstMem | SrcImm | ModRM),
2742 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
2743 X4(D(SrcMem | ModRM)),
2744 };
2745
2746 static struct opcode group4[] = {
2747 D(ByteOp | DstMem | SrcNone | ModRM | Lock), D(ByteOp | DstMem | SrcNone | ModRM | Lock),
2748 N, N, N, N, N, N,
2749 };
2750
2751 static struct opcode group5[] = {
2752 D(DstMem | SrcNone | ModRM | Lock), D(DstMem | SrcNone | ModRM | Lock),
2753 D(SrcMem | ModRM | Stack),
2754 I(SrcMemFAddr | ModRM | ImplicitOps | Stack, em_call_far),
2755 D(SrcMem | ModRM | Stack), D(SrcMemFAddr | ModRM | ImplicitOps),
2756 D(SrcMem | ModRM | Stack), N,
2757 };
2758
2759 static struct opcode group6[] = {
2760 DI(ModRM | Prot, sldt),
2761 DI(ModRM | Prot, str),
2762 DI(ModRM | Prot | Priv, lldt),
2763 DI(ModRM | Prot | Priv, ltr),
2764 N, N, N, N,
2765 };
2766
2767 static struct group_dual group7 = { {
2768 DI(ModRM | Mov | DstMem | Priv, sgdt),
2769 DI(ModRM | Mov | DstMem | Priv, sidt),
2770 DI(ModRM | SrcMem | Priv, lgdt), DI(ModRM | SrcMem | Priv, lidt),
2771 DI(SrcNone | ModRM | DstMem | Mov, smsw), N,
2772 DI(SrcMem16 | ModRM | Mov | Priv, lmsw),
2773 DI(SrcMem | ModRM | ByteOp | Priv | NoAccess, invlpg),
2774 }, {
2775 D(SrcNone | ModRM | Priv | VendorSpecific), EXT(0, group7_rm1),
2776 N, EXT(0, group7_rm3),
2777 DI(SrcNone | ModRM | DstMem | Mov, smsw), N,
2778 DI(SrcMem16 | ModRM | Mov | Priv, lmsw), EXT(0, group7_rm7),
2779 } };
2780
2781 static struct opcode group8[] = {
2782 N, N, N, N,
2783 D(DstMem | SrcImmByte | ModRM), D(DstMem | SrcImmByte | ModRM | Lock),
2784 D(DstMem | SrcImmByte | ModRM | Lock), D(DstMem | SrcImmByte | ModRM | Lock),
2785 };
2786
2787 static struct group_dual group9 = { {
2788 N, D(DstMem64 | ModRM | Lock), N, N, N, N, N, N,
2789 }, {
2790 N, N, N, N, N, N, N, N,
2791 } };
2792
2793 static struct opcode group11[] = {
2794 I(DstMem | SrcImm | ModRM | Mov, em_mov), X7(D(Undefined)),
2795 };
2796
2797 static struct gprefix pfx_0f_6f_0f_7f = {
2798 N, N, N, I(Sse, em_movdqu),
2799 };
2800
2801 static struct opcode opcode_table[256] = {
2802 /* 0x00 - 0x07 */
2803 D6ALU(Lock),
2804 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2805 /* 0x08 - 0x0F */
2806 D6ALU(Lock),
2807 D(ImplicitOps | Stack | No64), N,
2808 /* 0x10 - 0x17 */
2809 D6ALU(Lock),
2810 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2811 /* 0x18 - 0x1F */
2812 D6ALU(Lock),
2813 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2814 /* 0x20 - 0x27 */
2815 D6ALU(Lock), N, N,
2816 /* 0x28 - 0x2F */
2817 D6ALU(Lock), N, I(ByteOp | DstAcc | No64, em_das),
2818 /* 0x30 - 0x37 */
2819 D6ALU(Lock), N, N,
2820 /* 0x38 - 0x3F */
2821 D6ALU(0), N, N,
2822 /* 0x40 - 0x4F */
2823 X16(D(DstReg)),
2824 /* 0x50 - 0x57 */
2825 X8(I(SrcReg | Stack, em_push)),
2826 /* 0x58 - 0x5F */
2827 X8(D(DstReg | Stack)),
2828 /* 0x60 - 0x67 */
2829 D(ImplicitOps | Stack | No64), D(ImplicitOps | Stack | No64),
2830 N, D(DstReg | SrcMem32 | ModRM | Mov) /* movsxd (x86/64) */ ,
2831 N, N, N, N,
2832 /* 0x68 - 0x6F */
2833 I(SrcImm | Mov | Stack, em_push),
2834 I(DstReg | SrcMem | ModRM | Src2Imm, em_imul_3op),
2835 I(SrcImmByte | Mov | Stack, em_push),
2836 I(DstReg | SrcMem | ModRM | Src2ImmByte, em_imul_3op),
2837 D2bvIP(DstDI | Mov | String, ins, check_perm_in), /* insb, insw/insd */
2838 D2bvIP(SrcSI | ImplicitOps | String, outs, check_perm_out), /* outsb, outsw/outsd */
2839 /* 0x70 - 0x7F */
2840 X16(D(SrcImmByte)),
2841 /* 0x80 - 0x87 */
2842 G(ByteOp | DstMem | SrcImm | ModRM | Group, group1),
2843 G(DstMem | SrcImm | ModRM | Group, group1),
2844 G(ByteOp | DstMem | SrcImm | ModRM | No64 | Group, group1),
2845 G(DstMem | SrcImmByte | ModRM | Group, group1),
2846 D2bv(DstMem | SrcReg | ModRM), D2bv(DstMem | SrcReg | ModRM | Lock),
2847 /* 0x88 - 0x8F */
2848 I2bv(DstMem | SrcReg | ModRM | Mov, em_mov),
2849 I2bv(DstReg | SrcMem | ModRM | Mov, em_mov),
2850 D(DstMem | SrcNone | ModRM | Mov), D(ModRM | SrcMem | NoAccess | DstReg),
2851 D(ImplicitOps | SrcMem16 | ModRM), G(0, group1A),
2852 /* 0x90 - 0x97 */
2853 DI(SrcAcc | DstReg, pause), X7(D(SrcAcc | DstReg)),
2854 /* 0x98 - 0x9F */
2855 D(DstAcc | SrcNone), I(ImplicitOps | SrcAcc, em_cwd),
2856 I(SrcImmFAddr | No64, em_call_far), N,
2857 DI(ImplicitOps | Stack, pushf), DI(ImplicitOps | Stack, popf), N, N,
2858 /* 0xA0 - 0xA7 */
2859 I2bv(DstAcc | SrcMem | Mov | MemAbs, em_mov),
2860 I2bv(DstMem | SrcAcc | Mov | MemAbs, em_mov),
2861 I2bv(SrcSI | DstDI | Mov | String, em_mov),
2862 D2bv(SrcSI | DstDI | String),
2863 /* 0xA8 - 0xAF */
2864 D2bv(DstAcc | SrcImm),
2865 I2bv(SrcAcc | DstDI | Mov | String, em_mov),
2866 I2bv(SrcSI | DstAcc | Mov | String, em_mov),
2867 D2bv(SrcAcc | DstDI | String),
2868 /* 0xB0 - 0xB7 */
2869 X8(I(ByteOp | DstReg | SrcImm | Mov, em_mov)),
2870 /* 0xB8 - 0xBF */
2871 X8(I(DstReg | SrcImm | Mov, em_mov)),
2872 /* 0xC0 - 0xC7 */
2873 D2bv(DstMem | SrcImmByte | ModRM),
2874 I(ImplicitOps | Stack | SrcImmU16, em_ret_near_imm),
2875 D(ImplicitOps | Stack),
2876 D(DstReg | SrcMemFAddr | ModRM | No64), D(DstReg | SrcMemFAddr | ModRM | No64),
2877 G(ByteOp, group11), G(0, group11),
2878 /* 0xC8 - 0xCF */
2879 N, N, N, D(ImplicitOps | Stack),
2880 D(ImplicitOps), DI(SrcImmByte, intn),
2881 D(ImplicitOps | No64), DI(ImplicitOps, iret),
2882 /* 0xD0 - 0xD7 */
2883 D2bv(DstMem | SrcOne | ModRM), D2bv(DstMem | ModRM),
2884 N, N, N, N,
2885 /* 0xD8 - 0xDF */
2886 N, N, N, N, N, N, N, N,
2887 /* 0xE0 - 0xE7 */
2888 X4(D(SrcImmByte)),
2889 D2bvIP(SrcImmUByte | DstAcc, in, check_perm_in),
2890 D2bvIP(SrcAcc | DstImmUByte, out, check_perm_out),
2891 /* 0xE8 - 0xEF */
2892 D(SrcImm | Stack), D(SrcImm | ImplicitOps),
2893 D(SrcImmFAddr | No64), D(SrcImmByte | ImplicitOps),
2894 D2bvIP(SrcNone | DstAcc, in, check_perm_in),
2895 D2bvIP(SrcAcc | ImplicitOps, out, check_perm_out),
2896 /* 0xF0 - 0xF7 */
2897 N, DI(ImplicitOps, icebp), N, N,
2898 DI(ImplicitOps | Priv, hlt), D(ImplicitOps),
2899 G(ByteOp, group3), G(0, group3),
2900 /* 0xF8 - 0xFF */
2901 D(ImplicitOps), D(ImplicitOps), D(ImplicitOps), D(ImplicitOps),
2902 D(ImplicitOps), D(ImplicitOps), G(0, group4), G(0, group5),
2903 };
2904
2905 static struct opcode twobyte_table[256] = {
2906 /* 0x00 - 0x0F */
2907 G(0, group6), GD(0, &group7), N, N,
2908 N, D(ImplicitOps | VendorSpecific), DI(ImplicitOps | Priv, clts), N,
2909 DI(ImplicitOps | Priv, invd), DI(ImplicitOps | Priv, wbinvd), N, N,
2910 N, D(ImplicitOps | ModRM), N, N,
2911 /* 0x10 - 0x1F */
2912 N, N, N, N, N, N, N, N, D(ImplicitOps | ModRM), N, N, N, N, N, N, N,
2913 /* 0x20 - 0x2F */
2914 DIP(ModRM | DstMem | Priv | Op3264, cr_read, check_cr_read),
2915 DIP(ModRM | DstMem | Priv | Op3264, dr_read, check_dr_read),
2916 DIP(ModRM | SrcMem | Priv | Op3264, cr_write, check_cr_write),
2917 DIP(ModRM | SrcMem | Priv | Op3264, dr_write, check_dr_write),
2918 N, N, N, N,
2919 N, N, N, N, N, N, N, N,
2920 /* 0x30 - 0x3F */
2921 DI(ImplicitOps | Priv, wrmsr),
2922 IIP(ImplicitOps, em_rdtsc, rdtsc, check_rdtsc),
2923 DI(ImplicitOps | Priv, rdmsr),
2924 DIP(ImplicitOps | Priv, rdpmc, check_rdpmc),
2925 D(ImplicitOps | VendorSpecific), D(ImplicitOps | Priv | VendorSpecific),
2926 N, N,
2927 N, N, N, N, N, N, N, N,
2928 /* 0x40 - 0x4F */
2929 X16(D(DstReg | SrcMem | ModRM | Mov)),
2930 /* 0x50 - 0x5F */
2931 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2932 /* 0x60 - 0x6F */
2933 N, N, N, N,
2934 N, N, N, N,
2935 N, N, N, N,
2936 N, N, N, GP(SrcMem | DstReg | ModRM | Mov, &pfx_0f_6f_0f_7f),
2937 /* 0x70 - 0x7F */
2938 N, N, N, N,
2939 N, N, N, N,
2940 N, N, N, N,
2941 N, N, N, GP(SrcReg | DstMem | ModRM | Mov, &pfx_0f_6f_0f_7f),
2942 /* 0x80 - 0x8F */
2943 X16(D(SrcImm)),
2944 /* 0x90 - 0x9F */
2945 X16(D(ByteOp | DstMem | SrcNone | ModRM| Mov)),
2946 /* 0xA0 - 0xA7 */
2947 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
2948 DI(ImplicitOps, cpuid), D(DstMem | SrcReg | ModRM | BitOp),
2949 D(DstMem | SrcReg | Src2ImmByte | ModRM),
2950 D(DstMem | SrcReg | Src2CL | ModRM), N, N,
2951 /* 0xA8 - 0xAF */
2952 D(ImplicitOps | Stack), D(ImplicitOps | Stack),
2953 DI(ImplicitOps, rsm), D(DstMem | SrcReg | ModRM | BitOp | Lock),
2954 D(DstMem | SrcReg | Src2ImmByte | ModRM),
2955 D(DstMem | SrcReg | Src2CL | ModRM),
2956 D(ModRM), I(DstReg | SrcMem | ModRM, em_imul),
2957 /* 0xB0 - 0xB7 */
2958 D2bv(DstMem | SrcReg | ModRM | Lock),
2959 D(DstReg | SrcMemFAddr | ModRM), D(DstMem | SrcReg | ModRM | BitOp | Lock),
2960 D(DstReg | SrcMemFAddr | ModRM), D(DstReg | SrcMemFAddr | ModRM),
2961 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
2962 /* 0xB8 - 0xBF */
2963 N, N,
2964 G(BitOp, group8), D(DstMem | SrcReg | ModRM | BitOp | Lock),
2965 D(DstReg | SrcMem | ModRM), D(DstReg | SrcMem | ModRM),
2966 D(ByteOp | DstReg | SrcMem | ModRM | Mov), D(DstReg | SrcMem16 | ModRM | Mov),
2967 /* 0xC0 - 0xCF */
2968 D2bv(DstMem | SrcReg | ModRM | Lock),
2969 N, D(DstMem | SrcReg | ModRM | Mov),
2970 N, N, N, GD(0, &group9),
2971 N, N, N, N, N, N, N, N,
2972 /* 0xD0 - 0xDF */
2973 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2974 /* 0xE0 - 0xEF */
2975 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N,
2976 /* 0xF0 - 0xFF */
2977 N, N, N, N, N, N, N, N, N, N, N, N, N, N, N, N
2978 };
2979
2980 #undef D
2981 #undef N
2982 #undef G
2983 #undef GD
2984 #undef I
2985 #undef GP
2986 #undef EXT
2987
2988 #undef D2bv
2989 #undef D2bvIP
2990 #undef I2bv
2991 #undef D6ALU
2992
2993 static unsigned imm_size(struct decode_cache *c)
2994 {
2995 unsigned size;
2996
2997 size = (c->d & ByteOp) ? 1 : c->op_bytes;
2998 if (size == 8)
2999 size = 4;
3000 return size;
3001 }
3002
3003 static int decode_imm(struct x86_emulate_ctxt *ctxt, struct operand *op,
3004 unsigned size, bool sign_extension)
3005 {
3006 struct decode_cache *c = &ctxt->decode;
3007 struct x86_emulate_ops *ops = ctxt->ops;
3008 int rc = X86EMUL_CONTINUE;
3009
3010 op->type = OP_IMM;
3011 op->bytes = size;
3012 op->addr.mem.ea = c->eip;
3013 /* NB. Immediates are sign-extended as necessary. */
3014 switch (op->bytes) {
3015 case 1:
3016 op->val = insn_fetch(s8, 1, c->eip);
3017 break;
3018 case 2:
3019 op->val = insn_fetch(s16, 2, c->eip);
3020 break;
3021 case 4:
3022 op->val = insn_fetch(s32, 4, c->eip);
3023 break;
3024 }
3025 if (!sign_extension) {
3026 switch (op->bytes) {
3027 case 1:
3028 op->val &= 0xff;
3029 break;
3030 case 2:
3031 op->val &= 0xffff;
3032 break;
3033 case 4:
3034 op->val &= 0xffffffff;
3035 break;
3036 }
3037 }
3038 done:
3039 return rc;
3040 }
3041
3042 int
3043 x86_decode_insn(struct x86_emulate_ctxt *ctxt, void *insn, int insn_len)
3044 {
3045 struct x86_emulate_ops *ops = ctxt->ops;
3046 struct decode_cache *c = &ctxt->decode;
3047 int rc = X86EMUL_CONTINUE;
3048 int mode = ctxt->mode;
3049 int def_op_bytes, def_ad_bytes, dual, goffset, simd_prefix;
3050 bool op_prefix = false;
3051 struct opcode opcode, *g_mod012, *g_mod3;
3052 struct operand memop = { .type = OP_NONE };
3053
3054 c->eip = ctxt->eip;
3055 c->fetch.start = c->eip;
3056 c->fetch.end = c->fetch.start + insn_len;
3057 if (insn_len > 0)
3058 memcpy(c->fetch.data, insn, insn_len);
3059 ctxt->cs_base = seg_base(ctxt, ops, VCPU_SREG_CS);
3060
3061 switch (mode) {
3062 case X86EMUL_MODE_REAL:
3063 case X86EMUL_MODE_VM86:
3064 case X86EMUL_MODE_PROT16:
3065 def_op_bytes = def_ad_bytes = 2;
3066 break;
3067 case X86EMUL_MODE_PROT32:
3068 def_op_bytes = def_ad_bytes = 4;
3069 break;
3070 #ifdef CONFIG_X86_64
3071 case X86EMUL_MODE_PROT64:
3072 def_op_bytes = 4;
3073 def_ad_bytes = 8;
3074 break;
3075 #endif
3076 default:
3077 return -1;
3078 }
3079
3080 c->op_bytes = def_op_bytes;
3081 c->ad_bytes = def_ad_bytes;
3082
3083 /* Legacy prefixes. */
3084 for (;;) {
3085 switch (c->b = insn_fetch(u8, 1, c->eip)) {
3086 case 0x66: /* operand-size override */
3087 op_prefix = true;
3088 /* switch between 2/4 bytes */
3089 c->op_bytes = def_op_bytes ^ 6;
3090 break;
3091 case 0x67: /* address-size override */
3092 if (mode == X86EMUL_MODE_PROT64)
3093 /* switch between 4/8 bytes */
3094 c->ad_bytes = def_ad_bytes ^ 12;
3095 else
3096 /* switch between 2/4 bytes */
3097 c->ad_bytes = def_ad_bytes ^ 6;
3098 break;
3099 case 0x26: /* ES override */
3100 case 0x2e: /* CS override */
3101 case 0x36: /* SS override */
3102 case 0x3e: /* DS override */
3103 set_seg_override(c, (c->b >> 3) & 3);
3104 break;
3105 case 0x64: /* FS override */
3106 case 0x65: /* GS override */
3107 set_seg_override(c, c->b & 7);
3108 break;
3109 case 0x40 ... 0x4f: /* REX */
3110 if (mode != X86EMUL_MODE_PROT64)
3111 goto done_prefixes;
3112 c->rex_prefix = c->b;
3113 continue;
3114 case 0xf0: /* LOCK */
3115 c->lock_prefix = 1;
3116 break;
3117 case 0xf2: /* REPNE/REPNZ */
3118 case 0xf3: /* REP/REPE/REPZ */
3119 c->rep_prefix = c->b;
3120 break;
3121 default:
3122 goto done_prefixes;
3123 }
3124
3125 /* Any legacy prefix after a REX prefix nullifies its effect. */
3126
3127 c->rex_prefix = 0;
3128 }
3129
3130 done_prefixes:
3131
3132 /* REX prefix. */
3133 if (c->rex_prefix & 8)
3134 c->op_bytes = 8; /* REX.W */
3135
3136 /* Opcode byte(s). */
3137 opcode = opcode_table[c->b];
3138 /* Two-byte opcode? */
3139 if (c->b == 0x0f) {
3140 c->twobyte = 1;
3141 c->b = insn_fetch(u8, 1, c->eip);
3142 opcode = twobyte_table[c->b];
3143 }
3144 c->d = opcode.flags;
3145
3146 if (c->d & Group) {
3147 dual = c->d & GroupDual;
3148 c->modrm = insn_fetch(u8, 1, c->eip);
3149 --c->eip;
3150
3151 if (c->d & GroupDual) {
3152 g_mod012 = opcode.u.gdual->mod012;
3153 g_mod3 = opcode.u.gdual->mod3;
3154 } else
3155 g_mod012 = g_mod3 = opcode.u.group;
3156
3157 c->d &= ~(Group | GroupDual);
3158
3159 goffset = (c->modrm >> 3) & 7;
3160
3161 if ((c->modrm >> 6) == 3)
3162 opcode = g_mod3[goffset];
3163 else
3164 opcode = g_mod012[goffset];
3165
3166 if (opcode.flags & RMExt) {
3167 goffset = c->modrm & 7;
3168 opcode = opcode.u.group[goffset];
3169 }
3170
3171 c->d |= opcode.flags;
3172 }
3173
3174 if (c->d & Prefix) {
3175 if (c->rep_prefix && op_prefix)
3176 return X86EMUL_UNHANDLEABLE;
3177 simd_prefix = op_prefix ? 0x66 : c->rep_prefix;
3178 switch (simd_prefix) {
3179 case 0x00: opcode = opcode.u.gprefix->pfx_no; break;
3180 case 0x66: opcode = opcode.u.gprefix->pfx_66; break;
3181 case 0xf2: opcode = opcode.u.gprefix->pfx_f2; break;
3182 case 0xf3: opcode = opcode.u.gprefix->pfx_f3; break;
3183 }
3184 c->d |= opcode.flags;
3185 }
3186
3187 c->execute = opcode.u.execute;
3188 c->check_perm = opcode.check_perm;
3189 c->intercept = opcode.intercept;
3190
3191 /* Unrecognised? */
3192 if (c->d == 0 || (c->d & Undefined))
3193 return -1;
3194
3195 if (!(c->d & VendorSpecific) && ctxt->only_vendor_specific_insn)
3196 return -1;
3197
3198 if (mode == X86EMUL_MODE_PROT64 && (c->d & Stack))
3199 c->op_bytes = 8;
3200
3201 if (c->d & Op3264) {
3202 if (mode == X86EMUL_MODE_PROT64)
3203 c->op_bytes = 8;
3204 else
3205 c->op_bytes = 4;
3206 }
3207
3208 if (c->d & Sse)
3209 c->op_bytes = 16;
3210
3211 /* ModRM and SIB bytes. */
3212 if (c->d & ModRM) {
3213 rc = decode_modrm(ctxt, ops, &memop);
3214 if (!c->has_seg_override)
3215 set_seg_override(c, c->modrm_seg);
3216 } else if (c->d & MemAbs)
3217 rc = decode_abs(ctxt, ops, &memop);
3218 if (rc != X86EMUL_CONTINUE)
3219 goto done;
3220
3221 if (!c->has_seg_override)
3222 set_seg_override(c, VCPU_SREG_DS);
3223
3224 memop.addr.mem.seg = seg_override(ctxt, ops, c);
3225
3226 if (memop.type == OP_MEM && c->ad_bytes != 8)
3227 memop.addr.mem.ea = (u32)memop.addr.mem.ea;
3228
3229 if (memop.type == OP_MEM && c->rip_relative)
3230 memop.addr.mem.ea += c->eip;
3231
3232 /*
3233 * Decode and fetch the source operand: register, memory
3234 * or immediate.
3235 */
3236 switch (c->d & SrcMask) {
3237 case SrcNone:
3238 break;
3239 case SrcReg:
3240 decode_register_operand(ctxt, &c->src, c, 0);
3241 break;
3242 case SrcMem16:
3243 memop.bytes = 2;
3244 goto srcmem_common;
3245 case SrcMem32:
3246 memop.bytes = 4;
3247 goto srcmem_common;
3248 case SrcMem:
3249 memop.bytes = (c->d & ByteOp) ? 1 :
3250 c->op_bytes;
3251 srcmem_common:
3252 c->src = memop;
3253 break;
3254 case SrcImmU16:
3255 rc = decode_imm(ctxt, &c->src, 2, false);
3256 break;
3257 case SrcImm:
3258 rc = decode_imm(ctxt, &c->src, imm_size(c), true);
3259 break;
3260 case SrcImmU:
3261 rc = decode_imm(ctxt, &c->src, imm_size(c), false);
3262 break;
3263 case SrcImmByte:
3264 rc = decode_imm(ctxt, &c->src, 1, true);
3265 break;
3266 case SrcImmUByte:
3267 rc = decode_imm(ctxt, &c->src, 1, false);
3268 break;
3269 case SrcAcc:
3270 c->src.type = OP_REG;
3271 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
3272 c->src.addr.reg = &c->regs[VCPU_REGS_RAX];
3273 fetch_register_operand(&c->src);
3274 break;
3275 case SrcOne:
3276 c->src.bytes = 1;
3277 c->src.val = 1;
3278 break;
3279 case SrcSI:
3280 c->src.type = OP_MEM;
3281 c->src.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
3282 c->src.addr.mem.ea =
3283 register_address(c, c->regs[VCPU_REGS_RSI]);
3284 c->src.addr.mem.seg = seg_override(ctxt, ops, c),
3285 c->src.val = 0;
3286 break;
3287 case SrcImmFAddr:
3288 c->src.type = OP_IMM;
3289 c->src.addr.mem.ea = c->eip;
3290 c->src.bytes = c->op_bytes + 2;
3291 insn_fetch_arr(c->src.valptr, c->src.bytes, c->eip);
3292 break;
3293 case SrcMemFAddr:
3294 memop.bytes = c->op_bytes + 2;
3295 goto srcmem_common;
3296 break;
3297 }
3298
3299 if (rc != X86EMUL_CONTINUE)
3300 goto done;
3301
3302 /*
3303 * Decode and fetch the second source operand: register, memory
3304 * or immediate.
3305 */
3306 switch (c->d & Src2Mask) {
3307 case Src2None:
3308 break;
3309 case Src2CL:
3310 c->src2.bytes = 1;
3311 c->src2.val = c->regs[VCPU_REGS_RCX] & 0x8;
3312 break;
3313 case Src2ImmByte:
3314 rc = decode_imm(ctxt, &c->src2, 1, true);
3315 break;
3316 case Src2One:
3317 c->src2.bytes = 1;
3318 c->src2.val = 1;
3319 break;
3320 case Src2Imm:
3321 rc = decode_imm(ctxt, &c->src2, imm_size(c), true);
3322 break;
3323 }
3324
3325 if (rc != X86EMUL_CONTINUE)
3326 goto done;
3327
3328 /* Decode and fetch the destination operand: register or memory. */
3329 switch (c->d & DstMask) {
3330 case DstReg:
3331 decode_register_operand(ctxt, &c->dst, c,
3332 c->twobyte && (c->b == 0xb6 || c->b == 0xb7));
3333 break;
3334 case DstImmUByte:
3335 c->dst.type = OP_IMM;
3336 c->dst.addr.mem.ea = c->eip;
3337 c->dst.bytes = 1;
3338 c->dst.val = insn_fetch(u8, 1, c->eip);
3339 break;
3340 case DstMem:
3341 case DstMem64:
3342 c->dst = memop;
3343 if ((c->d & DstMask) == DstMem64)
3344 c->dst.bytes = 8;
3345 else
3346 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
3347 if (c->d & BitOp)
3348 fetch_bit_operand(c);
3349 c->dst.orig_val = c->dst.val;
3350 break;
3351 case DstAcc:
3352 c->dst.type = OP_REG;
3353 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
3354 c->dst.addr.reg = &c->regs[VCPU_REGS_RAX];
3355 fetch_register_operand(&c->dst);
3356 c->dst.orig_val = c->dst.val;
3357 break;
3358 case DstDI:
3359 c->dst.type = OP_MEM;
3360 c->dst.bytes = (c->d & ByteOp) ? 1 : c->op_bytes;
3361 c->dst.addr.mem.ea =
3362 register_address(c, c->regs[VCPU_REGS_RDI]);
3363 c->dst.addr.mem.seg = VCPU_SREG_ES;
3364 c->dst.val = 0;
3365 break;
3366 case ImplicitOps:
3367 /* Special instructions do their own operand decoding. */
3368 default:
3369 c->dst.type = OP_NONE; /* Disable writeback. */
3370 return 0;
3371 }
3372
3373 done:
3374 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
3375 }
3376
3377 static bool string_insn_completed(struct x86_emulate_ctxt *ctxt)
3378 {
3379 struct decode_cache *c = &ctxt->decode;
3380
3381 /* The second termination condition only applies for REPE
3382 * and REPNE. Test if the repeat string operation prefix is
3383 * REPE/REPZ or REPNE/REPNZ and if it's the case it tests the
3384 * corresponding termination condition according to:
3385 * - if REPE/REPZ and ZF = 0 then done
3386 * - if REPNE/REPNZ and ZF = 1 then done
3387 */
3388 if (((c->b == 0xa6) || (c->b == 0xa7) ||
3389 (c->b == 0xae) || (c->b == 0xaf))
3390 && (((c->rep_prefix == REPE_PREFIX) &&
3391 ((ctxt->eflags & EFLG_ZF) == 0))
3392 || ((c->rep_prefix == REPNE_PREFIX) &&
3393 ((ctxt->eflags & EFLG_ZF) == EFLG_ZF))))
3394 return true;
3395
3396 return false;
3397 }
3398
3399 int
3400 x86_emulate_insn(struct x86_emulate_ctxt *ctxt)
3401 {
3402 struct x86_emulate_ops *ops = ctxt->ops;
3403 u64 msr_data;
3404 struct decode_cache *c = &ctxt->decode;
3405 int rc = X86EMUL_CONTINUE;
3406 int saved_dst_type = c->dst.type;
3407 int irq; /* Used for int 3, int, and into */
3408
3409 ctxt->decode.mem_read.pos = 0;
3410
3411 if (ctxt->mode == X86EMUL_MODE_PROT64 && (c->d & No64)) {
3412 rc = emulate_ud(ctxt);
3413 goto done;
3414 }
3415
3416 /* LOCK prefix is allowed only with some instructions */
3417 if (c->lock_prefix && (!(c->d & Lock) || c->dst.type != OP_MEM)) {
3418 rc = emulate_ud(ctxt);
3419 goto done;
3420 }
3421
3422 if ((c->d & SrcMask) == SrcMemFAddr && c->src.type != OP_MEM) {
3423 rc = emulate_ud(ctxt);
3424 goto done;
3425 }
3426
3427 if ((c->d & Sse)
3428 && ((ops->get_cr(0, ctxt->vcpu) & X86_CR0_EM)
3429 || !(ops->get_cr(4, ctxt->vcpu) & X86_CR4_OSFXSR))) {
3430 rc = emulate_ud(ctxt);
3431 goto done;
3432 }
3433
3434 if ((c->d & Sse) && (ops->get_cr(0, ctxt->vcpu) & X86_CR0_TS)) {
3435 rc = emulate_nm(ctxt);
3436 goto done;
3437 }
3438
3439 if (unlikely(ctxt->guest_mode) && c->intercept) {
3440 rc = emulator_check_intercept(ctxt, c->intercept,
3441 X86_ICPT_PRE_EXCEPT);
3442 if (rc != X86EMUL_CONTINUE)
3443 goto done;
3444 }
3445
3446 /* Privileged instruction can be executed only in CPL=0 */
3447 if ((c->d & Priv) && ops->cpl(ctxt->vcpu)) {
3448 rc = emulate_gp(ctxt, 0);
3449 goto done;
3450 }
3451
3452 /* Instruction can only be executed in protected mode */
3453 if ((c->d & Prot) && !(ctxt->mode & X86EMUL_MODE_PROT)) {
3454 rc = emulate_ud(ctxt);
3455 goto done;
3456 }
3457
3458 /* Do instruction specific permission checks */
3459 if (c->check_perm) {
3460 rc = c->check_perm(ctxt);
3461 if (rc != X86EMUL_CONTINUE)
3462 goto done;
3463 }
3464
3465 if (unlikely(ctxt->guest_mode) && c->intercept) {
3466 rc = emulator_check_intercept(ctxt, c->intercept,
3467 X86_ICPT_POST_EXCEPT);
3468 if (rc != X86EMUL_CONTINUE)
3469 goto done;
3470 }
3471
3472 if (c->rep_prefix && (c->d & String)) {
3473 /* All REP prefixes have the same first termination condition */
3474 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0) {
3475 ctxt->eip = c->eip;
3476 goto done;
3477 }
3478 }
3479
3480 if ((c->src.type == OP_MEM) && !(c->d & NoAccess)) {
3481 rc = segmented_read(ctxt, c->src.addr.mem,
3482 c->src.valptr, c->src.bytes);
3483 if (rc != X86EMUL_CONTINUE)
3484 goto done;
3485 c->src.orig_val64 = c->src.val64;
3486 }
3487
3488 if (c->src2.type == OP_MEM) {
3489 rc = segmented_read(ctxt, c->src2.addr.mem,
3490 &c->src2.val, c->src2.bytes);
3491 if (rc != X86EMUL_CONTINUE)
3492 goto done;
3493 }
3494
3495 if ((c->d & DstMask) == ImplicitOps)
3496 goto special_insn;
3497
3498
3499 if ((c->dst.type == OP_MEM) && !(c->d & Mov)) {
3500 /* optimisation - avoid slow emulated read if Mov */
3501 rc = segmented_read(ctxt, c->dst.addr.mem,
3502 &c->dst.val, c->dst.bytes);
3503 if (rc != X86EMUL_CONTINUE)
3504 goto done;
3505 }
3506 c->dst.orig_val = c->dst.val;
3507
3508 special_insn:
3509
3510 if (unlikely(ctxt->guest_mode) && c->intercept) {
3511 rc = emulator_check_intercept(ctxt, c->intercept,
3512 X86_ICPT_POST_MEMACCESS);
3513 if (rc != X86EMUL_CONTINUE)
3514 goto done;
3515 }
3516
3517 if (c->execute) {
3518 rc = c->execute(ctxt);
3519 if (rc != X86EMUL_CONTINUE)
3520 goto done;
3521 goto writeback;
3522 }
3523
3524 if (c->twobyte)
3525 goto twobyte_insn;
3526
3527 switch (c->b) {
3528 case 0x00 ... 0x05:
3529 add: /* add */
3530 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
3531 break;
3532 case 0x06: /* push es */
3533 emulate_push_sreg(ctxt, ops, VCPU_SREG_ES);
3534 break;
3535 case 0x07: /* pop es */
3536 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_ES);
3537 break;
3538 case 0x08 ... 0x0d:
3539 or: /* or */
3540 emulate_2op_SrcV("or", c->src, c->dst, ctxt->eflags);
3541 break;
3542 case 0x0e: /* push cs */
3543 emulate_push_sreg(ctxt, ops, VCPU_SREG_CS);
3544 break;
3545 case 0x10 ... 0x15:
3546 adc: /* adc */
3547 emulate_2op_SrcV("adc", c->src, c->dst, ctxt->eflags);
3548 break;
3549 case 0x16: /* push ss */
3550 emulate_push_sreg(ctxt, ops, VCPU_SREG_SS);
3551 break;
3552 case 0x17: /* pop ss */
3553 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_SS);
3554 break;
3555 case 0x18 ... 0x1d:
3556 sbb: /* sbb */
3557 emulate_2op_SrcV("sbb", c->src, c->dst, ctxt->eflags);
3558 break;
3559 case 0x1e: /* push ds */
3560 emulate_push_sreg(ctxt, ops, VCPU_SREG_DS);
3561 break;
3562 case 0x1f: /* pop ds */
3563 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_DS);
3564 break;
3565 case 0x20 ... 0x25:
3566 and: /* and */
3567 emulate_2op_SrcV("and", c->src, c->dst, ctxt->eflags);
3568 break;
3569 case 0x28 ... 0x2d:
3570 sub: /* sub */
3571 emulate_2op_SrcV("sub", c->src, c->dst, ctxt->eflags);
3572 break;
3573 case 0x30 ... 0x35:
3574 xor: /* xor */
3575 emulate_2op_SrcV("xor", c->src, c->dst, ctxt->eflags);
3576 break;
3577 case 0x38 ... 0x3d:
3578 cmp: /* cmp */
3579 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
3580 break;
3581 case 0x40 ... 0x47: /* inc r16/r32 */
3582 emulate_1op("inc", c->dst, ctxt->eflags);
3583 break;
3584 case 0x48 ... 0x4f: /* dec r16/r32 */
3585 emulate_1op("dec", c->dst, ctxt->eflags);
3586 break;
3587 case 0x58 ... 0x5f: /* pop reg */
3588 pop_instruction:
3589 rc = emulate_pop(ctxt, ops, &c->dst.val, c->op_bytes);
3590 break;
3591 case 0x60: /* pusha */
3592 rc = emulate_pusha(ctxt, ops);
3593 break;
3594 case 0x61: /* popa */
3595 rc = emulate_popa(ctxt, ops);
3596 break;
3597 case 0x63: /* movsxd */
3598 if (ctxt->mode != X86EMUL_MODE_PROT64)
3599 goto cannot_emulate;
3600 c->dst.val = (s32) c->src.val;
3601 break;
3602 case 0x6c: /* insb */
3603 case 0x6d: /* insw/insd */
3604 c->src.val = c->regs[VCPU_REGS_RDX];
3605 goto do_io_in;
3606 case 0x6e: /* outsb */
3607 case 0x6f: /* outsw/outsd */
3608 c->dst.val = c->regs[VCPU_REGS_RDX];
3609 goto do_io_out;
3610 break;
3611 case 0x70 ... 0x7f: /* jcc (short) */
3612 if (test_cc(c->b, ctxt->eflags))
3613 jmp_rel(c, c->src.val);
3614 break;
3615 case 0x80 ... 0x83: /* Grp1 */
3616 switch (c->modrm_reg) {
3617 case 0:
3618 goto add;
3619 case 1:
3620 goto or;
3621 case 2:
3622 goto adc;
3623 case 3:
3624 goto sbb;
3625 case 4:
3626 goto and;
3627 case 5:
3628 goto sub;
3629 case 6:
3630 goto xor;
3631 case 7:
3632 goto cmp;
3633 }
3634 break;
3635 case 0x84 ... 0x85:
3636 test:
3637 emulate_2op_SrcV("test", c->src, c->dst, ctxt->eflags);
3638 break;
3639 case 0x86 ... 0x87: /* xchg */
3640 xchg:
3641 /* Write back the register source. */
3642 c->src.val = c->dst.val;
3643 write_register_operand(&c->src);
3644 /*
3645 * Write back the memory destination with implicit LOCK
3646 * prefix.
3647 */
3648 c->dst.val = c->src.orig_val;
3649 c->lock_prefix = 1;
3650 break;
3651 case 0x8c: /* mov r/m, sreg */
3652 if (c->modrm_reg > VCPU_SREG_GS) {
3653 rc = emulate_ud(ctxt);
3654 goto done;
3655 }
3656 c->dst.val = ops->get_segment_selector(c->modrm_reg, ctxt->vcpu);
3657 break;
3658 case 0x8d: /* lea r16/r32, m */
3659 c->dst.val = c->src.addr.mem.ea;
3660 break;
3661 case 0x8e: { /* mov seg, r/m16 */
3662 uint16_t sel;
3663
3664 sel = c->src.val;
3665
3666 if (c->modrm_reg == VCPU_SREG_CS ||
3667 c->modrm_reg > VCPU_SREG_GS) {
3668 rc = emulate_ud(ctxt);
3669 goto done;
3670 }
3671
3672 if (c->modrm_reg == VCPU_SREG_SS)
3673 ctxt->interruptibility = KVM_X86_SHADOW_INT_MOV_SS;
3674
3675 rc = load_segment_descriptor(ctxt, ops, sel, c->modrm_reg);
3676
3677 c->dst.type = OP_NONE; /* Disable writeback. */
3678 break;
3679 }
3680 case 0x8f: /* pop (sole member of Grp1a) */
3681 rc = emulate_grp1a(ctxt, ops);
3682 break;
3683 case 0x90 ... 0x97: /* nop / xchg reg, rax */
3684 if (c->dst.addr.reg == &c->regs[VCPU_REGS_RAX])
3685 break;
3686 goto xchg;
3687 case 0x98: /* cbw/cwde/cdqe */
3688 switch (c->op_bytes) {
3689 case 2: c->dst.val = (s8)c->dst.val; break;
3690 case 4: c->dst.val = (s16)c->dst.val; break;
3691 case 8: c->dst.val = (s32)c->dst.val; break;
3692 }
3693 break;
3694 case 0x9c: /* pushf */
3695 c->src.val = (unsigned long) ctxt->eflags;
3696 emulate_push(ctxt, ops);
3697 break;
3698 case 0x9d: /* popf */
3699 c->dst.type = OP_REG;
3700 c->dst.addr.reg = &ctxt->eflags;
3701 c->dst.bytes = c->op_bytes;
3702 rc = emulate_popf(ctxt, ops, &c->dst.val, c->op_bytes);
3703 break;
3704 case 0xa6 ... 0xa7: /* cmps */
3705 c->dst.type = OP_NONE; /* Disable writeback. */
3706 goto cmp;
3707 case 0xa8 ... 0xa9: /* test ax, imm */
3708 goto test;
3709 case 0xae ... 0xaf: /* scas */
3710 goto cmp;
3711 case 0xc0 ... 0xc1:
3712 emulate_grp2(ctxt);
3713 break;
3714 case 0xc3: /* ret */
3715 c->dst.type = OP_REG;
3716 c->dst.addr.reg = &c->eip;
3717 c->dst.bytes = c->op_bytes;
3718 goto pop_instruction;
3719 case 0xc4: /* les */
3720 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_ES);
3721 break;
3722 case 0xc5: /* lds */
3723 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_DS);
3724 break;
3725 case 0xcb: /* ret far */
3726 rc = emulate_ret_far(ctxt, ops);
3727 break;
3728 case 0xcc: /* int3 */
3729 irq = 3;
3730 goto do_interrupt;
3731 case 0xcd: /* int n */
3732 irq = c->src.val;
3733 do_interrupt:
3734 rc = emulate_int(ctxt, ops, irq);
3735 break;
3736 case 0xce: /* into */
3737 if (ctxt->eflags & EFLG_OF) {
3738 irq = 4;
3739 goto do_interrupt;
3740 }
3741 break;
3742 case 0xcf: /* iret */
3743 rc = emulate_iret(ctxt, ops);
3744 break;
3745 case 0xd0 ... 0xd1: /* Grp2 */
3746 emulate_grp2(ctxt);
3747 break;
3748 case 0xd2 ... 0xd3: /* Grp2 */
3749 c->src.val = c->regs[VCPU_REGS_RCX];
3750 emulate_grp2(ctxt);
3751 break;
3752 case 0xe0 ... 0xe2: /* loop/loopz/loopnz */
3753 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3754 if (address_mask(c, c->regs[VCPU_REGS_RCX]) != 0 &&
3755 (c->b == 0xe2 || test_cc(c->b ^ 0x5, ctxt->eflags)))
3756 jmp_rel(c, c->src.val);
3757 break;
3758 case 0xe3: /* jcxz/jecxz/jrcxz */
3759 if (address_mask(c, c->regs[VCPU_REGS_RCX]) == 0)
3760 jmp_rel(c, c->src.val);
3761 break;
3762 case 0xe4: /* inb */
3763 case 0xe5: /* in */
3764 goto do_io_in;
3765 case 0xe6: /* outb */
3766 case 0xe7: /* out */
3767 goto do_io_out;
3768 case 0xe8: /* call (near) */ {
3769 long int rel = c->src.val;
3770 c->src.val = (unsigned long) c->eip;
3771 jmp_rel(c, rel);
3772 emulate_push(ctxt, ops);
3773 break;
3774 }
3775 case 0xe9: /* jmp rel */
3776 goto jmp;
3777 case 0xea: { /* jmp far */
3778 unsigned short sel;
3779 jump_far:
3780 memcpy(&sel, c->src.valptr + c->op_bytes, 2);
3781
3782 if (load_segment_descriptor(ctxt, ops, sel, VCPU_SREG_CS))
3783 goto done;
3784
3785 c->eip = 0;
3786 memcpy(&c->eip, c->src.valptr, c->op_bytes);
3787 break;
3788 }
3789 case 0xeb:
3790 jmp: /* jmp rel short */
3791 jmp_rel(c, c->src.val);
3792 c->dst.type = OP_NONE; /* Disable writeback. */
3793 break;
3794 case 0xec: /* in al,dx */
3795 case 0xed: /* in (e/r)ax,dx */
3796 c->src.val = c->regs[VCPU_REGS_RDX];
3797 do_io_in:
3798 if (!pio_in_emulated(ctxt, ops, c->dst.bytes, c->src.val,
3799 &c->dst.val))
3800 goto done; /* IO is needed */
3801 break;
3802 case 0xee: /* out dx,al */
3803 case 0xef: /* out dx,(e/r)ax */
3804 c->dst.val = c->regs[VCPU_REGS_RDX];
3805 do_io_out:
3806 ops->pio_out_emulated(c->src.bytes, c->dst.val,
3807 &c->src.val, 1, ctxt->vcpu);
3808 c->dst.type = OP_NONE; /* Disable writeback. */
3809 break;
3810 case 0xf4: /* hlt */
3811 ctxt->vcpu->arch.halt_request = 1;
3812 break;
3813 case 0xf5: /* cmc */
3814 /* complement carry flag from eflags reg */
3815 ctxt->eflags ^= EFLG_CF;
3816 break;
3817 case 0xf6 ... 0xf7: /* Grp3 */
3818 rc = emulate_grp3(ctxt, ops);
3819 break;
3820 case 0xf8: /* clc */
3821 ctxt->eflags &= ~EFLG_CF;
3822 break;
3823 case 0xf9: /* stc */
3824 ctxt->eflags |= EFLG_CF;
3825 break;
3826 case 0xfa: /* cli */
3827 if (emulator_bad_iopl(ctxt, ops)) {
3828 rc = emulate_gp(ctxt, 0);
3829 goto done;
3830 } else
3831 ctxt->eflags &= ~X86_EFLAGS_IF;
3832 break;
3833 case 0xfb: /* sti */
3834 if (emulator_bad_iopl(ctxt, ops)) {
3835 rc = emulate_gp(ctxt, 0);
3836 goto done;
3837 } else {
3838 ctxt->interruptibility = KVM_X86_SHADOW_INT_STI;
3839 ctxt->eflags |= X86_EFLAGS_IF;
3840 }
3841 break;
3842 case 0xfc: /* cld */
3843 ctxt->eflags &= ~EFLG_DF;
3844 break;
3845 case 0xfd: /* std */
3846 ctxt->eflags |= EFLG_DF;
3847 break;
3848 case 0xfe: /* Grp4 */
3849 grp45:
3850 rc = emulate_grp45(ctxt, ops);
3851 break;
3852 case 0xff: /* Grp5 */
3853 if (c->modrm_reg == 5)
3854 goto jump_far;
3855 goto grp45;
3856 default:
3857 goto cannot_emulate;
3858 }
3859
3860 if (rc != X86EMUL_CONTINUE)
3861 goto done;
3862
3863 writeback:
3864 rc = writeback(ctxt, ops);
3865 if (rc != X86EMUL_CONTINUE)
3866 goto done;
3867
3868 /*
3869 * restore dst type in case the decoding will be reused
3870 * (happens for string instruction )
3871 */
3872 c->dst.type = saved_dst_type;
3873
3874 if ((c->d & SrcMask) == SrcSI)
3875 string_addr_inc(ctxt, seg_override(ctxt, ops, c),
3876 VCPU_REGS_RSI, &c->src);
3877
3878 if ((c->d & DstMask) == DstDI)
3879 string_addr_inc(ctxt, VCPU_SREG_ES, VCPU_REGS_RDI,
3880 &c->dst);
3881
3882 if (c->rep_prefix && (c->d & String)) {
3883 struct read_cache *r = &ctxt->decode.io_read;
3884 register_address_increment(c, &c->regs[VCPU_REGS_RCX], -1);
3885
3886 if (!string_insn_completed(ctxt)) {
3887 /*
3888 * Re-enter guest when pio read ahead buffer is empty
3889 * or, if it is not used, after each 1024 iteration.
3890 */
3891 if ((r->end != 0 || c->regs[VCPU_REGS_RCX] & 0x3ff) &&
3892 (r->end == 0 || r->end != r->pos)) {
3893 /*
3894 * Reset read cache. Usually happens before
3895 * decode, but since instruction is restarted
3896 * we have to do it here.
3897 */
3898 ctxt->decode.mem_read.end = 0;
3899 return EMULATION_RESTART;
3900 }
3901 goto done; /* skip rip writeback */
3902 }
3903 }
3904
3905 ctxt->eip = c->eip;
3906
3907 done:
3908 if (rc == X86EMUL_PROPAGATE_FAULT)
3909 ctxt->have_exception = true;
3910 if (rc == X86EMUL_INTERCEPTED)
3911 return EMULATION_INTERCEPTED;
3912
3913 return (rc == X86EMUL_UNHANDLEABLE) ? EMULATION_FAILED : EMULATION_OK;
3914
3915 twobyte_insn:
3916 switch (c->b) {
3917 case 0x01: /* lgdt, lidt, lmsw */
3918 switch (c->modrm_reg) {
3919 u16 size;
3920 unsigned long address;
3921
3922 case 0: /* vmcall */
3923 if (c->modrm_mod != 3 || c->modrm_rm != 1)
3924 goto cannot_emulate;
3925
3926 rc = kvm_fix_hypercall(ctxt->vcpu);
3927 if (rc != X86EMUL_CONTINUE)
3928 goto done;
3929
3930 /* Let the processor re-execute the fixed hypercall */
3931 c->eip = ctxt->eip;
3932 /* Disable writeback. */
3933 c->dst.type = OP_NONE;
3934 break;
3935 case 2: /* lgdt */
3936 rc = read_descriptor(ctxt, ops, c->src.addr.mem,
3937 &size, &address, c->op_bytes);
3938 if (rc != X86EMUL_CONTINUE)
3939 goto done;
3940 realmode_lgdt(ctxt->vcpu, size, address);
3941 /* Disable writeback. */
3942 c->dst.type = OP_NONE;
3943 break;
3944 case 3: /* lidt/vmmcall */
3945 if (c->modrm_mod == 3) {
3946 switch (c->modrm_rm) {
3947 case 1:
3948 rc = kvm_fix_hypercall(ctxt->vcpu);
3949 break;
3950 default:
3951 goto cannot_emulate;
3952 }
3953 } else {
3954 rc = read_descriptor(ctxt, ops, c->src.addr.mem,
3955 &size, &address,
3956 c->op_bytes);
3957 if (rc != X86EMUL_CONTINUE)
3958 goto done;
3959 realmode_lidt(ctxt->vcpu, size, address);
3960 }
3961 /* Disable writeback. */
3962 c->dst.type = OP_NONE;
3963 break;
3964 case 4: /* smsw */
3965 c->dst.bytes = 2;
3966 c->dst.val = ops->get_cr(0, ctxt->vcpu);
3967 break;
3968 case 6: /* lmsw */
3969 ops->set_cr(0, (ops->get_cr(0, ctxt->vcpu) & ~0x0eul) |
3970 (c->src.val & 0x0f), ctxt->vcpu);
3971 c->dst.type = OP_NONE;
3972 break;
3973 case 5: /* not defined */
3974 emulate_ud(ctxt);
3975 rc = X86EMUL_PROPAGATE_FAULT;
3976 goto done;
3977 case 7: /* invlpg*/
3978 rc = em_invlpg(ctxt);
3979 break;
3980 default:
3981 goto cannot_emulate;
3982 }
3983 break;
3984 case 0x05: /* syscall */
3985 rc = emulate_syscall(ctxt, ops);
3986 break;
3987 case 0x06:
3988 emulate_clts(ctxt->vcpu);
3989 break;
3990 case 0x09: /* wbinvd */
3991 kvm_emulate_wbinvd(ctxt->vcpu);
3992 break;
3993 case 0x08: /* invd */
3994 case 0x0d: /* GrpP (prefetch) */
3995 case 0x18: /* Grp16 (prefetch/nop) */
3996 break;
3997 case 0x20: /* mov cr, reg */
3998 c->dst.val = ops->get_cr(c->modrm_reg, ctxt->vcpu);
3999 break;
4000 case 0x21: /* mov from dr to reg */
4001 ops->get_dr(c->modrm_reg, &c->dst.val, ctxt->vcpu);
4002 break;
4003 case 0x22: /* mov reg, cr */
4004 if (ops->set_cr(c->modrm_reg, c->src.val, ctxt->vcpu)) {
4005 emulate_gp(ctxt, 0);
4006 rc = X86EMUL_PROPAGATE_FAULT;
4007 goto done;
4008 }
4009 c->dst.type = OP_NONE;
4010 break;
4011 case 0x23: /* mov from reg to dr */
4012 if (ops->set_dr(c->modrm_reg, c->src.val &
4013 ((ctxt->mode == X86EMUL_MODE_PROT64) ?
4014 ~0ULL : ~0U), ctxt->vcpu) < 0) {
4015 /* #UD condition is already handled by the code above */
4016 emulate_gp(ctxt, 0);
4017 rc = X86EMUL_PROPAGATE_FAULT;
4018 goto done;
4019 }
4020
4021 c->dst.type = OP_NONE; /* no writeback */
4022 break;
4023 case 0x30:
4024 /* wrmsr */
4025 msr_data = (u32)c->regs[VCPU_REGS_RAX]
4026 | ((u64)c->regs[VCPU_REGS_RDX] << 32);
4027 if (ops->set_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], msr_data)) {
4028 emulate_gp(ctxt, 0);
4029 rc = X86EMUL_PROPAGATE_FAULT;
4030 goto done;
4031 }
4032 rc = X86EMUL_CONTINUE;
4033 break;
4034 case 0x32:
4035 /* rdmsr */
4036 if (ops->get_msr(ctxt->vcpu, c->regs[VCPU_REGS_RCX], &msr_data)) {
4037 emulate_gp(ctxt, 0);
4038 rc = X86EMUL_PROPAGATE_FAULT;
4039 goto done;
4040 } else {
4041 c->regs[VCPU_REGS_RAX] = (u32)msr_data;
4042 c->regs[VCPU_REGS_RDX] = msr_data >> 32;
4043 }
4044 rc = X86EMUL_CONTINUE;
4045 break;
4046 case 0x34: /* sysenter */
4047 rc = emulate_sysenter(ctxt, ops);
4048 break;
4049 case 0x35: /* sysexit */
4050 rc = emulate_sysexit(ctxt, ops);
4051 break;
4052 case 0x40 ... 0x4f: /* cmov */
4053 c->dst.val = c->dst.orig_val = c->src.val;
4054 if (!test_cc(c->b, ctxt->eflags))
4055 c->dst.type = OP_NONE; /* no writeback */
4056 break;
4057 case 0x80 ... 0x8f: /* jnz rel, etc*/
4058 if (test_cc(c->b, ctxt->eflags))
4059 jmp_rel(c, c->src.val);
4060 break;
4061 case 0x90 ... 0x9f: /* setcc r/m8 */
4062 c->dst.val = test_cc(c->b, ctxt->eflags);
4063 break;
4064 case 0xa0: /* push fs */
4065 emulate_push_sreg(ctxt, ops, VCPU_SREG_FS);
4066 break;
4067 case 0xa1: /* pop fs */
4068 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_FS);
4069 break;
4070 case 0xa3:
4071 bt: /* bt */
4072 c->dst.type = OP_NONE;
4073 /* only subword offset */
4074 c->src.val &= (c->dst.bytes << 3) - 1;
4075 emulate_2op_SrcV_nobyte("bt", c->src, c->dst, ctxt->eflags);
4076 break;
4077 case 0xa4: /* shld imm8, r, r/m */
4078 case 0xa5: /* shld cl, r, r/m */
4079 emulate_2op_cl("shld", c->src2, c->src, c->dst, ctxt->eflags);
4080 break;
4081 case 0xa8: /* push gs */
4082 emulate_push_sreg(ctxt, ops, VCPU_SREG_GS);
4083 break;
4084 case 0xa9: /* pop gs */
4085 rc = emulate_pop_sreg(ctxt, ops, VCPU_SREG_GS);
4086 break;
4087 case 0xab:
4088 bts: /* bts */
4089 emulate_2op_SrcV_nobyte("bts", c->src, c->dst, ctxt->eflags);
4090 break;
4091 case 0xac: /* shrd imm8, r, r/m */
4092 case 0xad: /* shrd cl, r, r/m */
4093 emulate_2op_cl("shrd", c->src2, c->src, c->dst, ctxt->eflags);
4094 break;
4095 case 0xae: /* clflush */
4096 break;
4097 case 0xb0 ... 0xb1: /* cmpxchg */
4098 /*
4099 * Save real source value, then compare EAX against
4100 * destination.
4101 */
4102 c->src.orig_val = c->src.val;
4103 c->src.val = c->regs[VCPU_REGS_RAX];
4104 emulate_2op_SrcV("cmp", c->src, c->dst, ctxt->eflags);
4105 if (ctxt->eflags & EFLG_ZF) {
4106 /* Success: write back to memory. */
4107 c->dst.val = c->src.orig_val;
4108 } else {
4109 /* Failure: write the value we saw to EAX. */
4110 c->dst.type = OP_REG;
4111 c->dst.addr.reg = (unsigned long *)&c->regs[VCPU_REGS_RAX];
4112 }
4113 break;
4114 case 0xb2: /* lss */
4115 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_SS);
4116 break;
4117 case 0xb3:
4118 btr: /* btr */
4119 emulate_2op_SrcV_nobyte("btr", c->src, c->dst, ctxt->eflags);
4120 break;
4121 case 0xb4: /* lfs */
4122 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_FS);
4123 break;
4124 case 0xb5: /* lgs */
4125 rc = emulate_load_segment(ctxt, ops, VCPU_SREG_GS);
4126 break;
4127 case 0xb6 ... 0xb7: /* movzx */
4128 c->dst.bytes = c->op_bytes;
4129 c->dst.val = (c->d & ByteOp) ? (u8) c->src.val
4130 : (u16) c->src.val;
4131 break;
4132 case 0xba: /* Grp8 */
4133 switch (c->modrm_reg & 3) {
4134 case 0:
4135 goto bt;
4136 case 1:
4137 goto bts;
4138 case 2:
4139 goto btr;
4140 case 3:
4141 goto btc;
4142 }
4143 break;
4144 case 0xbb:
4145 btc: /* btc */
4146 emulate_2op_SrcV_nobyte("btc", c->src, c->dst, ctxt->eflags);
4147 break;
4148 case 0xbc: { /* bsf */
4149 u8 zf;
4150 __asm__ ("bsf %2, %0; setz %1"
4151 : "=r"(c->dst.val), "=q"(zf)
4152 : "r"(c->src.val));
4153 ctxt->eflags &= ~X86_EFLAGS_ZF;
4154 if (zf) {
4155 ctxt->eflags |= X86_EFLAGS_ZF;
4156 c->dst.type = OP_NONE; /* Disable writeback. */
4157 }
4158 break;
4159 }
4160 case 0xbd: { /* bsr */
4161 u8 zf;
4162 __asm__ ("bsr %2, %0; setz %1"
4163 : "=r"(c->dst.val), "=q"(zf)
4164 : "r"(c->src.val));
4165 ctxt->eflags &= ~X86_EFLAGS_ZF;
4166 if (zf) {
4167 ctxt->eflags |= X86_EFLAGS_ZF;
4168 c->dst.type = OP_NONE; /* Disable writeback. */
4169 }
4170 break;
4171 }
4172 case 0xbe ... 0xbf: /* movsx */
4173 c->dst.bytes = c->op_bytes;
4174 c->dst.val = (c->d & ByteOp) ? (s8) c->src.val :
4175 (s16) c->src.val;
4176 break;
4177 case 0xc0 ... 0xc1: /* xadd */
4178 emulate_2op_SrcV("add", c->src, c->dst, ctxt->eflags);
4179 /* Write back the register source. */
4180 c->src.val = c->dst.orig_val;
4181 write_register_operand(&c->src);
4182 break;
4183 case 0xc3: /* movnti */
4184 c->dst.bytes = c->op_bytes;
4185 c->dst.val = (c->op_bytes == 4) ? (u32) c->src.val :
4186 (u64) c->src.val;
4187 break;
4188 case 0xc7: /* Grp9 (cmpxchg8b) */
4189 rc = emulate_grp9(ctxt, ops);
4190 break;
4191 default:
4192 goto cannot_emulate;
4193 }
4194
4195 if (rc != X86EMUL_CONTINUE)
4196 goto done;
4197
4198 goto writeback;
4199
4200 cannot_emulate:
4201 return EMULATION_FAILED;
4202 }
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree