drivers/ata/pata_mpiix.c

   1 /*
   2  * pata_mpiix.c         - Intel MPIIX PATA for new ATA layer
   3  *                        (C) 2005-2006 Red Hat Inc
   4  *                        Alan Cox <alan@redhat.com>
   5  *
   6  * The MPIIX is different enough to the PIIX4 and friends that we give it
   7  * a separate driver. The old ide/pci code handles this by just not tuning
   8  * MPIIX at all.
   9  *
  10  * The MPIIX also differs in another important way from the majority of PIIX
  11  * devices. The chip is a bridge (pardon the pun) between the old world of
  12  * ISA IDE and PCI IDE. Although the ATA timings are PCI configured the actual
  13  * IDE controller is not decoded in PCI space and the chip does not claim to
  14  * be IDE class PCI. This requires slightly non-standard probe logic compared
  15  * with PCI IDE and also that we do not disable the device when our driver is
  16  * unloaded (as it has many other functions).
  17  *
  18  * The driver conciously keeps this logic internally to avoid pushing quirky
  19  * PATA history into the clean libata layer.
  20  *
  21  * Thinkpad specific note: If you boot an MPIIX using a thinkpad with a PCMCIA
  22  * hard disk present this driver will not detect it. This is not a bug. In this
  23  * configuration the secondary port of the MPIIX is disabled and the addresses
  24  * are decoded by the PCMCIA bridge and therefore are for a generic IDE driver
  25  * to operate.
  26  */
  27
  28 #include <linux/kernel.h>
  29 #include <linux/module.h>
  30 #include <linux/pci.h>
  31 #include <linux/init.h>
  32 #include <linux/blkdev.h>
  33 #include <linux/delay.h>
  34 #include <scsi/scsi_host.h>
  35 #include <linux/libata.h>
  36
  37 #define DRV_NAME "pata_mpiix"
  38 #define DRV_VERSION "0.7.2"
  39
  40 enum {
  41         IDETIM = 0x6C,          /* IDE control register */
  42         IORDY = (1 << 1),
  43         PPE = (1 << 2),
  44         FTIM = (1 << 0),
  45         ENABLED = (1 << 15),
  46         SECONDARY = (1 << 14)
  47 };
  48
  49 static int mpiix_pre_reset(struct ata_port *ap)
  50 {
  51         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  52         static const struct pci_bits mpiix_enable_bits[] = {
  53                 { 0x6D, 1, 0x80, 0x80 },
  54                 { 0x6F, 1, 0x80, 0x80 }
  55         };
  56
  57         if (!pci_test_config_bits(pdev, &mpiix_enable_bits[ap->port_no]))
  58                 return -ENOENT;
  59         ap->cbl = ATA_CBL_PATA40;
  60         return ata_std_prereset(ap);
  61 }
  62
  63 /**
  64  *      mpiix_error_handler             -       probe reset
  65  *      @ap: ATA port
  66  *
  67  *      Perform the ATA probe and bus reset sequence plus specific handling
  68  *      for this hardware. The MPIIX has the enable bits in a different place
  69  *      to PIIX4 and friends. As a pure PIO device it has no cable detect
  70  */
  71
  72 static void mpiix_error_handler(struct ata_port *ap)
  73 {
  74         ata_bmdma_drive_eh(ap, mpiix_pre_reset, ata_std_softreset, NULL, ata_std_postreset);
  75 }
  76
  77 /**
  78  *      mpiix_set_piomode       -       set initial PIO mode data
  79  *      @ap: ATA interface
  80  *      @adev: ATA device
  81  *
  82  *      Called to do the PIO mode setup. The MPIIX allows us to program the
  83  *      IORDY sample point (2-5 clocks), recovery 1-4 clocks and whether
  84  *      prefetching or iordy are used.
  85  *
  86  *      This would get very ugly because we can only program timing for one
  87  *      device at a time, the other gets PIO0. Fortunately libata calls
  88  *      our qc_issue_prot command before a command is issued so we can
  89  *      flip the timings back and forth to reduce the pain.
  90  */
  91
  92 static void mpiix_set_piomode(struct ata_port *ap, struct ata_device *adev)
  93 {
  94         int control = 0;
  95         int pio = adev->pio_mode - XFER_PIO_0;
  96         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
  97         u16 idetim;
  98         static const     /* ISP  RTC */
  99         u8 timings[][2] = { { 0, 0 },
 100                             { 0, 0 },
 101                             { 1, 0 },
 102                             { 2, 1 },
 103                             { 2, 3 }, };
 104
 105         pci_read_config_word(pdev, IDETIM, &idetim);
 106         /* Mask the IORDY/TIME/PPE0 bank for this device */
 107         if (adev->class == ATA_DEV_ATA)
 108                 control |= PPE;         /* PPE enable for disk */
 109         if (ata_pio_need_iordy(adev))
 110                 control |= IORDY;       /* IORDY */
 111         if (pio > 0)
 112                 control |= FTIM;        /* This drive is on the fast timing bank */
 113
 114         /* Mask out timing and clear both TIME bank selects */
 115         idetim &= 0xCCEE;
 116         idetim &= ~(0x07  << (2 * adev->devno));
 117         idetim |= (control << (2 * adev->devno));
 118
 119         idetim |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
 120         pci_write_config_word(pdev, IDETIM, idetim);
 121
 122         /* We use ap->private_data as a pointer to the device currently
 123            loaded for timing */
 124         ap->private_data = adev;
 125 }
 126
 127 /**
 128  *      mpiix_qc_issue_prot     -       command issue
 129  *      @qc: command pending
 130  *
 131  *      Called when the libata layer is about to issue a command. We wrap
 132  *      this interface so that we can load the correct ATA timings if
 133  *      neccessary. Our logic also clears TIME0/TIME1 for the other device so
 134  *      that, even if we get this wrong, cycles to the other device will
 135  *      be made PIO0.
 136  */
 137
 138 static unsigned int mpiix_qc_issue_prot(struct ata_queued_cmd *qc)
 139 {
 140         struct ata_port *ap = qc->ap;
 141         struct ata_device *adev = qc->dev;
 142
 143         /* If modes have been configured and the channel data is not loaded
 144            then load it. We have to check if pio_mode is set as the core code
 145            does not set adev->pio_mode to XFER_PIO_0 while probing as would be
 146            logical */
 147
 148         if (adev->pio_mode && adev != ap->private_data)
 149                 mpiix_set_piomode(ap, adev);
 150
 151         return ata_qc_issue_prot(qc);
 152 }
 153
 154 static struct scsi_host_template mpiix_sht = {
 155         .module                 = THIS_MODULE,
 156         .name                   = DRV_NAME,
 157         .ioctl                  = ata_scsi_ioctl,
 158         .queuecommand           = ata_scsi_queuecmd,
 159         .can_queue              = ATA_DEF_QUEUE,
 160         .this_id                = ATA_SHT_THIS_ID,
 161         .sg_tablesize           = LIBATA_MAX_PRD,
 162         .max_sectors            = ATA_MAX_SECTORS,
 163         .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
 164         .emulated               = ATA_SHT_EMULATED,
 165         .use_clustering         = ATA_SHT_USE_CLUSTERING,
 166         .proc_name              = DRV_NAME,
 167         .dma_boundary           = ATA_DMA_BOUNDARY,
 168         .slave_configure        = ata_scsi_slave_config,
 169         .bios_param             = ata_std_bios_param,
 170 };
 171
 172 static struct ata_port_operations mpiix_port_ops = {
 173         .port_disable   = ata_port_disable,
 174         .set_piomode    = mpiix_set_piomode,
 175
 176         .tf_load        = ata_tf_load,
 177         .tf_read        = ata_tf_read,
 178         .check_status   = ata_check_status,
 179         .exec_command   = ata_exec_command,
 180         .dev_select     = ata_std_dev_select,
 181
 182         .freeze         = ata_bmdma_freeze,
 183         .thaw           = ata_bmdma_thaw,
 184         .error_handler  = mpiix_error_handler,
 185         .post_internal_cmd = ata_bmdma_post_internal_cmd,
 186
 187         .qc_prep        = ata_qc_prep,
 188         .qc_issue       = mpiix_qc_issue_prot,
 189         .data_xfer      = ata_pio_data_xfer,
 190
 191         .irq_handler    = ata_interrupt,
 192         .irq_clear      = ata_bmdma_irq_clear,
 193
 194         .port_start     = ata_port_start,
 195         .port_stop      = ata_port_stop,
 196         .host_stop      = ata_host_stop
 197 };
 198
 199 static int mpiix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
 200 {
 201         /* Single threaded by the PCI probe logic */
 202         static struct ata_probe_ent probe[2];
 203         static int printed_version;
 204         u16 idetim;
 205         int enabled;
 206
 207         if (!printed_version++)
 208                 dev_printk(KERN_DEBUG, &dev->dev, "version " DRV_VERSION "\n");
 209
 210         /* MPIIX has many functions which can be turned on or off according
 211            to other devices present. Make sure IDE is enabled before we try
 212            and use it */
 213
 214         pci_read_config_word(dev, IDETIM, &idetim);
 215         if (!(idetim & ENABLED))
 216                 return -ENODEV;
 217
 218         /* We do our own plumbing to avoid leaking special cases for whacko
 219            ancient hardware into the core code. There are two issues to
 220            worry about.  #1 The chip is a bridge so if in legacy mode and
 221            without BARs set fools the setup.  #2 If you pci_disable_device
 222            the MPIIX your box goes castors up */
 223
 224         INIT_LIST_HEAD(&probe[0].node);
 225         probe[0].dev = pci_dev_to_dev(dev);
 226         probe[0].port_ops = &mpiix_port_ops;
 227         probe[0].sht = &mpiix_sht;
 228         probe[0].pio_mask = 0x1F;
 229         probe[0].irq = 14;
 230         probe[0].irq_flags = SA_SHIRQ;
 231         probe[0].port_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST;
 232         probe[0].n_ports = 1;
 233         probe[0].port[0].cmd_addr = 0x1F0;
 234         probe[0].port[0].ctl_addr = 0x3F6;
 235         probe[0].port[0].altstatus_addr = 0x3F6;
 236
 237         /* The secondary lurks at different addresses but is otherwise
 238            the same beastie */
 239
 240         INIT_LIST_HEAD(&probe[1].node);
 241         probe[1] = probe[0];
 242         probe[1].irq = 15;
 243         probe[1].port[0].cmd_addr = 0x170;
 244         probe[1].port[0].ctl_addr = 0x376;
 245         probe[1].port[0].altstatus_addr = 0x376;
 246
 247         /* Let libata fill in the port details */
 248         ata_std_ports(&probe[0].port[0]);
 249         ata_std_ports(&probe[1].port[0]);
 250
 251         /* Now add the port that is active */
 252         enabled = (idetim & SECONDARY) ? 1 : 0;
 253
 254         if (ata_device_add(&probe[enabled]))
 255                 return 0;
 256         return -ENODEV;
 257 }
 258
 259 /**
 260  *      mpiix_remove_one        -       device unload
 261  *      @pdev: PCI device being removed
 262  *
 263  *      Handle an unplug/unload event for a PCI device. Unload the
 264  *      PCI driver but do not use the default handler as we *MUST NOT*
 265  *      disable the device as it has other functions.
 266  */
 267
 268 static void __devexit mpiix_remove_one(struct pci_dev *pdev)
 269 {
 270         struct device *dev = pci_dev_to_dev(pdev);
 271         struct ata_host *host = dev_get_drvdata(dev);
 272
 273         ata_host_remove(host);
 274         dev_set_drvdata(dev, NULL);
 275 }
 276
 277 static const struct pci_device_id mpiix[] = {
 278         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371MX), },
 279
 280         { },
 281 };
 282
 283 static struct pci_driver mpiix_pci_driver = {
 284         .name           = DRV_NAME,
 285         .id_table       = mpiix,
 286         .probe          = mpiix_init_one,
 287         .remove         = mpiix_remove_one
 288 };
 289
 290 static int __init mpiix_init(void)
 291 {
 292         return pci_register_driver(&mpiix_pci_driver);
 293 }
 294
 295 static void __exit mpiix_exit(void)
 296 {
 297         pci_unregister_driver(&mpiix_pci_driver);
 298 }
 299
 300 MODULE_AUTHOR("Alan Cox");
 301 MODULE_DESCRIPTION("low-level driver for Intel MPIIX");
 302 MODULE_LICENSE("GPL");
 303 MODULE_DEVICE_TABLE(pci, mpiix);
 304 MODULE_VERSION(DRV_VERSION);
 305
 306 module_init(mpiix_init);
 307 module_exit(mpiix_exit);