3 * arch/arm/mach-u300/clock.c
6 * Copyright (C) 2007-2009 ST-Ericsson AB
7 * License terms: GNU General Public License (GPL) version 2
8 * Define clocks in the app platform.
9 * Author: Linus Walleij <linus.walleij@stericsson.com>
10 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/list.h>
16 #include <linux/errno.h>
17 #include <linux/err.h>
18 #include <linux/string.h>
19 #include <linux/clk.h>
20 #include <linux/mutex.h>
21 #include <linux/spinlock.h>
22 #include <linux/debugfs.h>
23 #include <linux/device.h>
24 #include <linux/init.h>
25 #include <linux/timer.h>
27 #include <linux/seq_file.h>
29 #include <asm/clkdev.h>
30 #include <mach/hardware.h>
31 #include <mach/syscon.h>
37 * - move all handling of the CCR register into this file and create
38 * a spinlock for the CCR register
39 * - switch to the clkdevice lookup mechanism that maps clocks to
40 * device ID:s instead when it becomes available in kernel 2.6.29.
41 * - implement rate get/set for all clocks that need it.
45 * Syscon clock I/O registers lock so clock requests don't collide
46 * NOTE: this is a local lock only used to lock access to clock and
47 * reset registers in syscon.
49 static DEFINE_SPINLOCK(syscon_clkreg_lock
);
50 static DEFINE_SPINLOCK(syscon_resetreg_lock
);
53 * The clocking hierarchy currently looks like this.
54 * NOTE: the idea is NOT to show how the clocks are routed on the chip!
55 * The ideas is to show dependencies, so a clock higher up in the
56 * hierarchy has to be on in order for another clock to be on. Now,
57 * both CPU and DMA can actually be on top of the hierarchy, and that
58 * is not modeled currently. Instead we have the backbone AMBA bus on
59 * top. This bus cannot be programmed in any way but conceptually it
60 * needs to be active for the bridges and devices to transport data.
62 * Please be aware that a few clocks are hw controlled, which mean that
63 * the hw itself can turn on/off or change the rate of the clock when
69 * +- NANDIF NAND Flash interface
70 * +- SEMI Shared Memory interface
71 * +- ISP Image Signal Processor (U335 only)
73 * +- DMA Direct Memory Access Controller
74 * +- AAIF APP/ACC Inteface (Mobile Scalable Link, MSL)
76 * +- VIDEO_ENC AVE2/3 Video Encoder
77 * +- XGAM Graphics Accelerator Controller
82 * | +- ahb:1 INTCON Interrupt controller
83 * | +- ahb:3 MSPRO Memory Stick Pro controller
84 * | +- ahb:4 EMIF External Memory interface
86 * +- fast:0 FAST bridge
88 * | +- fast:1 MMCSD MMC/SD card reader controller
89 * | +- fast:2 I2S0 PCM I2S channel 0 controller
90 * | +- fast:3 I2S1 PCM I2S channel 1 controller
91 * | +- fast:4 I2C0 I2C channel 0 controller
92 * | +- fast:5 I2C1 I2C channel 1 controller
93 * | +- fast:6 SPI SPI controller
94 * | +- fast:7 UART1 Secondary UART (U335 only)
96 * +- slow:0 SLOW bridge
98 * +- slow:1 SYSCON (not possible to control)
99 * +- slow:2 WDOG Watchdog
100 * +- slow:3 UART0 primary UART
101 * +- slow:4 TIMER_APP Application timer - used in Linux
102 * +- slow:5 KEYPAD controller
103 * +- slow:6 GPIO controller
104 * +- slow:7 RTC controller
105 * +- slow:8 BT Bus Tracer (not used currently)
106 * +- slow:9 EH Event Handler (not used currently)
107 * +- slow:a TIMER_ACC Access style timer (not used currently)
108 * +- slow:b PPM (U335 only, what is that?)
112 * Reset control functions. We remember if a block has been
113 * taken out of reset and don't remove the reset assertion again
114 * and vice versa. Currently we only remove resets so the
115 * enablement function is defined out.
117 static void syscon_block_reset_enable(struct clk
*clk
)
120 unsigned long iflags
;
122 /* Not all blocks support resetting */
123 if (!clk
->res_reg
|| !clk
->res_mask
)
125 spin_lock_irqsave(&syscon_resetreg_lock
, iflags
);
126 val
= readw(clk
->res_reg
);
127 val
|= clk
->res_mask
;
128 writew(val
, clk
->res_reg
);
129 spin_unlock_irqrestore(&syscon_resetreg_lock
, iflags
);
133 static void syscon_block_reset_disable(struct clk
*clk
)
136 unsigned long iflags
;
138 /* Not all blocks support resetting */
139 if (!clk
->res_reg
|| !clk
->res_mask
)
141 spin_lock_irqsave(&syscon_resetreg_lock
, iflags
);
142 val
= readw(clk
->res_reg
);
143 val
&= ~clk
->res_mask
;
144 writew(val
, clk
->res_reg
);
145 spin_unlock_irqrestore(&syscon_resetreg_lock
, iflags
);
149 int __clk_get(struct clk
*clk
)
153 /* The MMC and MSPRO clocks need some special set-up */
154 if (!strcmp(clk
->name
, "MCLK")) {
155 /* Set default MMC clock divisor to 18.9 MHz */
156 writew(0x0054U
, U300_SYSCON_VBASE
+ U300_SYSCON_MMF0R
);
157 val
= readw(U300_SYSCON_VBASE
+ U300_SYSCON_MMCR
);
158 /* Disable the MMC feedback clock */
159 val
&= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE
;
160 /* Disable MSPRO frequency */
161 val
&= ~U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE
;
162 writew(val
, U300_SYSCON_VBASE
+ U300_SYSCON_MMCR
);
164 if (!strcmp(clk
->name
, "MSPRO")) {
165 val
= readw(U300_SYSCON_VBASE
+ U300_SYSCON_MMCR
);
166 /* Disable the MMC feedback clock */
167 val
&= ~U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE
;
168 /* Enable MSPRO frequency */
169 val
|= U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE
;
170 writew(val
, U300_SYSCON_VBASE
+ U300_SYSCON_MMCR
);
174 EXPORT_SYMBOL(__clk_get
);
176 void __clk_put(struct clk
*clk
)
179 EXPORT_SYMBOL(__clk_put
);
181 static void syscon_clk_disable(struct clk
*clk
)
183 unsigned long iflags
;
185 /* Don't touch the hardware controlled clocks */
189 spin_lock_irqsave(&syscon_clkreg_lock
, iflags
);
190 writew(clk
->clk_val
, U300_SYSCON_VBASE
+ U300_SYSCON_SBCDR
);
191 spin_unlock_irqrestore(&syscon_clkreg_lock
, iflags
);
194 static void syscon_clk_enable(struct clk
*clk
)
196 unsigned long iflags
;
198 /* Don't touch the hardware controlled clocks */
202 spin_lock_irqsave(&syscon_clkreg_lock
, iflags
);
203 writew(clk
->clk_val
, U300_SYSCON_VBASE
+ U300_SYSCON_SBCER
);
204 spin_unlock_irqrestore(&syscon_clkreg_lock
, iflags
);
207 static u16
syscon_clk_get_rate(void)
210 unsigned long iflags
;
212 spin_lock_irqsave(&syscon_clkreg_lock
, iflags
);
213 val
= readw(U300_SYSCON_VBASE
+ U300_SYSCON_CCR
);
214 val
&= U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK
;
215 spin_unlock_irqrestore(&syscon_clkreg_lock
, iflags
);
219 #ifdef CONFIG_MACH_U300_USE_I2S_AS_MASTER
220 static void enable_i2s0_vcxo(void)
223 unsigned long iflags
;
225 spin_lock_irqsave(&syscon_clkreg_lock
, iflags
);
226 /* Set I2S0 to use the VCXO 26 MHz clock */
227 val
= readw(U300_SYSCON_VBASE
+ U300_SYSCON_CCR
);
228 val
|= U300_SYSCON_CCR_TURN_VCXO_ON
;
229 writew(val
, U300_SYSCON_VBASE
+ U300_SYSCON_CCR
);
230 val
|= U300_SYSCON_CCR_I2S0_USE_VCXO
;
231 writew(val
, U300_SYSCON_VBASE
+ U300_SYSCON_CCR
);
232 val
= readw(U300_SYSCON_VBASE
+ U300_SYSCON_CEFR
);
233 val
|= U300_SYSCON_CEFR_I2S0_CLK_EN
;
234 writew(val
, U300_SYSCON_VBASE
+ U300_SYSCON_CEFR
);
235 spin_unlock_irqrestore(&syscon_clkreg_lock
, iflags
);
238 static void enable_i2s1_vcxo(void)
241 unsigned long iflags
;
243 spin_lock_irqsave(&syscon_clkreg_lock
, iflags
);
244 /* Set I2S1 to use the VCXO 26 MHz clock */
245 val
= readw(U300_SYSCON_VBASE
+ U300_SYSCON_CCR
);
246 val
|= U300_SYSCON_CCR_TURN_VCXO_ON
;
247 writew(val
, U300_SYSCON_VBASE
+ U300_SYSCON_CCR
);
248 val
|= U300_SYSCON_CCR_I2S1_USE_VCXO
;
249 writew(val
, U300_SYSCON_VBASE
+ U300_SYSCON_CCR
);
250 val
= readw(U300_SYSCON_VBASE
+ U300_SYSCON_CEFR
);
251 val
|= U300_SYSCON_CEFR_I2S1_CLK_EN
;
252 writew(val
, U300_SYSCON_VBASE
+ U300_SYSCON_CEFR
);
253 spin_unlock_irqrestore(&syscon_clkreg_lock
, iflags
);
256 static void disable_i2s0_vcxo(void)
259 unsigned long iflags
;
261 spin_lock_irqsave(&syscon_clkreg_lock
, iflags
);
262 /* Disable I2S0 use of the VCXO 26 MHz clock */
263 val
= readw(U300_SYSCON_VBASE
+ U300_SYSCON_CCR
);
264 val
&= ~U300_SYSCON_CCR_I2S0_USE_VCXO
;
265 writew(val
, U300_SYSCON_VBASE
+ U300_SYSCON_CCR
);
266 /* Deactivate VCXO if noone else is using VCXO */
267 if (!(val
& U300_SYSCON_CCR_I2S1_USE_VCXO
))
268 val
&= ~U300_SYSCON_CCR_TURN_VCXO_ON
;
269 writew(val
, U300_SYSCON_VBASE
+ U300_SYSCON_CCR
);
270 val
= readw(U300_SYSCON_VBASE
+ U300_SYSCON_CEFR
);
271 val
&= ~U300_SYSCON_CEFR_I2S0_CLK_EN
;
272 writew(val
, U300_SYSCON_VBASE
+ U300_SYSCON_CEFR
);
273 spin_unlock_irqrestore(&syscon_clkreg_lock
, iflags
);
276 static void disable_i2s1_vcxo(void)
279 unsigned long iflags
;
281 spin_lock_irqsave(&syscon_clkreg_lock
, iflags
);
282 /* Disable I2S1 use of the VCXO 26 MHz clock */
283 val
= readw(U300_SYSCON_VBASE
+ U300_SYSCON_CCR
);
284 val
&= ~U300_SYSCON_CCR_I2S1_USE_VCXO
;
285 writew(val
, U300_SYSCON_VBASE
+ U300_SYSCON_CCR
);
286 /* Deactivate VCXO if noone else is using VCXO */
287 if (!(val
& U300_SYSCON_CCR_I2S0_USE_VCXO
))
288 val
&= ~U300_SYSCON_CCR_TURN_VCXO_ON
;
289 writew(val
, U300_SYSCON_VBASE
+ U300_SYSCON_CCR
);
290 val
= readw(U300_SYSCON_VBASE
+ U300_SYSCON_CEFR
);
291 val
&= ~U300_SYSCON_CEFR_I2S0_CLK_EN
;
292 writew(val
, U300_SYSCON_VBASE
+ U300_SYSCON_CEFR
);
293 spin_unlock_irqrestore(&syscon_clkreg_lock
, iflags
);
295 #endif /* CONFIG_MACH_U300_USE_I2S_AS_MASTER */
298 static void syscon_clk_rate_set_mclk(unsigned long rate
)
302 unsigned long iflags
;
333 printk(KERN_ERR
"Trying to set MCLK to unknown speed! %ld\n",
338 spin_lock_irqsave(&syscon_clkreg_lock
, iflags
);
339 reg
= readw(U300_SYSCON_VBASE
+ U300_SYSCON_MMF0R
) &
340 ~U300_SYSCON_MMF0R_MASK
;
341 writew(reg
| val
, U300_SYSCON_VBASE
+ U300_SYSCON_MMF0R
);
342 spin_unlock_irqrestore(&syscon_clkreg_lock
, iflags
);
345 void syscon_clk_rate_set_cpuclk(unsigned long rate
)
348 unsigned long iflags
;
352 val
= U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER
;
355 val
= U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE
;
358 val
= U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH
;
361 val
= U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST
;
366 spin_lock_irqsave(&syscon_clkreg_lock
, iflags
);
367 val
|= readw(U300_SYSCON_VBASE
+ U300_SYSCON_CCR
) &
368 ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK
;
369 writew(val
, U300_SYSCON_VBASE
+ U300_SYSCON_CCR
);
370 spin_unlock_irqrestore(&syscon_clkreg_lock
, iflags
);
372 EXPORT_SYMBOL(syscon_clk_rate_set_cpuclk
);
374 void clk_disable(struct clk
*clk
)
376 unsigned long iflags
;
378 spin_lock_irqsave(&clk
->lock
, iflags
);
379 if (clk
->usecount
> 0 && !(--clk
->usecount
)) {
380 /* some blocks lack clocking registers and cannot be disabled */
383 if (likely((u32
)clk
->parent
))
384 clk_disable(clk
->parent
);
386 #ifdef CONFIG_MACH_U300_USE_I2S_AS_MASTER
387 if (unlikely(!strcmp(clk
->name
, "I2S0")))
389 if (unlikely(!strcmp(clk
->name
, "I2S1")))
392 spin_unlock_irqrestore(&clk
->lock
, iflags
);
394 EXPORT_SYMBOL(clk_disable
);
396 int clk_enable(struct clk
*clk
)
399 unsigned long iflags
;
401 spin_lock_irqsave(&clk
->lock
, iflags
);
402 if (clk
->usecount
++ == 0) {
403 if (likely((u32
)clk
->parent
))
404 ret
= clk_enable(clk
->parent
);
406 if (unlikely(ret
!= 0))
409 /* remove reset line (we never enable reset again) */
410 syscon_block_reset_disable(clk
);
411 /* clocks without enable function are always on */
414 #ifdef CONFIG_MACH_U300_USE_I2S_AS_MASTER
415 if (unlikely(!strcmp(clk
->name
, "I2S0")))
417 if (unlikely(!strcmp(clk
->name
, "I2S1")))
422 spin_unlock_irqrestore(&clk
->lock
, iflags
);
426 EXPORT_SYMBOL(clk_enable
);
428 /* Returns the clock rate in Hz */
429 static unsigned long clk_get_rate_cpuclk(struct clk
*clk
)
433 val
= syscon_clk_get_rate();
436 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER
:
437 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW
:
439 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE
:
441 case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH
:
443 case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST
:
451 static unsigned long clk_get_rate_ahb_clk(struct clk
*clk
)
455 val
= syscon_clk_get_rate();
458 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER
:
459 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW
:
461 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE
:
463 case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH
:
464 case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST
:
473 static unsigned long clk_get_rate_emif_clk(struct clk
*clk
)
477 val
= syscon_clk_get_rate();
480 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER
:
481 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW
:
483 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE
:
485 case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH
:
486 case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST
:
495 static unsigned long clk_get_rate_xgamclk(struct clk
*clk
)
499 val
= syscon_clk_get_rate();
502 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER
:
503 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW
:
505 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE
:
507 case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH
:
508 case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST
:
517 static unsigned long clk_get_rate_mclk(struct clk
*clk
)
521 val
= syscon_clk_get_rate();
524 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER
:
526 * Here, the 208 MHz PLL gets shut down and the always
527 * on 13 MHz PLL used for RTC etc kicks into use
531 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW
:
532 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE
:
533 case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH
:
534 case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST
:
537 * This clock is under program control. The register is
538 * divided in two nybbles, bit 7-4 gives cycles-1 to count
539 * high, bit 3-0 gives cycles-1 to count low. Distribute
540 * these with no more than 1 cycle difference between
541 * low and high and add low and high to get the actual
542 * divisor. The base PLL is 208 MHz. Writing 0x00 will
543 * divide by 1 and 1 so the highest frequency possible
547 * f = 208 / ((5+1) + (4+1)) = 208 / 11 = 18.9 MHz
549 u16 val
= readw(U300_SYSCON_VBASE
+ U300_SYSCON_MMF0R
) &
550 U300_SYSCON_MMF0R_MASK
;
581 static unsigned long clk_get_rate_i2s_i2c_spi(struct clk
*clk
)
585 val
= syscon_clk_get_rate();
588 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER
:
589 case U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW
:
591 case U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE
:
592 case U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH
:
593 case U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST
:
602 unsigned long clk_get_rate(struct clk
*clk
)
605 return clk
->get_rate(clk
);
609 EXPORT_SYMBOL(clk_get_rate
);
611 static unsigned long clk_round_rate_mclk(struct clk
*clk
, unsigned long rate
)
613 if (rate
<= 18900000)
615 if (rate
<= 20800000)
617 if (rate
<= 23100000)
619 if (rate
<= 26000000)
621 if (rate
<= 29700000)
623 if (rate
<= 34700000)
625 if (rate
<= 41600000)
627 if (rate
<= 52000000)
632 static unsigned long clk_round_rate_cpuclk(struct clk
*clk
, unsigned long rate
)
634 if (rate
<= 13000000)
636 if (rate
<= 52000000)
638 if (rate
<= 104000000)
640 if (rate
<= 208000000)
646 * This adjusts a requested rate to the closest exact rate
647 * a certain clock can provide. For a fixed clock it's
650 long clk_round_rate(struct clk
*clk
, unsigned long rate
)
652 /* TODO: get apropriate switches for EMIFCLK, AHBCLK and MCLK */
653 /* Else default to fixed value */
655 if (clk
->round_rate
) {
656 return (long) clk
->round_rate(clk
, rate
);
658 printk(KERN_ERR
"clock: Failed to round rate of %s\n",
661 return (long) clk
->rate
;
663 EXPORT_SYMBOL(clk_round_rate
);
665 static int clk_set_rate_mclk(struct clk
*clk
, unsigned long rate
)
667 syscon_clk_rate_set_mclk(clk_round_rate(clk
, rate
));
671 static int clk_set_rate_cpuclk(struct clk
*clk
, unsigned long rate
)
673 syscon_clk_rate_set_cpuclk(clk_round_rate(clk
, rate
));
677 int clk_set_rate(struct clk
*clk
, unsigned long rate
)
679 /* TODO: set for EMIFCLK and AHBCLK */
680 /* Else assume the clock is fixed and fail */
682 return clk
->set_rate(clk
, rate
);
684 printk(KERN_ERR
"clock: Failed to set %s to %ld hz\n",
689 EXPORT_SYMBOL(clk_set_rate
);
692 * Clock definitions. The clock parents are set to respective
693 * bridge and the clock framework makes sure that the clocks have
694 * parents activated and are brought out of reset when in use.
696 * Clocks that have hw_ctrld = true are hw controlled, and the hw
697 * can by itself turn these clocks on and off.
698 * So in other words, we don't really have to care about them.
701 static struct clk amba_clk
= {
703 .rate
= 52000000, /* this varies! */
706 .lock
= __SPIN_LOCK_UNLOCKED(amba_clk
.lock
),
710 * These blocks are connected directly to the AMBA bus
714 static struct clk cpu_clk
= {
717 .rate
= 208000000, /* this varies! */
720 .res_reg
= U300_SYSCON_VBASE
+ U300_SYSCON_RRR
,
721 .res_mask
= U300_SYSCON_RRR_CPU_RESET_EN
,
722 .set_rate
= clk_set_rate_cpuclk
,
723 .get_rate
= clk_get_rate_cpuclk
,
724 .round_rate
= clk_round_rate_cpuclk
,
725 .lock
= __SPIN_LOCK_UNLOCKED(cpu_clk
.lock
),
728 static struct clk nandif_clk
= {
733 .res_reg
= U300_SYSCON_VBASE
+ U300_SYSCON_RRR
,
734 .res_mask
= U300_SYSCON_RRR_NANDIF_RESET_EN
,
735 .clk_val
= U300_SYSCON_SBCER_NANDIF_CLK_EN
,
736 .enable
= syscon_clk_enable
,
737 .disable
= syscon_clk_disable
,
738 .lock
= __SPIN_LOCK_UNLOCKED(nandif_clk
.lock
),
741 static struct clk semi_clk
= {
744 .rate
= 0, /* FIXME */
745 /* It is not possible to reset SEMI */
748 .clk_val
= U300_SYSCON_SBCER_SEMI_CLK_EN
,
749 .enable
= syscon_clk_enable
,
750 .disable
= syscon_clk_disable
,
751 .lock
= __SPIN_LOCK_UNLOCKED(semi_clk
.lock
),
754 #ifdef CONFIG_MACH_U300_BS335
755 static struct clk isp_clk
= {
758 .rate
= 0, /* FIXME */
761 .res_reg
= U300_SYSCON_VBASE
+ U300_SYSCON_RRR
,
762 .res_mask
= U300_SYSCON_RRR_ISP_RESET_EN
,
763 .clk_val
= U300_SYSCON_SBCER_ISP_CLK_EN
,
764 .enable
= syscon_clk_enable
,
765 .disable
= syscon_clk_disable
,
766 .lock
= __SPIN_LOCK_UNLOCKED(isp_clk
.lock
),
769 static struct clk cds_clk
= {
772 .rate
= 0, /* FIXME */
775 .res_reg
= U300_SYSCON_VBASE
+ U300_SYSCON_RRR
,
776 .res_mask
= U300_SYSCON_RRR_CDS_RESET_EN
,
777 .clk_val
= U300_SYSCON_SBCER_CDS_CLK_EN
,
778 .enable
= syscon_clk_enable
,
779 .disable
= syscon_clk_disable
,
780 .lock
= __SPIN_LOCK_UNLOCKED(cds_clk
.lock
),
784 static struct clk dma_clk
= {
787 .rate
= 52000000, /* this varies! */
790 .res_reg
= U300_SYSCON_VBASE
+ U300_SYSCON_RRR
,
791 .res_mask
= U300_SYSCON_RRR_DMAC_RESET_EN
,
792 .clk_val
= U300_SYSCON_SBCER_DMAC_CLK_EN
,
793 .enable
= syscon_clk_enable
,
794 .disable
= syscon_clk_disable
,
795 .lock
= __SPIN_LOCK_UNLOCKED(dma_clk
.lock
),
798 static struct clk aaif_clk
= {
801 .rate
= 52000000, /* this varies! */
804 .res_reg
= U300_SYSCON_VBASE
+ U300_SYSCON_RRR
,
805 .res_mask
= U300_SYSCON_RRR_AAIF_RESET_EN
,
806 .clk_val
= U300_SYSCON_SBCER_AAIF_CLK_EN
,
807 .enable
= syscon_clk_enable
,
808 .disable
= syscon_clk_disable
,
809 .lock
= __SPIN_LOCK_UNLOCKED(aaif_clk
.lock
),
812 static struct clk apex_clk
= {
815 .rate
= 0, /* FIXME */
818 .res_reg
= U300_SYSCON_VBASE
+ U300_SYSCON_RRR
,
819 .res_mask
= U300_SYSCON_RRR_APEX_RESET_EN
,
820 .clk_val
= U300_SYSCON_SBCER_APEX_CLK_EN
,
821 .enable
= syscon_clk_enable
,
822 .disable
= syscon_clk_disable
,
823 .lock
= __SPIN_LOCK_UNLOCKED(apex_clk
.lock
),
826 static struct clk video_enc_clk
= {
829 .rate
= 208000000, /* this varies! */
832 .res_reg
= U300_SYSCON_VBASE
+ U300_SYSCON_RRR
,
833 /* This has XGAM in the name but refers to the video encoder */
834 .res_mask
= U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN
,
835 .clk_val
= U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN
,
836 .enable
= syscon_clk_enable
,
837 .disable
= syscon_clk_disable
,
838 .lock
= __SPIN_LOCK_UNLOCKED(video_enc_clk
.lock
),
841 static struct clk xgam_clk
= {
844 .rate
= 52000000, /* this varies! */
847 .res_reg
= U300_SYSCON_VBASE
+ U300_SYSCON_RRR
,
848 .res_mask
= U300_SYSCON_RRR_XGAM_RESET_EN
,
849 .clk_val
= U300_SYSCON_SBCER_XGAM_CLK_EN
,
850 .get_rate
= clk_get_rate_xgamclk
,
851 .enable
= syscon_clk_enable
,
852 .disable
= syscon_clk_disable
,
853 .lock
= __SPIN_LOCK_UNLOCKED(xgam_clk
.lock
),
856 /* This clock is used to activate the video encoder */
857 static struct clk ahb_clk
= {
860 .rate
= 52000000, /* this varies! */
861 .hw_ctrld
= false, /* This one is set to false due to HW bug */
863 .res_reg
= U300_SYSCON_VBASE
+ U300_SYSCON_RRR
,
864 .res_mask
= U300_SYSCON_RRR_AHB_RESET_EN
,
865 .clk_val
= U300_SYSCON_SBCER_AHB_CLK_EN
,
866 .enable
= syscon_clk_enable
,
867 .disable
= syscon_clk_disable
,
868 .get_rate
= clk_get_rate_ahb_clk
,
869 .lock
= __SPIN_LOCK_UNLOCKED(ahb_clk
.lock
),
874 * Clocks on the AHB bridge
877 static struct clk ahb_subsys_clk
= {
878 .name
= "AHB_SUBSYS",
880 .rate
= 52000000, /* this varies! */
883 .clk_val
= U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN
,
884 .enable
= syscon_clk_enable
,
885 .disable
= syscon_clk_disable
,
886 .get_rate
= clk_get_rate_ahb_clk
,
887 .lock
= __SPIN_LOCK_UNLOCKED(ahb_subsys_clk
.lock
),
890 static struct clk intcon_clk
= {
892 .parent
= &ahb_subsys_clk
,
893 .rate
= 52000000, /* this varies! */
896 .res_reg
= U300_SYSCON_VBASE
+ U300_SYSCON_RRR
,
897 .res_mask
= U300_SYSCON_RRR_INTCON_RESET_EN
,
898 /* INTCON can be reset but not clock-gated */
899 .lock
= __SPIN_LOCK_UNLOCKED(intcon_clk
.lock
),
903 static struct clk mspro_clk
= {
905 .parent
= &ahb_subsys_clk
,
906 .rate
= 0, /* FIXME */
909 .res_reg
= U300_SYSCON_VBASE
+ U300_SYSCON_RRR
,
910 .res_mask
= U300_SYSCON_RRR_MSPRO_RESET_EN
,
911 .clk_val
= U300_SYSCON_SBCER_MSPRO_CLK_EN
,
912 .enable
= syscon_clk_enable
,
913 .disable
= syscon_clk_disable
,
914 .lock
= __SPIN_LOCK_UNLOCKED(mspro_clk
.lock
),
917 static struct clk emif_clk
= {
919 .parent
= &ahb_subsys_clk
,
920 .rate
= 104000000, /* this varies! */
923 .res_reg
= U300_SYSCON_VBASE
+ U300_SYSCON_RRR
,
924 .res_mask
= U300_SYSCON_RRR_EMIF_RESET_EN
,
925 .clk_val
= U300_SYSCON_SBCER_EMIF_CLK_EN
,
926 .enable
= syscon_clk_enable
,
927 .disable
= syscon_clk_disable
,
928 .get_rate
= clk_get_rate_emif_clk
,
929 .lock
= __SPIN_LOCK_UNLOCKED(emif_clk
.lock
),
934 * Clocks on the FAST bridge
936 static struct clk fast_clk
= {
937 .name
= "FAST_BRIDGE",
939 .rate
= 13000000, /* this varies! */
942 .res_reg
= U300_SYSCON_VBASE
+ U300_SYSCON_RFR
,
943 .res_mask
= U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE
,
944 .clk_val
= U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN
,
945 .enable
= syscon_clk_enable
,
946 .disable
= syscon_clk_disable
,
947 .lock
= __SPIN_LOCK_UNLOCKED(fast_clk
.lock
),
951 * The MMCI apb_pclk is hardwired to the same terminal as the
952 * external MCI clock. Thus this will be referenced twice.
954 static struct clk mmcsd_clk
= {
957 .rate
= 18900000, /* this varies! */
960 .res_reg
= U300_SYSCON_VBASE
+ U300_SYSCON_RFR
,
961 .res_mask
= U300_SYSCON_RFR_MMC_RESET_ENABLE
,
962 .clk_val
= U300_SYSCON_SBCER_MMC_CLK_EN
,
963 .get_rate
= clk_get_rate_mclk
,
964 .set_rate
= clk_set_rate_mclk
,
965 .round_rate
= clk_round_rate_mclk
,
966 .disable
= syscon_clk_disable
,
967 .enable
= syscon_clk_enable
,
968 .lock
= __SPIN_LOCK_UNLOCKED(mmcsd_clk
.lock
),
971 static struct clk i2s0_clk
= {
974 .rate
= 26000000, /* this varies! */
977 .res_reg
= U300_SYSCON_VBASE
+ U300_SYSCON_RFR
,
978 .res_mask
= U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE
,
979 .clk_val
= U300_SYSCON_SBCER_I2S0_CORE_CLK_EN
,
980 .enable
= syscon_clk_enable
,
981 .disable
= syscon_clk_disable
,
982 .get_rate
= clk_get_rate_i2s_i2c_spi
,
983 .lock
= __SPIN_LOCK_UNLOCKED(i2s0_clk
.lock
),
986 static struct clk i2s1_clk
= {
989 .rate
= 26000000, /* this varies! */
992 .res_reg
= U300_SYSCON_VBASE
+ U300_SYSCON_RFR
,
993 .res_mask
= U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE
,
994 .clk_val
= U300_SYSCON_SBCER_I2S1_CORE_CLK_EN
,
995 .enable
= syscon_clk_enable
,
996 .disable
= syscon_clk_disable
,
997 .get_rate
= clk_get_rate_i2s_i2c_spi
,
998 .lock
= __SPIN_LOCK_UNLOCKED(i2s1_clk
.lock
),
1001 static struct clk i2c0_clk
= {
1003 .parent
= &fast_clk
,
1004 .rate
= 26000000, /* this varies! */
1007 .res_reg
= U300_SYSCON_VBASE
+ U300_SYSCON_RFR
,
1008 .res_mask
= U300_SYSCON_RFR_I2C0_RESET_ENABLE
,
1009 .clk_val
= U300_SYSCON_SBCER_I2C0_CLK_EN
,
1010 .enable
= syscon_clk_enable
,
1011 .disable
= syscon_clk_disable
,
1012 .get_rate
= clk_get_rate_i2s_i2c_spi
,
1013 .lock
= __SPIN_LOCK_UNLOCKED(i2c0_clk
.lock
),
1016 static struct clk i2c1_clk
= {
1018 .parent
= &fast_clk
,
1019 .rate
= 26000000, /* this varies! */
1022 .res_reg
= U300_SYSCON_VBASE
+ U300_SYSCON_RFR
,
1023 .res_mask
= U300_SYSCON_RFR_I2C1_RESET_ENABLE
,
1024 .clk_val
= U300_SYSCON_SBCER_I2C1_CLK_EN
,
1025 .enable
= syscon_clk_enable
,
1026 .disable
= syscon_clk_disable
,
1027 .get_rate
= clk_get_rate_i2s_i2c_spi
,
1028 .lock
= __SPIN_LOCK_UNLOCKED(i2c1_clk
.lock
),
1032 * The SPI apb_pclk is hardwired to the same terminal as the
1033 * external SPI clock. Thus this will be referenced twice.
1035 static struct clk spi_clk
= {
1037 .parent
= &fast_clk
,
1038 .rate
= 26000000, /* this varies! */
1041 .res_reg
= U300_SYSCON_VBASE
+ U300_SYSCON_RFR
,
1042 .res_mask
= U300_SYSCON_RFR_SPI_RESET_ENABLE
,
1043 .clk_val
= U300_SYSCON_SBCER_SPI_CLK_EN
,
1044 .enable
= syscon_clk_enable
,
1045 .disable
= syscon_clk_disable
,
1046 .get_rate
= clk_get_rate_i2s_i2c_spi
,
1047 .lock
= __SPIN_LOCK_UNLOCKED(spi_clk
.lock
),
1050 #ifdef CONFIG_MACH_U300_BS335
1051 static struct clk uart1_pclk
= {
1052 .name
= "UART1_PCLK",
1053 .parent
= &fast_clk
,
1056 .res_reg
= U300_SYSCON_VBASE
+ U300_SYSCON_RFR
,
1057 .res_mask
= U300_SYSCON_RFR_UART1_RESET_ENABLE
,
1058 .clk_val
= U300_SYSCON_SBCER_UART1_CLK_EN
,
1059 .enable
= syscon_clk_enable
,
1060 .disable
= syscon_clk_disable
,
1061 .lock
= __SPIN_LOCK_UNLOCKED(uart1_pclk
.lock
),
1064 /* This one is hardwired to PLL13 */
1065 static struct clk uart1_clk
= {
1066 .name
= "UART1_CLK",
1069 .lock
= __SPIN_LOCK_UNLOCKED(uart1_clk
.lock
),
1075 * Clocks on the SLOW bridge
1077 static struct clk slow_clk
= {
1078 .name
= "SLOW_BRIDGE",
1079 .parent
= &amba_clk
,
1083 .res_reg
= U300_SYSCON_VBASE
+ U300_SYSCON_RSR
,
1084 .res_mask
= U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN
,
1085 .clk_val
= U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN
,
1086 .enable
= syscon_clk_enable
,
1087 .disable
= syscon_clk_disable
,
1088 .lock
= __SPIN_LOCK_UNLOCKED(slow_clk
.lock
),
1091 /* TODO: implement SYSCON clock? */
1093 static struct clk wdog_clk
= {
1095 .parent
= &slow_clk
,
1099 /* This is always on, cannot be enabled/disabled or reset */
1100 .lock
= __SPIN_LOCK_UNLOCKED(wdog_clk
.lock
),
1103 static struct clk uart0_pclk
= {
1104 .name
= "UART0_PCLK",
1105 .parent
= &slow_clk
,
1108 .res_reg
= U300_SYSCON_VBASE
+ U300_SYSCON_RSR
,
1109 .res_mask
= U300_SYSCON_RSR_UART_RESET_EN
,
1110 .clk_val
= U300_SYSCON_SBCER_UART_CLK_EN
,
1111 .enable
= syscon_clk_enable
,
1112 .disable
= syscon_clk_disable
,
1113 .lock
= __SPIN_LOCK_UNLOCKED(uart0_pclk
.lock
),
1116 /* This one is hardwired to PLL13 */
1117 static struct clk uart0_clk
= {
1118 .name
= "UART0_CLK",
1119 .parent
= &slow_clk
,
1122 .lock
= __SPIN_LOCK_UNLOCKED(uart0_clk
.lock
),
1125 static struct clk keypad_clk
= {
1127 .parent
= &slow_clk
,
1131 .res_reg
= U300_SYSCON_VBASE
+ U300_SYSCON_RSR
,
1132 .res_mask
= U300_SYSCON_RSR_KEYPAD_RESET_EN
,
1133 .clk_val
= U300_SYSCON_SBCER_KEYPAD_CLK_EN
,
1134 .enable
= syscon_clk_enable
,
1135 .disable
= syscon_clk_disable
,
1136 .lock
= __SPIN_LOCK_UNLOCKED(keypad_clk
.lock
),
1139 static struct clk gpio_clk
= {
1141 .parent
= &slow_clk
,
1145 .res_reg
= U300_SYSCON_VBASE
+ U300_SYSCON_RSR
,
1146 .res_mask
= U300_SYSCON_RSR_GPIO_RESET_EN
,
1147 .clk_val
= U300_SYSCON_SBCER_GPIO_CLK_EN
,
1148 .enable
= syscon_clk_enable
,
1149 .disable
= syscon_clk_disable
,
1150 .lock
= __SPIN_LOCK_UNLOCKED(gpio_clk
.lock
),
1153 static struct clk rtc_clk
= {
1155 .parent
= &slow_clk
,
1159 .res_reg
= U300_SYSCON_VBASE
+ U300_SYSCON_RSR
,
1160 .res_mask
= U300_SYSCON_RSR_RTC_RESET_EN
,
1161 /* This clock is always on, cannot be enabled/disabled */
1162 .lock
= __SPIN_LOCK_UNLOCKED(rtc_clk
.lock
),
1165 static struct clk bustr_clk
= {
1167 .parent
= &slow_clk
,
1171 .res_reg
= U300_SYSCON_VBASE
+ U300_SYSCON_RSR
,
1172 .res_mask
= U300_SYSCON_RSR_BTR_RESET_EN
,
1173 .clk_val
= U300_SYSCON_SBCER_BTR_CLK_EN
,
1174 .enable
= syscon_clk_enable
,
1175 .disable
= syscon_clk_disable
,
1176 .lock
= __SPIN_LOCK_UNLOCKED(bustr_clk
.lock
),
1179 static struct clk evhist_clk
= {
1181 .parent
= &slow_clk
,
1185 .res_reg
= U300_SYSCON_VBASE
+ U300_SYSCON_RSR
,
1186 .res_mask
= U300_SYSCON_RSR_EH_RESET_EN
,
1187 .clk_val
= U300_SYSCON_SBCER_EH_CLK_EN
,
1188 .enable
= syscon_clk_enable
,
1189 .disable
= syscon_clk_disable
,
1190 .lock
= __SPIN_LOCK_UNLOCKED(evhist_clk
.lock
),
1193 static struct clk timer_clk
= {
1195 .parent
= &slow_clk
,
1199 .res_reg
= U300_SYSCON_VBASE
+ U300_SYSCON_RSR
,
1200 .res_mask
= U300_SYSCON_RSR_ACC_TMR_RESET_EN
,
1201 .clk_val
= U300_SYSCON_SBCER_ACC_TMR_CLK_EN
,
1202 .enable
= syscon_clk_enable
,
1203 .disable
= syscon_clk_disable
,
1204 .lock
= __SPIN_LOCK_UNLOCKED(timer_clk
.lock
),
1207 static struct clk app_timer_clk
= {
1208 .name
= "TIMER_APP",
1209 .parent
= &slow_clk
,
1213 .res_reg
= U300_SYSCON_VBASE
+ U300_SYSCON_RSR
,
1214 .res_mask
= U300_SYSCON_RSR_APP_TMR_RESET_EN
,
1215 .clk_val
= U300_SYSCON_SBCER_APP_TMR_CLK_EN
,
1216 .enable
= syscon_clk_enable
,
1217 .disable
= syscon_clk_disable
,
1218 .lock
= __SPIN_LOCK_UNLOCKED(app_timer_clk
.lock
),
1221 #ifdef CONFIG_MACH_U300_BS335
1222 static struct clk ppm_clk
= {
1224 .parent
= &slow_clk
,
1225 .rate
= 0, /* FIXME */
1226 .hw_ctrld
= true, /* TODO: Look up if it is hw ctrld or not */
1228 .res_reg
= U300_SYSCON_VBASE
+ U300_SYSCON_RSR
,
1229 .res_mask
= U300_SYSCON_RSR_PPM_RESET_EN
,
1230 .clk_val
= U300_SYSCON_SBCER_PPM_CLK_EN
,
1231 .enable
= syscon_clk_enable
,
1232 .disable
= syscon_clk_disable
,
1233 .lock
= __SPIN_LOCK_UNLOCKED(ppm_clk
.lock
),
1237 #define DEF_LOOKUP(devid, clkref) \
1243 #define DEF_LOOKUP_CON(devid, conid, clkref) \
1251 * Here we only define clocks that are meaningful to
1252 * look up through clockdevice.
1254 static struct clk_lookup lookups
[] = {
1255 /* Connected directly to the AMBA bus */
1256 DEF_LOOKUP("amba", &amba_clk
),
1257 DEF_LOOKUP("cpu", &cpu_clk
),
1258 DEF_LOOKUP("fsmc", &nandif_clk
),
1259 DEF_LOOKUP("semi", &semi_clk
),
1260 #ifdef CONFIG_MACH_U300_BS335
1261 DEF_LOOKUP("isp", &isp_clk
),
1262 DEF_LOOKUP("cds", &cds_clk
),
1264 DEF_LOOKUP("dma", &dma_clk
),
1265 DEF_LOOKUP("msl", &aaif_clk
),
1266 DEF_LOOKUP("apex", &apex_clk
),
1267 DEF_LOOKUP("video_enc", &video_enc_clk
),
1268 DEF_LOOKUP("xgam", &xgam_clk
),
1269 DEF_LOOKUP("ahb", &ahb_clk
),
1270 /* AHB bridge clocks */
1271 DEF_LOOKUP("ahb_subsys", &ahb_subsys_clk
),
1272 DEF_LOOKUP("intcon", &intcon_clk
),
1273 DEF_LOOKUP_CON("intcon", "apb_pclk", &intcon_clk
),
1274 DEF_LOOKUP("mspro", &mspro_clk
),
1275 DEF_LOOKUP("pl172", &emif_clk
),
1276 DEF_LOOKUP_CON("pl172", "apb_pclk", &emif_clk
),
1277 /* FAST bridge clocks */
1278 DEF_LOOKUP("fast", &fast_clk
),
1279 DEF_LOOKUP("mmci", &mmcsd_clk
),
1280 DEF_LOOKUP_CON("mmci", "apb_pclk", &mmcsd_clk
),
1282 * The .0 and .1 identifiers on these comes from the platform device
1283 * .id field and are assigned when the platform devices are registered.
1285 DEF_LOOKUP("i2s.0", &i2s0_clk
),
1286 DEF_LOOKUP("i2s.1", &i2s1_clk
),
1287 DEF_LOOKUP("stu300.0", &i2c0_clk
),
1288 DEF_LOOKUP("stu300.1", &i2c1_clk
),
1289 DEF_LOOKUP("pl022", &spi_clk
),
1290 DEF_LOOKUP_CON("pl022", "apb_pclk", &spi_clk
),
1291 #ifdef CONFIG_MACH_U300_BS335
1292 DEF_LOOKUP("uart1", &uart1_clk
),
1293 DEF_LOOKUP_CON("uart1", "apb_pclk", &uart1_pclk
),
1295 /* SLOW bridge clocks */
1296 DEF_LOOKUP("slow", &slow_clk
),
1297 DEF_LOOKUP("coh901327_wdog", &wdog_clk
),
1298 DEF_LOOKUP("uart0", &uart0_clk
),
1299 DEF_LOOKUP_CON("uart0", "apb_pclk", &uart0_pclk
),
1300 DEF_LOOKUP("apptimer", &app_timer_clk
),
1301 DEF_LOOKUP("coh901461-keypad", &keypad_clk
),
1302 DEF_LOOKUP("u300-gpio", &gpio_clk
),
1303 DEF_LOOKUP("rtc-coh901331", &rtc_clk
),
1304 DEF_LOOKUP("bustr", &bustr_clk
),
1305 DEF_LOOKUP("evhist", &evhist_clk
),
1306 DEF_LOOKUP("timer", &timer_clk
),
1307 #ifdef CONFIG_MACH_U300_BS335
1308 DEF_LOOKUP("ppm", &ppm_clk
),
1312 static void __init
clk_register(void)
1314 /* Register the lookups */
1315 clkdev_add_table(lookups
, ARRAY_SIZE(lookups
));
1319 * The interrupt controller is enabled before the clock API is registered.
1321 void u300_enable_intcon_clock(void)
1323 clk_enable(&intcon_clk
);
1325 EXPORT_SYMBOL(u300_enable_intcon_clock
);
1328 * The timer is enabled before the clock API is registered.
1330 void u300_enable_timer_clock(void)
1332 clk_enable(&app_timer_clk
);
1334 EXPORT_SYMBOL(u300_enable_timer_clock
);
1337 #if (defined(CONFIG_DEBUG_FS) && defined(CONFIG_U300_DEBUG))
1339 * The following makes it possible to view the status (especially
1340 * reference count and reset status) for the clocks in the platform
1341 * by looking into the special file <debugfs>/u300_clocks
1344 /* A list of all clocks in the platform */
1345 static struct clk
*clks
[] = {
1346 /* Top node clock for the AMBA bus */
1348 /* Connected directly to the AMBA bus */
1352 #ifdef CONFIG_MACH_U300_BS335
1363 /* AHB bridge clocks */
1368 /* FAST bridge clocks */
1376 #ifdef CONFIG_MACH_U300_BS335
1380 /* SLOW bridge clocks */
1392 #ifdef CONFIG_MACH_U300_BS335
1397 static int u300_clocks_show(struct seq_file
*s
, void *data
)
1402 seq_printf(s
, "CLOCK DEVICE RESET STATE\t" \
1403 "ACTIVE\tUSERS\tHW CTRL FREQ\n");
1404 seq_printf(s
, "---------------------------------------------" \
1405 "-----------------------------------------\n");
1406 for (i
= 0; i
< ARRAY_SIZE(clks
); i
++) {
1408 if (clk
!= ERR_PTR(-ENOENT
)) {
1409 /* Format clock and device name nicely */
1413 chars
= snprintf(&cdp
[0], 17, "%s", clk
->name
);
1414 while (chars
< 16) {
1418 chars
= snprintf(&cdp
[16], 17, "%s", clk
->dev
?
1419 dev_name(clk
->dev
) : "N/A");
1420 while (chars
< 16) {
1421 cdp
[chars
+16] = ' ';
1425 if (clk
->get_rate
|| clk
->rate
!= 0)
1427 "%s%s\t%s\t%d\t%s\t%lu Hz\n",
1430 "ASSERTED" : "RELEASED",
1431 clk
->usecount
? "ON" : "OFF",
1433 clk
->hw_ctrld
? "YES" : "NO ",
1437 "%s%s\t%s\t%d\t%s\t" \
1441 "ASSERTED" : "RELEASED",
1442 clk
->usecount
? "ON" : "OFF",
1444 clk
->hw_ctrld
? "YES" : "NO ");
1450 static int u300_clocks_open(struct inode
*inode
, struct file
*file
)
1452 return single_open(file
, u300_clocks_show
, NULL
);
1455 static const struct file_operations u300_clocks_operations
= {
1456 .open
= u300_clocks_open
,
1458 .llseek
= seq_lseek
,
1459 .release
= single_release
,
1462 static int __init
init_clk_read_debugfs(void)
1464 /* Expose a simple debugfs interface to view all clocks */
1465 (void) debugfs_create_file("u300_clocks", S_IFREG
| S_IRUGO
,
1467 &u300_clocks_operations
);
1471 * This needs to come in after the core_initcall() for the
1472 * overall clocks, because debugfs is not available until
1473 * the subsystems come up.
1475 module_init(init_clk_read_debugfs
);
1478 int __init
u300_clock_init(void)
1483 * FIXME: shall all this powermanagement stuff really live here???
1486 /* Set system to run at PLL208, max performance, a known state. */
1487 val
= readw(U300_SYSCON_VBASE
+ U300_SYSCON_CCR
);
1488 val
&= ~U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK
;
1489 writew(val
, U300_SYSCON_VBASE
+ U300_SYSCON_CCR
);
1490 /* Wait for the PLL208 to lock if not locked in yet */
1491 while (!(readw(U300_SYSCON_VBASE
+ U300_SYSCON_CSR
) &
1492 U300_SYSCON_CSR_PLL208_LOCK_IND
));
1494 /* Power management enable */
1495 val
= readw(U300_SYSCON_VBASE
+ U300_SYSCON_PMCR
);
1496 val
|= U300_SYSCON_PMCR_PWR_MGNT_ENABLE
;
1497 writew(val
, U300_SYSCON_VBASE
+ U300_SYSCON_PMCR
);
1502 * Some of these may be on when we boot the system so make sure they
1505 syscon_block_reset_enable(&timer_clk
);
1506 timer_clk
.disable(&timer_clk
);
1509 * These shall be turned on by default when we boot the system
1510 * so make sure they are ON. (Adding CPU here is a bit too much.)
1511 * These clocks will be claimed by drivers later.
1513 syscon_block_reset_disable(&semi_clk
);
1514 syscon_block_reset_disable(&emif_clk
);
1515 clk_enable(&semi_clk
);
1516 clk_enable(&emif_clk
);