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KVM: SVM: Add support for perf-kvm
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / arch / x86 / kvm / svm.c
blobbfb49489566e3e73c9d236a5a828c599aab75fdf
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * AMD SVM support
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
8 *
9 * Authors:
10 * Yaniv Kamay <yaniv@qumranet.com>
11 * Avi Kivity <avi@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17 #include <linux/kvm_host.h>
18
19 #include "irq.h"
20 #include "mmu.h"
21 #include "kvm_cache_regs.h"
22 #include "x86.h"
23
24 #include <linux/module.h>
25 #include <linux/kernel.h>
26 #include <linux/vmalloc.h>
27 #include <linux/highmem.h>
28 #include <linux/sched.h>
29 #include <linux/ftrace_event.h>
30 #include <linux/slab.h>
31
32 #include <asm/tlbflush.h>
33 #include <asm/desc.h>
34 #include <asm/kvm_para.h>
35
36 #include <asm/virtext.h>
37 #include "trace.h"
38
39 #define __ex(x) __kvm_handle_fault_on_reboot(x)
40
41 MODULE_AUTHOR("Qumranet");
42 MODULE_LICENSE("GPL");
43
44 #define IOPM_ALLOC_ORDER 2
45 #define MSRPM_ALLOC_ORDER 1
46
47 #define SEG_TYPE_LDT 2
48 #define SEG_TYPE_BUSY_TSS16 3
49
50 #define SVM_FEATURE_NPT (1 << 0)
51 #define SVM_FEATURE_LBRV (1 << 1)
52 #define SVM_FEATURE_SVML (1 << 2)
53 #define SVM_FEATURE_NRIP (1 << 3)
54 #define SVM_FEATURE_TSC_RATE (1 << 4)
55 #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
56 #define SVM_FEATURE_FLUSH_ASID (1 << 6)
57 #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
58 #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
59
60 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
61 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
62 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
63
64 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
65
66 static bool erratum_383_found __read_mostly;
67
68 static const u32 host_save_user_msrs[] = {
69 #ifdef CONFIG_X86_64
70 MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
71 MSR_FS_BASE,
72 #endif
73 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
74 };
75
76 #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
77
78 struct kvm_vcpu;
79
80 struct nested_state {
81 struct vmcb *hsave;
82 u64 hsave_msr;
83 u64 vm_cr_msr;
84 u64 vmcb;
85
86 /* These are the merged vectors */
87 u32 *msrpm;
88
89 /* gpa pointers to the real vectors */
90 u64 vmcb_msrpm;
91 u64 vmcb_iopm;
92
93 /* A VMEXIT is required but not yet emulated */
94 bool exit_required;
95
96 /*
97 * If we vmexit during an instruction emulation we need this to restore
98 * the l1 guest rip after the emulation
99 */
100 unsigned long vmexit_rip;
101 unsigned long vmexit_rsp;
102 unsigned long vmexit_rax;
103
104 /* cache for intercepts of the guest */
105 u32 intercept_cr;
106 u32 intercept_dr;
107 u32 intercept_exceptions;
108 u64 intercept;
109
110 /* Nested Paging related state */
111 u64 nested_cr3;
112 };
113
114 #define MSRPM_OFFSETS 16
115 static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
116
117 struct vcpu_svm {
118 struct kvm_vcpu vcpu;
119 struct vmcb *vmcb;
120 unsigned long vmcb_pa;
121 struct svm_cpu_data *svm_data;
122 uint64_t asid_generation;
123 uint64_t sysenter_esp;
124 uint64_t sysenter_eip;
125
126 u64 next_rip;
127
128 u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
129 struct {
130 u16 fs;
131 u16 gs;
132 u16 ldt;
133 u64 gs_base;
134 } host;
135
136 u32 *msrpm;
137
138 struct nested_state nested;
139
140 bool nmi_singlestep;
141
142 unsigned int3_injected;
143 unsigned long int3_rip;
144 u32 apf_reason;
145 };
146
147 #define MSR_INVALID 0xffffffffU
148
149 static struct svm_direct_access_msrs {
150 u32 index; /* Index of the MSR */
151 bool always; /* True if intercept is always on */
152 } direct_access_msrs[] = {
153 { .index = MSR_STAR, .always = true },
154 { .index = MSR_IA32_SYSENTER_CS, .always = true },
155 #ifdef CONFIG_X86_64
156 { .index = MSR_GS_BASE, .always = true },
157 { .index = MSR_FS_BASE, .always = true },
158 { .index = MSR_KERNEL_GS_BASE, .always = true },
159 { .index = MSR_LSTAR, .always = true },
160 { .index = MSR_CSTAR, .always = true },
161 { .index = MSR_SYSCALL_MASK, .always = true },
162 #endif
163 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
164 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
165 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
166 { .index = MSR_IA32_LASTINTTOIP, .always = false },
167 { .index = MSR_INVALID, .always = false },
168 };
169
170 /* enable NPT for AMD64 and X86 with PAE */
171 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
172 static bool npt_enabled = true;
173 #else
174 static bool npt_enabled;
175 #endif
176 static int npt = 1;
177
178 module_param(npt, int, S_IRUGO);
179
180 static int nested = 1;
181 module_param(nested, int, S_IRUGO);
182
183 static void svm_flush_tlb(struct kvm_vcpu *vcpu);
184 static void svm_complete_interrupts(struct vcpu_svm *svm);
185
186 static int nested_svm_exit_handled(struct vcpu_svm *svm);
187 static int nested_svm_intercept(struct vcpu_svm *svm);
188 static int nested_svm_vmexit(struct vcpu_svm *svm);
189 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
190 bool has_error_code, u32 error_code);
191
192 enum {
193 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
194 pause filter count */
195 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
196 VMCB_ASID, /* ASID */
197 VMCB_INTR, /* int_ctl, int_vector */
198 VMCB_NPT, /* npt_en, nCR3, gPAT */
199 VMCB_CR, /* CR0, CR3, CR4, EFER */
200 VMCB_DR, /* DR6, DR7 */
201 VMCB_DT, /* GDT, IDT */
202 VMCB_SEG, /* CS, DS, SS, ES, CPL */
203 VMCB_CR2, /* CR2 only */
204 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
205 VMCB_DIRTY_MAX,
206 };
207
208 /* TPR and CR2 are always written before VMRUN */
209 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
210
211 static inline void mark_all_dirty(struct vmcb *vmcb)
212 {
213 vmcb->control.clean = 0;
214 }
215
216 static inline void mark_all_clean(struct vmcb *vmcb)
217 {
218 vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
219 & ~VMCB_ALWAYS_DIRTY_MASK;
220 }
221
222 static inline void mark_dirty(struct vmcb *vmcb, int bit)
223 {
224 vmcb->control.clean &= ~(1 << bit);
225 }
226
227 static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
228 {
229 return container_of(vcpu, struct vcpu_svm, vcpu);
230 }
231
232 static void recalc_intercepts(struct vcpu_svm *svm)
233 {
234 struct vmcb_control_area *c, *h;
235 struct nested_state *g;
236
237 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
238
239 if (!is_guest_mode(&svm->vcpu))
240 return;
241
242 c = &svm->vmcb->control;
243 h = &svm->nested.hsave->control;
244 g = &svm->nested;
245
246 c->intercept_cr = h->intercept_cr | g->intercept_cr;
247 c->intercept_dr = h->intercept_dr | g->intercept_dr;
248 c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
249 c->intercept = h->intercept | g->intercept;
250 }
251
252 static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
253 {
254 if (is_guest_mode(&svm->vcpu))
255 return svm->nested.hsave;
256 else
257 return svm->vmcb;
258 }
259
260 static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
261 {
262 struct vmcb *vmcb = get_host_vmcb(svm);
263
264 vmcb->control.intercept_cr |= (1U << bit);
265
266 recalc_intercepts(svm);
267 }
268
269 static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
270 {
271 struct vmcb *vmcb = get_host_vmcb(svm);
272
273 vmcb->control.intercept_cr &= ~(1U << bit);
274
275 recalc_intercepts(svm);
276 }
277
278 static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
279 {
280 struct vmcb *vmcb = get_host_vmcb(svm);
281
282 return vmcb->control.intercept_cr & (1U << bit);
283 }
284
285 static inline void set_dr_intercept(struct vcpu_svm *svm, int bit)
286 {
287 struct vmcb *vmcb = get_host_vmcb(svm);
288
289 vmcb->control.intercept_dr |= (1U << bit);
290
291 recalc_intercepts(svm);
292 }
293
294 static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit)
295 {
296 struct vmcb *vmcb = get_host_vmcb(svm);
297
298 vmcb->control.intercept_dr &= ~(1U << bit);
299
300 recalc_intercepts(svm);
301 }
302
303 static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
304 {
305 struct vmcb *vmcb = get_host_vmcb(svm);
306
307 vmcb->control.intercept_exceptions |= (1U << bit);
308
309 recalc_intercepts(svm);
310 }
311
312 static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
313 {
314 struct vmcb *vmcb = get_host_vmcb(svm);
315
316 vmcb->control.intercept_exceptions &= ~(1U << bit);
317
318 recalc_intercepts(svm);
319 }
320
321 static inline void set_intercept(struct vcpu_svm *svm, int bit)
322 {
323 struct vmcb *vmcb = get_host_vmcb(svm);
324
325 vmcb->control.intercept |= (1ULL << bit);
326
327 recalc_intercepts(svm);
328 }
329
330 static inline void clr_intercept(struct vcpu_svm *svm, int bit)
331 {
332 struct vmcb *vmcb = get_host_vmcb(svm);
333
334 vmcb->control.intercept &= ~(1ULL << bit);
335
336 recalc_intercepts(svm);
337 }
338
339 static inline void enable_gif(struct vcpu_svm *svm)
340 {
341 svm->vcpu.arch.hflags |= HF_GIF_MASK;
342 }
343
344 static inline void disable_gif(struct vcpu_svm *svm)
345 {
346 svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
347 }
348
349 static inline bool gif_set(struct vcpu_svm *svm)
350 {
351 return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
352 }
353
354 static unsigned long iopm_base;
355
356 struct kvm_ldttss_desc {
357 u16 limit0;
358 u16 base0;
359 unsigned base1:8, type:5, dpl:2, p:1;
360 unsigned limit1:4, zero0:3, g:1, base2:8;
361 u32 base3;
362 u32 zero1;
363 } __attribute__((packed));
364
365 struct svm_cpu_data {
366 int cpu;
367
368 u64 asid_generation;
369 u32 max_asid;
370 u32 next_asid;
371 struct kvm_ldttss_desc *tss_desc;
372
373 struct page *save_area;
374 };
375
376 static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
377 static uint32_t svm_features;
378
379 struct svm_init_data {
380 int cpu;
381 int r;
382 };
383
384 static u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
385
386 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
387 #define MSRS_RANGE_SIZE 2048
388 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
389
390 static u32 svm_msrpm_offset(u32 msr)
391 {
392 u32 offset;
393 int i;
394
395 for (i = 0; i < NUM_MSR_MAPS; i++) {
396 if (msr < msrpm_ranges[i] ||
397 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
398 continue;
399
400 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
401 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
402
403 /* Now we have the u8 offset - but need the u32 offset */
404 return offset / 4;
405 }
406
407 /* MSR not in any range */
408 return MSR_INVALID;
409 }
410
411 #define MAX_INST_SIZE 15
412
413 static inline void clgi(void)
414 {
415 asm volatile (__ex(SVM_CLGI));
416 }
417
418 static inline void stgi(void)
419 {
420 asm volatile (__ex(SVM_STGI));
421 }
422
423 static inline void invlpga(unsigned long addr, u32 asid)
424 {
425 asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
426 }
427
428 static int get_npt_level(void)
429 {
430 #ifdef CONFIG_X86_64
431 return PT64_ROOT_LEVEL;
432 #else
433 return PT32E_ROOT_LEVEL;
434 #endif
435 }
436
437 static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
438 {
439 vcpu->arch.efer = efer;
440 if (!npt_enabled && !(efer & EFER_LMA))
441 efer &= ~EFER_LME;
442
443 to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
444 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
445 }
446
447 static int is_external_interrupt(u32 info)
448 {
449 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
450 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
451 }
452
453 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
454 {
455 struct vcpu_svm *svm = to_svm(vcpu);
456 u32 ret = 0;
457
458 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
459 ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
460 return ret & mask;
461 }
462
463 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
464 {
465 struct vcpu_svm *svm = to_svm(vcpu);
466
467 if (mask == 0)
468 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
469 else
470 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
471
472 }
473
474 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
475 {
476 struct vcpu_svm *svm = to_svm(vcpu);
477
478 if (svm->vmcb->control.next_rip != 0)
479 svm->next_rip = svm->vmcb->control.next_rip;
480
481 if (!svm->next_rip) {
482 if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
483 EMULATE_DONE)
484 printk(KERN_DEBUG "%s: NOP\n", __func__);
485 return;
486 }
487 if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
488 printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
489 __func__, kvm_rip_read(vcpu), svm->next_rip);
490
491 kvm_rip_write(vcpu, svm->next_rip);
492 svm_set_interrupt_shadow(vcpu, 0);
493 }
494
495 static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
496 bool has_error_code, u32 error_code,
497 bool reinject)
498 {
499 struct vcpu_svm *svm = to_svm(vcpu);
500
501 /*
502 * If we are within a nested VM we'd better #VMEXIT and let the guest
503 * handle the exception
504 */
505 if (!reinject &&
506 nested_svm_check_exception(svm, nr, has_error_code, error_code))
507 return;
508
509 if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
510 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
511
512 /*
513 * For guest debugging where we have to reinject #BP if some
514 * INT3 is guest-owned:
515 * Emulate nRIP by moving RIP forward. Will fail if injection
516 * raises a fault that is not intercepted. Still better than
517 * failing in all cases.
518 */
519 skip_emulated_instruction(&svm->vcpu);
520 rip = kvm_rip_read(&svm->vcpu);
521 svm->int3_rip = rip + svm->vmcb->save.cs.base;
522 svm->int3_injected = rip - old_rip;
523 }
524
525 svm->vmcb->control.event_inj = nr
526 | SVM_EVTINJ_VALID
527 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
528 | SVM_EVTINJ_TYPE_EXEPT;
529 svm->vmcb->control.event_inj_err = error_code;
530 }
531
532 static void svm_init_erratum_383(void)
533 {
534 u32 low, high;
535 int err;
536 u64 val;
537
538 if (!cpu_has_amd_erratum(amd_erratum_383))
539 return;
540
541 /* Use _safe variants to not break nested virtualization */
542 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
543 if (err)
544 return;
545
546 val |= (1ULL << 47);
547
548 low = lower_32_bits(val);
549 high = upper_32_bits(val);
550
551 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
552
553 erratum_383_found = true;
554 }
555
556 static int has_svm(void)
557 {
558 const char *msg;
559
560 if (!cpu_has_svm(&msg)) {
561 printk(KERN_INFO "has_svm: %s\n", msg);
562 return 0;
563 }
564
565 return 1;
566 }
567
568 static void svm_hardware_disable(void *garbage)
569 {
570 cpu_svm_disable();
571 }
572
573 static int svm_hardware_enable(void *garbage)
574 {
575
576 struct svm_cpu_data *sd;
577 uint64_t efer;
578 struct desc_ptr gdt_descr;
579 struct desc_struct *gdt;
580 int me = raw_smp_processor_id();
581
582 rdmsrl(MSR_EFER, efer);
583 if (efer & EFER_SVME)
584 return -EBUSY;
585
586 if (!has_svm()) {
587 printk(KERN_ERR "svm_hardware_enable: err EOPNOTSUPP on %d\n",
588 me);
589 return -EINVAL;
590 }
591 sd = per_cpu(svm_data, me);
592
593 if (!sd) {
594 printk(KERN_ERR "svm_hardware_enable: svm_data is NULL on %d\n",
595 me);
596 return -EINVAL;
597 }
598
599 sd->asid_generation = 1;
600 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
601 sd->next_asid = sd->max_asid + 1;
602
603 native_store_gdt(&gdt_descr);
604 gdt = (struct desc_struct *)gdt_descr.address;
605 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
606
607 wrmsrl(MSR_EFER, efer | EFER_SVME);
608
609 wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
610
611 svm_init_erratum_383();
612
613 return 0;
614 }
615
616 static void svm_cpu_uninit(int cpu)
617 {
618 struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
619
620 if (!sd)
621 return;
622
623 per_cpu(svm_data, raw_smp_processor_id()) = NULL;
624 __free_page(sd->save_area);
625 kfree(sd);
626 }
627
628 static int svm_cpu_init(int cpu)
629 {
630 struct svm_cpu_data *sd;
631 int r;
632
633 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
634 if (!sd)
635 return -ENOMEM;
636 sd->cpu = cpu;
637 sd->save_area = alloc_page(GFP_KERNEL);
638 r = -ENOMEM;
639 if (!sd->save_area)
640 goto err_1;
641
642 per_cpu(svm_data, cpu) = sd;
643
644 return 0;
645
646 err_1:
647 kfree(sd);
648 return r;
649
650 }
651
652 static bool valid_msr_intercept(u32 index)
653 {
654 int i;
655
656 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
657 if (direct_access_msrs[i].index == index)
658 return true;
659
660 return false;
661 }
662
663 static void set_msr_interception(u32 *msrpm, unsigned msr,
664 int read, int write)
665 {
666 u8 bit_read, bit_write;
667 unsigned long tmp;
668 u32 offset;
669
670 /*
671 * If this warning triggers extend the direct_access_msrs list at the
672 * beginning of the file
673 */
674 WARN_ON(!valid_msr_intercept(msr));
675
676 offset = svm_msrpm_offset(msr);
677 bit_read = 2 * (msr & 0x0f);
678 bit_write = 2 * (msr & 0x0f) + 1;
679 tmp = msrpm[offset];
680
681 BUG_ON(offset == MSR_INVALID);
682
683 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
684 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
685
686 msrpm[offset] = tmp;
687 }
688
689 static void svm_vcpu_init_msrpm(u32 *msrpm)
690 {
691 int i;
692
693 memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
694
695 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
696 if (!direct_access_msrs[i].always)
697 continue;
698
699 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
700 }
701 }
702
703 static void add_msr_offset(u32 offset)
704 {
705 int i;
706
707 for (i = 0; i < MSRPM_OFFSETS; ++i) {
708
709 /* Offset already in list? */
710 if (msrpm_offsets[i] == offset)
711 return;
712
713 /* Slot used by another offset? */
714 if (msrpm_offsets[i] != MSR_INVALID)
715 continue;
716
717 /* Add offset to list */
718 msrpm_offsets[i] = offset;
719
720 return;
721 }
722
723 /*
724 * If this BUG triggers the msrpm_offsets table has an overflow. Just
725 * increase MSRPM_OFFSETS in this case.
726 */
727 BUG();
728 }
729
730 static void init_msrpm_offsets(void)
731 {
732 int i;
733
734 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
735
736 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
737 u32 offset;
738
739 offset = svm_msrpm_offset(direct_access_msrs[i].index);
740 BUG_ON(offset == MSR_INVALID);
741
742 add_msr_offset(offset);
743 }
744 }
745
746 static void svm_enable_lbrv(struct vcpu_svm *svm)
747 {
748 u32 *msrpm = svm->msrpm;
749
750 svm->vmcb->control.lbr_ctl = 1;
751 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
752 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
753 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
754 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
755 }
756
757 static void svm_disable_lbrv(struct vcpu_svm *svm)
758 {
759 u32 *msrpm = svm->msrpm;
760
761 svm->vmcb->control.lbr_ctl = 0;
762 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
763 set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
764 set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
765 set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
766 }
767
768 static __init int svm_hardware_setup(void)
769 {
770 int cpu;
771 struct page *iopm_pages;
772 void *iopm_va;
773 int r;
774
775 iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
776
777 if (!iopm_pages)
778 return -ENOMEM;
779
780 iopm_va = page_address(iopm_pages);
781 memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
782 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
783
784 init_msrpm_offsets();
785
786 if (boot_cpu_has(X86_FEATURE_NX))
787 kvm_enable_efer_bits(EFER_NX);
788
789 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
790 kvm_enable_efer_bits(EFER_FFXSR);
791
792 if (nested) {
793 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
794 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
795 }
796
797 for_each_possible_cpu(cpu) {
798 r = svm_cpu_init(cpu);
799 if (r)
800 goto err;
801 }
802
803 svm_features = cpuid_edx(SVM_CPUID_FUNC);
804
805 if (!boot_cpu_has(X86_FEATURE_NPT))
806 npt_enabled = false;
807
808 if (npt_enabled && !npt) {
809 printk(KERN_INFO "kvm: Nested Paging disabled\n");
810 npt_enabled = false;
811 }
812
813 if (npt_enabled) {
814 printk(KERN_INFO "kvm: Nested Paging enabled\n");
815 kvm_enable_tdp();
816 } else
817 kvm_disable_tdp();
818
819 return 0;
820
821 err:
822 __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
823 iopm_base = 0;
824 return r;
825 }
826
827 static __exit void svm_hardware_unsetup(void)
828 {
829 int cpu;
830
831 for_each_possible_cpu(cpu)
832 svm_cpu_uninit(cpu);
833
834 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
835 iopm_base = 0;
836 }
837
838 static void init_seg(struct vmcb_seg *seg)
839 {
840 seg->selector = 0;
841 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
842 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
843 seg->limit = 0xffff;
844 seg->base = 0;
845 }
846
847 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
848 {
849 seg->selector = 0;
850 seg->attrib = SVM_SELECTOR_P_MASK | type;
851 seg->limit = 0xffff;
852 seg->base = 0;
853 }
854
855 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
856 {
857 struct vcpu_svm *svm = to_svm(vcpu);
858 u64 g_tsc_offset = 0;
859
860 if (is_guest_mode(vcpu)) {
861 g_tsc_offset = svm->vmcb->control.tsc_offset -
862 svm->nested.hsave->control.tsc_offset;
863 svm->nested.hsave->control.tsc_offset = offset;
864 }
865
866 svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
867
868 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
869 }
870
871 static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment)
872 {
873 struct vcpu_svm *svm = to_svm(vcpu);
874
875 svm->vmcb->control.tsc_offset += adjustment;
876 if (is_guest_mode(vcpu))
877 svm->nested.hsave->control.tsc_offset += adjustment;
878 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
879 }
880
881 static void init_vmcb(struct vcpu_svm *svm)
882 {
883 struct vmcb_control_area *control = &svm->vmcb->control;
884 struct vmcb_save_area *save = &svm->vmcb->save;
885
886 svm->vcpu.fpu_active = 1;
887 svm->vcpu.arch.hflags = 0;
888
889 set_cr_intercept(svm, INTERCEPT_CR0_READ);
890 set_cr_intercept(svm, INTERCEPT_CR3_READ);
891 set_cr_intercept(svm, INTERCEPT_CR4_READ);
892 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
893 set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
894 set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
895 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
896
897 set_dr_intercept(svm, INTERCEPT_DR0_READ);
898 set_dr_intercept(svm, INTERCEPT_DR1_READ);
899 set_dr_intercept(svm, INTERCEPT_DR2_READ);
900 set_dr_intercept(svm, INTERCEPT_DR3_READ);
901 set_dr_intercept(svm, INTERCEPT_DR4_READ);
902 set_dr_intercept(svm, INTERCEPT_DR5_READ);
903 set_dr_intercept(svm, INTERCEPT_DR6_READ);
904 set_dr_intercept(svm, INTERCEPT_DR7_READ);
905
906 set_dr_intercept(svm, INTERCEPT_DR0_WRITE);
907 set_dr_intercept(svm, INTERCEPT_DR1_WRITE);
908 set_dr_intercept(svm, INTERCEPT_DR2_WRITE);
909 set_dr_intercept(svm, INTERCEPT_DR3_WRITE);
910 set_dr_intercept(svm, INTERCEPT_DR4_WRITE);
911 set_dr_intercept(svm, INTERCEPT_DR5_WRITE);
912 set_dr_intercept(svm, INTERCEPT_DR6_WRITE);
913 set_dr_intercept(svm, INTERCEPT_DR7_WRITE);
914
915 set_exception_intercept(svm, PF_VECTOR);
916 set_exception_intercept(svm, UD_VECTOR);
917 set_exception_intercept(svm, MC_VECTOR);
918
919 set_intercept(svm, INTERCEPT_INTR);
920 set_intercept(svm, INTERCEPT_NMI);
921 set_intercept(svm, INTERCEPT_SMI);
922 set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
923 set_intercept(svm, INTERCEPT_CPUID);
924 set_intercept(svm, INTERCEPT_INVD);
925 set_intercept(svm, INTERCEPT_HLT);
926 set_intercept(svm, INTERCEPT_INVLPG);
927 set_intercept(svm, INTERCEPT_INVLPGA);
928 set_intercept(svm, INTERCEPT_IOIO_PROT);
929 set_intercept(svm, INTERCEPT_MSR_PROT);
930 set_intercept(svm, INTERCEPT_TASK_SWITCH);
931 set_intercept(svm, INTERCEPT_SHUTDOWN);
932 set_intercept(svm, INTERCEPT_VMRUN);
933 set_intercept(svm, INTERCEPT_VMMCALL);
934 set_intercept(svm, INTERCEPT_VMLOAD);
935 set_intercept(svm, INTERCEPT_VMSAVE);
936 set_intercept(svm, INTERCEPT_STGI);
937 set_intercept(svm, INTERCEPT_CLGI);
938 set_intercept(svm, INTERCEPT_SKINIT);
939 set_intercept(svm, INTERCEPT_WBINVD);
940 set_intercept(svm, INTERCEPT_MONITOR);
941 set_intercept(svm, INTERCEPT_MWAIT);
942 set_intercept(svm, INTERCEPT_XSETBV);
943
944 control->iopm_base_pa = iopm_base;
945 control->msrpm_base_pa = __pa(svm->msrpm);
946 control->int_ctl = V_INTR_MASKING_MASK;
947
948 init_seg(&save->es);
949 init_seg(&save->ss);
950 init_seg(&save->ds);
951 init_seg(&save->fs);
952 init_seg(&save->gs);
953
954 save->cs.selector = 0xf000;
955 /* Executable/Readable Code Segment */
956 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
957 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
958 save->cs.limit = 0xffff;
959 /*
960 * cs.base should really be 0xffff0000, but vmx can't handle that, so
961 * be consistent with it.
962 *
963 * Replace when we have real mode working for vmx.
964 */
965 save->cs.base = 0xf0000;
966
967 save->gdtr.limit = 0xffff;
968 save->idtr.limit = 0xffff;
969
970 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
971 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
972
973 svm_set_efer(&svm->vcpu, 0);
974 save->dr6 = 0xffff0ff0;
975 save->dr7 = 0x400;
976 save->rflags = 2;
977 save->rip = 0x0000fff0;
978 svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
979
980 /*
981 * This is the guest-visible cr0 value.
982 * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
983 */
984 svm->vcpu.arch.cr0 = 0;
985 (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
986
987 save->cr4 = X86_CR4_PAE;
988 /* rdx = ?? */
989
990 if (npt_enabled) {
991 /* Setup VMCB for Nested Paging */
992 control->nested_ctl = 1;
993 clr_intercept(svm, INTERCEPT_TASK_SWITCH);
994 clr_intercept(svm, INTERCEPT_INVLPG);
995 clr_exception_intercept(svm, PF_VECTOR);
996 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
997 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
998 save->g_pat = 0x0007040600070406ULL;
999 save->cr3 = 0;
1000 save->cr4 = 0;
1001 }
1002 svm->asid_generation = 0;
1003
1004 svm->nested.vmcb = 0;
1005 svm->vcpu.arch.hflags = 0;
1006
1007 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
1008 control->pause_filter_count = 3000;
1009 set_intercept(svm, INTERCEPT_PAUSE);
1010 }
1011
1012 mark_all_dirty(svm->vmcb);
1013
1014 enable_gif(svm);
1015 }
1016
1017 static int svm_vcpu_reset(struct kvm_vcpu *vcpu)
1018 {
1019 struct vcpu_svm *svm = to_svm(vcpu);
1020
1021 init_vmcb(svm);
1022
1023 if (!kvm_vcpu_is_bsp(vcpu)) {
1024 kvm_rip_write(vcpu, 0);
1025 svm->vmcb->save.cs.base = svm->vcpu.arch.sipi_vector << 12;
1026 svm->vmcb->save.cs.selector = svm->vcpu.arch.sipi_vector << 8;
1027 }
1028 vcpu->arch.regs_avail = ~0;
1029 vcpu->arch.regs_dirty = ~0;
1030
1031 return 0;
1032 }
1033
1034 static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
1035 {
1036 struct vcpu_svm *svm;
1037 struct page *page;
1038 struct page *msrpm_pages;
1039 struct page *hsave_page;
1040 struct page *nested_msrpm_pages;
1041 int err;
1042
1043 svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
1044 if (!svm) {
1045 err = -ENOMEM;
1046 goto out;
1047 }
1048
1049 err = kvm_vcpu_init(&svm->vcpu, kvm, id);
1050 if (err)
1051 goto free_svm;
1052
1053 err = -ENOMEM;
1054 page = alloc_page(GFP_KERNEL);
1055 if (!page)
1056 goto uninit;
1057
1058 msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1059 if (!msrpm_pages)
1060 goto free_page1;
1061
1062 nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
1063 if (!nested_msrpm_pages)
1064 goto free_page2;
1065
1066 hsave_page = alloc_page(GFP_KERNEL);
1067 if (!hsave_page)
1068 goto free_page3;
1069
1070 svm->nested.hsave = page_address(hsave_page);
1071
1072 svm->msrpm = page_address(msrpm_pages);
1073 svm_vcpu_init_msrpm(svm->msrpm);
1074
1075 svm->nested.msrpm = page_address(nested_msrpm_pages);
1076 svm_vcpu_init_msrpm(svm->nested.msrpm);
1077
1078 svm->vmcb = page_address(page);
1079 clear_page(svm->vmcb);
1080 svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
1081 svm->asid_generation = 0;
1082 init_vmcb(svm);
1083 kvm_write_tsc(&svm->vcpu, 0);
1084
1085 err = fx_init(&svm->vcpu);
1086 if (err)
1087 goto free_page4;
1088
1089 svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
1090 if (kvm_vcpu_is_bsp(&svm->vcpu))
1091 svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1092
1093 return &svm->vcpu;
1094
1095 free_page4:
1096 __free_page(hsave_page);
1097 free_page3:
1098 __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1099 free_page2:
1100 __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1101 free_page1:
1102 __free_page(page);
1103 uninit:
1104 kvm_vcpu_uninit(&svm->vcpu);
1105 free_svm:
1106 kmem_cache_free(kvm_vcpu_cache, svm);
1107 out:
1108 return ERR_PTR(err);
1109 }
1110
1111 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1112 {
1113 struct vcpu_svm *svm = to_svm(vcpu);
1114
1115 __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
1116 __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1117 __free_page(virt_to_page(svm->nested.hsave));
1118 __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1119 kvm_vcpu_uninit(vcpu);
1120 kmem_cache_free(kvm_vcpu_cache, svm);
1121 }
1122
1123 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1124 {
1125 struct vcpu_svm *svm = to_svm(vcpu);
1126 int i;
1127
1128 if (unlikely(cpu != vcpu->cpu)) {
1129 svm->asid_generation = 0;
1130 mark_all_dirty(svm->vmcb);
1131 }
1132
1133 #ifdef CONFIG_X86_64
1134 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1135 #endif
1136 savesegment(fs, svm->host.fs);
1137 savesegment(gs, svm->host.gs);
1138 svm->host.ldt = kvm_read_ldt();
1139
1140 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1141 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1142 }
1143
1144 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1145 {
1146 struct vcpu_svm *svm = to_svm(vcpu);
1147 int i;
1148
1149 ++vcpu->stat.host_state_reload;
1150 kvm_load_ldt(svm->host.ldt);
1151 #ifdef CONFIG_X86_64
1152 loadsegment(fs, svm->host.fs);
1153 wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
1154 load_gs_index(svm->host.gs);
1155 #else
1156 loadsegment(gs, svm->host.gs);
1157 #endif
1158 for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1159 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1160 }
1161
1162 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1163 {
1164 return to_svm(vcpu)->vmcb->save.rflags;
1165 }
1166
1167 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1168 {
1169 to_svm(vcpu)->vmcb->save.rflags = rflags;
1170 }
1171
1172 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1173 {
1174 switch (reg) {
1175 case VCPU_EXREG_PDPTR:
1176 BUG_ON(!npt_enabled);
1177 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1178 break;
1179 default:
1180 BUG();
1181 }
1182 }
1183
1184 static void svm_set_vintr(struct vcpu_svm *svm)
1185 {
1186 set_intercept(svm, INTERCEPT_VINTR);
1187 }
1188
1189 static void svm_clear_vintr(struct vcpu_svm *svm)
1190 {
1191 clr_intercept(svm, INTERCEPT_VINTR);
1192 }
1193
1194 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1195 {
1196 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1197
1198 switch (seg) {
1199 case VCPU_SREG_CS: return &save->cs;
1200 case VCPU_SREG_DS: return &save->ds;
1201 case VCPU_SREG_ES: return &save->es;
1202 case VCPU_SREG_FS: return &save->fs;
1203 case VCPU_SREG_GS: return &save->gs;
1204 case VCPU_SREG_SS: return &save->ss;
1205 case VCPU_SREG_TR: return &save->tr;
1206 case VCPU_SREG_LDTR: return &save->ldtr;
1207 }
1208 BUG();
1209 return NULL;
1210 }
1211
1212 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1213 {
1214 struct vmcb_seg *s = svm_seg(vcpu, seg);
1215
1216 return s->base;
1217 }
1218
1219 static void svm_get_segment(struct kvm_vcpu *vcpu,
1220 struct kvm_segment *var, int seg)
1221 {
1222 struct vmcb_seg *s = svm_seg(vcpu, seg);
1223
1224 var->base = s->base;
1225 var->limit = s->limit;
1226 var->selector = s->selector;
1227 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1228 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1229 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1230 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1231 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1232 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1233 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1234 var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
1235
1236 /*
1237 * AMD's VMCB does not have an explicit unusable field, so emulate it
1238 * for cross vendor migration purposes by "not present"
1239 */
1240 var->unusable = !var->present || (var->type == 0);
1241
1242 switch (seg) {
1243 case VCPU_SREG_CS:
1244 /*
1245 * SVM always stores 0 for the 'G' bit in the CS selector in
1246 * the VMCB on a VMEXIT. This hurts cross-vendor migration:
1247 * Intel's VMENTRY has a check on the 'G' bit.
1248 */
1249 var->g = s->limit > 0xfffff;
1250 break;
1251 case VCPU_SREG_TR:
1252 /*
1253 * Work around a bug where the busy flag in the tr selector
1254 * isn't exposed
1255 */
1256 var->type |= 0x2;
1257 break;
1258 case VCPU_SREG_DS:
1259 case VCPU_SREG_ES:
1260 case VCPU_SREG_FS:
1261 case VCPU_SREG_GS:
1262 /*
1263 * The accessed bit must always be set in the segment
1264 * descriptor cache, although it can be cleared in the
1265 * descriptor, the cached bit always remains at 1. Since
1266 * Intel has a check on this, set it here to support
1267 * cross-vendor migration.
1268 */
1269 if (!var->unusable)
1270 var->type |= 0x1;
1271 break;
1272 case VCPU_SREG_SS:
1273 /*
1274 * On AMD CPUs sometimes the DB bit in the segment
1275 * descriptor is left as 1, although the whole segment has
1276 * been made unusable. Clear it here to pass an Intel VMX
1277 * entry check when cross vendor migrating.
1278 */
1279 if (var->unusable)
1280 var->db = 0;
1281 break;
1282 }
1283 }
1284
1285 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1286 {
1287 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1288
1289 return save->cpl;
1290 }
1291
1292 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1293 {
1294 struct vcpu_svm *svm = to_svm(vcpu);
1295
1296 dt->size = svm->vmcb->save.idtr.limit;
1297 dt->address = svm->vmcb->save.idtr.base;
1298 }
1299
1300 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1301 {
1302 struct vcpu_svm *svm = to_svm(vcpu);
1303
1304 svm->vmcb->save.idtr.limit = dt->size;
1305 svm->vmcb->save.idtr.base = dt->address ;
1306 mark_dirty(svm->vmcb, VMCB_DT);
1307 }
1308
1309 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1310 {
1311 struct vcpu_svm *svm = to_svm(vcpu);
1312
1313 dt->size = svm->vmcb->save.gdtr.limit;
1314 dt->address = svm->vmcb->save.gdtr.base;
1315 }
1316
1317 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1318 {
1319 struct vcpu_svm *svm = to_svm(vcpu);
1320
1321 svm->vmcb->save.gdtr.limit = dt->size;
1322 svm->vmcb->save.gdtr.base = dt->address ;
1323 mark_dirty(svm->vmcb, VMCB_DT);
1324 }
1325
1326 static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
1327 {
1328 }
1329
1330 static void svm_decache_cr3(struct kvm_vcpu *vcpu)
1331 {
1332 }
1333
1334 static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1335 {
1336 }
1337
1338 static void update_cr0_intercept(struct vcpu_svm *svm)
1339 {
1340 ulong gcr0 = svm->vcpu.arch.cr0;
1341 u64 *hcr0 = &svm->vmcb->save.cr0;
1342
1343 if (!svm->vcpu.fpu_active)
1344 *hcr0 |= SVM_CR0_SELECTIVE_MASK;
1345 else
1346 *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1347 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1348
1349 mark_dirty(svm->vmcb, VMCB_CR);
1350
1351 if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
1352 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1353 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1354 } else {
1355 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1356 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1357 }
1358 }
1359
1360 static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1361 {
1362 struct vcpu_svm *svm = to_svm(vcpu);
1363
1364 if (is_guest_mode(vcpu)) {
1365 /*
1366 * We are here because we run in nested mode, the host kvm
1367 * intercepts cr0 writes but the l1 hypervisor does not.
1368 * But the L1 hypervisor may intercept selective cr0 writes.
1369 * This needs to be checked here.
1370 */
1371 unsigned long old, new;
1372
1373 /* Remove bits that would trigger a real cr0 write intercept */
1374 old = vcpu->arch.cr0 & SVM_CR0_SELECTIVE_MASK;
1375 new = cr0 & SVM_CR0_SELECTIVE_MASK;
1376
1377 if (old == new) {
1378 /* cr0 write with ts and mp unchanged */
1379 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
1380 if (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE) {
1381 svm->nested.vmexit_rip = kvm_rip_read(vcpu);
1382 svm->nested.vmexit_rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
1383 svm->nested.vmexit_rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
1384 return;
1385 }
1386 }
1387 }
1388
1389 #ifdef CONFIG_X86_64
1390 if (vcpu->arch.efer & EFER_LME) {
1391 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1392 vcpu->arch.efer |= EFER_LMA;
1393 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1394 }
1395
1396 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1397 vcpu->arch.efer &= ~EFER_LMA;
1398 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1399 }
1400 }
1401 #endif
1402 vcpu->arch.cr0 = cr0;
1403
1404 if (!npt_enabled)
1405 cr0 |= X86_CR0_PG | X86_CR0_WP;
1406
1407 if (!vcpu->fpu_active)
1408 cr0 |= X86_CR0_TS;
1409 /*
1410 * re-enable caching here because the QEMU bios
1411 * does not do it - this results in some delay at
1412 * reboot
1413 */
1414 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1415 svm->vmcb->save.cr0 = cr0;
1416 mark_dirty(svm->vmcb, VMCB_CR);
1417 update_cr0_intercept(svm);
1418 }
1419
1420 static void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1421 {
1422 unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
1423 unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1424
1425 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1426 svm_flush_tlb(vcpu);
1427
1428 vcpu->arch.cr4 = cr4;
1429 if (!npt_enabled)
1430 cr4 |= X86_CR4_PAE;
1431 cr4 |= host_cr4_mce;
1432 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1433 mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1434 }
1435
1436 static void svm_set_segment(struct kvm_vcpu *vcpu,
1437 struct kvm_segment *var, int seg)
1438 {
1439 struct vcpu_svm *svm = to_svm(vcpu);
1440 struct vmcb_seg *s = svm_seg(vcpu, seg);
1441
1442 s->base = var->base;
1443 s->limit = var->limit;
1444 s->selector = var->selector;
1445 if (var->unusable)
1446 s->attrib = 0;
1447 else {
1448 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1449 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1450 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1451 s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
1452 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1453 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1454 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1455 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1456 }
1457 if (seg == VCPU_SREG_CS)
1458 svm->vmcb->save.cpl
1459 = (svm->vmcb->save.cs.attrib
1460 >> SVM_SELECTOR_DPL_SHIFT) & 3;
1461
1462 mark_dirty(svm->vmcb, VMCB_SEG);
1463 }
1464
1465 static void update_db_intercept(struct kvm_vcpu *vcpu)
1466 {
1467 struct vcpu_svm *svm = to_svm(vcpu);
1468
1469 clr_exception_intercept(svm, DB_VECTOR);
1470 clr_exception_intercept(svm, BP_VECTOR);
1471
1472 if (svm->nmi_singlestep)
1473 set_exception_intercept(svm, DB_VECTOR);
1474
1475 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1476 if (vcpu->guest_debug &
1477 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
1478 set_exception_intercept(svm, DB_VECTOR);
1479 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1480 set_exception_intercept(svm, BP_VECTOR);
1481 } else
1482 vcpu->guest_debug = 0;
1483 }
1484
1485 static void svm_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1486 {
1487 struct vcpu_svm *svm = to_svm(vcpu);
1488
1489 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1490 svm->vmcb->save.dr7 = dbg->arch.debugreg[7];
1491 else
1492 svm->vmcb->save.dr7 = vcpu->arch.dr7;
1493
1494 mark_dirty(svm->vmcb, VMCB_DR);
1495
1496 update_db_intercept(vcpu);
1497 }
1498
1499 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1500 {
1501 if (sd->next_asid > sd->max_asid) {
1502 ++sd->asid_generation;
1503 sd->next_asid = 1;
1504 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1505 }
1506
1507 svm->asid_generation = sd->asid_generation;
1508 svm->vmcb->control.asid = sd->next_asid++;
1509
1510 mark_dirty(svm->vmcb, VMCB_ASID);
1511 }
1512
1513 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1514 {
1515 struct vcpu_svm *svm = to_svm(vcpu);
1516
1517 svm->vmcb->save.dr7 = value;
1518 mark_dirty(svm->vmcb, VMCB_DR);
1519 }
1520
1521 static int pf_interception(struct vcpu_svm *svm)
1522 {
1523 u64 fault_address = svm->vmcb->control.exit_info_2;
1524 u32 error_code;
1525 int r = 1;
1526
1527 switch (svm->apf_reason) {
1528 default:
1529 error_code = svm->vmcb->control.exit_info_1;
1530
1531 trace_kvm_page_fault(fault_address, error_code);
1532 if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
1533 kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
1534 r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1535 svm->vmcb->control.insn_bytes,
1536 svm->vmcb->control.insn_len);
1537 break;
1538 case KVM_PV_REASON_PAGE_NOT_PRESENT:
1539 svm->apf_reason = 0;
1540 local_irq_disable();
1541 kvm_async_pf_task_wait(fault_address);
1542 local_irq_enable();
1543 break;
1544 case KVM_PV_REASON_PAGE_READY:
1545 svm->apf_reason = 0;
1546 local_irq_disable();
1547 kvm_async_pf_task_wake(fault_address);
1548 local_irq_enable();
1549 break;
1550 }
1551 return r;
1552 }
1553
1554 static int db_interception(struct vcpu_svm *svm)
1555 {
1556 struct kvm_run *kvm_run = svm->vcpu.run;
1557
1558 if (!(svm->vcpu.guest_debug &
1559 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1560 !svm->nmi_singlestep) {
1561 kvm_queue_exception(&svm->vcpu, DB_VECTOR);
1562 return 1;
1563 }
1564
1565 if (svm->nmi_singlestep) {
1566 svm->nmi_singlestep = false;
1567 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
1568 svm->vmcb->save.rflags &=
1569 ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1570 update_db_intercept(&svm->vcpu);
1571 }
1572
1573 if (svm->vcpu.guest_debug &
1574 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1575 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1576 kvm_run->debug.arch.pc =
1577 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1578 kvm_run->debug.arch.exception = DB_VECTOR;
1579 return 0;
1580 }
1581
1582 return 1;
1583 }
1584
1585 static int bp_interception(struct vcpu_svm *svm)
1586 {
1587 struct kvm_run *kvm_run = svm->vcpu.run;
1588
1589 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1590 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1591 kvm_run->debug.arch.exception = BP_VECTOR;
1592 return 0;
1593 }
1594
1595 static int ud_interception(struct vcpu_svm *svm)
1596 {
1597 int er;
1598
1599 er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
1600 if (er != EMULATE_DONE)
1601 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1602 return 1;
1603 }
1604
1605 static void svm_fpu_activate(struct kvm_vcpu *vcpu)
1606 {
1607 struct vcpu_svm *svm = to_svm(vcpu);
1608
1609 clr_exception_intercept(svm, NM_VECTOR);
1610
1611 svm->vcpu.fpu_active = 1;
1612 update_cr0_intercept(svm);
1613 }
1614
1615 static int nm_interception(struct vcpu_svm *svm)
1616 {
1617 svm_fpu_activate(&svm->vcpu);
1618 return 1;
1619 }
1620
1621 static bool is_erratum_383(void)
1622 {
1623 int err, i;
1624 u64 value;
1625
1626 if (!erratum_383_found)
1627 return false;
1628
1629 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1630 if (err)
1631 return false;
1632
1633 /* Bit 62 may or may not be set for this mce */
1634 value &= ~(1ULL << 62);
1635
1636 if (value != 0xb600000000010015ULL)
1637 return false;
1638
1639 /* Clear MCi_STATUS registers */
1640 for (i = 0; i < 6; ++i)
1641 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1642
1643 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1644 if (!err) {
1645 u32 low, high;
1646
1647 value &= ~(1ULL << 2);
1648 low = lower_32_bits(value);
1649 high = upper_32_bits(value);
1650
1651 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1652 }
1653
1654 /* Flush tlb to evict multi-match entries */
1655 __flush_tlb_all();
1656
1657 return true;
1658 }
1659
1660 static void svm_handle_mce(struct vcpu_svm *svm)
1661 {
1662 if (is_erratum_383()) {
1663 /*
1664 * Erratum 383 triggered. Guest state is corrupt so kill the
1665 * guest.
1666 */
1667 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1668
1669 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1670
1671 return;
1672 }
1673
1674 /*
1675 * On an #MC intercept the MCE handler is not called automatically in
1676 * the host. So do it by hand here.
1677 */
1678 asm volatile (
1679 "int $0x12\n");
1680 /* not sure if we ever come back to this point */
1681
1682 return;
1683 }
1684
1685 static int mc_interception(struct vcpu_svm *svm)
1686 {
1687 return 1;
1688 }
1689
1690 static int shutdown_interception(struct vcpu_svm *svm)
1691 {
1692 struct kvm_run *kvm_run = svm->vcpu.run;
1693
1694 /*
1695 * VMCB is undefined after a SHUTDOWN intercept
1696 * so reinitialize it.
1697 */
1698 clear_page(svm->vmcb);
1699 init_vmcb(svm);
1700
1701 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1702 return 0;
1703 }
1704
1705 static int io_interception(struct vcpu_svm *svm)
1706 {
1707 struct kvm_vcpu *vcpu = &svm->vcpu;
1708 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1709 int size, in, string;
1710 unsigned port;
1711
1712 ++svm->vcpu.stat.io_exits;
1713 string = (io_info & SVM_IOIO_STR_MASK) != 0;
1714 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1715 if (string || in)
1716 return emulate_instruction(vcpu, 0) == EMULATE_DONE;
1717
1718 port = io_info >> 16;
1719 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1720 svm->next_rip = svm->vmcb->control.exit_info_2;
1721 skip_emulated_instruction(&svm->vcpu);
1722
1723 return kvm_fast_pio_out(vcpu, size, port);
1724 }
1725
1726 static int nmi_interception(struct vcpu_svm *svm)
1727 {
1728 return 1;
1729 }
1730
1731 static int intr_interception(struct vcpu_svm *svm)
1732 {
1733 ++svm->vcpu.stat.irq_exits;
1734 return 1;
1735 }
1736
1737 static int nop_on_interception(struct vcpu_svm *svm)
1738 {
1739 return 1;
1740 }
1741
1742 static int halt_interception(struct vcpu_svm *svm)
1743 {
1744 svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
1745 skip_emulated_instruction(&svm->vcpu);
1746 return kvm_emulate_halt(&svm->vcpu);
1747 }
1748
1749 static int vmmcall_interception(struct vcpu_svm *svm)
1750 {
1751 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
1752 skip_emulated_instruction(&svm->vcpu);
1753 kvm_emulate_hypercall(&svm->vcpu);
1754 return 1;
1755 }
1756
1757 static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
1758 {
1759 struct vcpu_svm *svm = to_svm(vcpu);
1760
1761 return svm->nested.nested_cr3;
1762 }
1763
1764 static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
1765 unsigned long root)
1766 {
1767 struct vcpu_svm *svm = to_svm(vcpu);
1768
1769 svm->vmcb->control.nested_cr3 = root;
1770 mark_dirty(svm->vmcb, VMCB_NPT);
1771 svm_flush_tlb(vcpu);
1772 }
1773
1774 static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
1775 struct x86_exception *fault)
1776 {
1777 struct vcpu_svm *svm = to_svm(vcpu);
1778
1779 svm->vmcb->control.exit_code = SVM_EXIT_NPF;
1780 svm->vmcb->control.exit_code_hi = 0;
1781 svm->vmcb->control.exit_info_1 = fault->error_code;
1782 svm->vmcb->control.exit_info_2 = fault->address;
1783
1784 nested_svm_vmexit(svm);
1785 }
1786
1787 static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
1788 {
1789 int r;
1790
1791 r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
1792
1793 vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
1794 vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
1795 vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
1796 vcpu->arch.mmu.shadow_root_level = get_npt_level();
1797 vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
1798
1799 return r;
1800 }
1801
1802 static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
1803 {
1804 vcpu->arch.walk_mmu = &vcpu->arch.mmu;
1805 }
1806
1807 static int nested_svm_check_permissions(struct vcpu_svm *svm)
1808 {
1809 if (!(svm->vcpu.arch.efer & EFER_SVME)
1810 || !is_paging(&svm->vcpu)) {
1811 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
1812 return 1;
1813 }
1814
1815 if (svm->vmcb->save.cpl) {
1816 kvm_inject_gp(&svm->vcpu, 0);
1817 return 1;
1818 }
1819
1820 return 0;
1821 }
1822
1823 static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
1824 bool has_error_code, u32 error_code)
1825 {
1826 int vmexit;
1827
1828 if (!is_guest_mode(&svm->vcpu))
1829 return 0;
1830
1831 svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
1832 svm->vmcb->control.exit_code_hi = 0;
1833 svm->vmcb->control.exit_info_1 = error_code;
1834 svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
1835
1836 vmexit = nested_svm_intercept(svm);
1837 if (vmexit == NESTED_EXIT_DONE)
1838 svm->nested.exit_required = true;
1839
1840 return vmexit;
1841 }
1842
1843 /* This function returns true if it is save to enable the irq window */
1844 static inline bool nested_svm_intr(struct vcpu_svm *svm)
1845 {
1846 if (!is_guest_mode(&svm->vcpu))
1847 return true;
1848
1849 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
1850 return true;
1851
1852 if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
1853 return false;
1854
1855 /*
1856 * if vmexit was already requested (by intercepted exception
1857 * for instance) do not overwrite it with "external interrupt"
1858 * vmexit.
1859 */
1860 if (svm->nested.exit_required)
1861 return false;
1862
1863 svm->vmcb->control.exit_code = SVM_EXIT_INTR;
1864 svm->vmcb->control.exit_info_1 = 0;
1865 svm->vmcb->control.exit_info_2 = 0;
1866
1867 if (svm->nested.intercept & 1ULL) {
1868 /*
1869 * The #vmexit can't be emulated here directly because this
1870 * code path runs with irqs and preemtion disabled. A
1871 * #vmexit emulation might sleep. Only signal request for
1872 * the #vmexit here.
1873 */
1874 svm->nested.exit_required = true;
1875 trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
1876 return false;
1877 }
1878
1879 return true;
1880 }
1881
1882 /* This function returns true if it is save to enable the nmi window */
1883 static inline bool nested_svm_nmi(struct vcpu_svm *svm)
1884 {
1885 if (!is_guest_mode(&svm->vcpu))
1886 return true;
1887
1888 if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
1889 return true;
1890
1891 svm->vmcb->control.exit_code = SVM_EXIT_NMI;
1892 svm->nested.exit_required = true;
1893
1894 return false;
1895 }
1896
1897 static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
1898 {
1899 struct page *page;
1900
1901 might_sleep();
1902
1903 page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
1904 if (is_error_page(page))
1905 goto error;
1906
1907 *_page = page;
1908
1909 return kmap(page);
1910
1911 error:
1912 kvm_release_page_clean(page);
1913 kvm_inject_gp(&svm->vcpu, 0);
1914
1915 return NULL;
1916 }
1917
1918 static void nested_svm_unmap(struct page *page)
1919 {
1920 kunmap(page);
1921 kvm_release_page_dirty(page);
1922 }
1923
1924 static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
1925 {
1926 unsigned port;
1927 u8 val, bit;
1928 u64 gpa;
1929
1930 if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
1931 return NESTED_EXIT_HOST;
1932
1933 port = svm->vmcb->control.exit_info_1 >> 16;
1934 gpa = svm->nested.vmcb_iopm + (port / 8);
1935 bit = port % 8;
1936 val = 0;
1937
1938 if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
1939 val &= (1 << bit);
1940
1941 return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1942 }
1943
1944 static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
1945 {
1946 u32 offset, msr, value;
1947 int write, mask;
1948
1949 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
1950 return NESTED_EXIT_HOST;
1951
1952 msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
1953 offset = svm_msrpm_offset(msr);
1954 write = svm->vmcb->control.exit_info_1 & 1;
1955 mask = 1 << ((2 * (msr & 0xf)) + write);
1956
1957 if (offset == MSR_INVALID)
1958 return NESTED_EXIT_DONE;
1959
1960 /* Offset is in 32 bit units but need in 8 bit units */
1961 offset *= 4;
1962
1963 if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
1964 return NESTED_EXIT_DONE;
1965
1966 return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
1967 }
1968
1969 static int nested_svm_exit_special(struct vcpu_svm *svm)
1970 {
1971 u32 exit_code = svm->vmcb->control.exit_code;
1972
1973 switch (exit_code) {
1974 case SVM_EXIT_INTR:
1975 case SVM_EXIT_NMI:
1976 case SVM_EXIT_EXCP_BASE + MC_VECTOR:
1977 return NESTED_EXIT_HOST;
1978 case SVM_EXIT_NPF:
1979 /* For now we are always handling NPFs when using them */
1980 if (npt_enabled)
1981 return NESTED_EXIT_HOST;
1982 break;
1983 case SVM_EXIT_EXCP_BASE + PF_VECTOR:
1984 /* When we're shadowing, trap PFs, but not async PF */
1985 if (!npt_enabled && svm->apf_reason == 0)
1986 return NESTED_EXIT_HOST;
1987 break;
1988 case SVM_EXIT_EXCP_BASE + NM_VECTOR:
1989 nm_interception(svm);
1990 break;
1991 default:
1992 break;
1993 }
1994
1995 return NESTED_EXIT_CONTINUE;
1996 }
1997
1998 /*
1999 * If this function returns true, this #vmexit was already handled
2000 */
2001 static int nested_svm_intercept(struct vcpu_svm *svm)
2002 {
2003 u32 exit_code = svm->vmcb->control.exit_code;
2004 int vmexit = NESTED_EXIT_HOST;
2005
2006 switch (exit_code) {
2007 case SVM_EXIT_MSR:
2008 vmexit = nested_svm_exit_handled_msr(svm);
2009 break;
2010 case SVM_EXIT_IOIO:
2011 vmexit = nested_svm_intercept_ioio(svm);
2012 break;
2013 case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
2014 u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
2015 if (svm->nested.intercept_cr & bit)
2016 vmexit = NESTED_EXIT_DONE;
2017 break;
2018 }
2019 case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
2020 u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
2021 if (svm->nested.intercept_dr & bit)
2022 vmexit = NESTED_EXIT_DONE;
2023 break;
2024 }
2025 case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
2026 u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
2027 if (svm->nested.intercept_exceptions & excp_bits)
2028 vmexit = NESTED_EXIT_DONE;
2029 /* async page fault always cause vmexit */
2030 else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
2031 svm->apf_reason != 0)
2032 vmexit = NESTED_EXIT_DONE;
2033 break;
2034 }
2035 case SVM_EXIT_ERR: {
2036 vmexit = NESTED_EXIT_DONE;
2037 break;
2038 }
2039 default: {
2040 u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
2041 if (svm->nested.intercept & exit_bits)
2042 vmexit = NESTED_EXIT_DONE;
2043 }
2044 }
2045
2046 return vmexit;
2047 }
2048
2049 static int nested_svm_exit_handled(struct vcpu_svm *svm)
2050 {
2051 int vmexit;
2052
2053 vmexit = nested_svm_intercept(svm);
2054
2055 if (vmexit == NESTED_EXIT_DONE)
2056 nested_svm_vmexit(svm);
2057
2058 return vmexit;
2059 }
2060
2061 static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
2062 {
2063 struct vmcb_control_area *dst = &dst_vmcb->control;
2064 struct vmcb_control_area *from = &from_vmcb->control;
2065
2066 dst->intercept_cr = from->intercept_cr;
2067 dst->intercept_dr = from->intercept_dr;
2068 dst->intercept_exceptions = from->intercept_exceptions;
2069 dst->intercept = from->intercept;
2070 dst->iopm_base_pa = from->iopm_base_pa;
2071 dst->msrpm_base_pa = from->msrpm_base_pa;
2072 dst->tsc_offset = from->tsc_offset;
2073 dst->asid = from->asid;
2074 dst->tlb_ctl = from->tlb_ctl;
2075 dst->int_ctl = from->int_ctl;
2076 dst->int_vector = from->int_vector;
2077 dst->int_state = from->int_state;
2078 dst->exit_code = from->exit_code;
2079 dst->exit_code_hi = from->exit_code_hi;
2080 dst->exit_info_1 = from->exit_info_1;
2081 dst->exit_info_2 = from->exit_info_2;
2082 dst->exit_int_info = from->exit_int_info;
2083 dst->exit_int_info_err = from->exit_int_info_err;
2084 dst->nested_ctl = from->nested_ctl;
2085 dst->event_inj = from->event_inj;
2086 dst->event_inj_err = from->event_inj_err;
2087 dst->nested_cr3 = from->nested_cr3;
2088 dst->lbr_ctl = from->lbr_ctl;
2089 }
2090
2091 static int nested_svm_vmexit(struct vcpu_svm *svm)
2092 {
2093 struct vmcb *nested_vmcb;
2094 struct vmcb *hsave = svm->nested.hsave;
2095 struct vmcb *vmcb = svm->vmcb;
2096 struct page *page;
2097
2098 trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
2099 vmcb->control.exit_info_1,
2100 vmcb->control.exit_info_2,
2101 vmcb->control.exit_int_info,
2102 vmcb->control.exit_int_info_err);
2103
2104 nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
2105 if (!nested_vmcb)
2106 return 1;
2107
2108 /* Exit Guest-Mode */
2109 leave_guest_mode(&svm->vcpu);
2110 svm->nested.vmcb = 0;
2111
2112 /* Give the current vmcb to the guest */
2113 disable_gif(svm);
2114
2115 nested_vmcb->save.es = vmcb->save.es;
2116 nested_vmcb->save.cs = vmcb->save.cs;
2117 nested_vmcb->save.ss = vmcb->save.ss;
2118 nested_vmcb->save.ds = vmcb->save.ds;
2119 nested_vmcb->save.gdtr = vmcb->save.gdtr;
2120 nested_vmcb->save.idtr = vmcb->save.idtr;
2121 nested_vmcb->save.efer = svm->vcpu.arch.efer;
2122 nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
2123 nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
2124 nested_vmcb->save.cr2 = vmcb->save.cr2;
2125 nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
2126 nested_vmcb->save.rflags = vmcb->save.rflags;
2127 nested_vmcb->save.rip = vmcb->save.rip;
2128 nested_vmcb->save.rsp = vmcb->save.rsp;
2129 nested_vmcb->save.rax = vmcb->save.rax;
2130 nested_vmcb->save.dr7 = vmcb->save.dr7;
2131 nested_vmcb->save.dr6 = vmcb->save.dr6;
2132 nested_vmcb->save.cpl = vmcb->save.cpl;
2133
2134 nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
2135 nested_vmcb->control.int_vector = vmcb->control.int_vector;
2136 nested_vmcb->control.int_state = vmcb->control.int_state;
2137 nested_vmcb->control.exit_code = vmcb->control.exit_code;
2138 nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
2139 nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
2140 nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
2141 nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
2142 nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
2143 nested_vmcb->control.next_rip = vmcb->control.next_rip;
2144
2145 /*
2146 * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
2147 * to make sure that we do not lose injected events. So check event_inj
2148 * here and copy it to exit_int_info if it is valid.
2149 * Exit_int_info and event_inj can't be both valid because the case
2150 * below only happens on a VMRUN instruction intercept which has
2151 * no valid exit_int_info set.
2152 */
2153 if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
2154 struct vmcb_control_area *nc = &nested_vmcb->control;
2155
2156 nc->exit_int_info = vmcb->control.event_inj;
2157 nc->exit_int_info_err = vmcb->control.event_inj_err;
2158 }
2159
2160 nested_vmcb->control.tlb_ctl = 0;
2161 nested_vmcb->control.event_inj = 0;
2162 nested_vmcb->control.event_inj_err = 0;
2163
2164 /* We always set V_INTR_MASKING and remember the old value in hflags */
2165 if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
2166 nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
2167
2168 /* Restore the original control entries */
2169 copy_vmcb_control_area(vmcb, hsave);
2170
2171 kvm_clear_exception_queue(&svm->vcpu);
2172 kvm_clear_interrupt_queue(&svm->vcpu);
2173
2174 svm->nested.nested_cr3 = 0;
2175
2176 /* Restore selected save entries */
2177 svm->vmcb->save.es = hsave->save.es;
2178 svm->vmcb->save.cs = hsave->save.cs;
2179 svm->vmcb->save.ss = hsave->save.ss;
2180 svm->vmcb->save.ds = hsave->save.ds;
2181 svm->vmcb->save.gdtr = hsave->save.gdtr;
2182 svm->vmcb->save.idtr = hsave->save.idtr;
2183 svm->vmcb->save.rflags = hsave->save.rflags;
2184 svm_set_efer(&svm->vcpu, hsave->save.efer);
2185 svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
2186 svm_set_cr4(&svm->vcpu, hsave->save.cr4);
2187 if (npt_enabled) {
2188 svm->vmcb->save.cr3 = hsave->save.cr3;
2189 svm->vcpu.arch.cr3 = hsave->save.cr3;
2190 } else {
2191 (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
2192 }
2193 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
2194 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
2195 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
2196 svm->vmcb->save.dr7 = 0;
2197 svm->vmcb->save.cpl = 0;
2198 svm->vmcb->control.exit_int_info = 0;
2199
2200 mark_all_dirty(svm->vmcb);
2201
2202 nested_svm_unmap(page);
2203
2204 nested_svm_uninit_mmu_context(&svm->vcpu);
2205 kvm_mmu_reset_context(&svm->vcpu);
2206 kvm_mmu_load(&svm->vcpu);
2207
2208 return 0;
2209 }
2210
2211 static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
2212 {
2213 /*
2214 * This function merges the msr permission bitmaps of kvm and the
2215 * nested vmcb. It is omptimized in that it only merges the parts where
2216 * the kvm msr permission bitmap may contain zero bits
2217 */
2218 int i;
2219
2220 if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
2221 return true;
2222
2223 for (i = 0; i < MSRPM_OFFSETS; i++) {
2224 u32 value, p;
2225 u64 offset;
2226
2227 if (msrpm_offsets[i] == 0xffffffff)
2228 break;
2229
2230 p = msrpm_offsets[i];
2231 offset = svm->nested.vmcb_msrpm + (p * 4);
2232
2233 if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
2234 return false;
2235
2236 svm->nested.msrpm[p] = svm->msrpm[p] | value;
2237 }
2238
2239 svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
2240
2241 return true;
2242 }
2243
2244 static bool nested_vmcb_checks(struct vmcb *vmcb)
2245 {
2246 if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
2247 return false;
2248
2249 if (vmcb->control.asid == 0)
2250 return false;
2251
2252 if (vmcb->control.nested_ctl && !npt_enabled)
2253 return false;
2254
2255 return true;
2256 }
2257
2258 static bool nested_svm_vmrun(struct vcpu_svm *svm)
2259 {
2260 struct vmcb *nested_vmcb;
2261 struct vmcb *hsave = svm->nested.hsave;
2262 struct vmcb *vmcb = svm->vmcb;
2263 struct page *page;
2264 u64 vmcb_gpa;
2265
2266 vmcb_gpa = svm->vmcb->save.rax;
2267
2268 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2269 if (!nested_vmcb)
2270 return false;
2271
2272 if (!nested_vmcb_checks(nested_vmcb)) {
2273 nested_vmcb->control.exit_code = SVM_EXIT_ERR;
2274 nested_vmcb->control.exit_code_hi = 0;
2275 nested_vmcb->control.exit_info_1 = 0;
2276 nested_vmcb->control.exit_info_2 = 0;
2277
2278 nested_svm_unmap(page);
2279
2280 return false;
2281 }
2282
2283 trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
2284 nested_vmcb->save.rip,
2285 nested_vmcb->control.int_ctl,
2286 nested_vmcb->control.event_inj,
2287 nested_vmcb->control.nested_ctl);
2288
2289 trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
2290 nested_vmcb->control.intercept_cr >> 16,
2291 nested_vmcb->control.intercept_exceptions,
2292 nested_vmcb->control.intercept);
2293
2294 /* Clear internal status */
2295 kvm_clear_exception_queue(&svm->vcpu);
2296 kvm_clear_interrupt_queue(&svm->vcpu);
2297
2298 /*
2299 * Save the old vmcb, so we don't need to pick what we save, but can
2300 * restore everything when a VMEXIT occurs
2301 */
2302 hsave->save.es = vmcb->save.es;
2303 hsave->save.cs = vmcb->save.cs;
2304 hsave->save.ss = vmcb->save.ss;
2305 hsave->save.ds = vmcb->save.ds;
2306 hsave->save.gdtr = vmcb->save.gdtr;
2307 hsave->save.idtr = vmcb->save.idtr;
2308 hsave->save.efer = svm->vcpu.arch.efer;
2309 hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
2310 hsave->save.cr4 = svm->vcpu.arch.cr4;
2311 hsave->save.rflags = vmcb->save.rflags;
2312 hsave->save.rip = kvm_rip_read(&svm->vcpu);
2313 hsave->save.rsp = vmcb->save.rsp;
2314 hsave->save.rax = vmcb->save.rax;
2315 if (npt_enabled)
2316 hsave->save.cr3 = vmcb->save.cr3;
2317 else
2318 hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
2319
2320 copy_vmcb_control_area(hsave, vmcb);
2321
2322 if (svm->vmcb->save.rflags & X86_EFLAGS_IF)
2323 svm->vcpu.arch.hflags |= HF_HIF_MASK;
2324 else
2325 svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
2326
2327 if (nested_vmcb->control.nested_ctl) {
2328 kvm_mmu_unload(&svm->vcpu);
2329 svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
2330 nested_svm_init_mmu_context(&svm->vcpu);
2331 }
2332
2333 /* Load the nested guest state */
2334 svm->vmcb->save.es = nested_vmcb->save.es;
2335 svm->vmcb->save.cs = nested_vmcb->save.cs;
2336 svm->vmcb->save.ss = nested_vmcb->save.ss;
2337 svm->vmcb->save.ds = nested_vmcb->save.ds;
2338 svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
2339 svm->vmcb->save.idtr = nested_vmcb->save.idtr;
2340 svm->vmcb->save.rflags = nested_vmcb->save.rflags;
2341 svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
2342 svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
2343 svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
2344 if (npt_enabled) {
2345 svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
2346 svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
2347 } else
2348 (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
2349
2350 /* Guest paging mode is active - reset mmu */
2351 kvm_mmu_reset_context(&svm->vcpu);
2352
2353 svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
2354 kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
2355 kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
2356 kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
2357
2358 /* In case we don't even reach vcpu_run, the fields are not updated */
2359 svm->vmcb->save.rax = nested_vmcb->save.rax;
2360 svm->vmcb->save.rsp = nested_vmcb->save.rsp;
2361 svm->vmcb->save.rip = nested_vmcb->save.rip;
2362 svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
2363 svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
2364 svm->vmcb->save.cpl = nested_vmcb->save.cpl;
2365
2366 svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
2367 svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
2368
2369 /* cache intercepts */
2370 svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
2371 svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
2372 svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
2373 svm->nested.intercept = nested_vmcb->control.intercept;
2374
2375 svm_flush_tlb(&svm->vcpu);
2376 svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
2377 if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
2378 svm->vcpu.arch.hflags |= HF_VINTR_MASK;
2379 else
2380 svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
2381
2382 if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
2383 /* We only want the cr8 intercept bits of the guest */
2384 clr_cr_intercept(svm, INTERCEPT_CR8_READ);
2385 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2386 }
2387
2388 /* We don't want to see VMMCALLs from a nested guest */
2389 clr_intercept(svm, INTERCEPT_VMMCALL);
2390
2391 svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
2392 svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
2393 svm->vmcb->control.int_state = nested_vmcb->control.int_state;
2394 svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
2395 svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
2396 svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
2397
2398 nested_svm_unmap(page);
2399
2400 /* Enter Guest-Mode */
2401 enter_guest_mode(&svm->vcpu);
2402
2403 /*
2404 * Merge guest and host intercepts - must be called with vcpu in
2405 * guest-mode to take affect here
2406 */
2407 recalc_intercepts(svm);
2408
2409 svm->nested.vmcb = vmcb_gpa;
2410
2411 enable_gif(svm);
2412
2413 mark_all_dirty(svm->vmcb);
2414
2415 return true;
2416 }
2417
2418 static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
2419 {
2420 to_vmcb->save.fs = from_vmcb->save.fs;
2421 to_vmcb->save.gs = from_vmcb->save.gs;
2422 to_vmcb->save.tr = from_vmcb->save.tr;
2423 to_vmcb->save.ldtr = from_vmcb->save.ldtr;
2424 to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
2425 to_vmcb->save.star = from_vmcb->save.star;
2426 to_vmcb->save.lstar = from_vmcb->save.lstar;
2427 to_vmcb->save.cstar = from_vmcb->save.cstar;
2428 to_vmcb->save.sfmask = from_vmcb->save.sfmask;
2429 to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
2430 to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
2431 to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
2432 }
2433
2434 static int vmload_interception(struct vcpu_svm *svm)
2435 {
2436 struct vmcb *nested_vmcb;
2437 struct page *page;
2438
2439 if (nested_svm_check_permissions(svm))
2440 return 1;
2441
2442 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2443 skip_emulated_instruction(&svm->vcpu);
2444
2445 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2446 if (!nested_vmcb)
2447 return 1;
2448
2449 nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
2450 nested_svm_unmap(page);
2451
2452 return 1;
2453 }
2454
2455 static int vmsave_interception(struct vcpu_svm *svm)
2456 {
2457 struct vmcb *nested_vmcb;
2458 struct page *page;
2459
2460 if (nested_svm_check_permissions(svm))
2461 return 1;
2462
2463 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2464 skip_emulated_instruction(&svm->vcpu);
2465
2466 nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
2467 if (!nested_vmcb)
2468 return 1;
2469
2470 nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
2471 nested_svm_unmap(page);
2472
2473 return 1;
2474 }
2475
2476 static int vmrun_interception(struct vcpu_svm *svm)
2477 {
2478 if (nested_svm_check_permissions(svm))
2479 return 1;
2480
2481 /* Save rip after vmrun instruction */
2482 kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
2483
2484 if (!nested_svm_vmrun(svm))
2485 return 1;
2486
2487 if (!nested_svm_vmrun_msrpm(svm))
2488 goto failed;
2489
2490 return 1;
2491
2492 failed:
2493
2494 svm->vmcb->control.exit_code = SVM_EXIT_ERR;
2495 svm->vmcb->control.exit_code_hi = 0;
2496 svm->vmcb->control.exit_info_1 = 0;
2497 svm->vmcb->control.exit_info_2 = 0;
2498
2499 nested_svm_vmexit(svm);
2500
2501 return 1;
2502 }
2503
2504 static int stgi_interception(struct vcpu_svm *svm)
2505 {
2506 if (nested_svm_check_permissions(svm))
2507 return 1;
2508
2509 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2510 skip_emulated_instruction(&svm->vcpu);
2511 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2512
2513 enable_gif(svm);
2514
2515 return 1;
2516 }
2517
2518 static int clgi_interception(struct vcpu_svm *svm)
2519 {
2520 if (nested_svm_check_permissions(svm))
2521 return 1;
2522
2523 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2524 skip_emulated_instruction(&svm->vcpu);
2525
2526 disable_gif(svm);
2527
2528 /* After a CLGI no interrupts should come */
2529 svm_clear_vintr(svm);
2530 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
2531
2532 mark_dirty(svm->vmcb, VMCB_INTR);
2533
2534 return 1;
2535 }
2536
2537 static int invlpga_interception(struct vcpu_svm *svm)
2538 {
2539 struct kvm_vcpu *vcpu = &svm->vcpu;
2540
2541 trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
2542 vcpu->arch.regs[VCPU_REGS_RAX]);
2543
2544 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2545 kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
2546
2547 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2548 skip_emulated_instruction(&svm->vcpu);
2549 return 1;
2550 }
2551
2552 static int skinit_interception(struct vcpu_svm *svm)
2553 {
2554 trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
2555
2556 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2557 return 1;
2558 }
2559
2560 static int xsetbv_interception(struct vcpu_svm *svm)
2561 {
2562 u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2563 u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
2564
2565 if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2566 svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
2567 skip_emulated_instruction(&svm->vcpu);
2568 }
2569
2570 return 1;
2571 }
2572
2573 static int invalid_op_interception(struct vcpu_svm *svm)
2574 {
2575 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2576 return 1;
2577 }
2578
2579 static int task_switch_interception(struct vcpu_svm *svm)
2580 {
2581 u16 tss_selector;
2582 int reason;
2583 int int_type = svm->vmcb->control.exit_int_info &
2584 SVM_EXITINTINFO_TYPE_MASK;
2585 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2586 uint32_t type =
2587 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2588 uint32_t idt_v =
2589 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2590 bool has_error_code = false;
2591 u32 error_code = 0;
2592
2593 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2594
2595 if (svm->vmcb->control.exit_info_2 &
2596 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2597 reason = TASK_SWITCH_IRET;
2598 else if (svm->vmcb->control.exit_info_2 &
2599 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2600 reason = TASK_SWITCH_JMP;
2601 else if (idt_v)
2602 reason = TASK_SWITCH_GATE;
2603 else
2604 reason = TASK_SWITCH_CALL;
2605
2606 if (reason == TASK_SWITCH_GATE) {
2607 switch (type) {
2608 case SVM_EXITINTINFO_TYPE_NMI:
2609 svm->vcpu.arch.nmi_injected = false;
2610 break;
2611 case SVM_EXITINTINFO_TYPE_EXEPT:
2612 if (svm->vmcb->control.exit_info_2 &
2613 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2614 has_error_code = true;
2615 error_code =
2616 (u32)svm->vmcb->control.exit_info_2;
2617 }
2618 kvm_clear_exception_queue(&svm->vcpu);
2619 break;
2620 case SVM_EXITINTINFO_TYPE_INTR:
2621 kvm_clear_interrupt_queue(&svm->vcpu);
2622 break;
2623 default:
2624 break;
2625 }
2626 }
2627
2628 if (reason != TASK_SWITCH_GATE ||
2629 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2630 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2631 (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
2632 skip_emulated_instruction(&svm->vcpu);
2633
2634 if (kvm_task_switch(&svm->vcpu, tss_selector, reason,
2635 has_error_code, error_code) == EMULATE_FAIL) {
2636 svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2637 svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
2638 svm->vcpu.run->internal.ndata = 0;
2639 return 0;
2640 }
2641 return 1;
2642 }
2643
2644 static int cpuid_interception(struct vcpu_svm *svm)
2645 {
2646 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2647 kvm_emulate_cpuid(&svm->vcpu);
2648 return 1;
2649 }
2650
2651 static int iret_interception(struct vcpu_svm *svm)
2652 {
2653 ++svm->vcpu.stat.nmi_window_exits;
2654 clr_intercept(svm, INTERCEPT_IRET);
2655 svm->vcpu.arch.hflags |= HF_IRET_MASK;
2656 return 1;
2657 }
2658
2659 static int invlpg_interception(struct vcpu_svm *svm)
2660 {
2661 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2662 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2663
2664 kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2665 skip_emulated_instruction(&svm->vcpu);
2666 return 1;
2667 }
2668
2669 static int emulate_on_interception(struct vcpu_svm *svm)
2670 {
2671 return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
2672 }
2673
2674 #define CR_VALID (1ULL << 63)
2675
2676 static int cr_interception(struct vcpu_svm *svm)
2677 {
2678 int reg, cr;
2679 unsigned long val;
2680 int err;
2681
2682 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2683 return emulate_on_interception(svm);
2684
2685 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2686 return emulate_on_interception(svm);
2687
2688 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2689 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2690
2691 err = 0;
2692 if (cr >= 16) { /* mov to cr */
2693 cr -= 16;
2694 val = kvm_register_read(&svm->vcpu, reg);
2695 switch (cr) {
2696 case 0:
2697 err = kvm_set_cr0(&svm->vcpu, val);
2698 break;
2699 case 3:
2700 err = kvm_set_cr3(&svm->vcpu, val);
2701 break;
2702 case 4:
2703 err = kvm_set_cr4(&svm->vcpu, val);
2704 break;
2705 case 8:
2706 err = kvm_set_cr8(&svm->vcpu, val);
2707 break;
2708 default:
2709 WARN(1, "unhandled write to CR%d", cr);
2710 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2711 return 1;
2712 }
2713 } else { /* mov from cr */
2714 switch (cr) {
2715 case 0:
2716 val = kvm_read_cr0(&svm->vcpu);
2717 break;
2718 case 2:
2719 val = svm->vcpu.arch.cr2;
2720 break;
2721 case 3:
2722 val = kvm_read_cr3(&svm->vcpu);
2723 break;
2724 case 4:
2725 val = kvm_read_cr4(&svm->vcpu);
2726 break;
2727 case 8:
2728 val = kvm_get_cr8(&svm->vcpu);
2729 break;
2730 default:
2731 WARN(1, "unhandled read from CR%d", cr);
2732 kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2733 return 1;
2734 }
2735 kvm_register_write(&svm->vcpu, reg, val);
2736 }
2737 kvm_complete_insn_gp(&svm->vcpu, err);
2738
2739 return 1;
2740 }
2741
2742 static int cr0_write_interception(struct vcpu_svm *svm)
2743 {
2744 struct kvm_vcpu *vcpu = &svm->vcpu;
2745 int r;
2746
2747 r = cr_interception(svm);
2748
2749 if (svm->nested.vmexit_rip) {
2750 kvm_register_write(vcpu, VCPU_REGS_RIP, svm->nested.vmexit_rip);
2751 kvm_register_write(vcpu, VCPU_REGS_RSP, svm->nested.vmexit_rsp);
2752 kvm_register_write(vcpu, VCPU_REGS_RAX, svm->nested.vmexit_rax);
2753 svm->nested.vmexit_rip = 0;
2754 }
2755
2756 return r;
2757 }
2758
2759 static int dr_interception(struct vcpu_svm *svm)
2760 {
2761 int reg, dr;
2762 unsigned long val;
2763 int err;
2764
2765 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2766 return emulate_on_interception(svm);
2767
2768 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2769 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2770
2771 if (dr >= 16) { /* mov to DRn */
2772 val = kvm_register_read(&svm->vcpu, reg);
2773 kvm_set_dr(&svm->vcpu, dr - 16, val);
2774 } else {
2775 err = kvm_get_dr(&svm->vcpu, dr, &val);
2776 if (!err)
2777 kvm_register_write(&svm->vcpu, reg, val);
2778 }
2779
2780 skip_emulated_instruction(&svm->vcpu);
2781
2782 return 1;
2783 }
2784
2785 static int cr8_write_interception(struct vcpu_svm *svm)
2786 {
2787 struct kvm_run *kvm_run = svm->vcpu.run;
2788 int r;
2789
2790 u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2791 /* instruction emulation calls kvm_set_cr8() */
2792 r = cr_interception(svm);
2793 if (irqchip_in_kernel(svm->vcpu.kvm)) {
2794 clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
2795 return r;
2796 }
2797 if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2798 return r;
2799 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2800 return 0;
2801 }
2802
2803 static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
2804 {
2805 struct vcpu_svm *svm = to_svm(vcpu);
2806
2807 switch (ecx) {
2808 case MSR_IA32_TSC: {
2809 struct vmcb *vmcb = get_host_vmcb(svm);
2810
2811 *data = vmcb->control.tsc_offset + native_read_tsc();
2812 break;
2813 }
2814 case MSR_STAR:
2815 *data = svm->vmcb->save.star;
2816 break;
2817 #ifdef CONFIG_X86_64
2818 case MSR_LSTAR:
2819 *data = svm->vmcb->save.lstar;
2820 break;
2821 case MSR_CSTAR:
2822 *data = svm->vmcb->save.cstar;
2823 break;
2824 case MSR_KERNEL_GS_BASE:
2825 *data = svm->vmcb->save.kernel_gs_base;
2826 break;
2827 case MSR_SYSCALL_MASK:
2828 *data = svm->vmcb->save.sfmask;
2829 break;
2830 #endif
2831 case MSR_IA32_SYSENTER_CS:
2832 *data = svm->vmcb->save.sysenter_cs;
2833 break;
2834 case MSR_IA32_SYSENTER_EIP:
2835 *data = svm->sysenter_eip;
2836 break;
2837 case MSR_IA32_SYSENTER_ESP:
2838 *data = svm->sysenter_esp;
2839 break;
2840 /*
2841 * Nobody will change the following 5 values in the VMCB so we can
2842 * safely return them on rdmsr. They will always be 0 until LBRV is
2843 * implemented.
2844 */
2845 case MSR_IA32_DEBUGCTLMSR:
2846 *data = svm->vmcb->save.dbgctl;
2847 break;
2848 case MSR_IA32_LASTBRANCHFROMIP:
2849 *data = svm->vmcb->save.br_from;
2850 break;
2851 case MSR_IA32_LASTBRANCHTOIP:
2852 *data = svm->vmcb->save.br_to;
2853 break;
2854 case MSR_IA32_LASTINTFROMIP:
2855 *data = svm->vmcb->save.last_excp_from;
2856 break;
2857 case MSR_IA32_LASTINTTOIP:
2858 *data = svm->vmcb->save.last_excp_to;
2859 break;
2860 case MSR_VM_HSAVE_PA:
2861 *data = svm->nested.hsave_msr;
2862 break;
2863 case MSR_VM_CR:
2864 *data = svm->nested.vm_cr_msr;
2865 break;
2866 case MSR_IA32_UCODE_REV:
2867 *data = 0x01000065;
2868 break;
2869 default:
2870 return kvm_get_msr_common(vcpu, ecx, data);
2871 }
2872 return 0;
2873 }
2874
2875 static int rdmsr_interception(struct vcpu_svm *svm)
2876 {
2877 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2878 u64 data;
2879
2880 if (svm_get_msr(&svm->vcpu, ecx, &data)) {
2881 trace_kvm_msr_read_ex(ecx);
2882 kvm_inject_gp(&svm->vcpu, 0);
2883 } else {
2884 trace_kvm_msr_read(ecx, data);
2885
2886 svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
2887 svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
2888 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2889 skip_emulated_instruction(&svm->vcpu);
2890 }
2891 return 1;
2892 }
2893
2894 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2895 {
2896 struct vcpu_svm *svm = to_svm(vcpu);
2897 int svm_dis, chg_mask;
2898
2899 if (data & ~SVM_VM_CR_VALID_MASK)
2900 return 1;
2901
2902 chg_mask = SVM_VM_CR_VALID_MASK;
2903
2904 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2905 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2906
2907 svm->nested.vm_cr_msr &= ~chg_mask;
2908 svm->nested.vm_cr_msr |= (data & chg_mask);
2909
2910 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2911
2912 /* check for svm_disable while efer.svme is set */
2913 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2914 return 1;
2915
2916 return 0;
2917 }
2918
2919 static int svm_set_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 data)
2920 {
2921 struct vcpu_svm *svm = to_svm(vcpu);
2922
2923 switch (ecx) {
2924 case MSR_IA32_TSC:
2925 kvm_write_tsc(vcpu, data);
2926 break;
2927 case MSR_STAR:
2928 svm->vmcb->save.star = data;
2929 break;
2930 #ifdef CONFIG_X86_64
2931 case MSR_LSTAR:
2932 svm->vmcb->save.lstar = data;
2933 break;
2934 case MSR_CSTAR:
2935 svm->vmcb->save.cstar = data;
2936 break;
2937 case MSR_KERNEL_GS_BASE:
2938 svm->vmcb->save.kernel_gs_base = data;
2939 break;
2940 case MSR_SYSCALL_MASK:
2941 svm->vmcb->save.sfmask = data;
2942 break;
2943 #endif
2944 case MSR_IA32_SYSENTER_CS:
2945 svm->vmcb->save.sysenter_cs = data;
2946 break;
2947 case MSR_IA32_SYSENTER_EIP:
2948 svm->sysenter_eip = data;
2949 svm->vmcb->save.sysenter_eip = data;
2950 break;
2951 case MSR_IA32_SYSENTER_ESP:
2952 svm->sysenter_esp = data;
2953 svm->vmcb->save.sysenter_esp = data;
2954 break;
2955 case MSR_IA32_DEBUGCTLMSR:
2956 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
2957 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2958 __func__, data);
2959 break;
2960 }
2961 if (data & DEBUGCTL_RESERVED_BITS)
2962 return 1;
2963
2964 svm->vmcb->save.dbgctl = data;
2965 mark_dirty(svm->vmcb, VMCB_LBR);
2966 if (data & (1ULL<<0))
2967 svm_enable_lbrv(svm);
2968 else
2969 svm_disable_lbrv(svm);
2970 break;
2971 case MSR_VM_HSAVE_PA:
2972 svm->nested.hsave_msr = data;
2973 break;
2974 case MSR_VM_CR:
2975 return svm_set_vm_cr(vcpu, data);
2976 case MSR_VM_IGNNE:
2977 pr_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2978 break;
2979 default:
2980 return kvm_set_msr_common(vcpu, ecx, data);
2981 }
2982 return 0;
2983 }
2984
2985 static int wrmsr_interception(struct vcpu_svm *svm)
2986 {
2987 u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
2988 u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
2989 | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
2990
2991
2992 svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
2993 if (svm_set_msr(&svm->vcpu, ecx, data)) {
2994 trace_kvm_msr_write_ex(ecx, data);
2995 kvm_inject_gp(&svm->vcpu, 0);
2996 } else {
2997 trace_kvm_msr_write(ecx, data);
2998 skip_emulated_instruction(&svm->vcpu);
2999 }
3000 return 1;
3001 }
3002
3003 static int msr_interception(struct vcpu_svm *svm)
3004 {
3005 if (svm->vmcb->control.exit_info_1)
3006 return wrmsr_interception(svm);
3007 else
3008 return rdmsr_interception(svm);
3009 }
3010
3011 static int interrupt_window_interception(struct vcpu_svm *svm)
3012 {
3013 struct kvm_run *kvm_run = svm->vcpu.run;
3014
3015 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3016 svm_clear_vintr(svm);
3017 svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
3018 mark_dirty(svm->vmcb, VMCB_INTR);
3019 /*
3020 * If the user space waits to inject interrupts, exit as soon as
3021 * possible
3022 */
3023 if (!irqchip_in_kernel(svm->vcpu.kvm) &&
3024 kvm_run->request_interrupt_window &&
3025 !kvm_cpu_has_interrupt(&svm->vcpu)) {
3026 ++svm->vcpu.stat.irq_window_exits;
3027 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3028 return 0;
3029 }
3030
3031 return 1;
3032 }
3033
3034 static int pause_interception(struct vcpu_svm *svm)
3035 {
3036 kvm_vcpu_on_spin(&(svm->vcpu));
3037 return 1;
3038 }
3039
3040 static int (*svm_exit_handlers[])(struct vcpu_svm *svm) = {
3041 [SVM_EXIT_READ_CR0] = cr_interception,
3042 [SVM_EXIT_READ_CR3] = cr_interception,
3043 [SVM_EXIT_READ_CR4] = cr_interception,
3044 [SVM_EXIT_READ_CR8] = cr_interception,
3045 [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
3046 [SVM_EXIT_WRITE_CR0] = cr0_write_interception,
3047 [SVM_EXIT_WRITE_CR3] = cr_interception,
3048 [SVM_EXIT_WRITE_CR4] = cr_interception,
3049 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
3050 [SVM_EXIT_READ_DR0] = dr_interception,
3051 [SVM_EXIT_READ_DR1] = dr_interception,
3052 [SVM_EXIT_READ_DR2] = dr_interception,
3053 [SVM_EXIT_READ_DR3] = dr_interception,
3054 [SVM_EXIT_READ_DR4] = dr_interception,
3055 [SVM_EXIT_READ_DR5] = dr_interception,
3056 [SVM_EXIT_READ_DR6] = dr_interception,
3057 [SVM_EXIT_READ_DR7] = dr_interception,
3058 [SVM_EXIT_WRITE_DR0] = dr_interception,
3059 [SVM_EXIT_WRITE_DR1] = dr_interception,
3060 [SVM_EXIT_WRITE_DR2] = dr_interception,
3061 [SVM_EXIT_WRITE_DR3] = dr_interception,
3062 [SVM_EXIT_WRITE_DR4] = dr_interception,
3063 [SVM_EXIT_WRITE_DR5] = dr_interception,
3064 [SVM_EXIT_WRITE_DR6] = dr_interception,
3065 [SVM_EXIT_WRITE_DR7] = dr_interception,
3066 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
3067 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
3068 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
3069 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
3070 [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
3071 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
3072 [SVM_EXIT_INTR] = intr_interception,
3073 [SVM_EXIT_NMI] = nmi_interception,
3074 [SVM_EXIT_SMI] = nop_on_interception,
3075 [SVM_EXIT_INIT] = nop_on_interception,
3076 [SVM_EXIT_VINTR] = interrupt_window_interception,
3077 [SVM_EXIT_CPUID] = cpuid_interception,
3078 [SVM_EXIT_IRET] = iret_interception,
3079 [SVM_EXIT_INVD] = emulate_on_interception,
3080 [SVM_EXIT_PAUSE] = pause_interception,
3081 [SVM_EXIT_HLT] = halt_interception,
3082 [SVM_EXIT_INVLPG] = invlpg_interception,
3083 [SVM_EXIT_INVLPGA] = invlpga_interception,
3084 [SVM_EXIT_IOIO] = io_interception,
3085 [SVM_EXIT_MSR] = msr_interception,
3086 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
3087 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3088 [SVM_EXIT_VMRUN] = vmrun_interception,
3089 [SVM_EXIT_VMMCALL] = vmmcall_interception,
3090 [SVM_EXIT_VMLOAD] = vmload_interception,
3091 [SVM_EXIT_VMSAVE] = vmsave_interception,
3092 [SVM_EXIT_STGI] = stgi_interception,
3093 [SVM_EXIT_CLGI] = clgi_interception,
3094 [SVM_EXIT_SKINIT] = skinit_interception,
3095 [SVM_EXIT_WBINVD] = emulate_on_interception,
3096 [SVM_EXIT_MONITOR] = invalid_op_interception,
3097 [SVM_EXIT_MWAIT] = invalid_op_interception,
3098 [SVM_EXIT_XSETBV] = xsetbv_interception,
3099 [SVM_EXIT_NPF] = pf_interception,
3100 };
3101
3102 void dump_vmcb(struct kvm_vcpu *vcpu)
3103 {
3104 struct vcpu_svm *svm = to_svm(vcpu);
3105 struct vmcb_control_area *control = &svm->vmcb->control;
3106 struct vmcb_save_area *save = &svm->vmcb->save;
3107
3108 pr_err("VMCB Control Area:\n");
3109 pr_err("cr_read: %04x\n", control->intercept_cr & 0xffff);
3110 pr_err("cr_write: %04x\n", control->intercept_cr >> 16);
3111 pr_err("dr_read: %04x\n", control->intercept_dr & 0xffff);
3112 pr_err("dr_write: %04x\n", control->intercept_dr >> 16);
3113 pr_err("exceptions: %08x\n", control->intercept_exceptions);
3114 pr_err("intercepts: %016llx\n", control->intercept);
3115 pr_err("pause filter count: %d\n", control->pause_filter_count);
3116 pr_err("iopm_base_pa: %016llx\n", control->iopm_base_pa);
3117 pr_err("msrpm_base_pa: %016llx\n", control->msrpm_base_pa);
3118 pr_err("tsc_offset: %016llx\n", control->tsc_offset);
3119 pr_err("asid: %d\n", control->asid);
3120 pr_err("tlb_ctl: %d\n", control->tlb_ctl);
3121 pr_err("int_ctl: %08x\n", control->int_ctl);
3122 pr_err("int_vector: %08x\n", control->int_vector);
3123 pr_err("int_state: %08x\n", control->int_state);
3124 pr_err("exit_code: %08x\n", control->exit_code);
3125 pr_err("exit_info1: %016llx\n", control->exit_info_1);
3126 pr_err("exit_info2: %016llx\n", control->exit_info_2);
3127 pr_err("exit_int_info: %08x\n", control->exit_int_info);
3128 pr_err("exit_int_info_err: %08x\n", control->exit_int_info_err);
3129 pr_err("nested_ctl: %lld\n", control->nested_ctl);
3130 pr_err("nested_cr3: %016llx\n", control->nested_cr3);
3131 pr_err("event_inj: %08x\n", control->event_inj);
3132 pr_err("event_inj_err: %08x\n", control->event_inj_err);
3133 pr_err("lbr_ctl: %lld\n", control->lbr_ctl);
3134 pr_err("next_rip: %016llx\n", control->next_rip);
3135 pr_err("VMCB State Save Area:\n");
3136 pr_err("es: s: %04x a: %04x l: %08x b: %016llx\n",
3137 save->es.selector, save->es.attrib,
3138 save->es.limit, save->es.base);
3139 pr_err("cs: s: %04x a: %04x l: %08x b: %016llx\n",
3140 save->cs.selector, save->cs.attrib,
3141 save->cs.limit, save->cs.base);
3142 pr_err("ss: s: %04x a: %04x l: %08x b: %016llx\n",
3143 save->ss.selector, save->ss.attrib,
3144 save->ss.limit, save->ss.base);
3145 pr_err("ds: s: %04x a: %04x l: %08x b: %016llx\n",
3146 save->ds.selector, save->ds.attrib,
3147 save->ds.limit, save->ds.base);
3148 pr_err("fs: s: %04x a: %04x l: %08x b: %016llx\n",
3149 save->fs.selector, save->fs.attrib,
3150 save->fs.limit, save->fs.base);
3151 pr_err("gs: s: %04x a: %04x l: %08x b: %016llx\n",
3152 save->gs.selector, save->gs.attrib,
3153 save->gs.limit, save->gs.base);
3154 pr_err("gdtr: s: %04x a: %04x l: %08x b: %016llx\n",
3155 save->gdtr.selector, save->gdtr.attrib,
3156 save->gdtr.limit, save->gdtr.base);
3157 pr_err("ldtr: s: %04x a: %04x l: %08x b: %016llx\n",
3158 save->ldtr.selector, save->ldtr.attrib,
3159 save->ldtr.limit, save->ldtr.base);
3160 pr_err("idtr: s: %04x a: %04x l: %08x b: %016llx\n",
3161 save->idtr.selector, save->idtr.attrib,
3162 save->idtr.limit, save->idtr.base);
3163 pr_err("tr: s: %04x a: %04x l: %08x b: %016llx\n",
3164 save->tr.selector, save->tr.attrib,
3165 save->tr.limit, save->tr.base);
3166 pr_err("cpl: %d efer: %016llx\n",
3167 save->cpl, save->efer);
3168 pr_err("cr0: %016llx cr2: %016llx\n",
3169 save->cr0, save->cr2);
3170 pr_err("cr3: %016llx cr4: %016llx\n",
3171 save->cr3, save->cr4);
3172 pr_err("dr6: %016llx dr7: %016llx\n",
3173 save->dr6, save->dr7);
3174 pr_err("rip: %016llx rflags: %016llx\n",
3175 save->rip, save->rflags);
3176 pr_err("rsp: %016llx rax: %016llx\n",
3177 save->rsp, save->rax);
3178 pr_err("star: %016llx lstar: %016llx\n",
3179 save->star, save->lstar);
3180 pr_err("cstar: %016llx sfmask: %016llx\n",
3181 save->cstar, save->sfmask);
3182 pr_err("kernel_gs_base: %016llx sysenter_cs: %016llx\n",
3183 save->kernel_gs_base, save->sysenter_cs);
3184 pr_err("sysenter_esp: %016llx sysenter_eip: %016llx\n",
3185 save->sysenter_esp, save->sysenter_eip);
3186 pr_err("gpat: %016llx dbgctl: %016llx\n",
3187 save->g_pat, save->dbgctl);
3188 pr_err("br_from: %016llx br_to: %016llx\n",
3189 save->br_from, save->br_to);
3190 pr_err("excp_from: %016llx excp_to: %016llx\n",
3191 save->last_excp_from, save->last_excp_to);
3192
3193 }
3194
3195 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
3196 {
3197 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3198
3199 *info1 = control->exit_info_1;
3200 *info2 = control->exit_info_2;
3201 }
3202
3203 static int handle_exit(struct kvm_vcpu *vcpu)
3204 {
3205 struct vcpu_svm *svm = to_svm(vcpu);
3206 struct kvm_run *kvm_run = vcpu->run;
3207 u32 exit_code = svm->vmcb->control.exit_code;
3208
3209 trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
3210
3211 if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
3212 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3213 if (npt_enabled)
3214 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3215
3216 if (unlikely(svm->nested.exit_required)) {
3217 nested_svm_vmexit(svm);
3218 svm->nested.exit_required = false;
3219
3220 return 1;
3221 }
3222
3223 if (is_guest_mode(vcpu)) {
3224 int vmexit;
3225
3226 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
3227 svm->vmcb->control.exit_info_1,
3228 svm->vmcb->control.exit_info_2,
3229 svm->vmcb->control.exit_int_info,
3230 svm->vmcb->control.exit_int_info_err);
3231
3232 vmexit = nested_svm_exit_special(svm);
3233
3234 if (vmexit == NESTED_EXIT_CONTINUE)
3235 vmexit = nested_svm_exit_handled(svm);
3236
3237 if (vmexit == NESTED_EXIT_DONE)
3238 return 1;
3239 }
3240
3241 svm_complete_interrupts(svm);
3242
3243 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3244 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3245 kvm_run->fail_entry.hardware_entry_failure_reason
3246 = svm->vmcb->control.exit_code;
3247 pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
3248 dump_vmcb(vcpu);
3249 return 0;
3250 }
3251
3252 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3253 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3254 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3255 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3256 printk(KERN_ERR "%s: unexpected exit_ini_info 0x%x "
3257 "exit_code 0x%x\n",
3258 __func__, svm->vmcb->control.exit_int_info,
3259 exit_code);
3260
3261 if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
3262 || !svm_exit_handlers[exit_code]) {
3263 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3264 kvm_run->hw.hardware_exit_reason = exit_code;
3265 return 0;
3266 }
3267
3268 return svm_exit_handlers[exit_code](svm);
3269 }
3270
3271 static void reload_tss(struct kvm_vcpu *vcpu)
3272 {
3273 int cpu = raw_smp_processor_id();
3274
3275 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3276 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3277 load_TR_desc();
3278 }
3279
3280 static void pre_svm_run(struct vcpu_svm *svm)
3281 {
3282 int cpu = raw_smp_processor_id();
3283
3284 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
3285
3286 /* FIXME: handle wraparound of asid_generation */
3287 if (svm->asid_generation != sd->asid_generation)
3288 new_asid(svm, sd);
3289 }
3290
3291 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3292 {
3293 struct vcpu_svm *svm = to_svm(vcpu);
3294
3295 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3296 vcpu->arch.hflags |= HF_NMI_MASK;
3297 set_intercept(svm, INTERCEPT_IRET);
3298 ++vcpu->stat.nmi_injections;
3299 }
3300
3301 static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
3302 {
3303 struct vmcb_control_area *control;
3304
3305 control = &svm->vmcb->control;
3306 control->int_vector = irq;
3307 control->int_ctl &= ~V_INTR_PRIO_MASK;
3308 control->int_ctl |= V_IRQ_MASK |
3309 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
3310 mark_dirty(svm->vmcb, VMCB_INTR);
3311 }
3312
3313 static void svm_set_irq(struct kvm_vcpu *vcpu)
3314 {
3315 struct vcpu_svm *svm = to_svm(vcpu);
3316
3317 BUG_ON(!(gif_set(svm)));
3318
3319 trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3320 ++vcpu->stat.irq_injections;
3321
3322 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3323 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3324 }
3325
3326 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3327 {
3328 struct vcpu_svm *svm = to_svm(vcpu);
3329
3330 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3331 return;
3332
3333 if (irr == -1)
3334 return;
3335
3336 if (tpr >= irr)
3337 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3338 }
3339
3340 static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
3341 {
3342 struct vcpu_svm *svm = to_svm(vcpu);
3343 struct vmcb *vmcb = svm->vmcb;
3344 int ret;
3345 ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
3346 !(svm->vcpu.arch.hflags & HF_NMI_MASK);
3347 ret = ret && gif_set(svm) && nested_svm_nmi(svm);
3348
3349 return ret;
3350 }
3351
3352 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3353 {
3354 struct vcpu_svm *svm = to_svm(vcpu);
3355
3356 return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3357 }
3358
3359 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3360 {
3361 struct vcpu_svm *svm = to_svm(vcpu);
3362
3363 if (masked) {
3364 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3365 set_intercept(svm, INTERCEPT_IRET);
3366 } else {
3367 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3368 clr_intercept(svm, INTERCEPT_IRET);
3369 }
3370 }
3371
3372 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
3373 {
3374 struct vcpu_svm *svm = to_svm(vcpu);
3375 struct vmcb *vmcb = svm->vmcb;
3376 int ret;
3377
3378 if (!gif_set(svm) ||
3379 (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
3380 return 0;
3381
3382 ret = !!(vmcb->save.rflags & X86_EFLAGS_IF);
3383
3384 if (is_guest_mode(vcpu))
3385 return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
3386
3387 return ret;
3388 }
3389
3390 static void enable_irq_window(struct kvm_vcpu *vcpu)
3391 {
3392 struct vcpu_svm *svm = to_svm(vcpu);
3393
3394 /*
3395 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3396 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3397 * get that intercept, this function will be called again though and
3398 * we'll get the vintr intercept.
3399 */
3400 if (gif_set(svm) && nested_svm_intr(svm)) {
3401 svm_set_vintr(svm);
3402 svm_inject_irq(svm, 0x0);
3403 }
3404 }
3405
3406 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3407 {
3408 struct vcpu_svm *svm = to_svm(vcpu);
3409
3410 if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3411 == HF_NMI_MASK)
3412 return; /* IRET will cause a vm exit */
3413
3414 /*
3415 * Something prevents NMI from been injected. Single step over possible
3416 * problem (IRET or exception injection or interrupt shadow)
3417 */
3418 svm->nmi_singlestep = true;
3419 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3420 update_db_intercept(vcpu);
3421 }
3422
3423 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3424 {
3425 return 0;
3426 }
3427
3428 static void svm_flush_tlb(struct kvm_vcpu *vcpu)
3429 {
3430 struct vcpu_svm *svm = to_svm(vcpu);
3431
3432 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3433 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3434 else
3435 svm->asid_generation--;
3436 }
3437
3438 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3439 {
3440 }
3441
3442 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3443 {
3444 struct vcpu_svm *svm = to_svm(vcpu);
3445
3446 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3447 return;
3448
3449 if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3450 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3451 kvm_set_cr8(vcpu, cr8);
3452 }
3453 }
3454
3455 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3456 {
3457 struct vcpu_svm *svm = to_svm(vcpu);
3458 u64 cr8;
3459
3460 if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
3461 return;
3462
3463 cr8 = kvm_get_cr8(vcpu);
3464 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3465 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3466 }
3467
3468 static void svm_complete_interrupts(struct vcpu_svm *svm)
3469 {
3470 u8 vector;
3471 int type;
3472 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3473 unsigned int3_injected = svm->int3_injected;
3474
3475 svm->int3_injected = 0;
3476
3477 if (svm->vcpu.arch.hflags & HF_IRET_MASK) {
3478 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3479 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3480 }
3481
3482 svm->vcpu.arch.nmi_injected = false;
3483 kvm_clear_exception_queue(&svm->vcpu);
3484 kvm_clear_interrupt_queue(&svm->vcpu);
3485
3486 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3487 return;
3488
3489 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3490
3491 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3492 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3493
3494 switch (type) {
3495 case SVM_EXITINTINFO_TYPE_NMI:
3496 svm->vcpu.arch.nmi_injected = true;
3497 break;
3498 case SVM_EXITINTINFO_TYPE_EXEPT:
3499 /*
3500 * In case of software exceptions, do not reinject the vector,
3501 * but re-execute the instruction instead. Rewind RIP first
3502 * if we emulated INT3 before.
3503 */
3504 if (kvm_exception_is_soft(vector)) {
3505 if (vector == BP_VECTOR && int3_injected &&
3506 kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3507 kvm_rip_write(&svm->vcpu,
3508 kvm_rip_read(&svm->vcpu) -
3509 int3_injected);
3510 break;
3511 }
3512 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3513 u32 err = svm->vmcb->control.exit_int_info_err;
3514 kvm_requeue_exception_e(&svm->vcpu, vector, err);
3515
3516 } else
3517 kvm_requeue_exception(&svm->vcpu, vector);
3518 break;
3519 case SVM_EXITINTINFO_TYPE_INTR:
3520 kvm_queue_interrupt(&svm->vcpu, vector, false);
3521 break;
3522 default:
3523 break;
3524 }
3525 }
3526
3527 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3528 {
3529 struct vcpu_svm *svm = to_svm(vcpu);
3530 struct vmcb_control_area *control = &svm->vmcb->control;
3531
3532 control->exit_int_info = control->event_inj;
3533 control->exit_int_info_err = control->event_inj_err;
3534 control->event_inj = 0;
3535 svm_complete_interrupts(svm);
3536 }
3537
3538 #ifdef CONFIG_X86_64
3539 #define R "r"
3540 #else
3541 #define R "e"
3542 #endif
3543
3544 static void svm_vcpu_run(struct kvm_vcpu *vcpu)
3545 {
3546 struct vcpu_svm *svm = to_svm(vcpu);
3547
3548 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3549 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3550 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3551
3552 /*
3553 * A vmexit emulation is required before the vcpu can be executed
3554 * again.
3555 */
3556 if (unlikely(svm->nested.exit_required))
3557 return;
3558
3559 pre_svm_run(svm);
3560
3561 sync_lapic_to_cr8(vcpu);
3562
3563 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3564
3565 clgi();
3566
3567 local_irq_enable();
3568
3569 asm volatile (
3570 "push %%"R"bp; \n\t"
3571 "mov %c[rbx](%[svm]), %%"R"bx \n\t"
3572 "mov %c[rcx](%[svm]), %%"R"cx \n\t"
3573 "mov %c[rdx](%[svm]), %%"R"dx \n\t"
3574 "mov %c[rsi](%[svm]), %%"R"si \n\t"
3575 "mov %c[rdi](%[svm]), %%"R"di \n\t"
3576 "mov %c[rbp](%[svm]), %%"R"bp \n\t"
3577 #ifdef CONFIG_X86_64
3578 "mov %c[r8](%[svm]), %%r8 \n\t"
3579 "mov %c[r9](%[svm]), %%r9 \n\t"
3580 "mov %c[r10](%[svm]), %%r10 \n\t"
3581 "mov %c[r11](%[svm]), %%r11 \n\t"
3582 "mov %c[r12](%[svm]), %%r12 \n\t"
3583 "mov %c[r13](%[svm]), %%r13 \n\t"
3584 "mov %c[r14](%[svm]), %%r14 \n\t"
3585 "mov %c[r15](%[svm]), %%r15 \n\t"
3586 #endif
3587
3588 /* Enter guest mode */
3589 "push %%"R"ax \n\t"
3590 "mov %c[vmcb](%[svm]), %%"R"ax \n\t"
3591 __ex(SVM_VMLOAD) "\n\t"
3592 __ex(SVM_VMRUN) "\n\t"
3593 __ex(SVM_VMSAVE) "\n\t"
3594 "pop %%"R"ax \n\t"
3595
3596 /* Save guest registers, load host registers */
3597 "mov %%"R"bx, %c[rbx](%[svm]) \n\t"
3598 "mov %%"R"cx, %c[rcx](%[svm]) \n\t"
3599 "mov %%"R"dx, %c[rdx](%[svm]) \n\t"
3600 "mov %%"R"si, %c[rsi](%[svm]) \n\t"
3601 "mov %%"R"di, %c[rdi](%[svm]) \n\t"
3602 "mov %%"R"bp, %c[rbp](%[svm]) \n\t"
3603 #ifdef CONFIG_X86_64
3604 "mov %%r8, %c[r8](%[svm]) \n\t"
3605 "mov %%r9, %c[r9](%[svm]) \n\t"
3606 "mov %%r10, %c[r10](%[svm]) \n\t"
3607 "mov %%r11, %c[r11](%[svm]) \n\t"
3608 "mov %%r12, %c[r12](%[svm]) \n\t"
3609 "mov %%r13, %c[r13](%[svm]) \n\t"
3610 "mov %%r14, %c[r14](%[svm]) \n\t"
3611 "mov %%r15, %c[r15](%[svm]) \n\t"
3612 #endif
3613 "pop %%"R"bp"
3614 :
3615 : [svm]"a"(svm),
3616 [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
3617 [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
3618 [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
3619 [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
3620 [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
3621 [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
3622 [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
3623 #ifdef CONFIG_X86_64
3624 , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
3625 [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
3626 [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
3627 [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
3628 [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
3629 [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
3630 [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
3631 [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
3632 #endif
3633 : "cc", "memory"
3634 , R"bx", R"cx", R"dx", R"si", R"di"
3635 #ifdef CONFIG_X86_64
3636 , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
3637 #endif
3638 );
3639
3640 #ifdef CONFIG_X86_64
3641 wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3642 #else
3643 loadsegment(fs, svm->host.fs);
3644 #endif
3645
3646 reload_tss(vcpu);
3647
3648 local_irq_disable();
3649
3650 vcpu->arch.cr2 = svm->vmcb->save.cr2;
3651 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3652 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3653 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3654
3655 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3656 kvm_before_handle_nmi(&svm->vcpu);
3657
3658 stgi();
3659
3660 /* Any pending NMI will happen here */
3661
3662 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3663 kvm_after_handle_nmi(&svm->vcpu);
3664
3665 sync_cr8_to_lapic(vcpu);
3666
3667 svm->next_rip = 0;
3668
3669 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3670
3671 /* if exit due to PF check for async PF */
3672 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3673 svm->apf_reason = kvm_read_and_reset_pf_reason();
3674
3675 if (npt_enabled) {
3676 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3677 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3678 }
3679
3680 /*
3681 * We need to handle MC intercepts here before the vcpu has a chance to
3682 * change the physical cpu
3683 */
3684 if (unlikely(svm->vmcb->control.exit_code ==
3685 SVM_EXIT_EXCP_BASE + MC_VECTOR))
3686 svm_handle_mce(svm);
3687
3688 mark_all_clean(svm->vmcb);
3689 }
3690
3691 #undef R
3692
3693 static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3694 {
3695 struct vcpu_svm *svm = to_svm(vcpu);
3696
3697 svm->vmcb->save.cr3 = root;
3698 mark_dirty(svm->vmcb, VMCB_CR);
3699 svm_flush_tlb(vcpu);
3700 }
3701
3702 static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
3703 {
3704 struct vcpu_svm *svm = to_svm(vcpu);
3705
3706 svm->vmcb->control.nested_cr3 = root;
3707 mark_dirty(svm->vmcb, VMCB_NPT);
3708
3709 /* Also sync guest cr3 here in case we live migrate */
3710 svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
3711 mark_dirty(svm->vmcb, VMCB_CR);
3712
3713 svm_flush_tlb(vcpu);
3714 }
3715
3716 static int is_disabled(void)
3717 {
3718 u64 vm_cr;
3719
3720 rdmsrl(MSR_VM_CR, vm_cr);
3721 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3722 return 1;
3723
3724 return 0;
3725 }
3726
3727 static void
3728 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3729 {
3730 /*
3731 * Patch in the VMMCALL instruction:
3732 */
3733 hypercall[0] = 0x0f;
3734 hypercall[1] = 0x01;
3735 hypercall[2] = 0xd9;
3736 }
3737
3738 static void svm_check_processor_compat(void *rtn)
3739 {
3740 *(int *)rtn = 0;
3741 }
3742
3743 static bool svm_cpu_has_accelerated_tpr(void)
3744 {
3745 return false;
3746 }
3747
3748 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3749 {
3750 return 0;
3751 }
3752
3753 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3754 {
3755 }
3756
3757 static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
3758 {
3759 switch (func) {
3760 case 0x80000001:
3761 if (nested)
3762 entry->ecx |= (1 << 2); /* Set SVM bit */
3763 break;
3764 case 0x8000000A:
3765 entry->eax = 1; /* SVM revision 1 */
3766 entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
3767 ASID emulation to nested SVM */
3768 entry->ecx = 0; /* Reserved */
3769 entry->edx = 0; /* Per default do not support any
3770 additional features */
3771
3772 /* Support next_rip if host supports it */
3773 if (boot_cpu_has(X86_FEATURE_NRIPS))
3774 entry->edx |= SVM_FEATURE_NRIP;
3775
3776 /* Support NPT for the guest if enabled */
3777 if (npt_enabled)
3778 entry->edx |= SVM_FEATURE_NPT;
3779
3780 break;
3781 }
3782 }
3783
3784 static const struct trace_print_flags svm_exit_reasons_str[] = {
3785 { SVM_EXIT_READ_CR0, "read_cr0" },
3786 { SVM_EXIT_READ_CR3, "read_cr3" },
3787 { SVM_EXIT_READ_CR4, "read_cr4" },
3788 { SVM_EXIT_READ_CR8, "read_cr8" },
3789 { SVM_EXIT_WRITE_CR0, "write_cr0" },
3790 { SVM_EXIT_WRITE_CR3, "write_cr3" },
3791 { SVM_EXIT_WRITE_CR4, "write_cr4" },
3792 { SVM_EXIT_WRITE_CR8, "write_cr8" },
3793 { SVM_EXIT_READ_DR0, "read_dr0" },
3794 { SVM_EXIT_READ_DR1, "read_dr1" },
3795 { SVM_EXIT_READ_DR2, "read_dr2" },
3796 { SVM_EXIT_READ_DR3, "read_dr3" },
3797 { SVM_EXIT_WRITE_DR0, "write_dr0" },
3798 { SVM_EXIT_WRITE_DR1, "write_dr1" },
3799 { SVM_EXIT_WRITE_DR2, "write_dr2" },
3800 { SVM_EXIT_WRITE_DR3, "write_dr3" },
3801 { SVM_EXIT_WRITE_DR5, "write_dr5" },
3802 { SVM_EXIT_WRITE_DR7, "write_dr7" },
3803 { SVM_EXIT_EXCP_BASE + DB_VECTOR, "DB excp" },
3804 { SVM_EXIT_EXCP_BASE + BP_VECTOR, "BP excp" },
3805 { SVM_EXIT_EXCP_BASE + UD_VECTOR, "UD excp" },
3806 { SVM_EXIT_EXCP_BASE + PF_VECTOR, "PF excp" },
3807 { SVM_EXIT_EXCP_BASE + NM_VECTOR, "NM excp" },
3808 { SVM_EXIT_EXCP_BASE + MC_VECTOR, "MC excp" },
3809 { SVM_EXIT_INTR, "interrupt" },
3810 { SVM_EXIT_NMI, "nmi" },
3811 { SVM_EXIT_SMI, "smi" },
3812 { SVM_EXIT_INIT, "init" },
3813 { SVM_EXIT_VINTR, "vintr" },
3814 { SVM_EXIT_CPUID, "cpuid" },
3815 { SVM_EXIT_INVD, "invd" },
3816 { SVM_EXIT_HLT, "hlt" },
3817 { SVM_EXIT_INVLPG, "invlpg" },
3818 { SVM_EXIT_INVLPGA, "invlpga" },
3819 { SVM_EXIT_IOIO, "io" },
3820 { SVM_EXIT_MSR, "msr" },
3821 { SVM_EXIT_TASK_SWITCH, "task_switch" },
3822 { SVM_EXIT_SHUTDOWN, "shutdown" },
3823 { SVM_EXIT_VMRUN, "vmrun" },
3824 { SVM_EXIT_VMMCALL, "hypercall" },
3825 { SVM_EXIT_VMLOAD, "vmload" },
3826 { SVM_EXIT_VMSAVE, "vmsave" },
3827 { SVM_EXIT_STGI, "stgi" },
3828 { SVM_EXIT_CLGI, "clgi" },
3829 { SVM_EXIT_SKINIT, "skinit" },
3830 { SVM_EXIT_WBINVD, "wbinvd" },
3831 { SVM_EXIT_MONITOR, "monitor" },
3832 { SVM_EXIT_MWAIT, "mwait" },
3833 { SVM_EXIT_XSETBV, "xsetbv" },
3834 { SVM_EXIT_NPF, "npf" },
3835 { -1, NULL }
3836 };
3837
3838 static int svm_get_lpage_level(void)
3839 {
3840 return PT_PDPE_LEVEL;
3841 }
3842
3843 static bool svm_rdtscp_supported(void)
3844 {
3845 return false;
3846 }
3847
3848 static bool svm_has_wbinvd_exit(void)
3849 {
3850 return true;
3851 }
3852
3853 static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
3854 {
3855 struct vcpu_svm *svm = to_svm(vcpu);
3856
3857 set_exception_intercept(svm, NM_VECTOR);
3858 update_cr0_intercept(svm);
3859 }
3860
3861 static struct kvm_x86_ops svm_x86_ops = {
3862 .cpu_has_kvm_support = has_svm,
3863 .disabled_by_bios = is_disabled,
3864 .hardware_setup = svm_hardware_setup,
3865 .hardware_unsetup = svm_hardware_unsetup,
3866 .check_processor_compatibility = svm_check_processor_compat,
3867 .hardware_enable = svm_hardware_enable,
3868 .hardware_disable = svm_hardware_disable,
3869 .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
3870
3871 .vcpu_create = svm_create_vcpu,
3872 .vcpu_free = svm_free_vcpu,
3873 .vcpu_reset = svm_vcpu_reset,
3874
3875 .prepare_guest_switch = svm_prepare_guest_switch,
3876 .vcpu_load = svm_vcpu_load,
3877 .vcpu_put = svm_vcpu_put,
3878
3879 .set_guest_debug = svm_guest_debug,
3880 .get_msr = svm_get_msr,
3881 .set_msr = svm_set_msr,
3882 .get_segment_base = svm_get_segment_base,
3883 .get_segment = svm_get_segment,
3884 .set_segment = svm_set_segment,
3885 .get_cpl = svm_get_cpl,
3886 .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
3887 .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
3888 .decache_cr3 = svm_decache_cr3,
3889 .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
3890 .set_cr0 = svm_set_cr0,
3891 .set_cr3 = svm_set_cr3,
3892 .set_cr4 = svm_set_cr4,
3893 .set_efer = svm_set_efer,
3894 .get_idt = svm_get_idt,
3895 .set_idt = svm_set_idt,
3896 .get_gdt = svm_get_gdt,
3897 .set_gdt = svm_set_gdt,
3898 .set_dr7 = svm_set_dr7,
3899 .cache_reg = svm_cache_reg,
3900 .get_rflags = svm_get_rflags,
3901 .set_rflags = svm_set_rflags,
3902 .fpu_activate = svm_fpu_activate,
3903 .fpu_deactivate = svm_fpu_deactivate,
3904
3905 .tlb_flush = svm_flush_tlb,
3906
3907 .run = svm_vcpu_run,
3908 .handle_exit = handle_exit,
3909 .skip_emulated_instruction = skip_emulated_instruction,
3910 .set_interrupt_shadow = svm_set_interrupt_shadow,
3911 .get_interrupt_shadow = svm_get_interrupt_shadow,
3912 .patch_hypercall = svm_patch_hypercall,
3913 .set_irq = svm_set_irq,
3914 .set_nmi = svm_inject_nmi,
3915 .queue_exception = svm_queue_exception,
3916 .cancel_injection = svm_cancel_injection,
3917 .interrupt_allowed = svm_interrupt_allowed,
3918 .nmi_allowed = svm_nmi_allowed,
3919 .get_nmi_mask = svm_get_nmi_mask,
3920 .set_nmi_mask = svm_set_nmi_mask,
3921 .enable_nmi_window = enable_nmi_window,
3922 .enable_irq_window = enable_irq_window,
3923 .update_cr8_intercept = update_cr8_intercept,
3924
3925 .set_tss_addr = svm_set_tss_addr,
3926 .get_tdp_level = get_npt_level,
3927 .get_mt_mask = svm_get_mt_mask,
3928
3929 .get_exit_info = svm_get_exit_info,
3930 .exit_reasons_str = svm_exit_reasons_str,
3931
3932 .get_lpage_level = svm_get_lpage_level,
3933
3934 .cpuid_update = svm_cpuid_update,
3935
3936 .rdtscp_supported = svm_rdtscp_supported,
3937
3938 .set_supported_cpuid = svm_set_supported_cpuid,
3939
3940 .has_wbinvd_exit = svm_has_wbinvd_exit,
3941
3942 .write_tsc_offset = svm_write_tsc_offset,
3943 .adjust_tsc_offset = svm_adjust_tsc_offset,
3944
3945 .set_tdp_cr3 = set_tdp_cr3,
3946 };
3947
3948 static int __init svm_init(void)
3949 {
3950 return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
3951 __alignof__(struct vcpu_svm), THIS_MODULE);
3952 }
3953
3954 static void __exit svm_exit(void)
3955 {
3956 kvm_exit();
3957 }
3958
3959 module_init(svm_init)
3960 module_exit(svm_exit)
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree