arch/blackfin/include/asm/mem_init.h

   1 /*
   2  * arch/blackfin/include/asm/mem_init.h - reprogram clocks / memory
   3  *
   4  * Copyright 2004-2008 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 #if defined(EBIU_SDGCTL)
  10 #if defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
  11     defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
  12     defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \
  13     defined(CONFIG_MEM_MT48LC32M8A2_75) || \
  14     defined(CONFIG_MEM_MT48LC8M32B2B5_7) || \
  15     defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
  16     defined(CONFIG_MEM_MT48LC32M8A2_75)
  17 #if (CONFIG_SCLK_HZ > 119402985)
  18 #define SDRAM_tRP       TRP_2
  19 #define SDRAM_tRP_num   2
  20 #define SDRAM_tRAS      TRAS_7
  21 #define SDRAM_tRAS_num  7
  22 #define SDRAM_tRCD      TRCD_2
  23 #define SDRAM_tWR       TWR_2
  24 #endif
  25 #if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
  26 #define SDRAM_tRP       TRP_2
  27 #define SDRAM_tRP_num   2
  28 #define SDRAM_tRAS      TRAS_6
  29 #define SDRAM_tRAS_num  6
  30 #define SDRAM_tRCD      TRCD_2
  31 #define SDRAM_tWR       TWR_2
  32 #endif
  33 #if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
  34 #define SDRAM_tRP       TRP_2
  35 #define SDRAM_tRP_num   2
  36 #define SDRAM_tRAS      TRAS_5
  37 #define SDRAM_tRAS_num  5
  38 #define SDRAM_tRCD      TRCD_2
  39 #define SDRAM_tWR       TWR_2
  40 #endif
  41 #if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
  42 #define SDRAM_tRP       TRP_2
  43 #define SDRAM_tRP_num   2
  44 #define SDRAM_tRAS      TRAS_4
  45 #define SDRAM_tRAS_num  4
  46 #define SDRAM_tRCD      TRCD_2
  47 #define SDRAM_tWR       TWR_2
  48 #endif
  49 #if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
  50 #define SDRAM_tRP       TRP_2
  51 #define SDRAM_tRP_num   2
  52 #define SDRAM_tRAS      TRAS_3
  53 #define SDRAM_tRAS_num  3
  54 #define SDRAM_tRCD      TRCD_2
  55 #define SDRAM_tWR       TWR_2
  56 #endif
  57 #if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
  58 #define SDRAM_tRP       TRP_1
  59 #define SDRAM_tRP_num   1
  60 #define SDRAM_tRAS      TRAS_4
  61 #define SDRAM_tRAS_num  4
  62 #define SDRAM_tRCD      TRCD_1
  63 #define SDRAM_tWR       TWR_2
  64 #endif
  65 #if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
  66 #define SDRAM_tRP       TRP_1
  67 #define SDRAM_tRP_num   1
  68 #define SDRAM_tRAS      TRAS_3
  69 #define SDRAM_tRAS_num  3
  70 #define SDRAM_tRCD      TRCD_1
  71 #define SDRAM_tWR       TWR_2
  72 #endif
  73 #if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
  74 #define SDRAM_tRP       TRP_1
  75 #define SDRAM_tRP_num   1
  76 #define SDRAM_tRAS      TRAS_2
  77 #define SDRAM_tRAS_num  2
  78 #define SDRAM_tRCD      TRCD_1
  79 #define SDRAM_tWR       TWR_2
  80 #endif
  81 #if (CONFIG_SCLK_HZ <= 29850746)
  82 #define SDRAM_tRP       TRP_1
  83 #define SDRAM_tRP_num   1
  84 #define SDRAM_tRAS      TRAS_1
  85 #define SDRAM_tRAS_num  1
  86 #define SDRAM_tRCD      TRCD_1
  87 #define SDRAM_tWR       TWR_2
  88 #endif
  89 #endif
  90
  91 /*
  92  * The BF526-EZ-Board changed SDRAM chips between revisions,
  93  * so we use below timings to accommodate both.
  94  */
  95 #if defined(CONFIG_MEM_MT48H32M16LFCJ_75)
  96 #if (CONFIG_SCLK_HZ > 119402985)
  97 #define SDRAM_tRP       TRP_2
  98 #define SDRAM_tRP_num   2
  99 #define SDRAM_tRAS      TRAS_8
 100 #define SDRAM_tRAS_num  8
 101 #define SDRAM_tRCD      TRCD_2
 102 #define SDRAM_tWR       TWR_2
 103 #endif
 104 #if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
 105 #define SDRAM_tRP       TRP_2
 106 #define SDRAM_tRP_num   2
 107 #define SDRAM_tRAS      TRAS_7
 108 #define SDRAM_tRAS_num  7
 109 #define SDRAM_tRCD      TRCD_2
 110 #define SDRAM_tWR       TWR_2
 111 #endif
 112 #if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
 113 #define SDRAM_tRP       TRP_2
 114 #define SDRAM_tRP_num   2
 115 #define SDRAM_tRAS      TRAS_6
 116 #define SDRAM_tRAS_num  6
 117 #define SDRAM_tRCD      TRCD_2
 118 #define SDRAM_tWR       TWR_2
 119 #endif
 120 #if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
 121 #define SDRAM_tRP       TRP_2
 122 #define SDRAM_tRP_num   2
 123 #define SDRAM_tRAS      TRAS_5
 124 #define SDRAM_tRAS_num  5
 125 #define SDRAM_tRCD      TRCD_2
 126 #define SDRAM_tWR       TWR_2
 127 #endif
 128 #if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
 129 #define SDRAM_tRP       TRP_2
 130 #define SDRAM_tRP_num   2
 131 #define SDRAM_tRAS      TRAS_4
 132 #define SDRAM_tRAS_num  4
 133 #define SDRAM_tRCD      TRCD_2
 134 #define SDRAM_tWR       TWR_2
 135 #endif
 136 #if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
 137 #define SDRAM_tRP       TRP_2
 138 #define SDRAM_tRP_num   2
 139 #define SDRAM_tRAS      TRAS_4
 140 #define SDRAM_tRAS_num  4
 141 #define SDRAM_tRCD      TRCD_1
 142 #define SDRAM_tWR       TWR_2
 143 #endif
 144 #if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
 145 #define SDRAM_tRP       TRP_2
 146 #define SDRAM_tRP_num   2
 147 #define SDRAM_tRAS      TRAS_3
 148 #define SDRAM_tRAS_num  3
 149 #define SDRAM_tRCD      TRCD_1
 150 #define SDRAM_tWR       TWR_2
 151 #endif
 152 #if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
 153 #define SDRAM_tRP       TRP_1
 154 #define SDRAM_tRP_num   1
 155 #define SDRAM_tRAS      TRAS_3
 156 #define SDRAM_tRAS_num  3
 157 #define SDRAM_tRCD      TRCD_1
 158 #define SDRAM_tWR       TWR_2
 159 #endif
 160 #if (CONFIG_SCLK_HZ <= 29850746)
 161 #define SDRAM_tRP       TRP_1
 162 #define SDRAM_tRP_num   1
 163 #define SDRAM_tRAS      TRAS_2
 164 #define SDRAM_tRAS_num  2
 165 #define SDRAM_tRCD      TRCD_1
 166 #define SDRAM_tWR       TWR_2
 167 #endif
 168 #endif
 169
 170 #if defined(CONFIG_MEM_MT48LC16M8A2TG_75) || \
 171     defined(CONFIG_MEM_MT48LC8M32B2B5_7)
 172   /*SDRAM INFORMATION: */
 173 #define SDRAM_Tref  64          /* Refresh period in milliseconds   */
 174 #define SDRAM_NRA   4096        /* Number of row addresses in SDRAM */
 175 #define SDRAM_CL    CL_3
 176 #endif
 177
 178 #if defined(CONFIG_MEM_MT48LC32M8A2_75) || \
 179     defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
 180     defined(CONFIG_MEM_MT48LC32M16A2TG_75) || \
 181     defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
 182     defined(CONFIG_MEM_MT48LC32M8A2_75)
 183   /*SDRAM INFORMATION: */
 184 #define SDRAM_Tref  64          /* Refresh period in milliseconds   */
 185 #define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
 186 #define SDRAM_CL    CL_3
 187 #endif
 188
 189 #if defined(CONFIG_MEM_MT48H32M16LFCJ_75)
 190   /*SDRAM INFORMATION: */
 191 #define SDRAM_Tref  64          /* Refresh period in milliseconds   */
 192 #define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
 193 #define SDRAM_CL    CL_2
 194 #endif
 195
 196
 197 #ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC
 198 /* Equation from section 17 (p17-46) of BF533 HRM */
 199 #define mem_SDRRC       (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
 200
 201 /* Enable SCLK Out */
 202 #define mem_SDGCTL        (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
 203 #else
 204 #define mem_SDRRC       CONFIG_MEM_SDRRC
 205 #define mem_SDGCTL      CONFIG_MEM_SDGCTL
 206 #endif
 207 #endif
 208
 209
 210 #if defined(EBIU_DDRCTL0)
 211 #define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1)
 212 #define MAX_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000)
 213 #define DDR_CLK_HZ(x)   (1000*1000*1000/x)
 214
 215 #if defined(CONFIG_MEM_MT46V32M16_6T)
 216 #define DDR_SIZE        DEVSZ_512
 217 #define DDR_WIDTH       DEVWD_16
 218 #define DDR_MAX_tCK     13
 219
 220 #define DDR_tRC         DDR_TRC(MIN_DDR_SCLK(60))
 221 #define DDR_tRAS        DDR_TRAS(MIN_DDR_SCLK(42))
 222 #define DDR_tRP         DDR_TRP(MIN_DDR_SCLK(15))
 223 #define DDR_tRFC        DDR_TRFC(MIN_DDR_SCLK(72))
 224 #define DDR_tREFI       DDR_TREFI(MAX_DDR_SCLK(7800))
 225
 226 #define DDR_tRCD        DDR_TRCD(MIN_DDR_SCLK(15))
 227 #define DDR_tWTR        DDR_TWTR(1)
 228 #define DDR_tMRD        DDR_TMRD(MIN_DDR_SCLK(12))
 229 #define DDR_tWR         DDR_TWR(MIN_DDR_SCLK(15))
 230 #endif
 231
 232 #if defined(CONFIG_MEM_MT46V32M16_5B)
 233 #define DDR_SIZE        DEVSZ_512
 234 #define DDR_WIDTH       DEVWD_16
 235 #define DDR_MAX_tCK     13
 236
 237 #define DDR_tRC         DDR_TRC(MIN_DDR_SCLK(55))
 238 #define DDR_tRAS        DDR_TRAS(MIN_DDR_SCLK(40))
 239 #define DDR_tRP         DDR_TRP(MIN_DDR_SCLK(15))
 240 #define DDR_tRFC        DDR_TRFC(MIN_DDR_SCLK(70))
 241 #define DDR_tREFI       DDR_TREFI(MAX_DDR_SCLK(7800))
 242
 243 #define DDR_tRCD        DDR_TRCD(MIN_DDR_SCLK(15))
 244 #define DDR_tWTR        DDR_TWTR(2)
 245 #define DDR_tMRD        DDR_TMRD(MIN_DDR_SCLK(10))
 246 #define DDR_tWR         DDR_TWR(MIN_DDR_SCLK(15))
 247 #endif
 248
 249 #if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK))
 250 # error "CONFIG_SCLK_HZ is too small (<DDR_CLK_HZ(DDR_MAX_tCK) Hz)."
 251 #elif(CONFIG_SCLK_HZ <= 133333333)
 252 # define        DDR_CL          CL_2
 253 #else
 254 # error "CONFIG_SCLK_HZ is too large (>133333333 Hz)."
 255 #endif
 256
 257 #ifdef CONFIG_BFIN_KERNEL_CLOCK_MEMINIT_CALC
 258 #define mem_DDRCTL0     (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI)
 259 #define mem_DDRCTL1     (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \
 260                         | DDR_tMRD | DDR_tWR | DDR_tRCD)
 261 #define mem_DDRCTL2     DDR_CL
 262 #else
 263 #define mem_DDRCTL0     CONFIG_MEM_DDRCTL0
 264 #define mem_DDRCTL1     CONFIG_MEM_DDRCTL1
 265 #define mem_DDRCTL2     CONFIG_MEM_DDRCTL2
 266 #endif
 267 #endif
 268
 269 #if defined CONFIG_CLKIN_HALF
 270 #define CLKIN_HALF       1
 271 #else
 272 #define CLKIN_HALF       0
 273 #endif
 274
 275 #if defined CONFIG_PLL_BYPASS
 276 #define PLL_BYPASS      1
 277 #else
 278 #define PLL_BYPASS       0
 279 #endif