1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include "i915_trace.h"
36 #include "intel_ringbuffer.h"
37 #include <linux/io-mapping.h>
38 #include <linux/i2c.h>
39 #include <drm/intel-gtt.h>
41 /* General customization:
44 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
46 #define DRIVER_NAME "i915"
47 #define DRIVER_DESC "Intel Graphics"
48 #define DRIVER_DATE "20080730"
60 #define I915_NUM_PIPE 2
62 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
67 * 1.2: Add Power Management
68 * 1.3: Add vblank support
69 * 1.4: Fix cmdbuffer path, add heap destroy
70 * 1.5: Add vblank pipe configuration
71 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
72 * - Support vertical blank on secondary display pipe
74 #define DRIVER_MAJOR 1
75 #define DRIVER_MINOR 6
76 #define DRIVER_PATCHLEVEL 0
78 #define WATCH_COHERENCY 0
82 #define WATCH_PWRITE 0
84 #define I915_GEM_PHYS_CURSOR_0 1
85 #define I915_GEM_PHYS_CURSOR_1 2
86 #define I915_GEM_PHYS_OVERLAY_REGS 3
87 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
89 struct drm_i915_gem_phys_object
{
91 struct page
**page_list
;
92 drm_dma_handle_t
*handle
;
93 struct drm_gem_object
*cur_obj
;
97 struct mem_block
*next
;
98 struct mem_block
*prev
;
101 struct drm_file
*file_priv
; /* NULL: free, -1: heap, other: real files */
104 struct opregion_header
;
105 struct opregion_acpi
;
106 struct opregion_swsci
;
107 struct opregion_asle
;
109 struct intel_opregion
{
110 struct opregion_header
*header
;
111 struct opregion_acpi
*acpi
;
112 struct opregion_swsci
*swsci
;
113 struct opregion_asle
*asle
;
116 #define OPREGION_SIZE (8*1024)
118 struct intel_overlay
;
119 struct intel_overlay_error_state
;
121 struct drm_i915_master_private
{
122 drm_local_map_t
*sarea
;
123 struct _drm_i915_sarea
*sarea_priv
;
125 #define I915_FENCE_REG_NONE -1
127 struct drm_i915_fence_reg
{
128 struct drm_gem_object
*obj
;
129 struct list_head lru_list
;
133 struct sdvo_device_mapping
{
143 struct drm_i915_error_state
{
152 u32 error
; /* gen6+ */
153 u32 bcs_acthd
; /* gen6+ blt engine */
158 u32 vcs_acthd
; /* gen6+ bsd engine */
169 struct drm_i915_error_object
{
173 } *ringbuffer
, *batchbuffer
[2];
174 struct drm_i915_error_buffer
{
189 struct intel_overlay_error_state
*overlay
;
192 struct drm_i915_display_funcs
{
193 void (*dpms
)(struct drm_crtc
*crtc
, int mode
);
194 bool (*fbc_enabled
)(struct drm_device
*dev
);
195 void (*enable_fbc
)(struct drm_crtc
*crtc
, unsigned long interval
);
196 void (*disable_fbc
)(struct drm_device
*dev
);
197 int (*get_display_clock_speed
)(struct drm_device
*dev
);
198 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
199 void (*update_wm
)(struct drm_device
*dev
, int planea_clock
,
200 int planeb_clock
, int sr_hdisplay
, int sr_htotal
,
202 /* clock updates for mode set */
204 /* render clock increase/decrease */
205 /* display clock increase/decrease */
206 /* pll clock increase/decrease */
207 /* clock gating init */
210 struct intel_device_info
{
220 u8 is_broadwater
: 1;
224 u8 has_pipe_cxsr
: 1;
226 u8 cursor_needs_physical
: 1;
228 u8 overlay_needs_physical
: 1;
235 FBC_NO_OUTPUT
, /* no outputs enabled to compress */
236 FBC_STOLEN_TOO_SMALL
, /* not enough space to hold compressed buffers */
237 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
238 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
239 FBC_BAD_PLANE
, /* fbc not supported on plane */
240 FBC_NOT_TILED
, /* buffer not tiled */
241 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
245 PCH_IBX
, /* Ibexpeak PCH */
246 PCH_CPT
, /* Cougarpoint PCH */
249 #define QUIRK_PIPEA_FORCE (1<<0)
253 typedef struct drm_i915_private
{
254 struct drm_device
*dev
;
256 const struct intel_device_info
*info
;
263 struct i2c_adapter adapter
;
264 struct i2c_adapter
*force_bit
;
268 struct pci_dev
*bridge_dev
;
269 struct intel_ring_buffer render_ring
;
270 struct intel_ring_buffer bsd_ring
;
271 struct intel_ring_buffer blt_ring
;
274 drm_dma_handle_t
*status_page_dmah
;
276 dma_addr_t dma_status_page
;
278 unsigned int seqno_gfx_addr
;
279 drm_local_map_t hws_map
;
280 struct drm_gem_object
*seqno_obj
;
281 struct drm_gem_object
*pwrctx
;
282 struct drm_gem_object
*renderctx
;
284 struct resource mch_res
;
292 wait_queue_head_t irq_queue
;
293 atomic_t irq_received
;
294 /** Protects user_irq_refcount and irq_mask_reg */
295 spinlock_t user_irq_lock
;
297 /** Cached value of IMR to avoid reads in updating the bitfield */
300 /** splitted irq regs for graphics and display engine on Ironlake,
301 irq_mask_reg is still used for display irq. */
303 u32 gt_irq_enable_reg
;
304 u32 de_irq_enable_reg
;
305 u32 pch_irq_mask_reg
;
306 u32 pch_irq_enable_reg
;
308 u32 hotplug_supported_mask
;
309 struct work_struct hotplug_work
;
311 int tex_lru_log_granularity
;
312 int allow_batchbuffer
;
313 struct mem_block
*agp_heap
;
314 unsigned int sr01
, adpa
, ppcr
, dvob
, dvoc
, lvds
;
318 /* For hangcheck timer */
319 #define DRM_I915_HANGCHECK_PERIOD 250 /* in ms */
320 struct timer_list hangcheck_timer
;
323 uint32_t last_instdone
;
324 uint32_t last_instdone1
;
326 unsigned long cfb_size
;
327 unsigned long cfb_pitch
;
328 unsigned long cfb_offset
;
335 struct intel_opregion opregion
;
338 struct intel_overlay
*overlay
;
341 int backlight_level
; /* restore backlight to this value */
342 struct drm_display_mode
*panel_fixed_mode
;
343 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
344 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
346 /* Feature bits from the VBIOS */
347 unsigned int int_tv_support
:1;
348 unsigned int lvds_dither
:1;
349 unsigned int lvds_vbt
:1;
350 unsigned int int_crt_support
:1;
351 unsigned int lvds_use_ssc
:1;
362 struct edp_power_seq pps
;
364 bool no_aux_handshake
;
366 struct notifier_block lid_notifier
;
369 struct drm_i915_fence_reg fence_regs
[16]; /* assume 965 */
370 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
371 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
373 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
375 spinlock_t error_lock
;
376 struct drm_i915_error_state
*first_error
;
377 struct work_struct error_work
;
378 struct completion error_completion
;
379 struct workqueue_struct
*wq
;
381 /* Display functions */
382 struct drm_i915_display_funcs display
;
384 /* PCH chipset type */
385 enum intel_pch pch_type
;
387 unsigned long quirks
;
412 u32 saveTRANS_HTOTAL_A
;
413 u32 saveTRANS_HBLANK_A
;
414 u32 saveTRANS_HSYNC_A
;
415 u32 saveTRANS_VTOTAL_A
;
416 u32 saveTRANS_VBLANK_A
;
417 u32 saveTRANS_VSYNC_A
;
425 u32 savePFIT_PGM_RATIOS
;
426 u32 saveBLC_HIST_CTL
;
428 u32 saveBLC_PWM_CTL2
;
429 u32 saveBLC_CPU_PWM_CTL
;
430 u32 saveBLC_CPU_PWM_CTL2
;
443 u32 saveTRANS_HTOTAL_B
;
444 u32 saveTRANS_HBLANK_B
;
445 u32 saveTRANS_HSYNC_B
;
446 u32 saveTRANS_VTOTAL_B
;
447 u32 saveTRANS_VBLANK_B
;
448 u32 saveTRANS_VSYNC_B
;
462 u32 savePP_ON_DELAYS
;
463 u32 savePP_OFF_DELAYS
;
471 u32 savePFIT_CONTROL
;
472 u32 save_palette_a
[256];
473 u32 save_palette_b
[256];
474 u32 saveDPFC_CB_BASE
;
475 u32 saveFBC_CFB_BASE
;
478 u32 saveFBC_CONTROL2
;
488 u32 saveCACHE_MODE_0
;
489 u32 saveMI_ARB_STATE
;
500 uint64_t saveFENCE
[16];
511 u32 savePIPEA_GMCH_DATA_M
;
512 u32 savePIPEB_GMCH_DATA_M
;
513 u32 savePIPEA_GMCH_DATA_N
;
514 u32 savePIPEB_GMCH_DATA_N
;
515 u32 savePIPEA_DP_LINK_M
;
516 u32 savePIPEB_DP_LINK_M
;
517 u32 savePIPEA_DP_LINK_N
;
518 u32 savePIPEB_DP_LINK_N
;
529 u32 savePCH_DREF_CONTROL
;
530 u32 saveDISP_ARB_CTL
;
531 u32 savePIPEA_DATA_M1
;
532 u32 savePIPEA_DATA_N1
;
533 u32 savePIPEA_LINK_M1
;
534 u32 savePIPEA_LINK_N1
;
535 u32 savePIPEB_DATA_M1
;
536 u32 savePIPEB_DATA_N1
;
537 u32 savePIPEB_LINK_M1
;
538 u32 savePIPEB_LINK_N1
;
539 u32 saveMCHBAR_RENDER_STANDBY
;
542 /** Bridge to intel-gtt-ko */
543 struct intel_gtt
*gtt
;
544 /** Memory allocator for GTT stolen memory */
546 /** Memory allocator for GTT */
547 struct drm_mm gtt_space
;
548 /** End of mappable part of GTT */
549 unsigned long gtt_mappable_end
;
551 struct io_mapping
*gtt_mapping
;
554 struct shrinker inactive_shrinker
;
557 * List of objects currently involved in rendering.
559 * Includes buffers having the contents of their GPU caches
560 * flushed, not necessarily primitives. last_rendering_seqno
561 * represents when the rendering involved will be completed.
563 * A reference is held on the buffer while on this list.
565 struct list_head active_list
;
568 * List of objects which are not in the ringbuffer but which
569 * still have a write_domain which needs to be flushed before
572 * last_rendering_seqno is 0 while an object is in this list.
574 * A reference is held on the buffer while on this list.
576 struct list_head flushing_list
;
579 * LRU list of objects which are not in the ringbuffer and
580 * are ready to unbind, but are still in the GTT.
582 * last_rendering_seqno is 0 while an object is in this list.
584 * A reference is not held on the buffer while on this list,
585 * as merely being GTT-bound shouldn't prevent its being
586 * freed, and we'll pull it off the list in the free path.
588 struct list_head inactive_list
;
591 * LRU list of objects which are not in the ringbuffer but
592 * are still pinned in the GTT.
594 struct list_head pinned_list
;
596 /** LRU list of objects with fence regs on them. */
597 struct list_head fence_list
;
600 * List of objects currently pending being freed.
602 * These objects are no longer in use, but due to a signal
603 * we were prevented from freeing them at the appointed time.
605 struct list_head deferred_free_list
;
608 * We leave the user IRQ off as much as possible,
609 * but this means that requests will finish and never
610 * be retired once the system goes idle. Set a timer to
611 * fire periodically while the ring is running. When it
612 * fires, go retire requests.
614 struct delayed_work retire_work
;
617 * Flag if the X Server, and thus DRM, is not currently in
618 * control of the device.
620 * This is set between LeaveVT and EnterVT. It needs to be
621 * replaced with a semaphore. It also needs to be
622 * transitioned away from for kernel modesetting.
627 * Flag if the hardware appears to be wedged.
629 * This is set when attempts to idle the device timeout.
630 * It prevents command submission from occuring and makes
631 * every pending request fail
635 /** Bit 6 swizzling required for X tiling */
636 uint32_t bit_6_swizzle_x
;
637 /** Bit 6 swizzling required for Y tiling */
638 uint32_t bit_6_swizzle_y
;
640 /* storage for physical objects */
641 struct drm_i915_gem_phys_object
*phys_objs
[I915_MAX_PHYS_OBJECT
];
643 /* accounting, useful for userland debugging */
644 size_t object_memory
;
647 size_t gtt_mappable_memory
;
648 size_t mappable_gtt_used
;
649 size_t mappable_gtt_total
;
653 u32 gtt_mappable_count
;
656 struct sdvo_device_mapping sdvo_mappings
[2];
657 /* indicate whether the LVDS_BORDER should be enabled or not */
658 unsigned int lvds_border_bits
;
659 /* Panel fitter placement and size for Ironlake+ */
660 u32 pch_pf_pos
, pch_pf_size
;
662 struct drm_crtc
*plane_to_crtc_mapping
[2];
663 struct drm_crtc
*pipe_to_crtc_mapping
[2];
664 wait_queue_head_t pending_flip_queue
;
665 bool flip_pending_is_done
;
667 /* Reclocking support */
668 bool render_reclock_avail
;
669 bool lvds_downclock_avail
;
670 /* indicates the reduced downclock for LVDS*/
672 struct work_struct idle_work
;
673 struct timer_list idle_timer
;
677 struct child_device_config
*child_dev
;
678 struct drm_connector
*int_lvds_connector
;
680 bool mchbar_need_disable
;
689 unsigned long last_time1
;
691 struct timespec last_time2
;
692 unsigned long gfx_power
;
696 spinlock_t
*mchdev_lock
;
698 enum no_fbc_reason no_fbc_reason
;
700 struct drm_mm_node
*compressed_fb
;
701 struct drm_mm_node
*compressed_llb
;
703 unsigned long last_gpu_reset
;
705 /* list of fbdev register on this device */
706 struct intel_fbdev
*fbdev
;
707 } drm_i915_private_t
;
709 /** driver private structure attached to each drm_gem_object */
710 struct drm_i915_gem_object
{
711 struct drm_gem_object base
;
713 /** Current space allocated to this object in the GTT, if any. */
714 struct drm_mm_node
*gtt_space
;
716 /** This object's place on the active/flushing/inactive lists */
717 struct list_head ring_list
;
718 struct list_head mm_list
;
719 /** This object's place on GPU write list */
720 struct list_head gpu_write_list
;
721 /** This object's place on eviction list */
722 struct list_head evict_list
;
725 * This is set if the object is on the active or flushing lists
726 * (has pending rendering), and is not set if it's on inactive (ready
729 unsigned int active
: 1;
732 * This is set if the object has been written to since last bound
735 unsigned int dirty
: 1;
738 * Fence register bits (if any) for this object. Will be set
739 * as needed when mapped into the GTT.
740 * Protected by dev->struct_mutex.
742 * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE)
744 signed int fence_reg
: 5;
747 * Used for checking the object doesn't appear more than once
748 * in an execbuffer object list.
750 unsigned int in_execbuffer
: 1;
753 * Advice: are the backing pages purgeable?
755 unsigned int madv
: 2;
758 * Current tiling mode for the object.
760 unsigned int tiling_mode
: 2;
762 /** How many users have pinned this object in GTT space. The following
763 * users can each hold at most one reference: pwrite/pread, pin_ioctl
764 * (via user_pin_count), execbuffer (objects are not allowed multiple
765 * times for the same batchbuffer), and the framebuffer code. When
766 * switching/pageflipping, the framebuffer code has at most two buffers
769 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
770 * bits with absolutely no headroom. So use 4 bits. */
771 unsigned int pin_count
: 4;
772 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
775 * Is the object at the current location in the gtt mappable and
776 * fenceable? Used to avoid costly recalculations.
778 unsigned int map_and_fenceable
: 1;
781 * Whether the current gtt mapping needs to be mappable (and isn't just
782 * mappable by accident). Track pin and fault separate for a more
783 * accurate mappable working set.
785 unsigned int fault_mappable
: 1;
786 unsigned int pin_mappable
: 1;
788 /** AGP memory structure for our GTT binding. */
789 DRM_AGP_MEM
*agp_mem
;
794 * Current offset of the object in GTT space.
796 * This is the same as gtt_space->start
800 /* Which ring is refering to is this object */
801 struct intel_ring_buffer
*ring
;
803 /** Breadcrumb of last rendering to the buffer. */
804 uint32_t last_rendering_seqno
;
806 /** Current tiling stride for the object, if it's tiled. */
809 /** Record of address bit 17 of each page at last unbind. */
810 unsigned long *bit_17
;
812 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
816 * If present, while GEM_DOMAIN_CPU is in the read domain this array
817 * flags which individual pages are valid.
819 uint8_t *page_cpu_valid
;
821 /** User space pin count and filp owning the pin */
822 uint32_t user_pin_count
;
823 struct drm_file
*pin_filp
;
825 /** for phy allocated objects */
826 struct drm_i915_gem_phys_object
*phys_obj
;
829 * Number of crtcs where this object is currently the fb, but
830 * will be page flipped away on the next vblank. When it
831 * reaches 0, dev_priv->pending_flip_queue will be woken up.
833 atomic_t pending_flip
;
836 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
839 * Request queue structure.
841 * The request queue allows us to note sequence numbers that have been emitted
842 * and may be associated with active buffers to be retired.
844 * By keeping this list, we can avoid having to do questionable
845 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
846 * an emission time with seqnos for tracking how far ahead of the GPU we are.
848 struct drm_i915_gem_request
{
849 /** On Which ring this request was generated */
850 struct intel_ring_buffer
*ring
;
852 /** GEM sequence number associated with this request. */
855 /** Time at which this request was emitted, in jiffies. */
856 unsigned long emitted_jiffies
;
858 /** global list entry for this request */
859 struct list_head list
;
861 struct drm_i915_file_private
*file_priv
;
862 /** file_priv list entry for this request */
863 struct list_head client_list
;
866 struct drm_i915_file_private
{
868 struct spinlock lock
;
869 struct list_head request_list
;
873 enum intel_chip_family
{
880 extern struct drm_ioctl_desc i915_ioctls
[];
881 extern int i915_max_ioctl
;
882 extern unsigned int i915_fbpercrtc
;
883 extern unsigned int i915_powersave
;
884 extern unsigned int i915_lvds_downclock
;
886 extern int i915_suspend(struct drm_device
*dev
, pm_message_t state
);
887 extern int i915_resume(struct drm_device
*dev
);
888 extern void i915_save_display(struct drm_device
*dev
);
889 extern void i915_restore_display(struct drm_device
*dev
);
890 extern int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
);
891 extern void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
);
894 extern void i915_kernel_lost_context(struct drm_device
* dev
);
895 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
896 extern int i915_driver_unload(struct drm_device
*);
897 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file_priv
);
898 extern void i915_driver_lastclose(struct drm_device
* dev
);
899 extern void i915_driver_preclose(struct drm_device
*dev
,
900 struct drm_file
*file_priv
);
901 extern void i915_driver_postclose(struct drm_device
*dev
,
902 struct drm_file
*file_priv
);
903 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
904 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
906 extern int i915_emit_box(struct drm_device
*dev
,
907 struct drm_clip_rect
*boxes
,
908 int i
, int DR1
, int DR4
);
909 extern int i915_reset(struct drm_device
*dev
, u8 flags
);
910 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
911 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
912 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
913 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
917 void i915_hangcheck_elapsed(unsigned long data
);
918 extern int i915_irq_emit(struct drm_device
*dev
, void *data
,
919 struct drm_file
*file_priv
);
920 extern int i915_irq_wait(struct drm_device
*dev
, void *data
,
921 struct drm_file
*file_priv
);
922 void i915_trace_irq_get(struct drm_device
*dev
, u32 seqno
);
923 extern void i915_enable_interrupt (struct drm_device
*dev
);
925 extern irqreturn_t
i915_driver_irq_handler(DRM_IRQ_ARGS
);
926 extern void i915_driver_irq_preinstall(struct drm_device
* dev
);
927 extern int i915_driver_irq_postinstall(struct drm_device
*dev
);
928 extern void i915_driver_irq_uninstall(struct drm_device
* dev
);
929 extern int i915_vblank_pipe_set(struct drm_device
*dev
, void *data
,
930 struct drm_file
*file_priv
);
931 extern int i915_vblank_pipe_get(struct drm_device
*dev
, void *data
,
932 struct drm_file
*file_priv
);
933 extern int i915_enable_vblank(struct drm_device
*dev
, int crtc
);
934 extern void i915_disable_vblank(struct drm_device
*dev
, int crtc
);
935 extern u32
i915_get_vblank_counter(struct drm_device
*dev
, int crtc
);
936 extern u32
gm45_get_vblank_counter(struct drm_device
*dev
, int crtc
);
937 extern int i915_vblank_swap(struct drm_device
*dev
, void *data
,
938 struct drm_file
*file_priv
);
939 extern void i915_enable_irq(drm_i915_private_t
*dev_priv
, u32 mask
);
940 extern void i915_disable_irq(drm_i915_private_t
*dev_priv
, u32 mask
);
941 extern void ironlake_enable_graphics_irq(drm_i915_private_t
*dev_priv
,
943 extern void ironlake_disable_graphics_irq(drm_i915_private_t
*dev_priv
,
947 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
950 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
952 void intel_enable_asle (struct drm_device
*dev
);
954 #ifdef CONFIG_DEBUG_FS
955 extern void i915_destroy_error_state(struct drm_device
*dev
);
957 #define i915_destroy_error_state(x)
962 extern int i915_mem_alloc(struct drm_device
*dev
, void *data
,
963 struct drm_file
*file_priv
);
964 extern int i915_mem_free(struct drm_device
*dev
, void *data
,
965 struct drm_file
*file_priv
);
966 extern int i915_mem_init_heap(struct drm_device
*dev
, void *data
,
967 struct drm_file
*file_priv
);
968 extern int i915_mem_destroy_heap(struct drm_device
*dev
, void *data
,
969 struct drm_file
*file_priv
);
970 extern void i915_mem_takedown(struct mem_block
**heap
);
971 extern void i915_mem_release(struct drm_device
* dev
,
972 struct drm_file
*file_priv
, struct mem_block
*heap
);
974 int i915_gem_check_is_wedged(struct drm_device
*dev
);
975 int i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
976 struct drm_file
*file_priv
);
977 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
978 struct drm_file
*file_priv
);
979 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
980 struct drm_file
*file_priv
);
981 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
982 struct drm_file
*file_priv
);
983 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
984 struct drm_file
*file_priv
);
985 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
986 struct drm_file
*file_priv
);
987 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
988 struct drm_file
*file_priv
);
989 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
990 struct drm_file
*file_priv
);
991 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
992 struct drm_file
*file_priv
);
993 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
994 struct drm_file
*file_priv
);
995 int i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
996 struct drm_file
*file_priv
);
997 int i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
998 struct drm_file
*file_priv
);
999 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
1000 struct drm_file
*file_priv
);
1001 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
1002 struct drm_file
*file_priv
);
1003 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
1004 struct drm_file
*file_priv
);
1005 int i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
1006 struct drm_file
*file_priv
);
1007 int i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
1008 struct drm_file
*file_priv
);
1009 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
1010 struct drm_file
*file_priv
);
1011 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
1012 struct drm_file
*file_priv
);
1013 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
1014 struct drm_file
*file_priv
);
1015 void i915_gem_load(struct drm_device
*dev
);
1016 int i915_gem_init_object(struct drm_gem_object
*obj
);
1017 struct drm_gem_object
* i915_gem_alloc_object(struct drm_device
*dev
,
1019 void i915_gem_free_object(struct drm_gem_object
*obj
);
1020 int i915_gem_object_pin(struct drm_gem_object
*obj
, uint32_t alignment
,
1021 bool map_and_fenceable
);
1022 void i915_gem_object_unpin(struct drm_gem_object
*obj
);
1023 int i915_gem_object_unbind(struct drm_gem_object
*obj
);
1024 void i915_gem_release_mmap(struct drm_gem_object
*obj
);
1025 void i915_gem_lastclose(struct drm_device
*dev
);
1028 * Returns true if seq1 is later than seq2.
1031 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
1033 return (int32_t)(seq1
- seq2
) >= 0;
1036 int i915_gem_object_get_fence_reg(struct drm_gem_object
*obj
,
1037 bool interruptible
);
1038 int i915_gem_object_put_fence_reg(struct drm_gem_object
*obj
,
1039 bool interruptible
);
1040 void i915_gem_retire_requests(struct drm_device
*dev
);
1041 void i915_gem_reset(struct drm_device
*dev
);
1042 void i915_gem_clflush_object(struct drm_gem_object
*obj
);
1043 int i915_gem_object_set_domain(struct drm_gem_object
*obj
,
1044 uint32_t read_domains
,
1045 uint32_t write_domain
);
1046 int i915_gem_init_ringbuffer(struct drm_device
*dev
);
1047 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
1048 int i915_gem_do_init(struct drm_device
*dev
, unsigned long start
,
1049 unsigned long mappable_end
, unsigned long end
);
1050 int i915_gpu_idle(struct drm_device
*dev
);
1051 int i915_gem_idle(struct drm_device
*dev
);
1052 int i915_add_request(struct drm_device
*dev
,
1053 struct drm_file
*file_priv
,
1054 struct drm_i915_gem_request
*request
,
1055 struct intel_ring_buffer
*ring
);
1056 int i915_do_wait_request(struct drm_device
*dev
,
1059 struct intel_ring_buffer
*ring
);
1060 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
1061 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object
*obj
,
1063 int i915_gem_object_set_to_display_plane(struct drm_gem_object
*obj
,
1065 int i915_gem_attach_phys_object(struct drm_device
*dev
,
1066 struct drm_gem_object
*obj
,
1069 void i915_gem_detach_phys_object(struct drm_device
*dev
,
1070 struct drm_gem_object
*obj
);
1071 void i915_gem_free_all_phys_object(struct drm_device
*dev
);
1072 void i915_gem_release(struct drm_device
* dev
, struct drm_file
*file_priv
);
1074 /* i915_gem_evict.c */
1075 int i915_gem_evict_something(struct drm_device
*dev
, int min_size
,
1076 unsigned alignment
, bool mappable
);
1077 int i915_gem_evict_everything(struct drm_device
*dev
, bool purgeable_only
);
1078 int i915_gem_evict_inactive(struct drm_device
*dev
, bool purgeable_only
);
1080 /* i915_gem_tiling.c */
1081 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
1082 void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object
*obj
);
1083 void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object
*obj
);
1085 /* i915_gem_debug.c */
1086 void i915_gem_dump_object(struct drm_gem_object
*obj
, int len
,
1087 const char *where
, uint32_t mark
);
1089 int i915_verify_lists(struct drm_device
*dev
);
1091 #define i915_verify_lists(dev) 0
1093 void i915_gem_object_check_coherency(struct drm_gem_object
*obj
, int handle
);
1094 void i915_gem_dump_object(struct drm_gem_object
*obj
, int len
,
1095 const char *where
, uint32_t mark
);
1097 /* i915_debugfs.c */
1098 int i915_debugfs_init(struct drm_minor
*minor
);
1099 void i915_debugfs_cleanup(struct drm_minor
*minor
);
1101 /* i915_suspend.c */
1102 extern int i915_save_state(struct drm_device
*dev
);
1103 extern int i915_restore_state(struct drm_device
*dev
);
1105 /* i915_suspend.c */
1106 extern int i915_save_state(struct drm_device
*dev
);
1107 extern int i915_restore_state(struct drm_device
*dev
);
1110 extern int intel_setup_gmbus(struct drm_device
*dev
);
1111 extern void intel_teardown_gmbus(struct drm_device
*dev
);
1112 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
1113 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
1114 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
1116 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
1118 extern void intel_i2c_reset(struct drm_device
*dev
);
1120 /* intel_opregion.c */
1121 extern int intel_opregion_setup(struct drm_device
*dev
);
1123 extern void intel_opregion_init(struct drm_device
*dev
);
1124 extern void intel_opregion_fini(struct drm_device
*dev
);
1125 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
1126 extern void intel_opregion_gse_intr(struct drm_device
*dev
);
1127 extern void intel_opregion_enable_asle(struct drm_device
*dev
);
1129 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
1130 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
1131 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
1132 static inline void intel_opregion_gse_intr(struct drm_device
*dev
) { return; }
1133 static inline void intel_opregion_enable_asle(struct drm_device
*dev
) { return; }
1138 extern void intel_register_dsm_handler(void);
1139 extern void intel_unregister_dsm_handler(void);
1141 static inline void intel_register_dsm_handler(void) { return; }
1142 static inline void intel_unregister_dsm_handler(void) { return; }
1143 #endif /* CONFIG_ACPI */
1146 extern void intel_modeset_init(struct drm_device
*dev
);
1147 extern void intel_modeset_cleanup(struct drm_device
*dev
);
1148 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
1149 extern void i8xx_disable_fbc(struct drm_device
*dev
);
1150 extern void g4x_disable_fbc(struct drm_device
*dev
);
1151 extern void ironlake_disable_fbc(struct drm_device
*dev
);
1152 extern void intel_disable_fbc(struct drm_device
*dev
);
1153 extern void intel_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
);
1154 extern bool intel_fbc_enabled(struct drm_device
*dev
);
1155 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
1156 extern void intel_detect_pch (struct drm_device
*dev
);
1157 extern int intel_trans_dp_port_sel (struct drm_crtc
*crtc
);
1160 #ifdef CONFIG_DEBUG_FS
1161 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
1162 extern void intel_overlay_print_error_state(struct seq_file
*m
, struct intel_overlay_error_state
*error
);
1166 * Lock test for when it's just for synchronization of ring access.
1168 * In that case, we don't need to do it when GEM is initialized as nobody else
1169 * has access to the ring.
1171 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
1172 if (((drm_i915_private_t *)dev->dev_private)->render_ring.gem_object \
1174 LOCK_TEST_WITH_RETURN(dev, file_priv); \
1177 static inline u32
i915_read(struct drm_i915_private
*dev_priv
, u32 reg
, int len
)
1183 val
= readq(dev_priv
->regs
+ reg
);
1186 val
= readl(dev_priv
->regs
+ reg
);
1189 val
= readw(dev_priv
->regs
+ reg
);
1192 val
= readb(dev_priv
->regs
+ reg
);
1195 trace_i915_reg_rw('R', reg
, val
, len
);
1201 i915_write(struct drm_i915_private
*dev_priv
, u32 reg
, u64 val
, int len
)
1203 /* Trace down the write operation before the real write */
1204 trace_i915_reg_rw('W', reg
, val
, len
);
1207 writeq(val
, dev_priv
->regs
+ reg
);
1210 writel(val
, dev_priv
->regs
+ reg
);
1213 writew(val
, dev_priv
->regs
+ reg
);
1216 writeb(val
, dev_priv
->regs
+ reg
);
1221 #define I915_READ(reg) i915_read(dev_priv, (reg), 4)
1222 #define I915_WRITE(reg, val) i915_write(dev_priv, (reg), (val), 4)
1223 #define I915_READ16(reg) i915_read(dev_priv, (reg), 2)
1224 #define I915_WRITE16(reg, val) i915_write(dev_priv, (reg), (val), 2)
1225 #define I915_READ8(reg) i915_read(dev_priv, (reg), 1)
1226 #define I915_WRITE8(reg, val) i915_write(dev_priv, (reg), (val), 1)
1227 #define I915_WRITE64(reg, val) i915_write(dev_priv, (reg), (val), 8)
1228 #define I915_READ64(reg) i915_read(dev_priv, (reg), 8)
1230 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1231 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1232 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1233 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1235 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1236 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
1239 #define BEGIN_LP_RING(n) \
1240 intel_ring_begin(&dev_priv->render_ring, (n))
1242 #define OUT_RING(x) \
1243 intel_ring_emit(&dev_priv->render_ring, x)
1245 #define ADVANCE_LP_RING() \
1246 intel_ring_advance(&dev_priv->render_ring)
1249 * Reads a dword out of the status page, which is written to from the command
1250 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
1251 * MI_STORE_DATA_IMM.
1253 * The following dwords have a reserved meaning:
1254 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
1255 * 0x04: ring 0 head pointer
1256 * 0x05: ring 1 head pointer (915-class)
1257 * 0x06: ring 2 head pointer (915-class)
1258 * 0x10-0x1b: Context status DWords (GM45)
1259 * 0x1f: Last written status offset. (GM45)
1261 * The area from dword 0x20 to 0x3ff is available for driver usage.
1263 #define READ_HWSP(dev_priv, reg) (((volatile u32 *)\
1264 (dev_priv->render_ring.status_page.page_addr))[reg])
1265 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
1266 #define I915_GEM_HWS_INDEX 0x20
1267 #define I915_BREADCRUMB_INDEX 0x21
1269 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1271 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1272 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1273 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1274 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1275 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1276 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1277 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1278 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1279 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1280 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1281 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1282 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1283 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1284 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1285 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1286 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1287 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1288 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1289 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1291 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1292 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1293 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1294 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1295 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1297 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1298 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1299 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1301 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1302 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1304 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1305 * rows, which changed the alignment requirements and fence programming.
1307 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1309 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1310 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1311 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1312 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1313 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1314 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1315 /* dsparb controlled by hw only */
1316 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1318 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1319 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1320 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1321 #define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
1323 #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev))
1324 #define HAS_PIPE_CONTROL(dev) (IS_GEN5(dev) || IS_GEN6(dev))
1326 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1327 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1328 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1330 #define PRIMARY_RINGBUFFER_SIZE (128*1024)