1 #include <linux/bootmem.h>
2 #include <linux/linkage.h>
3 #include <linux/bitops.h>
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <linux/string.h>
8 #include <linux/delay.h>
9 #include <linux/sched.h>
10 #include <linux/init.h>
11 #include <linux/kgdb.h>
12 #include <linux/smp.h>
15 #include <asm/stackprotector.h>
16 #include <asm/perf_counter.h>
17 #include <asm/mmu_context.h>
18 #include <asm/hypervisor.h>
19 #include <asm/processor.h>
20 #include <asm/sections.h>
21 #include <asm/topology.h>
22 #include <asm/cpumask.h>
23 #include <asm/pgtable.h>
24 #include <asm/atomic.h>
25 #include <asm/proto.h>
26 #include <asm/setup.h>
39 #ifdef CONFIG_X86_LOCAL_APIC
40 #include <asm/uv/uv.h>
45 /* all of these masks are initialized in setup_cpu_local_masks() */
46 cpumask_var_t cpu_initialized_mask
;
47 cpumask_var_t cpu_callout_mask
;
48 cpumask_var_t cpu_callin_mask
;
50 /* representing cpus for which sibling maps can be computed */
51 cpumask_var_t cpu_sibling_setup_mask
;
53 /* correctly size the local cpu masks */
54 void __init
setup_cpu_local_masks(void)
56 alloc_bootmem_cpumask_var(&cpu_initialized_mask
);
57 alloc_bootmem_cpumask_var(&cpu_callin_mask
);
58 alloc_bootmem_cpumask_var(&cpu_callout_mask
);
59 alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask
);
62 static const struct cpu_dev
*this_cpu __cpuinitdata
;
64 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page
, gdt_page
) = { .gdt
= {
67 * We need valid kernel segments for data and code in long mode too
68 * IRET will check the segment types kkeil 2000/10/28
69 * Also sysret mandates a special GDT layout
71 * TLS descriptors are currently at a different place compared to i386.
72 * Hopefully nobody expects them at a fixed place (Wine?)
74 [GDT_ENTRY_KERNEL32_CS
] = { { { 0x0000ffff, 0x00cf9b00 } } },
75 [GDT_ENTRY_KERNEL_CS
] = { { { 0x0000ffff, 0x00af9b00 } } },
76 [GDT_ENTRY_KERNEL_DS
] = { { { 0x0000ffff, 0x00cf9300 } } },
77 [GDT_ENTRY_DEFAULT_USER32_CS
] = { { { 0x0000ffff, 0x00cffb00 } } },
78 [GDT_ENTRY_DEFAULT_USER_DS
] = { { { 0x0000ffff, 0x00cff300 } } },
79 [GDT_ENTRY_DEFAULT_USER_CS
] = { { { 0x0000ffff, 0x00affb00 } } },
81 [GDT_ENTRY_KERNEL_CS
] = { { { 0x0000ffff, 0x00cf9a00 } } },
82 [GDT_ENTRY_KERNEL_DS
] = { { { 0x0000ffff, 0x00cf9200 } } },
83 [GDT_ENTRY_DEFAULT_USER_CS
] = { { { 0x0000ffff, 0x00cffa00 } } },
84 [GDT_ENTRY_DEFAULT_USER_DS
] = { { { 0x0000ffff, 0x00cff200 } } },
86 * Segments used for calling PnP BIOS have byte granularity.
87 * They code segments and data segments have fixed 64k limits,
88 * the transfer segment sizes are set at run time.
91 [GDT_ENTRY_PNPBIOS_CS32
] = { { { 0x0000ffff, 0x00409a00 } } },
93 [GDT_ENTRY_PNPBIOS_CS16
] = { { { 0x0000ffff, 0x00009a00 } } },
95 [GDT_ENTRY_PNPBIOS_DS
] = { { { 0x0000ffff, 0x00009200 } } },
97 [GDT_ENTRY_PNPBIOS_TS1
] = { { { 0x00000000, 0x00009200 } } },
99 [GDT_ENTRY_PNPBIOS_TS2
] = { { { 0x00000000, 0x00009200 } } },
101 * The APM segments have byte granularity and their bases
102 * are set at run time. All have 64k limits.
105 [GDT_ENTRY_APMBIOS_BASE
] = { { { 0x0000ffff, 0x00409a00 } } },
107 [GDT_ENTRY_APMBIOS_BASE
+1] = { { { 0x0000ffff, 0x00009a00 } } },
109 [GDT_ENTRY_APMBIOS_BASE
+2] = { { { 0x0000ffff, 0x00409200 } } },
111 [GDT_ENTRY_ESPFIX_SS
] = { { { 0x00000000, 0x00c09200 } } },
112 [GDT_ENTRY_PERCPU
] = { { { 0x0000ffff, 0x00cf9200 } } },
113 GDT_STACK_CANARY_INIT
116 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page
);
118 static int __init
x86_xsave_setup(char *s
)
120 setup_clear_cpu_cap(X86_FEATURE_XSAVE
);
123 __setup("noxsave", x86_xsave_setup
);
126 static int cachesize_override __cpuinitdata
= -1;
127 static int disable_x86_serial_nr __cpuinitdata
= 1;
129 static int __init
cachesize_setup(char *str
)
131 get_option(&str
, &cachesize_override
);
134 __setup("cachesize=", cachesize_setup
);
136 static int __init
x86_fxsr_setup(char *s
)
138 setup_clear_cpu_cap(X86_FEATURE_FXSR
);
139 setup_clear_cpu_cap(X86_FEATURE_XMM
);
142 __setup("nofxsr", x86_fxsr_setup
);
144 static int __init
x86_sep_setup(char *s
)
146 setup_clear_cpu_cap(X86_FEATURE_SEP
);
149 __setup("nosep", x86_sep_setup
);
151 /* Standard macro to see if a specific flag is changeable */
152 static inline int flag_is_changeable_p(u32 flag
)
157 * Cyrix and IDT cpus allow disabling of CPUID
158 * so the code below may return different results
159 * when it is executed before and after enabling
160 * the CPUID. Add "volatile" to not allow gcc to
161 * optimize the subsequent calls to this function.
163 asm volatile ("pushfl \n\t"
174 : "=&r" (f1
), "=&r" (f2
)
177 return ((f1
^f2
) & flag
) != 0;
180 /* Probe for the CPUID instruction */
181 static int __cpuinit
have_cpuid_p(void)
183 return flag_is_changeable_p(X86_EFLAGS_ID
);
186 static void __cpuinit
squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
188 unsigned long lo
, hi
;
190 if (!cpu_has(c
, X86_FEATURE_PN
) || !disable_x86_serial_nr
)
193 /* Disable processor serial number: */
195 rdmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
197 wrmsr(MSR_IA32_BBL_CR_CTL
, lo
, hi
);
199 printk(KERN_NOTICE
"CPU serial number disabled.\n");
200 clear_cpu_cap(c
, X86_FEATURE_PN
);
202 /* Disabling the serial number may affect the cpuid level */
203 c
->cpuid_level
= cpuid_eax(0);
206 static int __init
x86_serial_nr_setup(char *s
)
208 disable_x86_serial_nr
= 0;
211 __setup("serialnumber", x86_serial_nr_setup
);
213 static inline int flag_is_changeable_p(u32 flag
)
217 /* Probe for the CPUID instruction */
218 static inline int have_cpuid_p(void)
222 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86
*c
)
228 * Some CPU features depend on higher CPUID levels, which may not always
229 * be available due to CPUID level capping or broken virtualization
230 * software. Add those features to this table to auto-disable them.
232 struct cpuid_dependent_feature
{
237 static const struct cpuid_dependent_feature __cpuinitconst
238 cpuid_dependent_features
[] = {
239 { X86_FEATURE_MWAIT
, 0x00000005 },
240 { X86_FEATURE_DCA
, 0x00000009 },
241 { X86_FEATURE_XSAVE
, 0x0000000d },
245 static void __cpuinit
filter_cpuid_features(struct cpuinfo_x86
*c
, bool warn
)
247 const struct cpuid_dependent_feature
*df
;
249 for (df
= cpuid_dependent_features
; df
->feature
; df
++) {
251 if (!cpu_has(c
, df
->feature
))
254 * Note: cpuid_level is set to -1 if unavailable, but
255 * extended_extended_level is set to 0 if unavailable
256 * and the legitimate extended levels are all negative
257 * when signed; hence the weird messing around with
260 if (!((s32
)df
->level
< 0 ?
261 (u32
)df
->level
> (u32
)c
->extended_cpuid_level
:
262 (s32
)df
->level
> (s32
)c
->cpuid_level
))
265 clear_cpu_cap(c
, df
->feature
);
270 "CPU: CPU feature %s disabled, no CPUID level 0x%x\n",
271 x86_cap_flags
[df
->feature
], df
->level
);
276 * Naming convention should be: <Name> [(<Codename>)]
277 * This table only is used unless init_<vendor>() below doesn't set it;
278 * in particular, if CPUID levels 0x80000002..4 are supported, this
282 /* Look up CPU names by table lookup. */
283 static const char *__cpuinit
table_lookup_model(struct cpuinfo_x86
*c
)
285 const struct cpu_model_info
*info
;
287 if (c
->x86_model
>= 16)
288 return NULL
; /* Range check */
293 info
= this_cpu
->c_models
;
295 while (info
&& info
->family
) {
296 if (info
->family
== c
->x86
)
297 return info
->model_names
[c
->x86_model
];
300 return NULL
; /* Not found */
303 __u32 cpu_caps_cleared
[NCAPINTS
] __cpuinitdata
;
304 __u32 cpu_caps_set
[NCAPINTS
] __cpuinitdata
;
306 void load_percpu_segment(int cpu
)
309 loadsegment(fs
, __KERNEL_PERCPU
);
312 wrmsrl(MSR_GS_BASE
, (unsigned long)per_cpu(irq_stack_union
.gs_base
, cpu
));
314 load_stack_canary_segment();
318 * Current gdt points %fs at the "master" per-cpu area: after this,
319 * it's on the real one.
321 void switch_to_new_gdt(int cpu
)
323 struct desc_ptr gdt_descr
;
325 gdt_descr
.address
= (long)get_cpu_gdt_table(cpu
);
326 gdt_descr
.size
= GDT_SIZE
- 1;
327 load_gdt(&gdt_descr
);
328 /* Reload the per-cpu base */
330 load_percpu_segment(cpu
);
333 static const struct cpu_dev
*__cpuinitdata cpu_devs
[X86_VENDOR_NUM
] = {};
335 static void __cpuinit
default_init(struct cpuinfo_x86
*c
)
338 display_cacheinfo(c
);
340 /* Not much we can do here... */
341 /* Check if at least it has cpuid */
342 if (c
->cpuid_level
== -1) {
343 /* No cpuid. It must be an ancient CPU */
345 strcpy(c
->x86_model_id
, "486");
346 else if (c
->x86
== 3)
347 strcpy(c
->x86_model_id
, "386");
352 static const struct cpu_dev __cpuinitconst default_cpu
= {
353 .c_init
= default_init
,
354 .c_vendor
= "Unknown",
355 .c_x86_vendor
= X86_VENDOR_UNKNOWN
,
358 static void __cpuinit
get_model_name(struct cpuinfo_x86
*c
)
363 if (c
->extended_cpuid_level
< 0x80000004)
366 v
= (unsigned int *)c
->x86_model_id
;
367 cpuid(0x80000002, &v
[0], &v
[1], &v
[2], &v
[3]);
368 cpuid(0x80000003, &v
[4], &v
[5], &v
[6], &v
[7]);
369 cpuid(0x80000004, &v
[8], &v
[9], &v
[10], &v
[11]);
370 c
->x86_model_id
[48] = 0;
373 * Intel chips right-justify this string for some dumb reason;
374 * undo that brain damage:
376 p
= q
= &c
->x86_model_id
[0];
382 while (q
<= &c
->x86_model_id
[48])
383 *q
++ = '\0'; /* Zero-pad the rest */
387 void __cpuinit
display_cacheinfo(struct cpuinfo_x86
*c
)
389 unsigned int n
, dummy
, ebx
, ecx
, edx
, l2size
;
391 n
= c
->extended_cpuid_level
;
393 if (n
>= 0x80000005) {
394 cpuid(0x80000005, &dummy
, &ebx
, &ecx
, &edx
);
395 printk(KERN_INFO
"CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
396 edx
>>24, edx
&0xFF, ecx
>>24, ecx
&0xFF);
397 c
->x86_cache_size
= (ecx
>>24) + (edx
>>24);
399 /* On K8 L1 TLB is inclusive, so don't count it */
404 if (n
< 0x80000006) /* Some chips just has a large L1. */
407 cpuid(0x80000006, &dummy
, &ebx
, &ecx
, &edx
);
411 c
->x86_tlbsize
+= ((ebx
>> 16) & 0xfff) + (ebx
& 0xfff);
413 /* do processor-specific cache resizing */
414 if (this_cpu
->c_size_cache
)
415 l2size
= this_cpu
->c_size_cache(c
, l2size
);
417 /* Allow user to override all this if necessary. */
418 if (cachesize_override
!= -1)
419 l2size
= cachesize_override
;
422 return; /* Again, no L2 cache is possible */
425 c
->x86_cache_size
= l2size
;
427 printk(KERN_INFO
"CPU: L2 Cache: %dK (%d bytes/line)\n",
431 void __cpuinit
detect_ht(struct cpuinfo_x86
*c
)
434 u32 eax
, ebx
, ecx
, edx
;
435 int index_msb
, core_bits
;
437 if (!cpu_has(c
, X86_FEATURE_HT
))
440 if (cpu_has(c
, X86_FEATURE_CMP_LEGACY
))
443 if (cpu_has(c
, X86_FEATURE_XTOPOLOGY
))
446 cpuid(1, &eax
, &ebx
, &ecx
, &edx
);
448 smp_num_siblings
= (ebx
& 0xff0000) >> 16;
450 if (smp_num_siblings
== 1) {
451 printk(KERN_INFO
"CPU: Hyper-Threading is disabled\n");
455 if (smp_num_siblings
<= 1)
458 if (smp_num_siblings
> nr_cpu_ids
) {
459 pr_warning("CPU: Unsupported number of siblings %d",
461 smp_num_siblings
= 1;
465 index_msb
= get_count_order(smp_num_siblings
);
466 c
->phys_proc_id
= apic
->phys_pkg_id(c
->initial_apicid
, index_msb
);
468 smp_num_siblings
= smp_num_siblings
/ c
->x86_max_cores
;
470 index_msb
= get_count_order(smp_num_siblings
);
472 core_bits
= get_count_order(c
->x86_max_cores
);
474 c
->cpu_core_id
= apic
->phys_pkg_id(c
->initial_apicid
, index_msb
) &
475 ((1 << core_bits
) - 1);
478 if ((c
->x86_max_cores
* smp_num_siblings
) > 1) {
479 printk(KERN_INFO
"CPU: Physical Processor ID: %d\n",
481 printk(KERN_INFO
"CPU: Processor Core ID: %d\n",
487 static void __cpuinit
get_cpu_vendor(struct cpuinfo_x86
*c
)
489 char *v
= c
->x86_vendor_id
;
492 for (i
= 0; i
< X86_VENDOR_NUM
; i
++) {
496 if (!strcmp(v
, cpu_devs
[i
]->c_ident
[0]) ||
497 (cpu_devs
[i
]->c_ident
[1] &&
498 !strcmp(v
, cpu_devs
[i
]->c_ident
[1]))) {
500 this_cpu
= cpu_devs
[i
];
501 c
->x86_vendor
= this_cpu
->c_x86_vendor
;
507 "CPU: vendor_id '%s' unknown, using generic init.\n" \
508 "CPU: Your system may be unstable.\n", v
);
510 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
511 this_cpu
= &default_cpu
;
514 void __cpuinit
cpu_detect(struct cpuinfo_x86
*c
)
516 /* Get vendor name */
517 cpuid(0x00000000, (unsigned int *)&c
->cpuid_level
,
518 (unsigned int *)&c
->x86_vendor_id
[0],
519 (unsigned int *)&c
->x86_vendor_id
[8],
520 (unsigned int *)&c
->x86_vendor_id
[4]);
523 /* Intel-defined flags: level 0x00000001 */
524 if (c
->cpuid_level
>= 0x00000001) {
525 u32 junk
, tfms
, cap0
, misc
;
527 cpuid(0x00000001, &tfms
, &misc
, &junk
, &cap0
);
528 c
->x86
= (tfms
>> 8) & 0xf;
529 c
->x86_model
= (tfms
>> 4) & 0xf;
530 c
->x86_mask
= tfms
& 0xf;
533 c
->x86
+= (tfms
>> 20) & 0xff;
535 c
->x86_model
+= ((tfms
>> 16) & 0xf) << 4;
537 if (cap0
& (1<<19)) {
538 c
->x86_clflush_size
= ((misc
>> 8) & 0xff) * 8;
539 c
->x86_cache_alignment
= c
->x86_clflush_size
;
544 static void __cpuinit
get_cpu_cap(struct cpuinfo_x86
*c
)
549 /* Intel-defined flags: level 0x00000001 */
550 if (c
->cpuid_level
>= 0x00000001) {
551 u32 capability
, excap
;
553 cpuid(0x00000001, &tfms
, &ebx
, &excap
, &capability
);
554 c
->x86_capability
[0] = capability
;
555 c
->x86_capability
[4] = excap
;
558 /* AMD-defined flags: level 0x80000001 */
559 xlvl
= cpuid_eax(0x80000000);
560 c
->extended_cpuid_level
= xlvl
;
562 if ((xlvl
& 0xffff0000) == 0x80000000) {
563 if (xlvl
>= 0x80000001) {
564 c
->x86_capability
[1] = cpuid_edx(0x80000001);
565 c
->x86_capability
[6] = cpuid_ecx(0x80000001);
569 if (c
->extended_cpuid_level
>= 0x80000008) {
570 u32 eax
= cpuid_eax(0x80000008);
572 c
->x86_virt_bits
= (eax
>> 8) & 0xff;
573 c
->x86_phys_bits
= eax
& 0xff;
576 else if (cpu_has(c
, X86_FEATURE_PAE
) || cpu_has(c
, X86_FEATURE_PSE36
))
577 c
->x86_phys_bits
= 36;
580 if (c
->extended_cpuid_level
>= 0x80000007)
581 c
->x86_power
= cpuid_edx(0x80000007);
585 static void __cpuinit
identify_cpu_without_cpuid(struct cpuinfo_x86
*c
)
591 * First of all, decide if this is a 486 or higher
592 * It's a 486 if we can modify the AC flag
594 if (flag_is_changeable_p(X86_EFLAGS_AC
))
599 for (i
= 0; i
< X86_VENDOR_NUM
; i
++)
600 if (cpu_devs
[i
] && cpu_devs
[i
]->c_identify
) {
601 c
->x86_vendor_id
[0] = 0;
602 cpu_devs
[i
]->c_identify(c
);
603 if (c
->x86_vendor_id
[0]) {
612 * Do minimum CPU detection early.
613 * Fields really needed: vendor, cpuid_level, family, model, mask,
615 * The others are not touched to avoid unwanted side effects.
617 * WARNING: this function is only called on the BP. Don't add code here
618 * that is supposed to run on all CPUs.
620 static void __init
early_identify_cpu(struct cpuinfo_x86
*c
)
623 c
->x86_clflush_size
= 64;
624 c
->x86_phys_bits
= 36;
625 c
->x86_virt_bits
= 48;
627 c
->x86_clflush_size
= 32;
628 c
->x86_phys_bits
= 32;
629 c
->x86_virt_bits
= 32;
631 c
->x86_cache_alignment
= c
->x86_clflush_size
;
633 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
634 c
->extended_cpuid_level
= 0;
637 identify_cpu_without_cpuid(c
);
639 /* cyrix could have cpuid enabled via c_identify()*/
649 if (this_cpu
->c_early_init
)
650 this_cpu
->c_early_init(c
);
653 c
->cpu_index
= boot_cpu_id
;
655 filter_cpuid_features(c
, false);
658 void __init
early_cpu_init(void)
660 const struct cpu_dev
*const *cdev
;
663 printk(KERN_INFO
"KERNEL supported cpus:\n");
664 for (cdev
= __x86_cpu_dev_start
; cdev
< __x86_cpu_dev_end
; cdev
++) {
665 const struct cpu_dev
*cpudev
= *cdev
;
668 if (count
>= X86_VENDOR_NUM
)
670 cpu_devs
[count
] = cpudev
;
673 for (j
= 0; j
< 2; j
++) {
674 if (!cpudev
->c_ident
[j
])
676 printk(KERN_INFO
" %s %s\n", cpudev
->c_vendor
,
681 early_identify_cpu(&boot_cpu_data
);
685 * The NOPL instruction is supposed to exist on all CPUs with
686 * family >= 6; unfortunately, that's not true in practice because
687 * of early VIA chips and (more importantly) broken virtualizers that
688 * are not easy to detect. In the latter case it doesn't even *fail*
689 * reliably, so probing for it doesn't even work. Disable it completely
690 * unless we can find a reliable way to detect all the broken cases.
692 static void __cpuinit
detect_nopl(struct cpuinfo_x86
*c
)
694 clear_cpu_cap(c
, X86_FEATURE_NOPL
);
697 static void __cpuinit
generic_identify(struct cpuinfo_x86
*c
)
699 c
->extended_cpuid_level
= 0;
702 identify_cpu_without_cpuid(c
);
704 /* cyrix could have cpuid enabled via c_identify()*/
714 if (c
->cpuid_level
>= 0x00000001) {
715 c
->initial_apicid
= (cpuid_ebx(1) >> 24) & 0xFF;
717 # ifdef CONFIG_X86_HT
718 c
->apicid
= apic
->phys_pkg_id(c
->initial_apicid
, 0);
720 c
->apicid
= c
->initial_apicid
;
725 c
->phys_proc_id
= c
->initial_apicid
;
729 get_model_name(c
); /* Default name */
731 init_scattered_cpuid_features(c
);
736 * This does the hard work of actually picking apart the CPU stuff...
738 static void __cpuinit
identify_cpu(struct cpuinfo_x86
*c
)
742 c
->loops_per_jiffy
= loops_per_jiffy
;
743 c
->x86_cache_size
= -1;
744 c
->x86_vendor
= X86_VENDOR_UNKNOWN
;
745 c
->x86_model
= c
->x86_mask
= 0; /* So far unknown... */
746 c
->x86_vendor_id
[0] = '\0'; /* Unset */
747 c
->x86_model_id
[0] = '\0'; /* Unset */
748 c
->x86_max_cores
= 1;
749 c
->x86_coreid_bits
= 0;
751 c
->x86_clflush_size
= 64;
752 c
->x86_phys_bits
= 36;
753 c
->x86_virt_bits
= 48;
755 c
->cpuid_level
= -1; /* CPUID not detected */
756 c
->x86_clflush_size
= 32;
757 c
->x86_phys_bits
= 32;
758 c
->x86_virt_bits
= 32;
760 c
->x86_cache_alignment
= c
->x86_clflush_size
;
761 memset(&c
->x86_capability
, 0, sizeof c
->x86_capability
);
765 if (this_cpu
->c_identify
)
766 this_cpu
->c_identify(c
);
768 /* Clear/Set all flags overriden by options, after probe */
769 for (i
= 0; i
< NCAPINTS
; i
++) {
770 c
->x86_capability
[i
] &= ~cpu_caps_cleared
[i
];
771 c
->x86_capability
[i
] |= cpu_caps_set
[i
];
775 c
->apicid
= apic
->phys_pkg_id(c
->initial_apicid
, 0);
779 * Vendor-specific initialization. In this section we
780 * canonicalize the feature flags, meaning if there are
781 * features a certain CPU supports which CPUID doesn't
782 * tell us, CPUID claiming incorrect flags, or other bugs,
783 * we handle them here.
785 * At the end of this section, c->x86_capability better
786 * indicate the features this CPU genuinely supports!
788 if (this_cpu
->c_init
)
791 /* Disable the PN if appropriate */
792 squash_the_stupid_serial_number(c
);
795 * The vendor-specific functions might have changed features.
796 * Now we do "generic changes."
799 /* Filter out anything that depends on CPUID levels we don't have */
800 filter_cpuid_features(c
, true);
802 /* If the model name is still unset, do table lookup. */
803 if (!c
->x86_model_id
[0]) {
805 p
= table_lookup_model(c
);
807 strcpy(c
->x86_model_id
, p
);
810 sprintf(c
->x86_model_id
, "%02x/%02x",
811 c
->x86
, c
->x86_model
);
821 * Clear/Set all flags overriden by options, need do it
822 * before following smp all cpus cap AND.
824 for (i
= 0; i
< NCAPINTS
; i
++) {
825 c
->x86_capability
[i
] &= ~cpu_caps_cleared
[i
];
826 c
->x86_capability
[i
] |= cpu_caps_set
[i
];
830 * On SMP, boot_cpu_data holds the common feature set between
831 * all CPUs; so make sure that we indicate which features are
832 * common between the CPUs. The first time this routine gets
833 * executed, c == &boot_cpu_data.
835 if (c
!= &boot_cpu_data
) {
836 /* AND the already accumulated flags with these */
837 for (i
= 0; i
< NCAPINTS
; i
++)
838 boot_cpu_data
.x86_capability
[i
] &= c
->x86_capability
[i
];
841 #ifdef CONFIG_X86_MCE
842 /* Init Machine Check Exception if available. */
846 select_idle_routine(c
);
848 #if defined(CONFIG_NUMA) && defined(CONFIG_X86_64)
849 numa_add_cpu(smp_processor_id());
854 static void vgetcpu_set_mode(void)
856 if (cpu_has(&boot_cpu_data
, X86_FEATURE_RDTSCP
))
857 vgetcpu_mode
= VGETCPU_RDTSCP
;
859 vgetcpu_mode
= VGETCPU_LSL
;
863 void __init
identify_boot_cpu(void)
865 identify_cpu(&boot_cpu_data
);
873 init_hw_perf_counters();
876 void __cpuinit
identify_secondary_cpu(struct cpuinfo_x86
*c
)
878 BUG_ON(c
== &boot_cpu_data
);
891 static const struct msr_range msr_range_array
[] __cpuinitconst
= {
892 { 0x00000000, 0x00000418},
893 { 0xc0000000, 0xc000040b},
894 { 0xc0010000, 0xc0010142},
895 { 0xc0011000, 0xc001103b},
898 static void __cpuinit
print_cpu_msr(void)
900 unsigned index_min
, index_max
;
905 for (i
= 0; i
< ARRAY_SIZE(msr_range_array
); i
++) {
906 index_min
= msr_range_array
[i
].min
;
907 index_max
= msr_range_array
[i
].max
;
909 for (index
= index_min
; index
< index_max
; index
++) {
910 if (rdmsrl_amd_safe(index
, &val
))
912 printk(KERN_INFO
" MSR%08x: %016llx\n", index
, val
);
917 static int show_msr __cpuinitdata
;
919 static __init
int setup_show_msr(char *arg
)
923 get_option(&arg
, &num
);
929 __setup("show_msr=", setup_show_msr
);
931 static __init
int setup_noclflush(char *arg
)
933 setup_clear_cpu_cap(X86_FEATURE_CLFLSH
);
936 __setup("noclflush", setup_noclflush
);
938 void __cpuinit
print_cpu_info(struct cpuinfo_x86
*c
)
940 const char *vendor
= NULL
;
942 if (c
->x86_vendor
< X86_VENDOR_NUM
) {
943 vendor
= this_cpu
->c_vendor
;
945 if (c
->cpuid_level
>= 0)
946 vendor
= c
->x86_vendor_id
;
949 if (vendor
&& !strstr(c
->x86_model_id
, vendor
))
950 printk(KERN_CONT
"%s ", vendor
);
952 if (c
->x86_model_id
[0])
953 printk(KERN_CONT
"%s", c
->x86_model_id
);
955 printk(KERN_CONT
"%d86", c
->x86
);
957 if (c
->x86_mask
|| c
->cpuid_level
>= 0)
958 printk(KERN_CONT
" stepping %02x\n", c
->x86_mask
);
960 printk(KERN_CONT
"\n");
963 if (c
->cpu_index
< show_msr
)
971 static __init
int setup_disablecpuid(char *arg
)
975 if (get_option(&arg
, &bit
) && bit
< NCAPINTS
*32)
976 setup_clear_cpu_cap(bit
);
982 __setup("clearcpuid=", setup_disablecpuid
);
985 struct desc_ptr idt_descr
= { 256 * 16 - 1, (unsigned long) idt_table
};
987 DEFINE_PER_CPU_FIRST(union irq_stack_union
,
988 irq_stack_union
) __aligned(PAGE_SIZE
);
990 DEFINE_PER_CPU(char *, irq_stack_ptr
) =
991 init_per_cpu_var(irq_stack_union
.irq_stack
) + IRQ_STACK_SIZE
- 64;
993 DEFINE_PER_CPU(unsigned long, kernel_stack
) =
994 (unsigned long)&init_thread_union
- KERNEL_STACK_OFFSET
+ THREAD_SIZE
;
995 EXPORT_PER_CPU_SYMBOL(kernel_stack
);
997 DEFINE_PER_CPU(unsigned int, irq_count
) = -1;
1000 * Special IST stacks which the CPU switches to when it calls
1001 * an IST-marked descriptor entry. Up to 7 stacks (hardware
1002 * limit), all of them are 4K, except the debug stack which
1005 static const unsigned int exception_stack_sizes
[N_EXCEPTION_STACKS
] = {
1006 [0 ... N_EXCEPTION_STACKS
- 1] = EXCEPTION_STKSZ
,
1007 [DEBUG_STACK
- 1] = DEBUG_STKSZ
1010 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
1011 [(N_EXCEPTION_STACKS
- 1) * EXCEPTION_STKSZ
+ DEBUG_STKSZ
])
1012 __aligned(PAGE_SIZE
);
1014 /* May not be marked __init: used by software suspend */
1015 void syscall_init(void)
1018 * LSTAR and STAR live in a bit strange symbiosis.
1019 * They both write to the same internal register. STAR allows to
1020 * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
1022 wrmsrl(MSR_STAR
, ((u64
)__USER32_CS
)<<48 | ((u64
)__KERNEL_CS
)<<32);
1023 wrmsrl(MSR_LSTAR
, system_call
);
1024 wrmsrl(MSR_CSTAR
, ignore_sysret
);
1026 #ifdef CONFIG_IA32_EMULATION
1027 syscall32_cpu_init();
1030 /* Flags to clear on syscall */
1031 wrmsrl(MSR_SYSCALL_MASK
,
1032 X86_EFLAGS_TF
|X86_EFLAGS_DF
|X86_EFLAGS_IF
|X86_EFLAGS_IOPL
);
1035 unsigned long kernel_eflags
;
1038 * Copies of the original ist values from the tss are only accessed during
1039 * debugging, no special alignment required.
1041 DEFINE_PER_CPU(struct orig_ist
, orig_ist
);
1043 #else /* CONFIG_X86_64 */
1045 #ifdef CONFIG_CC_STACKPROTECTOR
1046 DEFINE_PER_CPU(unsigned long, stack_canary
);
1049 /* Make sure %fs and %gs are initialized properly in idle threads */
1050 struct pt_regs
* __cpuinit
idle_regs(struct pt_regs
*regs
)
1052 memset(regs
, 0, sizeof(struct pt_regs
));
1053 regs
->fs
= __KERNEL_PERCPU
;
1054 regs
->gs
= __KERNEL_STACK_CANARY
;
1058 #endif /* CONFIG_X86_64 */
1061 * Clear all 6 debug registers:
1063 static void clear_all_debug_regs(void)
1067 for (i
= 0; i
< 8; i
++) {
1068 /* Ignore db4, db5 */
1069 if ((i
== 4) || (i
== 5))
1077 * cpu_init() initializes state that is per-CPU. Some data is already
1078 * initialized (naturally) in the bootstrap process, such as the GDT
1079 * and IDT. We reload them nevertheless, this function acts as a
1080 * 'CPU state barrier', nothing should get across.
1081 * A lot of state is already set up in PDA init for 64 bit
1083 #ifdef CONFIG_X86_64
1085 void __cpuinit
cpu_init(void)
1087 struct orig_ist
*orig_ist
;
1088 struct task_struct
*me
;
1089 struct tss_struct
*t
;
1094 cpu
= stack_smp_processor_id();
1095 t
= &per_cpu(init_tss
, cpu
);
1096 orig_ist
= &per_cpu(orig_ist
, cpu
);
1099 if (cpu
!= 0 && percpu_read(node_number
) == 0 &&
1100 cpu_to_node(cpu
) != NUMA_NO_NODE
)
1101 percpu_write(node_number
, cpu_to_node(cpu
));
1106 if (cpumask_test_and_set_cpu(cpu
, cpu_initialized_mask
))
1107 panic("CPU#%d already initialized!\n", cpu
);
1109 printk(KERN_INFO
"Initializing CPU#%d\n", cpu
);
1111 clear_in_cr4(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
1114 * Initialize the per-CPU GDT with the boot GDT,
1115 * and set up the GDT descriptor:
1118 switch_to_new_gdt(cpu
);
1121 load_idt((const struct desc_ptr
*)&idt_descr
);
1123 memset(me
->thread
.tls_array
, 0, GDT_ENTRY_TLS_ENTRIES
* 8);
1126 wrmsrl(MSR_FS_BASE
, 0);
1127 wrmsrl(MSR_KERNEL_GS_BASE
, 0);
1135 * set up and load the per-CPU TSS
1137 if (!orig_ist
->ist
[0]) {
1138 char *estacks
= per_cpu(exception_stacks
, cpu
);
1140 for (v
= 0; v
< N_EXCEPTION_STACKS
; v
++) {
1141 estacks
+= exception_stack_sizes
[v
];
1142 orig_ist
->ist
[v
] = t
->x86_tss
.ist
[v
] =
1143 (unsigned long)estacks
;
1147 t
->x86_tss
.io_bitmap_base
= offsetof(struct tss_struct
, io_bitmap
);
1150 * <= is required because the CPU will access up to
1151 * 8 bits beyond the end of the IO permission bitmap.
1153 for (i
= 0; i
<= IO_BITMAP_LONGS
; i
++)
1154 t
->io_bitmap
[i
] = ~0UL;
1156 atomic_inc(&init_mm
.mm_count
);
1157 me
->active_mm
= &init_mm
;
1159 enter_lazy_tlb(&init_mm
, me
);
1161 load_sp0(t
, ¤t
->thread
);
1162 set_tss_desc(cpu
, t
);
1164 load_LDT(&init_mm
.context
);
1168 * If the kgdb is connected no debug regs should be altered. This
1169 * is only applicable when KGDB and a KGDB I/O module are built
1170 * into the kernel and you are using early debugging with
1171 * kgdbwait. KGDB will control the kernel HW breakpoint registers.
1173 if (kgdb_connected
&& arch_kgdb_ops
.correct_hw_break
)
1174 arch_kgdb_ops
.correct_hw_break();
1177 clear_all_debug_regs();
1181 raw_local_save_flags(kernel_eflags
);
1189 void __cpuinit
cpu_init(void)
1191 int cpu
= smp_processor_id();
1192 struct task_struct
*curr
= current
;
1193 struct tss_struct
*t
= &per_cpu(init_tss
, cpu
);
1194 struct thread_struct
*thread
= &curr
->thread
;
1196 if (cpumask_test_and_set_cpu(cpu
, cpu_initialized_mask
)) {
1197 printk(KERN_WARNING
"CPU#%d already initialized!\n", cpu
);
1202 printk(KERN_INFO
"Initializing CPU#%d\n", cpu
);
1204 if (cpu_has_vme
|| cpu_has_tsc
|| cpu_has_de
)
1205 clear_in_cr4(X86_CR4_VME
|X86_CR4_PVI
|X86_CR4_TSD
|X86_CR4_DE
);
1207 load_idt(&idt_descr
);
1208 switch_to_new_gdt(cpu
);
1211 * Set up and load the per-CPU TSS and LDT
1213 atomic_inc(&init_mm
.mm_count
);
1214 curr
->active_mm
= &init_mm
;
1216 enter_lazy_tlb(&init_mm
, curr
);
1218 load_sp0(t
, thread
);
1219 set_tss_desc(cpu
, t
);
1221 load_LDT(&init_mm
.context
);
1223 t
->x86_tss
.io_bitmap_base
= offsetof(struct tss_struct
, io_bitmap
);
1225 #ifdef CONFIG_DOUBLEFAULT
1226 /* Set up doublefault TSS pointer in the GDT */
1227 __set_tss_desc(cpu
, GDT_ENTRY_DOUBLEFAULT_TSS
, &doublefault_tss
);
1230 clear_all_debug_regs();
1233 * Force FPU initialization:
1236 current_thread_info()->status
= TS_XSAVE
;
1238 current_thread_info()->status
= 0;
1240 mxcsr_feature_mask_init();
1243 * Boot processor to setup the FP and extended state context info.
1245 if (smp_processor_id() == boot_cpu_id
)
1246 init_thread_xstate();