arch/ppc/syslib/m8xx_setup.c

   1 /*
   2  *  Copyright (C) 1995  Linus Torvalds
   3  *  Adapted from 'alpha' version by Gary Thomas
   4  *  Modified by Cort Dougan (cort@cs.nmt.edu)
   5  *  Modified for MBX using prep/chrp/pmac functions by Dan (dmalek@jlc.net)
   6  *  Further modified for generic 8xx by Dan.
   7  */
   8
   9 /*
  10  * bootup setup stuff..
  11  */
  12
  13 #include <linux/errno.h>
  14 #include <linux/sched.h>
  15 #include <linux/kernel.h>
  16 #include <linux/mm.h>
  17 #include <linux/stddef.h>
  18 #include <linux/unistd.h>
  19 #include <linux/ptrace.h>
  20 #include <linux/slab.h>
  21 #include <linux/user.h>
  22 #include <linux/a.out.h>
  23 #include <linux/tty.h>
  24 #include <linux/major.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/reboot.h>
  27 #include <linux/init.h>
  28 #include <linux/initrd.h>
  29 #include <linux/ioport.h>
  30 #include <linux/bootmem.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/root_dev.h>
  33
  34 #if defined(CONFIG_MTD) && defined(CONFIG_MTD_PHYSMAP)
  35 #include <linux/mtd/partitions.h>
  36 #include <linux/mtd/physmap.h>
  37 #include <linux/mtd/mtd.h>
  38 #include <linux/mtd/map.h>
  39 #endif
  40
  41 #include <asm/mmu.h>
  42 #include <asm/reg.h>
  43 #include <asm/residual.h>
  44 #include <asm/io.h>
  45 #include <asm/pgtable.h>
  46 #include <asm/mpc8xx.h>
  47 #include <asm/8xx_immap.h>
  48 #include <asm/machdep.h>
  49 #include <asm/bootinfo.h>
  50 #include <asm/time.h>
  51 #include <asm/xmon.h>
  52 #include <asm/ppc_sys.h>
  53
  54 #include "ppc8xx_pic.h"
  55
  56 #ifdef CONFIG_MTD_PHYSMAP
  57 #define MPC8xxADS_BANK_WIDTH 4
  58 #endif
  59
  60 #define MPC8xxADS_U_BOOT_SIZE          0x80000
  61 #define MPC8xxADS_FREE_AREA_OFFSET     MPC8xxADS_U_BOOT_SIZE
  62
  63 #if defined(CONFIG_MTD_PARTITIONS)
  64  /*
  65    NOTE: bank width and interleave relative to the installed flash
  66    should have been chosen within MTD_CFI_GEOMETRY options.
  67  */
  68 static struct mtd_partition mpc8xxads_partitions[] = {
  69         {
  70                 .name = "bootloader",
  71                 .size = MPC8xxADS_U_BOOT_SIZE,
  72                 .offset = 0,
  73                 .mask_flags   = MTD_WRITEABLE,  /* force read-only */
  74         }, {
  75                 .name = "User FS",
  76                 .offset = MPC8xxADS_FREE_AREA_OFFSET
  77         }
  78 };
  79
  80 #define mpc8xxads_part_num ARRAY_SIZE(mpc8xxads_partitions)
  81
  82 #endif
  83
  84 static int m8xx_set_rtc_time(unsigned long time);
  85 static unsigned long m8xx_get_rtc_time(void);
  86 void m8xx_calibrate_decr(void);
  87
  88 unsigned char __res[sizeof(bd_t)];
  89
  90 extern unsigned long find_available_memory(void);
  91 extern void m8xx_cpm_reset(void);
  92 extern void m8xx_wdt_handler_install(bd_t *bp);
  93 extern void rpxfb_alloc_pages(void);
  94 extern void cpm_interrupt_init(void);
  95
  96 void __attribute__ ((weak))
  97 board_init(void)
  98 {
  99 }
 100
 101 void __init
 102 m8xx_setup_arch(void)
 103 {
 104 #if defined(CONFIG_MTD) && defined(CONFIG_MTD_PHYSMAP)
 105         bd_t *binfo = (bd_t *)__res;
 106 #endif
 107
 108         /* Reset the Communication Processor Module.
 109         */
 110         m8xx_cpm_reset();
 111
 112 #ifdef CONFIG_FB_RPX
 113         rpxfb_alloc_pages();
 114 #endif
 115
 116 #ifdef notdef
 117         ROOT_DEV = Root_HDA1; /* hda1 */
 118 #endif
 119
 120 #ifdef CONFIG_BLK_DEV_INITRD
 121 #if 0
 122         ROOT_DEV = Root_FD0; /* floppy */
 123         rd_prompt = 1;
 124         rd_doload = 1;
 125         rd_image_start = 0;
 126 #endif
 127 #if 0   /* XXX this may need to be updated for the new bootmem stuff,
 128            or possibly just deleted (see set_phys_avail() in init.c).
 129            - paulus. */
 130         /* initrd_start and size are setup by boot/head.S and kernel/head.S */
 131         if ( initrd_start )
 132         {
 133                 if (initrd_end > *memory_end_p)
 134                 {
 135                         printk("initrd extends beyond end of memory "
 136                                "(0x%08lx > 0x%08lx)\ndisabling initrd\n",
 137                                initrd_end,*memory_end_p);
 138                         initrd_start = 0;
 139                 }
 140         }
 141 #endif
 142 #endif
 143
 144         board_init();
 145 }
 146
 147 void
 148 abort(void)
 149 {
 150 #ifdef CONFIG_XMON
 151         xmon(0);
 152 #endif
 153         machine_restart(NULL);
 154
 155         /* not reached */
 156         for (;;);
 157 }
 158
 159 /* A place holder for time base interrupts, if they are ever enabled. */
 160 irqreturn_t timebase_interrupt(int irq, void * dev)
 161 {
 162         printk ("timebase_interrupt()\n");
 163
 164         return IRQ_HANDLED;
 165 }
 166
 167 static struct irqaction tbint_irqaction = {
 168         .handler = timebase_interrupt,
 169         .mask = CPU_MASK_NONE,
 170         .name = "tbint",
 171 };
 172
 173 /* per-board overridable init_internal_rtc() function. */
 174 void __init __attribute__ ((weak))
 175 init_internal_rtc(void)
 176 {
 177         /* Disable the RTC one second and alarm interrupts. */
 178         clrbits16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc, (RTCSC_SIE | RTCSC_ALE));
 179
 180         /* Enable the RTC */
 181         setbits16(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtcsc, (RTCSC_RTF | RTCSC_RTE));
 182
 183 }
 184
 185 /* The decrementer counts at the system (internal) clock frequency divided by
 186  * sixteen, or external oscillator divided by four.  We force the processor
 187  * to use system clock divided by sixteen.
 188  */
 189 void __init m8xx_calibrate_decr(void)
 190 {
 191         bd_t    *binfo = (bd_t *)__res;
 192         int freq, fp, divisor;
 193
 194         /* Unlock the SCCR. */
 195         out_be32(&((immap_t *)IMAP_ADDR)->im_clkrstk.cark_sccrk, ~KAPWR_KEY);
 196         out_be32(&((immap_t *)IMAP_ADDR)->im_clkrstk.cark_sccrk, KAPWR_KEY);
 197
 198         /* Force all 8xx processors to use divide by 16 processor clock. */
 199         setbits32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_sccr, 0x02000000);
 200         /* Processor frequency is MHz.
 201          * The value 'fp' is the number of decrementer ticks per second.
 202          */
 203         fp = binfo->bi_intfreq / 16;
 204         freq = fp*60;   /* try to make freq/1e6 an integer */
 205         divisor = 60;
 206         printk("Decrementer Frequency = %d/%d\n", freq, divisor);
 207         tb_ticks_per_jiffy = freq / HZ / divisor;
 208         tb_to_us = mulhwu_scale_factor(freq / divisor, 1000000);
 209
 210         /* Perform some more timer/timebase initialization.  This used
 211          * to be done elsewhere, but other changes caused it to get
 212          * called more than once....that is a bad thing.
 213          *
 214          * First, unlock all of the registers we are going to modify.
 215          * To protect them from corruption during power down, registers
 216          * that are maintained by keep alive power are "locked".  To
 217          * modify these registers we have to write the key value to
 218          * the key location associated with the register.
 219          * Some boards power up with these unlocked, while others
 220          * are locked.  Writing anything (including the unlock code?)
 221          * to the unlocked registers will lock them again.  So, here
 222          * we guarantee the registers are locked, then we unlock them
 223          * for our use.
 224          */
 225         out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_tbscrk, ~KAPWR_KEY);
 226         out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_rtcsck, ~KAPWR_KEY);
 227         out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_tbk, ~KAPWR_KEY);
 228         out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_tbscrk, KAPWR_KEY);
 229         out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_rtcsck, KAPWR_KEY);
 230         out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_tbk, KAPWR_KEY);
 231
 232         init_internal_rtc();
 233
 234         /* Enabling the decrementer also enables the timebase interrupts
 235          * (or from the other point of view, to get decrementer interrupts
 236          * we have to enable the timebase).  The decrementer interrupt
 237          * is wired into the vector table, nothing to do here for that.
 238          */
 239         out_be16(&((immap_t *)IMAP_ADDR)->im_sit.sit_tbscr, (mk_int_int_mask(DEC_INTERRUPT) << 8) | (TBSCR_TBF | TBSCR_TBE));
 240
 241         if (setup_irq(DEC_INTERRUPT, &tbint_irqaction))
 242                 panic("Could not allocate timer IRQ!");
 243
 244 #ifdef CONFIG_8xx_WDT
 245         /* Install watchdog timer handler early because it might be
 246          * already enabled by the bootloader
 247          */
 248         m8xx_wdt_handler_install(binfo);
 249 #endif
 250 }
 251
 252 /* The RTC on the MPC8xx is an internal register.
 253  * We want to protect this during power down, so we need to unlock,
 254  * modify, and re-lock.
 255  */
 256 static int
 257 m8xx_set_rtc_time(unsigned long time)
 258 {
 259         out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_rtck, KAPWR_KEY);
 260         out_be32(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtc, time);
 261         out_be32(&((immap_t *)IMAP_ADDR)->im_sitk.sitk_rtck, ~KAPWR_KEY);
 262         return(0);
 263 }
 264
 265 static unsigned long
 266 m8xx_get_rtc_time(void)
 267 {
 268         /* Get time from the RTC. */
 269         return (unsigned long) in_be32(&((immap_t *)IMAP_ADDR)->im_sit.sit_rtc);
 270 }
 271
 272 static void
 273 m8xx_restart(char *cmd)
 274 {
 275         __volatile__ unsigned char dummy;
 276
 277         local_irq_disable();
 278
 279         setbits32(&((immap_t *)IMAP_ADDR)->im_clkrst.car_plprcr, 0x00000080);
 280         /* Clear the ME bit in MSR to cause checkstop on machine check
 281         */
 282         mtmsr(mfmsr() & ~0x1000);
 283
 284         dummy = in_8(&((immap_t *)IMAP_ADDR)->im_clkrst.res[0]);
 285         printk("Restart failed\n");
 286         while(1);
 287 }
 288
 289 static void
 290 m8xx_power_off(void)
 291 {
 292    m8xx_restart(NULL);
 293 }
 294
 295 static void
 296 m8xx_halt(void)
 297 {
 298    m8xx_restart(NULL);
 299 }
 300
 301
 302 static int
 303 m8xx_show_percpuinfo(struct seq_file *m, int i)
 304 {
 305         bd_t    *bp;
 306
 307         bp = (bd_t *)__res;
 308
 309         seq_printf(m, "clock\t\t: %uMHz\n"
 310                    "bus clock\t: %uMHz\n",
 311                    bp->bi_intfreq / 1000000,
 312                    bp->bi_busfreq / 1000000);
 313
 314         return 0;
 315 }
 316
 317 #ifdef CONFIG_PCI
 318 static struct irqaction mbx_i8259_irqaction = {
 319         .handler = mbx_i8259_action,
 320         .mask = CPU_MASK_NONE,
 321         .name = "i8259 cascade",
 322 };
 323 #endif
 324
 325 /* Initialize the internal interrupt controller.  The number of
 326  * interrupts supported can vary with the processor type, and the
 327  * 82xx family can have up to 64.
 328  * External interrupts can be either edge or level triggered, and
 329  * need to be initialized by the appropriate driver.
 330  */
 331 static void __init
 332 m8xx_init_IRQ(void)
 333 {
 334         int i;
 335
 336         for (i = SIU_IRQ_OFFSET ; i < SIU_IRQ_OFFSET + NR_SIU_INTS ; i++)
 337                 irq_desc[i].chip = &ppc8xx_pic;
 338
 339         cpm_interrupt_init();
 340
 341 #if defined(CONFIG_PCI)
 342         for (i = I8259_IRQ_OFFSET ; i < I8259_IRQ_OFFSET + NR_8259_INTS ; i++)
 343                 irq_desc[i].chip = &i8259_pic;
 344
 345         i8259_pic_irq_offset = I8259_IRQ_OFFSET;
 346         i8259_init(0);
 347
 348         /* The i8259 cascade interrupt must be level sensitive. */
 349
 350         clrbits32(&((immap_t *)IMAP_ADDR)->im_siu_conf.sc_siel, (0x80000000 >> ISA_BRIDGE_INT));
 351         if (setup_irq(ISA_BRIDGE_INT, &mbx_i8259_irqaction))
 352                 enable_irq(ISA_BRIDGE_INT);
 353 #endif  /* CONFIG_PCI */
 354 }
 355
 356 /* -------------------------------------------------------------------- */
 357
 358 /*
 359  * This is a big hack right now, but it may turn into something real
 360  * someday.
 361  *
 362  * For the 8xx boards (at this time anyway), there is nothing to initialize
 363  * associated the PROM.  Rather than include all of the prom.c
 364  * functions in the image just to get prom_init, all we really need right
 365  * now is the initialization of the physical memory region.
 366  */
 367 static unsigned long __init
 368 m8xx_find_end_of_memory(void)
 369 {
 370         bd_t    *binfo;
 371         extern unsigned char __res[];
 372
 373         binfo = (bd_t *)__res;
 374
 375         return binfo->bi_memsize;
 376 }
 377
 378 /*
 379  * Now map in some of the I/O space that is generically needed
 380  * or shared with multiple devices.
 381  * All of this fits into the same 4Mbyte region, so it only
 382  * requires one page table page.  (or at least it used to  -- paulus)
 383  */
 384 static void __init
 385 m8xx_map_io(void)
 386 {
 387         io_block_mapping(IMAP_ADDR, IMAP_ADDR, IMAP_SIZE, _PAGE_IO);
 388 #ifdef CONFIG_MBX
 389         io_block_mapping(NVRAM_ADDR, NVRAM_ADDR, NVRAM_SIZE, _PAGE_IO);
 390         io_block_mapping(MBX_CSR_ADDR, MBX_CSR_ADDR, MBX_CSR_SIZE, _PAGE_IO);
 391         io_block_mapping(PCI_CSR_ADDR, PCI_CSR_ADDR, PCI_CSR_SIZE, _PAGE_IO);
 392
 393         /* Map some of the PCI/ISA I/O space to get the IDE interface.
 394         */
 395         io_block_mapping(PCI_ISA_IO_ADDR, PCI_ISA_IO_ADDR, 0x4000, _PAGE_IO);
 396         io_block_mapping(PCI_IDE_ADDR, PCI_IDE_ADDR, 0x4000, _PAGE_IO);
 397 #endif
 398 #if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC)
 399         io_block_mapping(RPX_CSR_ADDR, RPX_CSR_ADDR, RPX_CSR_SIZE, _PAGE_IO);
 400 #if !defined(CONFIG_PCI)
 401         io_block_mapping(_IO_BASE,_IO_BASE,_IO_BASE_SIZE, _PAGE_IO);
 402 #endif
 403 #endif
 404 #if defined(CONFIG_RPXTOUCH) || defined(CONFIG_FB_RPX)
 405         io_block_mapping(HIOX_CSR_ADDR, HIOX_CSR_ADDR, HIOX_CSR_SIZE, _PAGE_IO);
 406 #endif
 407 #ifdef CONFIG_FADS
 408         io_block_mapping(BCSR_ADDR, BCSR_ADDR, BCSR_SIZE, _PAGE_IO);
 409 #endif
 410 #ifdef CONFIG_PCI
 411         io_block_mapping(PCI_CSR_ADDR, PCI_CSR_ADDR, PCI_CSR_SIZE, _PAGE_IO);
 412 #endif
 413 #if defined(CONFIG_NETTA)
 414         io_block_mapping(_IO_BASE,_IO_BASE,_IO_BASE_SIZE, _PAGE_IO);
 415 #endif
 416 }
 417
 418 void __init
 419 platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 420                 unsigned long r6, unsigned long r7)
 421 {
 422         parse_bootinfo(find_bootinfo());
 423
 424         if ( r3 )
 425                 memcpy( (void *)__res,(void *)(r3+KERNELBASE), sizeof(bd_t) );
 426
 427 #ifdef CONFIG_PCI
 428         m8xx_setup_pci_ptrs();
 429 #endif
 430
 431 #ifdef CONFIG_BLK_DEV_INITRD
 432         /* take care of initrd if we have one */
 433         if ( r4 )
 434         {
 435                 initrd_start = r4 + KERNELBASE;
 436                 initrd_end = r5 + KERNELBASE;
 437         }
 438 #endif /* CONFIG_BLK_DEV_INITRD */
 439         /* take care of cmd line */
 440         if ( r6 )
 441         {
 442                 *(char *)(r7+KERNELBASE) = 0;
 443                 strcpy(cmd_line, (char *)(r6+KERNELBASE));
 444         }
 445
 446         identify_ppc_sys_by_name(BOARD_CHIP_NAME);
 447
 448         ppc_md.setup_arch               = m8xx_setup_arch;
 449         ppc_md.show_percpuinfo          = m8xx_show_percpuinfo;
 450         ppc_md.init_IRQ                 = m8xx_init_IRQ;
 451         ppc_md.get_irq                  = m8xx_get_irq;
 452         ppc_md.init                     = NULL;
 453
 454         ppc_md.restart                  = m8xx_restart;
 455         ppc_md.power_off                = m8xx_power_off;
 456         ppc_md.halt                     = m8xx_halt;
 457
 458         ppc_md.time_init                = NULL;
 459         ppc_md.set_rtc_time             = m8xx_set_rtc_time;
 460         ppc_md.get_rtc_time             = m8xx_get_rtc_time;
 461         ppc_md.calibrate_decr           = m8xx_calibrate_decr;
 462
 463         ppc_md.find_end_of_memory       = m8xx_find_end_of_memory;
 464         ppc_md.setup_io_mappings        = m8xx_map_io;
 465 }