?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
brd: limit 'max_part' module param to DISK_MAX_PARTS
[linux-2.6/linux-acpi-2.6/ibm-acpi-2.6.git] / drivers / ata / ahci.c
blob54c096b1a71cb0f4c2c38de1298809e1efbc40f7
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
49 #include "ahci.h"
50
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
53
54 enum {
55 AHCI_PCI_BAR = 5,
56 };
57
58 enum board_ids {
59 /* board IDs by feature in alphabetical order */
60 board_ahci,
61 board_ahci_ign_iferr,
62 board_ahci_nosntf,
63 board_ahci_yes_fbs,
64
65 /* board IDs for specific chipsets in alphabetical order */
66 board_ahci_mcp65,
67 board_ahci_mcp77,
68 board_ahci_mcp89,
69 board_ahci_mv,
70 board_ahci_sb600,
71 board_ahci_sb700, /* for SB700 and SB800 */
72 board_ahci_vt8251,
73
74 /* aliases */
75 board_ahci_mcp_linux = board_ahci_mcp65,
76 board_ahci_mcp67 = board_ahci_mcp65,
77 board_ahci_mcp73 = board_ahci_mcp65,
78 board_ahci_mcp79 = board_ahci_mcp77,
79 };
80
81 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
82 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
83 unsigned long deadline);
84 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
88 #ifdef CONFIG_PM
89 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
90 static int ahci_pci_device_resume(struct pci_dev *pdev);
91 #endif
92
93 static struct scsi_host_template ahci_sht = {
94 AHCI_SHT("ahci"),
95 };
96
97 static struct ata_port_operations ahci_vt8251_ops = {
98 .inherits = &ahci_ops,
99 .hardreset = ahci_vt8251_hardreset,
100 };
101
102 static struct ata_port_operations ahci_p5wdh_ops = {
103 .inherits = &ahci_ops,
104 .hardreset = ahci_p5wdh_hardreset,
105 };
106
107 static struct ata_port_operations ahci_sb600_ops = {
108 .inherits = &ahci_ops,
109 .softreset = ahci_sb600_softreset,
110 .pmp_softreset = ahci_sb600_softreset,
111 };
112
113 #define AHCI_HFLAGS(flags) .private_data = (void *)(flags)
114
115 static const struct ata_port_info ahci_port_info[] = {
116 /* by features */
117 [board_ahci] =
118 {
119 .flags = AHCI_FLAG_COMMON,
120 .pio_mask = ATA_PIO4,
121 .udma_mask = ATA_UDMA6,
122 .port_ops = &ahci_ops,
123 },
124 [board_ahci_ign_iferr] =
125 {
126 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
127 .flags = AHCI_FLAG_COMMON,
128 .pio_mask = ATA_PIO4,
129 .udma_mask = ATA_UDMA6,
130 .port_ops = &ahci_ops,
131 },
132 [board_ahci_nosntf] =
133 {
134 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
135 .flags = AHCI_FLAG_COMMON,
136 .pio_mask = ATA_PIO4,
137 .udma_mask = ATA_UDMA6,
138 .port_ops = &ahci_ops,
139 },
140 [board_ahci_yes_fbs] =
141 {
142 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
143 .flags = AHCI_FLAG_COMMON,
144 .pio_mask = ATA_PIO4,
145 .udma_mask = ATA_UDMA6,
146 .port_ops = &ahci_ops,
147 },
148 /* by chipsets */
149 [board_ahci_mcp65] =
150 {
151 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
152 AHCI_HFLAG_YES_NCQ),
153 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
154 .pio_mask = ATA_PIO4,
155 .udma_mask = ATA_UDMA6,
156 .port_ops = &ahci_ops,
157 },
158 [board_ahci_mcp77] =
159 {
160 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
161 .flags = AHCI_FLAG_COMMON,
162 .pio_mask = ATA_PIO4,
163 .udma_mask = ATA_UDMA6,
164 .port_ops = &ahci_ops,
165 },
166 [board_ahci_mcp89] =
167 {
168 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
169 .flags = AHCI_FLAG_COMMON,
170 .pio_mask = ATA_PIO4,
171 .udma_mask = ATA_UDMA6,
172 .port_ops = &ahci_ops,
173 },
174 [board_ahci_mv] =
175 {
176 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
177 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
178 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
179 ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA,
180 .pio_mask = ATA_PIO4,
181 .udma_mask = ATA_UDMA6,
182 .port_ops = &ahci_ops,
183 },
184 [board_ahci_sb600] =
185 {
186 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
187 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
188 AHCI_HFLAG_32BIT_ONLY),
189 .flags = AHCI_FLAG_COMMON,
190 .pio_mask = ATA_PIO4,
191 .udma_mask = ATA_UDMA6,
192 .port_ops = &ahci_sb600_ops,
193 },
194 [board_ahci_sb700] = /* for SB700 and SB800 */
195 {
196 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
197 .flags = AHCI_FLAG_COMMON,
198 .pio_mask = ATA_PIO4,
199 .udma_mask = ATA_UDMA6,
200 .port_ops = &ahci_sb600_ops,
201 },
202 [board_ahci_vt8251] =
203 {
204 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
205 .flags = AHCI_FLAG_COMMON,
206 .pio_mask = ATA_PIO4,
207 .udma_mask = ATA_UDMA6,
208 .port_ops = &ahci_vt8251_ops,
209 },
210 };
211
212 static const struct pci_device_id ahci_pci_tbl[] = {
213 /* Intel */
214 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
215 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
216 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
217 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
218 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
219 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
220 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
221 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
222 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
223 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
224 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
225 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
226 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
227 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
228 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
229 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
230 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
231 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
232 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
233 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
234 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
235 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
236 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
237 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
238 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
239 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
240 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
241 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
242 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
243 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
244 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
245 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
246 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
247 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
248 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
249 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
250 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
251 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
252 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
253 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
254 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
255 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
256 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
257 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
258 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
259 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
260 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
261 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
262 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
263 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
264 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
265
266 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
267 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
268 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
269
270 /* ATI */
271 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
272 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
273 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
274 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
275 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
276 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
277 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
278
279 /* AMD */
280 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
281 /* AMD is using RAID class only for ahci controllers */
282 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
283 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
284
285 /* VIA */
286 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
287 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
288
289 /* NVIDIA */
290 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
291 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
292 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
293 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
294 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
295 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
296 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
297 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
298 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
299 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
300 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
301 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
302 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
303 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
304 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
305 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
306 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
307 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
308 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
309 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
310 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
311 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
312 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
313 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
314 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
315 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
316 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
317 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
318 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
319 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
320 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
321 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
322 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
323 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
324 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
325 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
326 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
327 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
328 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
329 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
330 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
331 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
332 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
333 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
334 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
335 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
336 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
337 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
338 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
339 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
340 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
341 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
342 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
343 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
344 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
345 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
346 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
347 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
348 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
349 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
350 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
351 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
352 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
353 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
354 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
355 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
356 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
357 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
358 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
359 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
360 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
361 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
362 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
363 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
364 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
365 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
366 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
367 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
368 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
369 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
370 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
371 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
372 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
373 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
374
375 /* SiS */
376 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
377 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
378 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
379
380 /* Marvell */
381 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
382 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
383 { PCI_DEVICE(0x1b4b, 0x9123),
384 .class = PCI_CLASS_STORAGE_SATA_AHCI,
385 .class_mask = 0xffffff,
386 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
387 { PCI_DEVICE(0x1b4b, 0x9125),
388 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
389
390 /* Promise */
391 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
392
393 /* Generic, PCI class code for AHCI */
394 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
395 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
396
397 { } /* terminate list */
398 };
399
400
401 static struct pci_driver ahci_pci_driver = {
402 .name = DRV_NAME,
403 .id_table = ahci_pci_tbl,
404 .probe = ahci_init_one,
405 .remove = ata_pci_remove_one,
406 #ifdef CONFIG_PM
407 .suspend = ahci_pci_device_suspend,
408 .resume = ahci_pci_device_resume,
409 #endif
410 };
411
412 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
413 static int marvell_enable;
414 #else
415 static int marvell_enable = 1;
416 #endif
417 module_param(marvell_enable, int, 0644);
418 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
419
420
421 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
422 struct ahci_host_priv *hpriv)
423 {
424 unsigned int force_port_map = 0;
425 unsigned int mask_port_map = 0;
426
427 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
428 dev_info(&pdev->dev, "JMB361 has only one port\n");
429 force_port_map = 1;
430 }
431
432 /*
433 * Temporary Marvell 6145 hack: PATA port presence
434 * is asserted through the standard AHCI port
435 * presence register, as bit 4 (counting from 0)
436 */
437 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
438 if (pdev->device == 0x6121)
439 mask_port_map = 0x3;
440 else
441 mask_port_map = 0xf;
442 dev_info(&pdev->dev,
443 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
444 }
445
446 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
447 mask_port_map);
448 }
449
450 static int ahci_pci_reset_controller(struct ata_host *host)
451 {
452 struct pci_dev *pdev = to_pci_dev(host->dev);
453
454 ahci_reset_controller(host);
455
456 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
457 struct ahci_host_priv *hpriv = host->private_data;
458 u16 tmp16;
459
460 /* configure PCS */
461 pci_read_config_word(pdev, 0x92, &tmp16);
462 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
463 tmp16 |= hpriv->port_map;
464 pci_write_config_word(pdev, 0x92, tmp16);
465 }
466 }
467
468 return 0;
469 }
470
471 static void ahci_pci_init_controller(struct ata_host *host)
472 {
473 struct ahci_host_priv *hpriv = host->private_data;
474 struct pci_dev *pdev = to_pci_dev(host->dev);
475 void __iomem *port_mmio;
476 u32 tmp;
477 int mv;
478
479 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
480 if (pdev->device == 0x6121)
481 mv = 2;
482 else
483 mv = 4;
484 port_mmio = __ahci_port_base(host, mv);
485
486 writel(0, port_mmio + PORT_IRQ_MASK);
487
488 /* clear port IRQ */
489 tmp = readl(port_mmio + PORT_IRQ_STAT);
490 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
491 if (tmp)
492 writel(tmp, port_mmio + PORT_IRQ_STAT);
493 }
494
495 ahci_init_controller(host);
496 }
497
498 static int ahci_sb600_check_ready(struct ata_link *link)
499 {
500 void __iomem *port_mmio = ahci_port_base(link->ap);
501 u8 status = readl(port_mmio + PORT_TFDATA) & 0xFF;
502 u32 irq_status = readl(port_mmio + PORT_IRQ_STAT);
503
504 /*
505 * There is no need to check TFDATA if BAD PMP is found due to HW bug,
506 * which can save timeout delay.
507 */
508 if (irq_status & PORT_IRQ_BAD_PMP)
509 return -EIO;
510
511 return ata_check_ready(status);
512 }
513
514 static int ahci_sb600_softreset(struct ata_link *link, unsigned int *class,
515 unsigned long deadline)
516 {
517 struct ata_port *ap = link->ap;
518 void __iomem *port_mmio = ahci_port_base(ap);
519 int pmp = sata_srst_pmp(link);
520 int rc;
521 u32 irq_sts;
522
523 DPRINTK("ENTER\n");
524
525 rc = ahci_do_softreset(link, class, pmp, deadline,
526 ahci_sb600_check_ready);
527
528 /*
529 * Soft reset fails on some ATI chips with IPMS set when PMP
530 * is enabled but SATA HDD/ODD is connected to SATA port,
531 * do soft reset again to port 0.
532 */
533 if (rc == -EIO) {
534 irq_sts = readl(port_mmio + PORT_IRQ_STAT);
535 if (irq_sts & PORT_IRQ_BAD_PMP) {
536 ata_link_printk(link, KERN_WARNING,
537 "applying SB600 PMP SRST workaround "
538 "and retrying\n");
539 rc = ahci_do_softreset(link, class, 0, deadline,
540 ahci_check_ready);
541 }
542 }
543
544 return rc;
545 }
546
547 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
548 unsigned long deadline)
549 {
550 struct ata_port *ap = link->ap;
551 bool online;
552 int rc;
553
554 DPRINTK("ENTER\n");
555
556 ahci_stop_engine(ap);
557
558 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
559 deadline, &online, NULL);
560
561 ahci_start_engine(ap);
562
563 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
564
565 /* vt8251 doesn't clear BSY on signature FIS reception,
566 * request follow-up softreset.
567 */
568 return online ? -EAGAIN : rc;
569 }
570
571 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
572 unsigned long deadline)
573 {
574 struct ata_port *ap = link->ap;
575 struct ahci_port_priv *pp = ap->private_data;
576 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
577 struct ata_taskfile tf;
578 bool online;
579 int rc;
580
581 ahci_stop_engine(ap);
582
583 /* clear D2H reception area to properly wait for D2H FIS */
584 ata_tf_init(link->device, &tf);
585 tf.command = 0x80;
586 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
587
588 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
589 deadline, &online, NULL);
590
591 ahci_start_engine(ap);
592
593 /* The pseudo configuration device on SIMG4726 attached to
594 * ASUS P5W-DH Deluxe doesn't send signature FIS after
595 * hardreset if no device is attached to the first downstream
596 * port && the pseudo device locks up on SRST w/ PMP==0. To
597 * work around this, wait for !BSY only briefly. If BSY isn't
598 * cleared, perform CLO and proceed to IDENTIFY (achieved by
599 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
600 *
601 * Wait for two seconds. Devices attached to downstream port
602 * which can't process the following IDENTIFY after this will
603 * have to be reset again. For most cases, this should
604 * suffice while making probing snappish enough.
605 */
606 if (online) {
607 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
608 ahci_check_ready);
609 if (rc)
610 ahci_kick_engine(ap);
611 }
612 return rc;
613 }
614
615 #ifdef CONFIG_PM
616 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
617 {
618 struct ata_host *host = dev_get_drvdata(&pdev->dev);
619 struct ahci_host_priv *hpriv = host->private_data;
620 void __iomem *mmio = hpriv->mmio;
621 u32 ctl;
622
623 if (mesg.event & PM_EVENT_SUSPEND &&
624 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
625 dev_printk(KERN_ERR, &pdev->dev,
626 "BIOS update required for suspend/resume\n");
627 return -EIO;
628 }
629
630 if (mesg.event & PM_EVENT_SLEEP) {
631 /* AHCI spec rev1.1 section 8.3.3:
632 * Software must disable interrupts prior to requesting a
633 * transition of the HBA to D3 state.
634 */
635 ctl = readl(mmio + HOST_CTL);
636 ctl &= ~HOST_IRQ_EN;
637 writel(ctl, mmio + HOST_CTL);
638 readl(mmio + HOST_CTL); /* flush */
639 }
640
641 return ata_pci_device_suspend(pdev, mesg);
642 }
643
644 static int ahci_pci_device_resume(struct pci_dev *pdev)
645 {
646 struct ata_host *host = dev_get_drvdata(&pdev->dev);
647 int rc;
648
649 rc = ata_pci_device_do_resume(pdev);
650 if (rc)
651 return rc;
652
653 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
654 rc = ahci_pci_reset_controller(host);
655 if (rc)
656 return rc;
657
658 ahci_pci_init_controller(host);
659 }
660
661 ata_host_resume(host);
662
663 return 0;
664 }
665 #endif
666
667 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
668 {
669 int rc;
670
671 if (using_dac &&
672 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
673 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
674 if (rc) {
675 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
676 if (rc) {
677 dev_printk(KERN_ERR, &pdev->dev,
678 "64-bit DMA enable failed\n");
679 return rc;
680 }
681 }
682 } else {
683 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
684 if (rc) {
685 dev_printk(KERN_ERR, &pdev->dev,
686 "32-bit DMA enable failed\n");
687 return rc;
688 }
689 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
690 if (rc) {
691 dev_printk(KERN_ERR, &pdev->dev,
692 "32-bit consistent DMA enable failed\n");
693 return rc;
694 }
695 }
696 return 0;
697 }
698
699 static void ahci_pci_print_info(struct ata_host *host)
700 {
701 struct pci_dev *pdev = to_pci_dev(host->dev);
702 u16 cc;
703 const char *scc_s;
704
705 pci_read_config_word(pdev, 0x0a, &cc);
706 if (cc == PCI_CLASS_STORAGE_IDE)
707 scc_s = "IDE";
708 else if (cc == PCI_CLASS_STORAGE_SATA)
709 scc_s = "SATA";
710 else if (cc == PCI_CLASS_STORAGE_RAID)
711 scc_s = "RAID";
712 else
713 scc_s = "unknown";
714
715 ahci_print_info(host, scc_s);
716 }
717
718 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
719 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
720 * support PMP and the 4726 either directly exports the device
721 * attached to the first downstream port or acts as a hardware storage
722 * controller and emulate a single ATA device (can be RAID 0/1 or some
723 * other configuration).
724 *
725 * When there's no device attached to the first downstream port of the
726 * 4726, "Config Disk" appears, which is a pseudo ATA device to
727 * configure the 4726. However, ATA emulation of the device is very
728 * lame. It doesn't send signature D2H Reg FIS after the initial
729 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
730 *
731 * The following function works around the problem by always using
732 * hardreset on the port and not depending on receiving signature FIS
733 * afterward. If signature FIS isn't received soon, ATA class is
734 * assumed without follow-up softreset.
735 */
736 static void ahci_p5wdh_workaround(struct ata_host *host)
737 {
738 static struct dmi_system_id sysids[] = {
739 {
740 .ident = "P5W DH Deluxe",
741 .matches = {
742 DMI_MATCH(DMI_SYS_VENDOR,
743 "ASUSTEK COMPUTER INC"),
744 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
745 },
746 },
747 { }
748 };
749 struct pci_dev *pdev = to_pci_dev(host->dev);
750
751 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
752 dmi_check_system(sysids)) {
753 struct ata_port *ap = host->ports[1];
754
755 dev_printk(KERN_INFO, &pdev->dev, "enabling ASUS P5W DH "
756 "Deluxe on-board SIMG4726 workaround\n");
757
758 ap->ops = &ahci_p5wdh_ops;
759 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
760 }
761 }
762
763 /* only some SB600 ahci controllers can do 64bit DMA */
764 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
765 {
766 static const struct dmi_system_id sysids[] = {
767 /*
768 * The oldest version known to be broken is 0901 and
769 * working is 1501 which was released on 2007-10-26.
770 * Enable 64bit DMA on 1501 and anything newer.
771 *
772 * Please read bko#9412 for more info.
773 */
774 {
775 .ident = "ASUS M2A-VM",
776 .matches = {
777 DMI_MATCH(DMI_BOARD_VENDOR,
778 "ASUSTeK Computer INC."),
779 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
780 },
781 .driver_data = "20071026", /* yyyymmdd */
782 },
783 /*
784 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
785 * support 64bit DMA.
786 *
787 * BIOS versions earlier than 1.5 had the Manufacturer DMI
788 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
789 * This spelling mistake was fixed in BIOS version 1.5, so
790 * 1.5 and later have the Manufacturer as
791 * "MICRO-STAR INTERNATIONAL CO.,LTD".
792 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
793 *
794 * BIOS versions earlier than 1.9 had a Board Product Name
795 * DMI field of "MS-7376". This was changed to be
796 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
797 * match on DMI_BOARD_NAME of "MS-7376".
798 */
799 {
800 .ident = "MSI K9A2 Platinum",
801 .matches = {
802 DMI_MATCH(DMI_BOARD_VENDOR,
803 "MICRO-STAR INTER"),
804 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
805 },
806 },
807 { }
808 };
809 const struct dmi_system_id *match;
810 int year, month, date;
811 char buf[9];
812
813 match = dmi_first_match(sysids);
814 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
815 !match)
816 return false;
817
818 if (!match->driver_data)
819 goto enable_64bit;
820
821 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
822 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
823
824 if (strcmp(buf, match->driver_data) >= 0)
825 goto enable_64bit;
826 else {
827 dev_printk(KERN_WARNING, &pdev->dev, "%s: BIOS too old, "
828 "forcing 32bit DMA, update BIOS\n", match->ident);
829 return false;
830 }
831
832 enable_64bit:
833 dev_printk(KERN_WARNING, &pdev->dev, "%s: enabling 64bit DMA\n",
834 match->ident);
835 return true;
836 }
837
838 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
839 {
840 static const struct dmi_system_id broken_systems[] = {
841 {
842 .ident = "HP Compaq nx6310",
843 .matches = {
844 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
845 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
846 },
847 /* PCI slot number of the controller */
848 .driver_data = (void *)0x1FUL,
849 },
850 {
851 .ident = "HP Compaq 6720s",
852 .matches = {
853 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
854 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
855 },
856 /* PCI slot number of the controller */
857 .driver_data = (void *)0x1FUL,
858 },
859
860 { } /* terminate list */
861 };
862 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
863
864 if (dmi) {
865 unsigned long slot = (unsigned long)dmi->driver_data;
866 /* apply the quirk only to on-board controllers */
867 return slot == PCI_SLOT(pdev->devfn);
868 }
869
870 return false;
871 }
872
873 static bool ahci_broken_suspend(struct pci_dev *pdev)
874 {
875 static const struct dmi_system_id sysids[] = {
876 /*
877 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
878 * to the harddisk doesn't become online after
879 * resuming from STR. Warn and fail suspend.
880 *
881 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
882 *
883 * Use dates instead of versions to match as HP is
884 * apparently recycling both product and version
885 * strings.
886 *
887 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
888 */
889 {
890 .ident = "dv4",
891 .matches = {
892 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
893 DMI_MATCH(DMI_PRODUCT_NAME,
894 "HP Pavilion dv4 Notebook PC"),
895 },
896 .driver_data = "20090105", /* F.30 */
897 },
898 {
899 .ident = "dv5",
900 .matches = {
901 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
902 DMI_MATCH(DMI_PRODUCT_NAME,
903 "HP Pavilion dv5 Notebook PC"),
904 },
905 .driver_data = "20090506", /* F.16 */
906 },
907 {
908 .ident = "dv6",
909 .matches = {
910 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
911 DMI_MATCH(DMI_PRODUCT_NAME,
912 "HP Pavilion dv6 Notebook PC"),
913 },
914 .driver_data = "20090423", /* F.21 */
915 },
916 {
917 .ident = "HDX18",
918 .matches = {
919 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
920 DMI_MATCH(DMI_PRODUCT_NAME,
921 "HP HDX18 Notebook PC"),
922 },
923 .driver_data = "20090430", /* F.23 */
924 },
925 /*
926 * Acer eMachines G725 has the same problem. BIOS
927 * V1.03 is known to be broken. V3.04 is known to
928 * work. Inbetween, there are V1.06, V2.06 and V3.03
929 * that we don't have much idea about. For now,
930 * blacklist anything older than V3.04.
931 *
932 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
933 */
934 {
935 .ident = "G725",
936 .matches = {
937 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
938 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
939 },
940 .driver_data = "20091216", /* V3.04 */
941 },
942 { } /* terminate list */
943 };
944 const struct dmi_system_id *dmi = dmi_first_match(sysids);
945 int year, month, date;
946 char buf[9];
947
948 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
949 return false;
950
951 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
952 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
953
954 return strcmp(buf, dmi->driver_data) < 0;
955 }
956
957 static bool ahci_broken_online(struct pci_dev *pdev)
958 {
959 #define ENCODE_BUSDEVFN(bus, slot, func) \
960 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
961 static const struct dmi_system_id sysids[] = {
962 /*
963 * There are several gigabyte boards which use
964 * SIMG5723s configured as hardware RAID. Certain
965 * 5723 firmware revisions shipped there keep the link
966 * online but fail to answer properly to SRST or
967 * IDENTIFY when no device is attached downstream
968 * causing libata to retry quite a few times leading
969 * to excessive detection delay.
970 *
971 * As these firmwares respond to the second reset try
972 * with invalid device signature, considering unknown
973 * sig as offline works around the problem acceptably.
974 */
975 {
976 .ident = "EP45-DQ6",
977 .matches = {
978 DMI_MATCH(DMI_BOARD_VENDOR,
979 "Gigabyte Technology Co., Ltd."),
980 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
981 },
982 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
983 },
984 {
985 .ident = "EP45-DS5",
986 .matches = {
987 DMI_MATCH(DMI_BOARD_VENDOR,
988 "Gigabyte Technology Co., Ltd."),
989 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
990 },
991 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
992 },
993 { } /* terminate list */
994 };
995 #undef ENCODE_BUSDEVFN
996 const struct dmi_system_id *dmi = dmi_first_match(sysids);
997 unsigned int val;
998
999 if (!dmi)
1000 return false;
1001
1002 val = (unsigned long)dmi->driver_data;
1003
1004 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1005 }
1006
1007 #ifdef CONFIG_ATA_ACPI
1008 static void ahci_gtf_filter_workaround(struct ata_host *host)
1009 {
1010 static const struct dmi_system_id sysids[] = {
1011 /*
1012 * Aspire 3810T issues a bunch of SATA enable commands
1013 * via _GTF including an invalid one and one which is
1014 * rejected by the device. Among the successful ones
1015 * is FPDMA non-zero offset enable which when enabled
1016 * only on the drive side leads to NCQ command
1017 * failures. Filter it out.
1018 */
1019 {
1020 .ident = "Aspire 3810T",
1021 .matches = {
1022 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1023 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1024 },
1025 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1026 },
1027 { }
1028 };
1029 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1030 unsigned int filter;
1031 int i;
1032
1033 if (!dmi)
1034 return;
1035
1036 filter = (unsigned long)dmi->driver_data;
1037 dev_printk(KERN_INFO, host->dev,
1038 "applying extra ACPI _GTF filter 0x%x for %s\n",
1039 filter, dmi->ident);
1040
1041 for (i = 0; i < host->n_ports; i++) {
1042 struct ata_port *ap = host->ports[i];
1043 struct ata_link *link;
1044 struct ata_device *dev;
1045
1046 ata_for_each_link(link, ap, EDGE)
1047 ata_for_each_dev(dev, link, ALL)
1048 dev->gtf_filter |= filter;
1049 }
1050 }
1051 #else
1052 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1053 {}
1054 #endif
1055
1056 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1057 {
1058 static int printed_version;
1059 unsigned int board_id = ent->driver_data;
1060 struct ata_port_info pi = ahci_port_info[board_id];
1061 const struct ata_port_info *ppi[] = { &pi, NULL };
1062 struct device *dev = &pdev->dev;
1063 struct ahci_host_priv *hpriv;
1064 struct ata_host *host;
1065 int n_ports, i, rc;
1066
1067 VPRINTK("ENTER\n");
1068
1069 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1070
1071 if (!printed_version++)
1072 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1073
1074 /* The AHCI driver can only drive the SATA ports, the PATA driver
1075 can drive them all so if both drivers are selected make sure
1076 AHCI stays out of the way */
1077 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1078 return -ENODEV;
1079
1080 /*
1081 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1082 * ahci, use ata_generic instead.
1083 */
1084 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1085 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1086 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1087 pdev->subsystem_device == 0xcb89)
1088 return -ENODEV;
1089
1090 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1091 * At the moment, we can only use the AHCI mode. Let the users know
1092 * that for SAS drives they're out of luck.
1093 */
1094 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1095 dev_printk(KERN_INFO, &pdev->dev, "PDC42819 "
1096 "can only drive SATA devices with this driver\n");
1097
1098 /* acquire resources */
1099 rc = pcim_enable_device(pdev);
1100 if (rc)
1101 return rc;
1102
1103 /* AHCI controllers often implement SFF compatible interface.
1104 * Grab all PCI BARs just in case.
1105 */
1106 rc = pcim_iomap_regions_request_all(pdev, 1 << AHCI_PCI_BAR, DRV_NAME);
1107 if (rc == -EBUSY)
1108 pcim_pin_device(pdev);
1109 if (rc)
1110 return rc;
1111
1112 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1113 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1114 u8 map;
1115
1116 /* ICH6s share the same PCI ID for both piix and ahci
1117 * modes. Enabling ahci mode while MAP indicates
1118 * combined mode is a bad idea. Yield to ata_piix.
1119 */
1120 pci_read_config_byte(pdev, ICH_MAP, &map);
1121 if (map & 0x3) {
1122 dev_printk(KERN_INFO, &pdev->dev, "controller is in "
1123 "combined mode, can't enable AHCI mode\n");
1124 return -ENODEV;
1125 }
1126 }
1127
1128 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1129 if (!hpriv)
1130 return -ENOMEM;
1131 hpriv->flags |= (unsigned long)pi.private_data;
1132
1133 /* MCP65 revision A1 and A2 can't do MSI */
1134 if (board_id == board_ahci_mcp65 &&
1135 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1136 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1137
1138 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1139 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1140 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1141
1142 /* only some SB600s can do 64bit DMA */
1143 if (ahci_sb600_enable_64bit(pdev))
1144 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1145
1146 if ((hpriv->flags & AHCI_HFLAG_NO_MSI) || pci_enable_msi(pdev))
1147 pci_intx(pdev, 1);
1148
1149 hpriv->mmio = pcim_iomap_table(pdev)[AHCI_PCI_BAR];
1150
1151 /* save initial config */
1152 ahci_pci_save_initial_config(pdev, hpriv);
1153
1154 /* prepare host */
1155 if (hpriv->cap & HOST_CAP_NCQ) {
1156 pi.flags |= ATA_FLAG_NCQ;
1157 /*
1158 * Auto-activate optimization is supposed to be
1159 * supported on all AHCI controllers indicating NCQ
1160 * capability, but it seems to be broken on some
1161 * chipsets including NVIDIAs.
1162 */
1163 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1164 pi.flags |= ATA_FLAG_FPDMA_AA;
1165 }
1166
1167 if (hpriv->cap & HOST_CAP_PMP)
1168 pi.flags |= ATA_FLAG_PMP;
1169
1170 ahci_set_em_messages(hpriv, &pi);
1171
1172 if (ahci_broken_system_poweroff(pdev)) {
1173 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1174 dev_info(&pdev->dev,
1175 "quirky BIOS, skipping spindown on poweroff\n");
1176 }
1177
1178 if (ahci_broken_suspend(pdev)) {
1179 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1180 dev_printk(KERN_WARNING, &pdev->dev,
1181 "BIOS update required for suspend/resume\n");
1182 }
1183
1184 if (ahci_broken_online(pdev)) {
1185 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1186 dev_info(&pdev->dev,
1187 "online status unreliable, applying workaround\n");
1188 }
1189
1190 /* CAP.NP sometimes indicate the index of the last enabled
1191 * port, at other times, that of the last possible port, so
1192 * determining the maximum port number requires looking at
1193 * both CAP.NP and port_map.
1194 */
1195 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1196
1197 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1198 if (!host)
1199 return -ENOMEM;
1200 host->private_data = hpriv;
1201
1202 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1203 host->flags |= ATA_HOST_PARALLEL_SCAN;
1204 else
1205 printk(KERN_INFO "ahci: SSS flag set, parallel bus scan disabled\n");
1206
1207 if (pi.flags & ATA_FLAG_EM)
1208 ahci_reset_em(host);
1209
1210 for (i = 0; i < host->n_ports; i++) {
1211 struct ata_port *ap = host->ports[i];
1212
1213 ata_port_pbar_desc(ap, AHCI_PCI_BAR, -1, "abar");
1214 ata_port_pbar_desc(ap, AHCI_PCI_BAR,
1215 0x100 + ap->port_no * 0x80, "port");
1216
1217 /* set enclosure management message type */
1218 if (ap->flags & ATA_FLAG_EM)
1219 ap->em_message_type = hpriv->em_msg_type;
1220
1221
1222 /* disabled/not-implemented port */
1223 if (!(hpriv->port_map & (1 << i)))
1224 ap->ops = &ata_dummy_port_ops;
1225 }
1226
1227 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1228 ahci_p5wdh_workaround(host);
1229
1230 /* apply gtf filter quirk */
1231 ahci_gtf_filter_workaround(host);
1232
1233 /* initialize adapter */
1234 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1235 if (rc)
1236 return rc;
1237
1238 rc = ahci_pci_reset_controller(host);
1239 if (rc)
1240 return rc;
1241
1242 ahci_pci_init_controller(host);
1243 ahci_pci_print_info(host);
1244
1245 pci_set_master(pdev);
1246 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1247 &ahci_sht);
1248 }
1249
1250 static int __init ahci_init(void)
1251 {
1252 return pci_register_driver(&ahci_pci_driver);
1253 }
1254
1255 static void __exit ahci_exit(void)
1256 {
1257 pci_unregister_driver(&ahci_pci_driver);
1258 }
1259
1260
1261 MODULE_AUTHOR("Jeff Garzik");
1262 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1263 MODULE_LICENSE("GPL");
1264 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1265 MODULE_VERSION(DRV_VERSION);
1266
1267 module_init(ahci_init);
1268 module_exit(ahci_exit);
Linux 2.6 ibm-acpi/thinkpad-acpi driver git tree