drivers/char/rocket.c

   1 /*
   2  * RocketPort device driver for Linux
   3  *
   4  * Written by Theodore Ts'o, 1995, 1996, 1997, 1998, 1999, 2000.
   5  *
   6  * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2000, 2003 by Comtrol, Inc.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of the
  11  * License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful, but
  14  * WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  16  * General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 /*
  24  * Kernel Synchronization:
  25  *
  26  * This driver has 2 kernel control paths - exception handlers (calls into the driver
  27  * from user mode) and the timer bottom half (tasklet).  This is a polled driver, interrupts
  28  * are not used.
  29  *
  30  * Critical data:
  31  * -  rp_table[], accessed through passed "info" pointers, is a global (static) array of
  32  *    serial port state information and the xmit_buf circular buffer.  Protected by
  33  *    a per port spinlock.
  34  * -  xmit_flags[], an array of ints indexed by line (port) number, indicating that there
  35  *    is data to be transmitted.  Protected by atomic bit operations.
  36  * -  rp_num_ports, int indicating number of open ports, protected by atomic operations.
  37  *
  38  * rp_write() and rp_write_char() functions use a per port semaphore to protect against
  39  * simultaneous access to the same port by more than one process.
  40  */
  41
  42 /****** Defines ******/
  43 #define ROCKET_PARANOIA_CHECK
  44 #define ROCKET_DISABLE_SIMUSAGE
  45
  46 #undef ROCKET_SOFT_FLOW
  47 #undef ROCKET_DEBUG_OPEN
  48 #undef ROCKET_DEBUG_INTR
  49 #undef ROCKET_DEBUG_WRITE
  50 #undef ROCKET_DEBUG_FLOW
  51 #undef ROCKET_DEBUG_THROTTLE
  52 #undef ROCKET_DEBUG_WAIT_UNTIL_SENT
  53 #undef ROCKET_DEBUG_RECEIVE
  54 #undef ROCKET_DEBUG_HANGUP
  55 #undef REV_PCI_ORDER
  56 #undef ROCKET_DEBUG_IO
  57
  58 #define POLL_PERIOD HZ/100      /*  Polling period .01 seconds (10ms) */
  59
  60 /****** Kernel includes ******/
  61
  62 #include <linux/module.h>
  63 #include <linux/errno.h>
  64 #include <linux/major.h>
  65 #include <linux/kernel.h>
  66 #include <linux/signal.h>
  67 #include <linux/slab.h>
  68 #include <linux/mm.h>
  69 #include <linux/sched.h>
  70 #include <linux/timer.h>
  71 #include <linux/interrupt.h>
  72 #include <linux/tty.h>
  73 #include <linux/tty_driver.h>
  74 #include <linux/tty_flip.h>
  75 #include <linux/serial.h>
  76 #include <linux/string.h>
  77 #include <linux/fcntl.h>
  78 #include <linux/ptrace.h>
  79 #include <linux/mutex.h>
  80 #include <linux/ioport.h>
  81 #include <linux/delay.h>
  82 #include <linux/completion.h>
  83 #include <linux/wait.h>
  84 #include <linux/pci.h>
  85 #include <linux/uaccess.h>
  86 #include <asm/atomic.h>
  87 #include <asm/unaligned.h>
  88 #include <linux/bitops.h>
  89 #include <linux/spinlock.h>
  90 #include <linux/init.h>
  91
  92 /****** RocketPort includes ******/
  93
  94 #include "rocket_int.h"
  95 #include "rocket.h"
  96
  97 #define ROCKET_VERSION "2.09"
  98 #define ROCKET_DATE "12-June-2003"
  99
 100 /****** RocketPort Local Variables ******/
 101
 102 static void rp_do_poll(unsigned long dummy);
 103
 104 static struct tty_driver *rocket_driver;
 105
 106 static struct rocket_version driver_version = {
 107         ROCKET_VERSION, ROCKET_DATE
 108 };
 109
 110 static struct r_port *rp_table[MAX_RP_PORTS];          /*  The main repository of serial port state information. */
 111 static unsigned int xmit_flags[NUM_BOARDS];            /*  Bit significant, indicates port had data to transmit. */
 112                                                        /*  eg.  Bit 0 indicates port 0 has xmit data, ...        */
 113 static atomic_t rp_num_ports_open;                     /*  Number of serial ports open                           */
 114 static DEFINE_TIMER(rocket_timer, rp_do_poll, 0, 0);
 115
 116 static unsigned long board1;                           /* ISA addresses, retrieved from rocketport.conf          */
 117 static unsigned long board2;
 118 static unsigned long board3;
 119 static unsigned long board4;
 120 static unsigned long controller;
 121 static int support_low_speed;
 122 static unsigned long modem1;
 123 static unsigned long modem2;
 124 static unsigned long modem3;
 125 static unsigned long modem4;
 126 static unsigned long pc104_1[8];
 127 static unsigned long pc104_2[8];
 128 static unsigned long pc104_3[8];
 129 static unsigned long pc104_4[8];
 130 static unsigned long *pc104[4] = { pc104_1, pc104_2, pc104_3, pc104_4 };
 131
 132 static int rp_baud_base[NUM_BOARDS];                   /*  Board config info (Someday make a per-board structure)  */
 133 static unsigned long rcktpt_io_addr[NUM_BOARDS];
 134 static int rcktpt_type[NUM_BOARDS];
 135 static int is_PCI[NUM_BOARDS];
 136 static rocketModel_t rocketModel[NUM_BOARDS];
 137 static int max_board;
 138 static const struct tty_port_operations rocket_port_ops;
 139
 140 /*
 141  * The following arrays define the interrupt bits corresponding to each AIOP.
 142  * These bits are different between the ISA and regular PCI boards and the
 143  * Universal PCI boards.
 144  */
 145
 146 static Word_t aiop_intr_bits[AIOP_CTL_SIZE] = {
 147         AIOP_INTR_BIT_0,
 148         AIOP_INTR_BIT_1,
 149         AIOP_INTR_BIT_2,
 150         AIOP_INTR_BIT_3
 151 };
 152
 153 static Word_t upci_aiop_intr_bits[AIOP_CTL_SIZE] = {
 154         UPCI_AIOP_INTR_BIT_0,
 155         UPCI_AIOP_INTR_BIT_1,
 156         UPCI_AIOP_INTR_BIT_2,
 157         UPCI_AIOP_INTR_BIT_3
 158 };
 159
 160 static Byte_t RData[RDATASIZE] = {
 161         0x00, 0x09, 0xf6, 0x82,
 162         0x02, 0x09, 0x86, 0xfb,
 163         0x04, 0x09, 0x00, 0x0a,
 164         0x06, 0x09, 0x01, 0x0a,
 165         0x08, 0x09, 0x8a, 0x13,
 166         0x0a, 0x09, 0xc5, 0x11,
 167         0x0c, 0x09, 0x86, 0x85,
 168         0x0e, 0x09, 0x20, 0x0a,
 169         0x10, 0x09, 0x21, 0x0a,
 170         0x12, 0x09, 0x41, 0xff,
 171         0x14, 0x09, 0x82, 0x00,
 172         0x16, 0x09, 0x82, 0x7b,
 173         0x18, 0x09, 0x8a, 0x7d,
 174         0x1a, 0x09, 0x88, 0x81,
 175         0x1c, 0x09, 0x86, 0x7a,
 176         0x1e, 0x09, 0x84, 0x81,
 177         0x20, 0x09, 0x82, 0x7c,
 178         0x22, 0x09, 0x0a, 0x0a
 179 };
 180
 181 static Byte_t RRegData[RREGDATASIZE] = {
 182         0x00, 0x09, 0xf6, 0x82, /* 00: Stop Rx processor */
 183         0x08, 0x09, 0x8a, 0x13, /* 04: Tx software flow control */
 184         0x0a, 0x09, 0xc5, 0x11, /* 08: XON char */
 185         0x0c, 0x09, 0x86, 0x85, /* 0c: XANY */
 186         0x12, 0x09, 0x41, 0xff, /* 10: Rx mask char */
 187         0x14, 0x09, 0x82, 0x00, /* 14: Compare/Ignore #0 */
 188         0x16, 0x09, 0x82, 0x7b, /* 18: Compare #1 */
 189         0x18, 0x09, 0x8a, 0x7d, /* 1c: Compare #2 */
 190         0x1a, 0x09, 0x88, 0x81, /* 20: Interrupt #1 */
 191         0x1c, 0x09, 0x86, 0x7a, /* 24: Ignore/Replace #1 */
 192         0x1e, 0x09, 0x84, 0x81, /* 28: Interrupt #2 */
 193         0x20, 0x09, 0x82, 0x7c, /* 2c: Ignore/Replace #2 */
 194         0x22, 0x09, 0x0a, 0x0a  /* 30: Rx FIFO Enable */
 195 };
 196
 197 static CONTROLLER_T sController[CTL_SIZE] = {
 198         {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
 199          {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
 200         {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
 201          {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
 202         {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
 203          {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}},
 204         {-1, -1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, {0, 0, 0, 0},
 205          {0, 0, 0, 0}, {-1, -1, -1, -1}, {0, 0, 0, 0}}
 206 };
 207
 208 static Byte_t sBitMapClrTbl[8] = {
 209         0xfe, 0xfd, 0xfb, 0xf7, 0xef, 0xdf, 0xbf, 0x7f
 210 };
 211
 212 static Byte_t sBitMapSetTbl[8] = {
 213         0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80
 214 };
 215
 216 static int sClockPrescale = 0x14;
 217
 218 /*
 219  *  Line number is the ttySIx number (x), the Minor number.  We
 220  *  assign them sequentially, starting at zero.  The following
 221  *  array keeps track of the line number assigned to a given board/aiop/channel.
 222  */
 223 static unsigned char lineNumbers[MAX_RP_PORTS];
 224 static unsigned long nextLineNumber;
 225
 226 /*****  RocketPort Static Prototypes   *********/
 227 static int __init init_ISA(int i);
 228 static void rp_wait_until_sent(struct tty_struct *tty, int timeout);
 229 static void rp_flush_buffer(struct tty_struct *tty);
 230 static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model);
 231 static unsigned char GetLineNumber(int ctrl, int aiop, int ch);
 232 static unsigned char SetLineNumber(int ctrl, int aiop, int ch);
 233 static void rp_start(struct tty_struct *tty);
 234 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
 235                      int ChanNum);
 236 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode);
 237 static void sFlushRxFIFO(CHANNEL_T * ChP);
 238 static void sFlushTxFIFO(CHANNEL_T * ChP);
 239 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags);
 240 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags);
 241 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on);
 242 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on);
 243 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data);
 244 static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
 245                               ByteIO_t * AiopIOList, int AiopIOListSize,
 246                               WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
 247                               int PeriodicOnly, int altChanRingIndicator,
 248                               int UPCIRingInd);
 249 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
 250                            ByteIO_t * AiopIOList, int AiopIOListSize,
 251                            int IRQNum, Byte_t Frequency, int PeriodicOnly);
 252 static int sReadAiopID(ByteIO_t io);
 253 static int sReadAiopNumChan(WordIO_t io);
 254
 255 MODULE_AUTHOR("Theodore Ts'o");
 256 MODULE_DESCRIPTION("Comtrol RocketPort driver");
 257 module_param(board1, ulong, 0);
 258 MODULE_PARM_DESC(board1, "I/O port for (ISA) board #1");
 259 module_param(board2, ulong, 0);
 260 MODULE_PARM_DESC(board2, "I/O port for (ISA) board #2");
 261 module_param(board3, ulong, 0);
 262 MODULE_PARM_DESC(board3, "I/O port for (ISA) board #3");
 263 module_param(board4, ulong, 0);
 264 MODULE_PARM_DESC(board4, "I/O port for (ISA) board #4");
 265 module_param(controller, ulong, 0);
 266 MODULE_PARM_DESC(controller, "I/O port for (ISA) rocketport controller");
 267 module_param(support_low_speed, bool, 0);
 268 MODULE_PARM_DESC(support_low_speed, "1 means support 50 baud, 0 means support 460400 baud");
 269 module_param(modem1, ulong, 0);
 270 MODULE_PARM_DESC(modem1, "1 means (ISA) board #1 is a RocketModem");
 271 module_param(modem2, ulong, 0);
 272 MODULE_PARM_DESC(modem2, "1 means (ISA) board #2 is a RocketModem");
 273 module_param(modem3, ulong, 0);
 274 MODULE_PARM_DESC(modem3, "1 means (ISA) board #3 is a RocketModem");
 275 module_param(modem4, ulong, 0);
 276 MODULE_PARM_DESC(modem4, "1 means (ISA) board #4 is a RocketModem");
 277 module_param_array(pc104_1, ulong, NULL, 0);
 278 MODULE_PARM_DESC(pc104_1, "set interface types for ISA(PC104) board #1 (e.g. pc104_1=232,232,485,485,...");
 279 module_param_array(pc104_2, ulong, NULL, 0);
 280 MODULE_PARM_DESC(pc104_2, "set interface types for ISA(PC104) board #2 (e.g. pc104_2=232,232,485,485,...");
 281 module_param_array(pc104_3, ulong, NULL, 0);
 282 MODULE_PARM_DESC(pc104_3, "set interface types for ISA(PC104) board #3 (e.g. pc104_3=232,232,485,485,...");
 283 module_param_array(pc104_4, ulong, NULL, 0);
 284 MODULE_PARM_DESC(pc104_4, "set interface types for ISA(PC104) board #4 (e.g. pc104_4=232,232,485,485,...");
 285
 286 static int rp_init(void);
 287 static void rp_cleanup_module(void);
 288
 289 module_init(rp_init);
 290 module_exit(rp_cleanup_module);
 291
 292
 293 MODULE_LICENSE("Dual BSD/GPL");
 294
 295 /*************************************************************************/
 296 /*                     Module code starts here                           */
 297
 298 static inline int rocket_paranoia_check(struct r_port *info,
 299                                         const char *routine)
 300 {
 301 #ifdef ROCKET_PARANOIA_CHECK
 302         if (!info)
 303                 return 1;
 304         if (info->magic != RPORT_MAGIC) {
 305                 printk(KERN_WARNING "Warning: bad magic number for rocketport "
 306                                 "struct in %s\n", routine);
 307                 return 1;
 308         }
 309 #endif
 310         return 0;
 311 }
 312
 313
 314 /*  Serial port receive data function.  Called (from timer poll) when an AIOPIC signals
 315  *  that receive data is present on a serial port.  Pulls data from FIFO, moves it into the
 316  *  tty layer.
 317  */
 318 static void rp_do_receive(struct r_port *info,
 319                           struct tty_struct *tty,
 320                           CHANNEL_t * cp, unsigned int ChanStatus)
 321 {
 322         unsigned int CharNStat;
 323         int ToRecv, wRecv, space;
 324         unsigned char *cbuf;
 325
 326         ToRecv = sGetRxCnt(cp);
 327 #ifdef ROCKET_DEBUG_INTR
 328         printk(KERN_INFO "rp_do_receive(%d)...\n", ToRecv);
 329 #endif
 330         if (ToRecv == 0)
 331                 return;
 332
 333         /*
 334          * if status indicates there are errored characters in the
 335          * FIFO, then enter status mode (a word in FIFO holds
 336          * character and status).
 337          */
 338         if (ChanStatus & (RXFOVERFL | RXBREAK | RXFRAME | RXPARITY)) {
 339                 if (!(ChanStatus & STATMODE)) {
 340 #ifdef ROCKET_DEBUG_RECEIVE
 341                         printk(KERN_INFO "Entering STATMODE...\n");
 342 #endif
 343                         ChanStatus |= STATMODE;
 344                         sEnRxStatusMode(cp);
 345                 }
 346         }
 347
 348         /*
 349          * if we previously entered status mode, then read down the
 350          * FIFO one word at a time, pulling apart the character and
 351          * the status.  Update error counters depending on status
 352          */
 353         if (ChanStatus & STATMODE) {
 354 #ifdef ROCKET_DEBUG_RECEIVE
 355                 printk(KERN_INFO "Ignore %x, read %x...\n",
 356                         info->ignore_status_mask, info->read_status_mask);
 357 #endif
 358                 while (ToRecv) {
 359                         char flag;
 360
 361                         CharNStat = sInW(sGetTxRxDataIO(cp));
 362 #ifdef ROCKET_DEBUG_RECEIVE
 363                         printk(KERN_INFO "%x...\n", CharNStat);
 364 #endif
 365                         if (CharNStat & STMBREAKH)
 366                                 CharNStat &= ~(STMFRAMEH | STMPARITYH);
 367                         if (CharNStat & info->ignore_status_mask) {
 368                                 ToRecv--;
 369                                 continue;
 370                         }
 371                         CharNStat &= info->read_status_mask;
 372                         if (CharNStat & STMBREAKH)
 373                                 flag = TTY_BREAK;
 374                         else if (CharNStat & STMPARITYH)
 375                                 flag = TTY_PARITY;
 376                         else if (CharNStat & STMFRAMEH)
 377                                 flag = TTY_FRAME;
 378                         else if (CharNStat & STMRCVROVRH)
 379                                 flag = TTY_OVERRUN;
 380                         else
 381                                 flag = TTY_NORMAL;
 382                         tty_insert_flip_char(tty, CharNStat & 0xff, flag);
 383                         ToRecv--;
 384                 }
 385
 386                 /*
 387                  * after we've emptied the FIFO in status mode, turn
 388                  * status mode back off
 389                  */
 390                 if (sGetRxCnt(cp) == 0) {
 391 #ifdef ROCKET_DEBUG_RECEIVE
 392                         printk(KERN_INFO "Status mode off.\n");
 393 #endif
 394                         sDisRxStatusMode(cp);
 395                 }
 396         } else {
 397                 /*
 398                  * we aren't in status mode, so read down the FIFO two
 399                  * characters at time by doing repeated word IO
 400                  * transfer.
 401                  */
 402                 space = tty_prepare_flip_string(tty, &cbuf, ToRecv);
 403                 if (space < ToRecv) {
 404 #ifdef ROCKET_DEBUG_RECEIVE
 405                         printk(KERN_INFO "rp_do_receive:insufficient space ToRecv=%d space=%d\n", ToRecv, space);
 406 #endif
 407                         if (space <= 0)
 408                                 return;
 409                         ToRecv = space;
 410                 }
 411                 wRecv = ToRecv >> 1;
 412                 if (wRecv)
 413                         sInStrW(sGetTxRxDataIO(cp), (unsigned short *) cbuf, wRecv);
 414                 if (ToRecv & 1)
 415                         cbuf[ToRecv - 1] = sInB(sGetTxRxDataIO(cp));
 416         }
 417         /*  Push the data up to the tty layer */
 418         tty_flip_buffer_push(tty);
 419 }
 420
 421 /*
 422  *  Serial port transmit data function.  Called from the timer polling loop as a
 423  *  result of a bit set in xmit_flags[], indicating data (from the tty layer) is ready
 424  *  to be sent out the serial port.  Data is buffered in rp_table[line].xmit_buf, it is
 425  *  moved to the port's xmit FIFO.  *info is critical data, protected by spinlocks.
 426  */
 427 static void rp_do_transmit(struct r_port *info)
 428 {
 429         int c;
 430         CHANNEL_t *cp = &info->channel;
 431         struct tty_struct *tty;
 432         unsigned long flags;
 433
 434 #ifdef ROCKET_DEBUG_INTR
 435         printk(KERN_DEBUG "%s\n", __func__);
 436 #endif
 437         if (!info)
 438                 return;
 439         tty = tty_port_tty_get(&info->port);
 440
 441         if (tty == NULL) {
 442                 printk(KERN_WARNING "rp: WARNING %s called with tty==NULL\n", __func__);
 443                 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
 444                 return;
 445         }
 446
 447         spin_lock_irqsave(&info->slock, flags);
 448         info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
 449
 450         /*  Loop sending data to FIFO until done or FIFO full */
 451         while (1) {
 452                 if (tty->stopped || tty->hw_stopped)
 453                         break;
 454                 c = min(info->xmit_fifo_room, info->xmit_cnt);
 455                 c = min(c, XMIT_BUF_SIZE - info->xmit_tail);
 456                 if (c <= 0 || info->xmit_fifo_room <= 0)
 457                         break;
 458                 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) (info->xmit_buf + info->xmit_tail), c / 2);
 459                 if (c & 1)
 460                         sOutB(sGetTxRxDataIO(cp), info->xmit_buf[info->xmit_tail + c - 1]);
 461                 info->xmit_tail += c;
 462                 info->xmit_tail &= XMIT_BUF_SIZE - 1;
 463                 info->xmit_cnt -= c;
 464                 info->xmit_fifo_room -= c;
 465 #ifdef ROCKET_DEBUG_INTR
 466                 printk(KERN_INFO "tx %d chars...\n", c);
 467 #endif
 468         }
 469
 470         if (info->xmit_cnt == 0)
 471                 clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
 472
 473         if (info->xmit_cnt < WAKEUP_CHARS) {
 474                 tty_wakeup(tty);
 475 #ifdef ROCKETPORT_HAVE_POLL_WAIT
 476                 wake_up_interruptible(&tty->poll_wait);
 477 #endif
 478         }
 479
 480         spin_unlock_irqrestore(&info->slock, flags);
 481         tty_kref_put(tty);
 482
 483 #ifdef ROCKET_DEBUG_INTR
 484         printk(KERN_DEBUG "(%d,%d,%d,%d)...\n", info->xmit_cnt, info->xmit_head,
 485                info->xmit_tail, info->xmit_fifo_room);
 486 #endif
 487 }
 488
 489 /*
 490  *  Called when a serial port signals it has read data in it's RX FIFO.
 491  *  It checks what interrupts are pending and services them, including
 492  *  receiving serial data.
 493  */
 494 static void rp_handle_port(struct r_port *info)
 495 {
 496         CHANNEL_t *cp;
 497         struct tty_struct *tty;
 498         unsigned int IntMask, ChanStatus;
 499
 500         if (!info)
 501                 return;
 502
 503         if ((info->port.flags & ASYNC_INITIALIZED) == 0) {
 504                 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
 505                                 "info->flags & NOT_INIT\n");
 506                 return;
 507         }
 508         tty = tty_port_tty_get(&info->port);
 509         if (!tty) {
 510                 printk(KERN_WARNING "rp: WARNING: rp_handle_port called with "
 511                                 "tty==NULL\n");
 512                 return;
 513         }
 514         cp = &info->channel;
 515
 516         IntMask = sGetChanIntID(cp) & info->intmask;
 517 #ifdef ROCKET_DEBUG_INTR
 518         printk(KERN_INFO "rp_interrupt %02x...\n", IntMask);
 519 #endif
 520         ChanStatus = sGetChanStatus(cp);
 521         if (IntMask & RXF_TRIG) {       /* Rx FIFO trigger level */
 522                 rp_do_receive(info, tty, cp, ChanStatus);
 523         }
 524         if (IntMask & DELTA_CD) {       /* CD change  */
 525 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_INTR) || defined(ROCKET_DEBUG_HANGUP))
 526                 printk(KERN_INFO "ttyR%d CD now %s...\n", info->line,
 527                        (ChanStatus & CD_ACT) ? "on" : "off");
 528 #endif
 529                 if (!(ChanStatus & CD_ACT) && info->cd_status) {
 530 #ifdef ROCKET_DEBUG_HANGUP
 531                         printk(KERN_INFO "CD drop, calling hangup.\n");
 532 #endif
 533                         tty_hangup(tty);
 534                 }
 535                 info->cd_status = (ChanStatus & CD_ACT) ? 1 : 0;
 536                 wake_up_interruptible(&info->port.open_wait);
 537         }
 538 #ifdef ROCKET_DEBUG_INTR
 539         if (IntMask & DELTA_CTS) {      /* CTS change */
 540                 printk(KERN_INFO "CTS change...\n");
 541         }
 542         if (IntMask & DELTA_DSR) {      /* DSR change */
 543                 printk(KERN_INFO "DSR change...\n");
 544         }
 545 #endif
 546         tty_kref_put(tty);
 547 }
 548
 549 /*
 550  *  The top level polling routine.  Repeats every 1/100 HZ (10ms).
 551  */
 552 static void rp_do_poll(unsigned long dummy)
 553 {
 554         CONTROLLER_t *ctlp;
 555         int ctrl, aiop, ch, line;
 556         unsigned int xmitmask, i;
 557         unsigned int CtlMask;
 558         unsigned char AiopMask;
 559         Word_t bit;
 560
 561         /*  Walk through all the boards (ctrl's) */
 562         for (ctrl = 0; ctrl < max_board; ctrl++) {
 563                 if (rcktpt_io_addr[ctrl] <= 0)
 564                         continue;
 565
 566                 /*  Get a ptr to the board's control struct */
 567                 ctlp = sCtlNumToCtlPtr(ctrl);
 568
 569                 /*  Get the interrupt status from the board */
 570 #ifdef CONFIG_PCI
 571                 if (ctlp->BusType == isPCI)
 572                         CtlMask = sPCIGetControllerIntStatus(ctlp);
 573                 else
 574 #endif
 575                         CtlMask = sGetControllerIntStatus(ctlp);
 576
 577                 /*  Check if any AIOP read bits are set */
 578                 for (aiop = 0; CtlMask; aiop++) {
 579                         bit = ctlp->AiopIntrBits[aiop];
 580                         if (CtlMask & bit) {
 581                                 CtlMask &= ~bit;
 582                                 AiopMask = sGetAiopIntStatus(ctlp, aiop);
 583
 584                                 /*  Check if any port read bits are set */
 585                                 for (ch = 0; AiopMask;  AiopMask >>= 1, ch++) {
 586                                         if (AiopMask & 1) {
 587
 588                                                 /*  Get the line number (/dev/ttyRx number). */
 589                                                 /*  Read the data from the port. */
 590                                                 line = GetLineNumber(ctrl, aiop, ch);
 591                                                 rp_handle_port(rp_table[line]);
 592                                         }
 593                                 }
 594                         }
 595                 }
 596
 597                 xmitmask = xmit_flags[ctrl];
 598
 599                 /*
 600                  *  xmit_flags contains bit-significant flags, indicating there is data
 601                  *  to xmit on the port. Bit 0 is port 0 on this board, bit 1 is port
 602                  *  1, ... (32 total possible).  The variable i has the aiop and ch
 603                  *  numbers encoded in it (port 0-7 are aiop0, 8-15 are aiop1, etc).
 604                  */
 605                 if (xmitmask) {
 606                         for (i = 0; i < rocketModel[ctrl].numPorts; i++) {
 607                                 if (xmitmask & (1 << i)) {
 608                                         aiop = (i & 0x18) >> 3;
 609                                         ch = i & 0x07;
 610                                         line = GetLineNumber(ctrl, aiop, ch);
 611                                         rp_do_transmit(rp_table[line]);
 612                                 }
 613                         }
 614                 }
 615         }
 616
 617         /*
 618          * Reset the timer so we get called at the next clock tick (10ms).
 619          */
 620         if (atomic_read(&rp_num_ports_open))
 621                 mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
 622 }
 623
 624 /*
 625  *  Initializes the r_port structure for a port, as well as enabling the port on
 626  *  the board.
 627  *  Inputs:  board, aiop, chan numbers
 628  */
 629 static void init_r_port(int board, int aiop, int chan, struct pci_dev *pci_dev)
 630 {
 631         unsigned rocketMode;
 632         struct r_port *info;
 633         int line;
 634         CONTROLLER_T *ctlp;
 635
 636         /*  Get the next available line number */
 637         line = SetLineNumber(board, aiop, chan);
 638
 639         ctlp = sCtlNumToCtlPtr(board);
 640
 641         /*  Get a r_port struct for the port, fill it in and save it globally, indexed by line number */
 642         info = kzalloc(sizeof (struct r_port), GFP_KERNEL);
 643         if (!info) {
 644                 printk(KERN_ERR "Couldn't allocate info struct for line #%d\n",
 645                                 line);
 646                 return;
 647         }
 648
 649         info->magic = RPORT_MAGIC;
 650         info->line = line;
 651         info->ctlp = ctlp;
 652         info->board = board;
 653         info->aiop = aiop;
 654         info->chan = chan;
 655         tty_port_init(&info->port);
 656         info->port.ops = &rocket_port_ops;
 657         init_completion(&info->close_wait);
 658         info->flags &= ~ROCKET_MODE_MASK;
 659         switch (pc104[board][line]) {
 660         case 422:
 661                 info->flags |= ROCKET_MODE_RS422;
 662                 break;
 663         case 485:
 664                 info->flags |= ROCKET_MODE_RS485;
 665                 break;
 666         case 232:
 667         default:
 668                 info->flags |= ROCKET_MODE_RS232;
 669                 break;
 670         }
 671
 672         info->intmask = RXF_TRIG | TXFIFO_MT | SRC_INT | DELTA_CD | DELTA_CTS | DELTA_DSR;
 673         if (sInitChan(ctlp, &info->channel, aiop, chan) == 0) {
 674                 printk(KERN_ERR "RocketPort sInitChan(%d, %d, %d) failed!\n",
 675                                 board, aiop, chan);
 676                 kfree(info);
 677                 return;
 678         }
 679
 680         rocketMode = info->flags & ROCKET_MODE_MASK;
 681
 682         if ((info->flags & ROCKET_RTS_TOGGLE) || (rocketMode == ROCKET_MODE_RS485))
 683                 sEnRTSToggle(&info->channel);
 684         else
 685                 sDisRTSToggle(&info->channel);
 686
 687         if (ctlp->boardType == ROCKET_TYPE_PC104) {
 688                 switch (rocketMode) {
 689                 case ROCKET_MODE_RS485:
 690                         sSetInterfaceMode(&info->channel, InterfaceModeRS485);
 691                         break;
 692                 case ROCKET_MODE_RS422:
 693                         sSetInterfaceMode(&info->channel, InterfaceModeRS422);
 694                         break;
 695                 case ROCKET_MODE_RS232:
 696                 default:
 697                         if (info->flags & ROCKET_RTS_TOGGLE)
 698                                 sSetInterfaceMode(&info->channel, InterfaceModeRS232T);
 699                         else
 700                                 sSetInterfaceMode(&info->channel, InterfaceModeRS232);
 701                         break;
 702                 }
 703         }
 704         spin_lock_init(&info->slock);
 705         mutex_init(&info->write_mtx);
 706         rp_table[line] = info;
 707         tty_register_device(rocket_driver, line, pci_dev ? &pci_dev->dev :
 708                         NULL);
 709 }
 710
 711 /*
 712  *  Configures a rocketport port according to its termio settings.  Called from
 713  *  user mode into the driver (exception handler).  *info CD manipulation is spinlock protected.
 714  */
 715 static void configure_r_port(struct tty_struct *tty, struct r_port *info,
 716                              struct ktermios *old_termios)
 717 {
 718         unsigned cflag;
 719         unsigned long flags;
 720         unsigned rocketMode;
 721         int bits, baud, divisor;
 722         CHANNEL_t *cp;
 723         struct ktermios *t = tty->termios;
 724
 725         cp = &info->channel;
 726         cflag = t->c_cflag;
 727
 728         /* Byte size and parity */
 729         if ((cflag & CSIZE) == CS8) {
 730                 sSetData8(cp);
 731                 bits = 10;
 732         } else {
 733                 sSetData7(cp);
 734                 bits = 9;
 735         }
 736         if (cflag & CSTOPB) {
 737                 sSetStop2(cp);
 738                 bits++;
 739         } else {
 740                 sSetStop1(cp);
 741         }
 742
 743         if (cflag & PARENB) {
 744                 sEnParity(cp);
 745                 bits++;
 746                 if (cflag & PARODD) {
 747                         sSetOddParity(cp);
 748                 } else {
 749                         sSetEvenParity(cp);
 750                 }
 751         } else {
 752                 sDisParity(cp);
 753         }
 754
 755         /* baud rate */
 756         baud = tty_get_baud_rate(tty);
 757         if (!baud)
 758                 baud = 9600;
 759         divisor = ((rp_baud_base[info->board] + (baud >> 1)) / baud) - 1;
 760         if ((divisor >= 8192 || divisor < 0) && old_termios) {
 761                 baud = tty_termios_baud_rate(old_termios);
 762                 if (!baud)
 763                         baud = 9600;
 764                 divisor = (rp_baud_base[info->board] / baud) - 1;
 765         }
 766         if (divisor >= 8192 || divisor < 0) {
 767                 baud = 9600;
 768                 divisor = (rp_baud_base[info->board] / baud) - 1;
 769         }
 770         info->cps = baud / bits;
 771         sSetBaud(cp, divisor);
 772
 773         /* FIXME: Should really back compute a baud rate from the divisor */
 774         tty_encode_baud_rate(tty, baud, baud);
 775
 776         if (cflag & CRTSCTS) {
 777                 info->intmask |= DELTA_CTS;
 778                 sEnCTSFlowCtl(cp);
 779         } else {
 780                 info->intmask &= ~DELTA_CTS;
 781                 sDisCTSFlowCtl(cp);
 782         }
 783         if (cflag & CLOCAL) {
 784                 info->intmask &= ~DELTA_CD;
 785         } else {
 786                 spin_lock_irqsave(&info->slock, flags);
 787                 if (sGetChanStatus(cp) & CD_ACT)
 788                         info->cd_status = 1;
 789                 else
 790                         info->cd_status = 0;
 791                 info->intmask |= DELTA_CD;
 792                 spin_unlock_irqrestore(&info->slock, flags);
 793         }
 794
 795         /*
 796          * Handle software flow control in the board
 797          */
 798 #ifdef ROCKET_SOFT_FLOW
 799         if (I_IXON(tty)) {
 800                 sEnTxSoftFlowCtl(cp);
 801                 if (I_IXANY(tty)) {
 802                         sEnIXANY(cp);
 803                 } else {
 804                         sDisIXANY(cp);
 805                 }
 806                 sSetTxXONChar(cp, START_CHAR(tty));
 807                 sSetTxXOFFChar(cp, STOP_CHAR(tty));
 808         } else {
 809                 sDisTxSoftFlowCtl(cp);
 810                 sDisIXANY(cp);
 811                 sClrTxXOFF(cp);
 812         }
 813 #endif
 814
 815         /*
 816          * Set up ignore/read mask words
 817          */
 818         info->read_status_mask = STMRCVROVRH | 0xFF;
 819         if (I_INPCK(tty))
 820                 info->read_status_mask |= STMFRAMEH | STMPARITYH;
 821         if (I_BRKINT(tty) || I_PARMRK(tty))
 822                 info->read_status_mask |= STMBREAKH;
 823
 824         /*
 825          * Characters to ignore
 826          */
 827         info->ignore_status_mask = 0;
 828         if (I_IGNPAR(tty))
 829                 info->ignore_status_mask |= STMFRAMEH | STMPARITYH;
 830         if (I_IGNBRK(tty)) {
 831                 info->ignore_status_mask |= STMBREAKH;
 832                 /*
 833                  * If we're ignoring parity and break indicators,
 834                  * ignore overruns too.  (For real raw support).
 835                  */
 836                 if (I_IGNPAR(tty))
 837                         info->ignore_status_mask |= STMRCVROVRH;
 838         }
 839
 840         rocketMode = info->flags & ROCKET_MODE_MASK;
 841
 842         if ((info->flags & ROCKET_RTS_TOGGLE)
 843             || (rocketMode == ROCKET_MODE_RS485))
 844                 sEnRTSToggle(cp);
 845         else
 846                 sDisRTSToggle(cp);
 847
 848         sSetRTS(&info->channel);
 849
 850         if (cp->CtlP->boardType == ROCKET_TYPE_PC104) {
 851                 switch (rocketMode) {
 852                 case ROCKET_MODE_RS485:
 853                         sSetInterfaceMode(cp, InterfaceModeRS485);
 854                         break;
 855                 case ROCKET_MODE_RS422:
 856                         sSetInterfaceMode(cp, InterfaceModeRS422);
 857                         break;
 858                 case ROCKET_MODE_RS232:
 859                 default:
 860                         if (info->flags & ROCKET_RTS_TOGGLE)
 861                                 sSetInterfaceMode(cp, InterfaceModeRS232T);
 862                         else
 863                                 sSetInterfaceMode(cp, InterfaceModeRS232);
 864                         break;
 865                 }
 866         }
 867 }
 868
 869 static int carrier_raised(struct tty_port *port)
 870 {
 871         struct r_port *info = container_of(port, struct r_port, port);
 872         return (sGetChanStatusLo(&info->channel) & CD_ACT) ? 1 : 0;
 873 }
 874
 875 static void dtr_rts(struct tty_port *port, int on)
 876 {
 877         struct r_port *info = container_of(port, struct r_port, port);
 878         if (on) {
 879                 sSetDTR(&info->channel);
 880                 sSetRTS(&info->channel);
 881         } else {
 882                 sClrDTR(&info->channel);
 883                 sClrRTS(&info->channel);
 884         }
 885 }
 886
 887 /*
 888  *  Exception handler that opens a serial port.  Creates xmit_buf storage, fills in
 889  *  port's r_port struct.  Initializes the port hardware.
 890  */
 891 static int rp_open(struct tty_struct *tty, struct file *filp)
 892 {
 893         struct r_port *info;
 894         struct tty_port *port;
 895         int line = 0, retval;
 896         CHANNEL_t *cp;
 897         unsigned long page;
 898
 899         line = tty->index;
 900         if (line < 0 || line >= MAX_RP_PORTS || ((info = rp_table[line]) == NULL))
 901                 return -ENXIO;
 902         port = &info->port;
 903
 904         page = __get_free_page(GFP_KERNEL);
 905         if (!page)
 906                 return -ENOMEM;
 907
 908         if (port->flags & ASYNC_CLOSING) {
 909                 retval = wait_for_completion_interruptible(&info->close_wait);
 910                 free_page(page);
 911                 if (retval)
 912                         return retval;
 913                 return ((port->flags & ASYNC_HUP_NOTIFY) ? -EAGAIN : -ERESTARTSYS);
 914         }
 915
 916         /*
 917          * We must not sleep from here until the port is marked fully in use.
 918          */
 919         if (info->xmit_buf)
 920                 free_page(page);
 921         else
 922                 info->xmit_buf = (unsigned char *) page;
 923
 924         tty->driver_data = info;
 925         tty_port_tty_set(port, tty);
 926
 927         if (port->count++ == 0) {
 928                 atomic_inc(&rp_num_ports_open);
 929
 930 #ifdef ROCKET_DEBUG_OPEN
 931                 printk(KERN_INFO "rocket mod++ = %d...\n",
 932                                 atomic_read(&rp_num_ports_open));
 933 #endif
 934         }
 935 #ifdef ROCKET_DEBUG_OPEN
 936         printk(KERN_INFO "rp_open ttyR%d, count=%d\n", info->line, info->port.count);
 937 #endif
 938
 939         /*
 940          * Info->count is now 1; so it's safe to sleep now.
 941          */
 942         if (!test_bit(ASYNCB_INITIALIZED, &port->flags)) {
 943                 cp = &info->channel;
 944                 sSetRxTrigger(cp, TRIG_1);
 945                 if (sGetChanStatus(cp) & CD_ACT)
 946                         info->cd_status = 1;
 947                 else
 948                         info->cd_status = 0;
 949                 sDisRxStatusMode(cp);
 950                 sFlushRxFIFO(cp);
 951                 sFlushTxFIFO(cp);
 952
 953                 sEnInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
 954                 sSetRxTrigger(cp, TRIG_1);
 955
 956                 sGetChanStatus(cp);
 957                 sDisRxStatusMode(cp);
 958                 sClrTxXOFF(cp);
 959
 960                 sDisCTSFlowCtl(cp);
 961                 sDisTxSoftFlowCtl(cp);
 962
 963                 sEnRxFIFO(cp);
 964                 sEnTransmit(cp);
 965
 966                 set_bit(ASYNCB_INITIALIZED, &info->port.flags);
 967
 968                 /*
 969                  * Set up the tty->alt_speed kludge
 970                  */
 971                 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
 972                         tty->alt_speed = 57600;
 973                 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
 974                         tty->alt_speed = 115200;
 975                 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
 976                         tty->alt_speed = 230400;
 977                 if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
 978                         tty->alt_speed = 460800;
 979
 980                 configure_r_port(tty, info, NULL);
 981                 if (tty->termios->c_cflag & CBAUD) {
 982                         sSetDTR(cp);
 983                         sSetRTS(cp);
 984                 }
 985         }
 986         /*  Starts (or resets) the maint polling loop */
 987         mod_timer(&rocket_timer, jiffies + POLL_PERIOD);
 988
 989         retval = tty_port_block_til_ready(port, tty, filp);
 990         if (retval) {
 991 #ifdef ROCKET_DEBUG_OPEN
 992                 printk(KERN_INFO "rp_open returning after block_til_ready with %d\n", retval);
 993 #endif
 994                 return retval;
 995         }
 996         return 0;
 997 }
 998
 999 /*
1000  *  Exception handler that closes a serial port. info->port.count is considered critical.
1001  */
1002 static void rp_close(struct tty_struct *tty, struct file *filp)
1003 {
1004         struct r_port *info = tty->driver_data;
1005         struct tty_port *port = &info->port;
1006         int timeout;
1007         CHANNEL_t *cp;
1008
1009         if (rocket_paranoia_check(info, "rp_close"))
1010                 return;
1011
1012 #ifdef ROCKET_DEBUG_OPEN
1013         printk(KERN_INFO "rp_close ttyR%d, count = %d\n", info->line, info->port.count);
1014 #endif
1015
1016         if (tty_port_close_start(port, tty, filp) == 0)
1017                 return;
1018
1019         mutex_lock(&port->mutex);
1020         cp = &info->channel;
1021         /*
1022          * Before we drop DTR, make sure the UART transmitter
1023          * has completely drained; this is especially
1024          * important if there is a transmit FIFO!
1025          */
1026         timeout = (sGetTxCnt(cp) + 1) * HZ / info->cps;
1027         if (timeout == 0)
1028                 timeout = 1;
1029         rp_wait_until_sent(tty, timeout);
1030         clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1031
1032         sDisTransmit(cp);
1033         sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1034         sDisCTSFlowCtl(cp);
1035         sDisTxSoftFlowCtl(cp);
1036         sClrTxXOFF(cp);
1037         sFlushRxFIFO(cp);
1038         sFlushTxFIFO(cp);
1039         sClrRTS(cp);
1040         if (C_HUPCL(tty))
1041                 sClrDTR(cp);
1042
1043         rp_flush_buffer(tty);
1044
1045         tty_ldisc_flush(tty);
1046
1047         clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1048
1049         /* We can't yet use tty_port_close_end as the buffer handling in this
1050            driver is a bit different to the usual */
1051
1052         if (port->blocked_open) {
1053                 if (port->close_delay) {
1054                         msleep_interruptible(jiffies_to_msecs(port->close_delay));
1055                 }
1056                 wake_up_interruptible(&port->open_wait);
1057         } else {
1058                 if (info->xmit_buf) {
1059                         free_page((unsigned long) info->xmit_buf);
1060                         info->xmit_buf = NULL;
1061                 }
1062         }
1063         spin_lock_irq(&port->lock);
1064         info->port.flags &= ~(ASYNC_INITIALIZED | ASYNC_CLOSING | ASYNC_NORMAL_ACTIVE);
1065         tty->closing = 0;
1066         spin_unlock_irq(&port->lock);
1067         mutex_unlock(&port->mutex);
1068         tty_port_tty_set(port, NULL);
1069
1070         wake_up_interruptible(&port->close_wait);
1071         complete_all(&info->close_wait);
1072         atomic_dec(&rp_num_ports_open);
1073
1074 #ifdef ROCKET_DEBUG_OPEN
1075         printk(KERN_INFO "rocket mod-- = %d...\n",
1076                         atomic_read(&rp_num_ports_open));
1077         printk(KERN_INFO "rp_close ttyR%d complete shutdown\n", info->line);
1078 #endif
1079
1080 }
1081
1082 static void rp_set_termios(struct tty_struct *tty,
1083                            struct ktermios *old_termios)
1084 {
1085         struct r_port *info = tty->driver_data;
1086         CHANNEL_t *cp;
1087         unsigned cflag;
1088
1089         if (rocket_paranoia_check(info, "rp_set_termios"))
1090                 return;
1091
1092         cflag = tty->termios->c_cflag;
1093
1094         /*
1095          * This driver doesn't support CS5 or CS6
1096          */
1097         if (((cflag & CSIZE) == CS5) || ((cflag & CSIZE) == CS6))
1098                 tty->termios->c_cflag =
1099                     ((cflag & ~CSIZE) | (old_termios->c_cflag & CSIZE));
1100         /* Or CMSPAR */
1101         tty->termios->c_cflag &= ~CMSPAR;
1102
1103         configure_r_port(tty, info, old_termios);
1104
1105         cp = &info->channel;
1106
1107         /* Handle transition to B0 status */
1108         if ((old_termios->c_cflag & CBAUD) && !(tty->termios->c_cflag & CBAUD)) {
1109                 sClrDTR(cp);
1110                 sClrRTS(cp);
1111         }
1112
1113         /* Handle transition away from B0 status */
1114         if (!(old_termios->c_cflag & CBAUD) && (tty->termios->c_cflag & CBAUD)) {
1115                 if (!tty->hw_stopped || !(tty->termios->c_cflag & CRTSCTS))
1116                         sSetRTS(cp);
1117                 sSetDTR(cp);
1118         }
1119
1120         if ((old_termios->c_cflag & CRTSCTS) && !(tty->termios->c_cflag & CRTSCTS)) {
1121                 tty->hw_stopped = 0;
1122                 rp_start(tty);
1123         }
1124 }
1125
1126 static int rp_break(struct tty_struct *tty, int break_state)
1127 {
1128         struct r_port *info = tty->driver_data;
1129         unsigned long flags;
1130
1131         if (rocket_paranoia_check(info, "rp_break"))
1132                 return -EINVAL;
1133
1134         spin_lock_irqsave(&info->slock, flags);
1135         if (break_state == -1)
1136                 sSendBreak(&info->channel);
1137         else
1138                 sClrBreak(&info->channel);
1139         spin_unlock_irqrestore(&info->slock, flags);
1140         return 0;
1141 }
1142
1143 /*
1144  * sGetChanRI used to be a macro in rocket_int.h. When the functionality for
1145  * the UPCI boards was added, it was decided to make this a function because
1146  * the macro was getting too complicated. All cases except the first one
1147  * (UPCIRingInd) are taken directly from the original macro.
1148  */
1149 static int sGetChanRI(CHANNEL_T * ChP)
1150 {
1151         CONTROLLER_t *CtlP = ChP->CtlP;
1152         int ChanNum = ChP->ChanNum;
1153         int RingInd = 0;
1154
1155         if (CtlP->UPCIRingInd)
1156                 RingInd = !(sInB(CtlP->UPCIRingInd) & sBitMapSetTbl[ChanNum]);
1157         else if (CtlP->AltChanRingIndicator)
1158                 RingInd = sInB((ByteIO_t) (ChP->ChanStat + 8)) & DSR_ACT;
1159         else if (CtlP->boardType == ROCKET_TYPE_PC104)
1160                 RingInd = !(sInB(CtlP->AiopIO[3]) & sBitMapSetTbl[ChanNum]);
1161
1162         return RingInd;
1163 }
1164
1165 /********************************************************************************************/
1166 /*  Here are the routines used by rp_ioctl.  These are all called from exception handlers.  */
1167
1168 /*
1169  *  Returns the state of the serial modem control lines.  These next 2 functions
1170  *  are the way kernel versions > 2.5 handle modem control lines rather than IOCTLs.
1171  */
1172 static int rp_tiocmget(struct tty_struct *tty, struct file *file)
1173 {
1174         struct r_port *info = tty->driver_data;
1175         unsigned int control, result, ChanStatus;
1176
1177         ChanStatus = sGetChanStatusLo(&info->channel);
1178         control = info->channel.TxControl[3];
1179         result = ((control & SET_RTS) ? TIOCM_RTS : 0) |
1180                 ((control & SET_DTR) ?  TIOCM_DTR : 0) |
1181                 ((ChanStatus & CD_ACT) ? TIOCM_CAR : 0) |
1182                 (sGetChanRI(&info->channel) ? TIOCM_RNG : 0) |
1183                 ((ChanStatus & DSR_ACT) ? TIOCM_DSR : 0) |
1184                 ((ChanStatus & CTS_ACT) ? TIOCM_CTS : 0);
1185
1186         return result;
1187 }
1188
1189 /*
1190  *  Sets the modem control lines
1191  */
1192 static int rp_tiocmset(struct tty_struct *tty, struct file *file,
1193                     unsigned int set, unsigned int clear)
1194 {
1195         struct r_port *info = tty->driver_data;
1196
1197         if (set & TIOCM_RTS)
1198                 info->channel.TxControl[3] |= SET_RTS;
1199         if (set & TIOCM_DTR)
1200                 info->channel.TxControl[3] |= SET_DTR;
1201         if (clear & TIOCM_RTS)
1202                 info->channel.TxControl[3] &= ~SET_RTS;
1203         if (clear & TIOCM_DTR)
1204                 info->channel.TxControl[3] &= ~SET_DTR;
1205
1206         out32(info->channel.IndexAddr, info->channel.TxControl);
1207         return 0;
1208 }
1209
1210 static int get_config(struct r_port *info, struct rocket_config __user *retinfo)
1211 {
1212         struct rocket_config tmp;
1213
1214         if (!retinfo)
1215                 return -EFAULT;
1216         memset(&tmp, 0, sizeof (tmp));
1217         mutex_lock(&info->port.mutex);
1218         tmp.line = info->line;
1219         tmp.flags = info->flags;
1220         tmp.close_delay = info->port.close_delay;
1221         tmp.closing_wait = info->port.closing_wait;
1222         tmp.port = rcktpt_io_addr[(info->line >> 5) & 3];
1223         mutex_unlock(&info->port.mutex);
1224
1225         if (copy_to_user(retinfo, &tmp, sizeof (*retinfo)))
1226                 return -EFAULT;
1227         return 0;
1228 }
1229
1230 static int set_config(struct tty_struct *tty, struct r_port *info,
1231                                         struct rocket_config __user *new_info)
1232 {
1233         struct rocket_config new_serial;
1234
1235         if (copy_from_user(&new_serial, new_info, sizeof (new_serial)))
1236                 return -EFAULT;
1237
1238         mutex_lock(&info->port.mutex);
1239         if (!capable(CAP_SYS_ADMIN))
1240         {
1241                 if ((new_serial.flags & ~ROCKET_USR_MASK) != (info->flags & ~ROCKET_USR_MASK)) {
1242                         mutex_unlock(&info->port.mutex);
1243                         return -EPERM;
1244                 }
1245                 info->flags = ((info->flags & ~ROCKET_USR_MASK) | (new_serial.flags & ROCKET_USR_MASK));
1246                 configure_r_port(tty, info, NULL);
1247                 mutex_unlock(&info->port.mutex);
1248                 return 0;
1249         }
1250
1251         info->flags = ((info->flags & ~ROCKET_FLAGS) | (new_serial.flags & ROCKET_FLAGS));
1252         info->port.close_delay = new_serial.close_delay;
1253         info->port.closing_wait = new_serial.closing_wait;
1254
1255         if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_HI)
1256                 tty->alt_speed = 57600;
1257         if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_VHI)
1258                 tty->alt_speed = 115200;
1259         if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_SHI)
1260                 tty->alt_speed = 230400;
1261         if ((info->flags & ROCKET_SPD_MASK) == ROCKET_SPD_WARP)
1262                 tty->alt_speed = 460800;
1263         mutex_unlock(&info->port.mutex);
1264
1265         configure_r_port(tty, info, NULL);
1266         return 0;
1267 }
1268
1269 /*
1270  *  This function fills in a rocket_ports struct with information
1271  *  about what boards/ports are in the system.  This info is passed
1272  *  to user space.  See setrocket.c where the info is used to create
1273  *  the /dev/ttyRx ports.
1274  */
1275 static int get_ports(struct r_port *info, struct rocket_ports __user *retports)
1276 {
1277         struct rocket_ports tmp;
1278         int board;
1279
1280         if (!retports)
1281                 return -EFAULT;
1282         memset(&tmp, 0, sizeof (tmp));
1283         tmp.tty_major = rocket_driver->major;
1284
1285         for (board = 0; board < 4; board++) {
1286                 tmp.rocketModel[board].model = rocketModel[board].model;
1287                 strcpy(tmp.rocketModel[board].modelString, rocketModel[board].modelString);
1288                 tmp.rocketModel[board].numPorts = rocketModel[board].numPorts;
1289                 tmp.rocketModel[board].loadrm2 = rocketModel[board].loadrm2;
1290                 tmp.rocketModel[board].startingPortNumber = rocketModel[board].startingPortNumber;
1291         }
1292         if (copy_to_user(retports, &tmp, sizeof (*retports)))
1293                 return -EFAULT;
1294         return 0;
1295 }
1296
1297 static int reset_rm2(struct r_port *info, void __user *arg)
1298 {
1299         int reset;
1300
1301         if (!capable(CAP_SYS_ADMIN))
1302                 return -EPERM;
1303
1304         if (copy_from_user(&reset, arg, sizeof (int)))
1305                 return -EFAULT;
1306         if (reset)
1307                 reset = 1;
1308
1309         if (rcktpt_type[info->board] != ROCKET_TYPE_MODEMII &&
1310             rcktpt_type[info->board] != ROCKET_TYPE_MODEMIII)
1311                 return -EINVAL;
1312
1313         if (info->ctlp->BusType == isISA)
1314                 sModemReset(info->ctlp, info->chan, reset);
1315         else
1316                 sPCIModemReset(info->ctlp, info->chan, reset);
1317
1318         return 0;
1319 }
1320
1321 static int get_version(struct r_port *info, struct rocket_version __user *retvers)
1322 {
1323         if (copy_to_user(retvers, &driver_version, sizeof (*retvers)))
1324                 return -EFAULT;
1325         return 0;
1326 }
1327
1328 /*  IOCTL call handler into the driver */
1329 static int rp_ioctl(struct tty_struct *tty, struct file *file,
1330                     unsigned int cmd, unsigned long arg)
1331 {
1332         struct r_port *info = tty->driver_data;
1333         void __user *argp = (void __user *)arg;
1334         int ret = 0;
1335
1336         if (cmd != RCKP_GET_PORTS && rocket_paranoia_check(info, "rp_ioctl"))
1337                 return -ENXIO;
1338
1339         switch (cmd) {
1340         case RCKP_GET_STRUCT:
1341                 if (copy_to_user(argp, info, sizeof (struct r_port)))
1342                         ret = -EFAULT;
1343                 break;
1344         case RCKP_GET_CONFIG:
1345                 ret = get_config(info, argp);
1346                 break;
1347         case RCKP_SET_CONFIG:
1348                 ret = set_config(tty, info, argp);
1349                 break;
1350         case RCKP_GET_PORTS:
1351                 ret = get_ports(info, argp);
1352                 break;
1353         case RCKP_RESET_RM2:
1354                 ret = reset_rm2(info, argp);
1355                 break;
1356         case RCKP_GET_VERSION:
1357                 ret = get_version(info, argp);
1358                 break;
1359         default:
1360                 ret = -ENOIOCTLCMD;
1361         }
1362         return ret;
1363 }
1364
1365 static void rp_send_xchar(struct tty_struct *tty, char ch)
1366 {
1367         struct r_port *info = tty->driver_data;
1368         CHANNEL_t *cp;
1369
1370         if (rocket_paranoia_check(info, "rp_send_xchar"))
1371                 return;
1372
1373         cp = &info->channel;
1374         if (sGetTxCnt(cp))
1375                 sWriteTxPrioByte(cp, ch);
1376         else
1377                 sWriteTxByte(sGetTxRxDataIO(cp), ch);
1378 }
1379
1380 static void rp_throttle(struct tty_struct *tty)
1381 {
1382         struct r_port *info = tty->driver_data;
1383         CHANNEL_t *cp;
1384
1385 #ifdef ROCKET_DEBUG_THROTTLE
1386         printk(KERN_INFO "throttle %s: %d....\n", tty->name,
1387                tty->ldisc.chars_in_buffer(tty));
1388 #endif
1389
1390         if (rocket_paranoia_check(info, "rp_throttle"))
1391                 return;
1392
1393         cp = &info->channel;
1394         if (I_IXOFF(tty))
1395                 rp_send_xchar(tty, STOP_CHAR(tty));
1396
1397         sClrRTS(&info->channel);
1398 }
1399
1400 static void rp_unthrottle(struct tty_struct *tty)
1401 {
1402         struct r_port *info = tty->driver_data;
1403         CHANNEL_t *cp;
1404 #ifdef ROCKET_DEBUG_THROTTLE
1405         printk(KERN_INFO "unthrottle %s: %d....\n", tty->name,
1406                tty->ldisc.chars_in_buffer(tty));
1407 #endif
1408
1409         if (rocket_paranoia_check(info, "rp_throttle"))
1410                 return;
1411
1412         cp = &info->channel;
1413         if (I_IXOFF(tty))
1414                 rp_send_xchar(tty, START_CHAR(tty));
1415
1416         sSetRTS(&info->channel);
1417 }
1418
1419 /*
1420  * ------------------------------------------------------------
1421  * rp_stop() and rp_start()
1422  *
1423  * This routines are called before setting or resetting tty->stopped.
1424  * They enable or disable transmitter interrupts, as necessary.
1425  * ------------------------------------------------------------
1426  */
1427 static void rp_stop(struct tty_struct *tty)
1428 {
1429         struct r_port *info = tty->driver_data;
1430
1431 #ifdef ROCKET_DEBUG_FLOW
1432         printk(KERN_INFO "stop %s: %d %d....\n", tty->name,
1433                info->xmit_cnt, info->xmit_fifo_room);
1434 #endif
1435
1436         if (rocket_paranoia_check(info, "rp_stop"))
1437                 return;
1438
1439         if (sGetTxCnt(&info->channel))
1440                 sDisTransmit(&info->channel);
1441 }
1442
1443 static void rp_start(struct tty_struct *tty)
1444 {
1445         struct r_port *info = tty->driver_data;
1446
1447 #ifdef ROCKET_DEBUG_FLOW
1448         printk(KERN_INFO "start %s: %d %d....\n", tty->name,
1449                info->xmit_cnt, info->xmit_fifo_room);
1450 #endif
1451
1452         if (rocket_paranoia_check(info, "rp_stop"))
1453                 return;
1454
1455         sEnTransmit(&info->channel);
1456         set_bit((info->aiop * 8) + info->chan,
1457                 (void *) &xmit_flags[info->board]);
1458 }
1459
1460 /*
1461  * rp_wait_until_sent() --- wait until the transmitter is empty
1462  */
1463 static void rp_wait_until_sent(struct tty_struct *tty, int timeout)
1464 {
1465         struct r_port *info = tty->driver_data;
1466         CHANNEL_t *cp;
1467         unsigned long orig_jiffies;
1468         int check_time, exit_time;
1469         int txcnt;
1470
1471         if (rocket_paranoia_check(info, "rp_wait_until_sent"))
1472                 return;
1473
1474         cp = &info->channel;
1475
1476         orig_jiffies = jiffies;
1477 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1478         printk(KERN_INFO "In RP_wait_until_sent(%d) (jiff=%lu)...\n", timeout,
1479                jiffies);
1480         printk(KERN_INFO "cps=%d...\n", info->cps);
1481 #endif
1482         while (1) {
1483                 txcnt = sGetTxCnt(cp);
1484                 if (!txcnt) {
1485                         if (sGetChanStatusLo(cp) & TXSHRMT)
1486                                 break;
1487                         check_time = (HZ / info->cps) / 5;
1488                 } else {
1489                         check_time = HZ * txcnt / info->cps;
1490                 }
1491                 if (timeout) {
1492                         exit_time = orig_jiffies + timeout - jiffies;
1493                         if (exit_time <= 0)
1494                                 break;
1495                         if (exit_time < check_time)
1496                                 check_time = exit_time;
1497                 }
1498                 if (check_time == 0)
1499                         check_time = 1;
1500 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1501                 printk(KERN_INFO "txcnt = %d (jiff=%lu,check=%d)...\n", txcnt,
1502                                 jiffies, check_time);
1503 #endif
1504                 msleep_interruptible(jiffies_to_msecs(check_time));
1505                 if (signal_pending(current))
1506                         break;
1507         }
1508         __set_current_state(TASK_RUNNING);
1509 #ifdef ROCKET_DEBUG_WAIT_UNTIL_SENT
1510         printk(KERN_INFO "txcnt = %d (jiff=%lu)...done\n", txcnt, jiffies);
1511 #endif
1512 }
1513
1514 /*
1515  * rp_hangup() --- called by tty_hangup() when a hangup is signaled.
1516  */
1517 static void rp_hangup(struct tty_struct *tty)
1518 {
1519         CHANNEL_t *cp;
1520         struct r_port *info = tty->driver_data;
1521         unsigned long flags;
1522
1523         if (rocket_paranoia_check(info, "rp_hangup"))
1524                 return;
1525
1526 #if (defined(ROCKET_DEBUG_OPEN) || defined(ROCKET_DEBUG_HANGUP))
1527         printk(KERN_INFO "rp_hangup of ttyR%d...\n", info->line);
1528 #endif
1529         rp_flush_buffer(tty);
1530         spin_lock_irqsave(&info->port.lock, flags);
1531         if (info->port.flags & ASYNC_CLOSING) {
1532                 spin_unlock_irqrestore(&info->port.lock, flags);
1533                 return;
1534         }
1535         if (info->port.count)
1536                 atomic_dec(&rp_num_ports_open);
1537         clear_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1538         spin_unlock_irqrestore(&info->port.lock, flags);
1539
1540         tty_port_hangup(&info->port);
1541
1542         cp = &info->channel;
1543         sDisRxFIFO(cp);
1544         sDisTransmit(cp);
1545         sDisInterrupts(cp, (TXINT_EN | MCINT_EN | RXINT_EN | SRCINT_EN | CHANINT_EN));
1546         sDisCTSFlowCtl(cp);
1547         sDisTxSoftFlowCtl(cp);
1548         sClrTxXOFF(cp);
1549         clear_bit(ASYNCB_INITIALIZED, &info->port.flags);
1550
1551         wake_up_interruptible(&info->port.open_wait);
1552 }
1553
1554 /*
1555  *  Exception handler - write char routine.  The RocketPort driver uses a
1556  *  double-buffering strategy, with the twist that if the in-memory CPU
1557  *  buffer is empty, and there's space in the transmit FIFO, the
1558  *  writing routines will write directly to transmit FIFO.
1559  *  Write buffer and counters protected by spinlocks
1560  */
1561 static int rp_put_char(struct tty_struct *tty, unsigned char ch)
1562 {
1563         struct r_port *info = tty->driver_data;
1564         CHANNEL_t *cp;
1565         unsigned long flags;
1566
1567         if (rocket_paranoia_check(info, "rp_put_char"))
1568                 return 0;
1569
1570         /*
1571          * Grab the port write mutex, locking out other processes that try to
1572          * write to this port
1573          */
1574         mutex_lock(&info->write_mtx);
1575
1576 #ifdef ROCKET_DEBUG_WRITE
1577         printk(KERN_INFO "rp_put_char %c...\n", ch);
1578 #endif
1579
1580         spin_lock_irqsave(&info->slock, flags);
1581         cp = &info->channel;
1582
1583         if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room == 0)
1584                 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1585
1586         if (tty->stopped || tty->hw_stopped || info->xmit_fifo_room == 0 || info->xmit_cnt != 0) {
1587                 info->xmit_buf[info->xmit_head++] = ch;
1588                 info->xmit_head &= XMIT_BUF_SIZE - 1;
1589                 info->xmit_cnt++;
1590                 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1591         } else {
1592                 sOutB(sGetTxRxDataIO(cp), ch);
1593                 info->xmit_fifo_room--;
1594         }
1595         spin_unlock_irqrestore(&info->slock, flags);
1596         mutex_unlock(&info->write_mtx);
1597         return 1;
1598 }
1599
1600 /*
1601  *  Exception handler - write routine, called when user app writes to the device.
1602  *  A per port write mutex is used to protect from another process writing to
1603  *  this port at the same time.  This other process could be running on the other CPU
1604  *  or get control of the CPU if the copy_from_user() blocks due to a page fault (swapped out).
1605  *  Spinlocks protect the info xmit members.
1606  */
1607 static int rp_write(struct tty_struct *tty,
1608                     const unsigned char *buf, int count)
1609 {
1610         struct r_port *info = tty->driver_data;
1611         CHANNEL_t *cp;
1612         const unsigned char *b;
1613         int c, retval = 0;
1614         unsigned long flags;
1615
1616         if (count <= 0 || rocket_paranoia_check(info, "rp_write"))
1617                 return 0;
1618
1619         if (mutex_lock_interruptible(&info->write_mtx))
1620                 return -ERESTARTSYS;
1621
1622 #ifdef ROCKET_DEBUG_WRITE
1623         printk(KERN_INFO "rp_write %d chars...\n", count);
1624 #endif
1625         cp = &info->channel;
1626
1627         if (!tty->stopped && !tty->hw_stopped && info->xmit_fifo_room < count)
1628                 info->xmit_fifo_room = TXFIFO_SIZE - sGetTxCnt(cp);
1629
1630         /*
1631          *  If the write queue for the port is empty, and there is FIFO space, stuff bytes
1632          *  into FIFO.  Use the write queue for temp storage.
1633          */
1634         if (!tty->stopped && !tty->hw_stopped && info->xmit_cnt == 0 && info->xmit_fifo_room > 0) {
1635                 c = min(count, info->xmit_fifo_room);
1636                 b = buf;
1637
1638                 /*  Push data into FIFO, 2 bytes at a time */
1639                 sOutStrW(sGetTxRxDataIO(cp), (unsigned short *) b, c / 2);
1640
1641                 /*  If there is a byte remaining, write it */
1642                 if (c & 1)
1643                         sOutB(sGetTxRxDataIO(cp), b[c - 1]);
1644
1645                 retval += c;
1646                 buf += c;
1647                 count -= c;
1648
1649                 spin_lock_irqsave(&info->slock, flags);
1650                 info->xmit_fifo_room -= c;
1651                 spin_unlock_irqrestore(&info->slock, flags);
1652         }
1653
1654         /* If count is zero, we wrote it all and are done */
1655         if (!count)
1656                 goto end;
1657
1658         /*  Write remaining data into the port's xmit_buf */
1659         while (1) {
1660                 /* Hung up ? */
1661                 if (!test_bit(ASYNCB_NORMAL_ACTIVE, &info->port.flags))
1662                         goto end;
1663                 c = min(count, XMIT_BUF_SIZE - info->xmit_cnt - 1);
1664                 c = min(c, XMIT_BUF_SIZE - info->xmit_head);
1665                 if (c <= 0)
1666                         break;
1667
1668                 b = buf;
1669                 memcpy(info->xmit_buf + info->xmit_head, b, c);
1670
1671                 spin_lock_irqsave(&info->slock, flags);
1672                 info->xmit_head =
1673                     (info->xmit_head + c) & (XMIT_BUF_SIZE - 1);
1674                 info->xmit_cnt += c;
1675                 spin_unlock_irqrestore(&info->slock, flags);
1676
1677                 buf += c;
1678                 count -= c;
1679                 retval += c;
1680         }
1681
1682         if ((retval > 0) && !tty->stopped && !tty->hw_stopped)
1683                 set_bit((info->aiop * 8) + info->chan, (void *) &xmit_flags[info->board]);
1684
1685 end:
1686         if (info->xmit_cnt < WAKEUP_CHARS) {
1687                 tty_wakeup(tty);
1688 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1689                 wake_up_interruptible(&tty->poll_wait);
1690 #endif
1691         }
1692         mutex_unlock(&info->write_mtx);
1693         return retval;
1694 }
1695
1696 /*
1697  * Return the number of characters that can be sent.  We estimate
1698  * only using the in-memory transmit buffer only, and ignore the
1699  * potential space in the transmit FIFO.
1700  */
1701 static int rp_write_room(struct tty_struct *tty)
1702 {
1703         struct r_port *info = tty->driver_data;
1704         int ret;
1705
1706         if (rocket_paranoia_check(info, "rp_write_room"))
1707                 return 0;
1708
1709         ret = XMIT_BUF_SIZE - info->xmit_cnt - 1;
1710         if (ret < 0)
1711                 ret = 0;
1712 #ifdef ROCKET_DEBUG_WRITE
1713         printk(KERN_INFO "rp_write_room returns %d...\n", ret);
1714 #endif
1715         return ret;
1716 }
1717
1718 /*
1719  * Return the number of characters in the buffer.  Again, this only
1720  * counts those characters in the in-memory transmit buffer.
1721  */
1722 static int rp_chars_in_buffer(struct tty_struct *tty)
1723 {
1724         struct r_port *info = tty->driver_data;
1725         CHANNEL_t *cp;
1726
1727         if (rocket_paranoia_check(info, "rp_chars_in_buffer"))
1728                 return 0;
1729
1730         cp = &info->channel;
1731
1732 #ifdef ROCKET_DEBUG_WRITE
1733         printk(KERN_INFO "rp_chars_in_buffer returns %d...\n", info->xmit_cnt);
1734 #endif
1735         return info->xmit_cnt;
1736 }
1737
1738 /*
1739  *  Flushes the TX fifo for a port, deletes data in the xmit_buf stored in the
1740  *  r_port struct for the port.  Note that spinlock are used to protect info members,
1741  *  do not call this function if the spinlock is already held.
1742  */
1743 static void rp_flush_buffer(struct tty_struct *tty)
1744 {
1745         struct r_port *info = tty->driver_data;
1746         CHANNEL_t *cp;
1747         unsigned long flags;
1748
1749         if (rocket_paranoia_check(info, "rp_flush_buffer"))
1750                 return;
1751
1752         spin_lock_irqsave(&info->slock, flags);
1753         info->xmit_cnt = info->xmit_head = info->xmit_tail = 0;
1754         spin_unlock_irqrestore(&info->slock, flags);
1755
1756 #ifdef ROCKETPORT_HAVE_POLL_WAIT
1757         wake_up_interruptible(&tty->poll_wait);
1758 #endif
1759         tty_wakeup(tty);
1760
1761         cp = &info->channel;
1762         sFlushTxFIFO(cp);
1763 }
1764
1765 #ifdef CONFIG_PCI
1766
1767 static struct pci_device_id __devinitdata rocket_pci_ids[] = {
1768         { PCI_DEVICE(PCI_VENDOR_ID_RP, PCI_ANY_ID) },
1769         { }
1770 };
1771 MODULE_DEVICE_TABLE(pci, rocket_pci_ids);
1772
1773 /*
1774  *  Called when a PCI card is found.  Retrieves and stores model information,
1775  *  init's aiopic and serial port hardware.
1776  *  Inputs:  i is the board number (0-n)
1777  */
1778 static __init int register_PCI(int i, struct pci_dev *dev)
1779 {
1780         int num_aiops, aiop, max_num_aiops, num_chan, chan;
1781         unsigned int aiopio[MAX_AIOPS_PER_BOARD];
1782         char *str, *board_type;
1783         CONTROLLER_t *ctlp;
1784
1785         int fast_clock = 0;
1786         int altChanRingIndicator = 0;
1787         int ports_per_aiop = 8;
1788         WordIO_t ConfigIO = 0;
1789         ByteIO_t UPCIRingInd = 0;
1790
1791         if (!dev || pci_enable_device(dev))
1792                 return 0;
1793
1794         rcktpt_io_addr[i] = pci_resource_start(dev, 0);
1795
1796         rcktpt_type[i] = ROCKET_TYPE_NORMAL;
1797         rocketModel[i].loadrm2 = 0;
1798         rocketModel[i].startingPortNumber = nextLineNumber;
1799
1800         /*  Depending on the model, set up some config variables */
1801         switch (dev->device) {
1802         case PCI_DEVICE_ID_RP4QUAD:
1803                 str = "Quadcable";
1804                 max_num_aiops = 1;
1805                 ports_per_aiop = 4;
1806                 rocketModel[i].model = MODEL_RP4QUAD;
1807                 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/quad cable");
1808                 rocketModel[i].numPorts = 4;
1809                 break;
1810         case PCI_DEVICE_ID_RP8OCTA:
1811                 str = "Octacable";
1812                 max_num_aiops = 1;
1813                 rocketModel[i].model = MODEL_RP8OCTA;
1814                 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable");
1815                 rocketModel[i].numPorts = 8;
1816                 break;
1817         case PCI_DEVICE_ID_URP8OCTA:
1818                 str = "Octacable";
1819                 max_num_aiops = 1;
1820                 rocketModel[i].model = MODEL_UPCI_RP8OCTA;
1821                 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable");
1822                 rocketModel[i].numPorts = 8;
1823                 break;
1824         case PCI_DEVICE_ID_RP8INTF:
1825                 str = "8";
1826                 max_num_aiops = 1;
1827                 rocketModel[i].model = MODEL_RP8INTF;
1828                 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F");
1829                 rocketModel[i].numPorts = 8;
1830                 break;
1831         case PCI_DEVICE_ID_URP8INTF:
1832                 str = "8";
1833                 max_num_aiops = 1;
1834                 rocketModel[i].model = MODEL_UPCI_RP8INTF;
1835                 strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F");
1836                 rocketModel[i].numPorts = 8;
1837                 break;
1838         case PCI_DEVICE_ID_RP8J:
1839                 str = "8J";
1840                 max_num_aiops = 1;
1841                 rocketModel[i].model = MODEL_RP8J;
1842                 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors");
1843                 rocketModel[i].numPorts = 8;
1844                 break;
1845         case PCI_DEVICE_ID_RP4J:
1846                 str = "4J";
1847                 max_num_aiops = 1;
1848                 ports_per_aiop = 4;
1849                 rocketModel[i].model = MODEL_RP4J;
1850                 strcpy(rocketModel[i].modelString, "RocketPort 4 port w/RJ45 connectors");
1851                 rocketModel[i].numPorts = 4;
1852                 break;
1853         case PCI_DEVICE_ID_RP8SNI:
1854                 str = "8 (DB78 Custom)";
1855                 max_num_aiops = 1;
1856                 rocketModel[i].model = MODEL_RP8SNI;
1857                 strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78");
1858                 rocketModel[i].numPorts = 8;
1859                 break;
1860         case PCI_DEVICE_ID_RP16SNI:
1861                 str = "16 (DB78 Custom)";
1862                 max_num_aiops = 2;
1863                 rocketModel[i].model = MODEL_RP16SNI;
1864                 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78");
1865                 rocketModel[i].numPorts = 16;
1866                 break;
1867         case PCI_DEVICE_ID_RP16INTF:
1868                 str = "16";
1869                 max_num_aiops = 2;
1870                 rocketModel[i].model = MODEL_RP16INTF;
1871                 strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F");
1872                 rocketModel[i].numPorts = 16;
1873                 break;
1874         case PCI_DEVICE_ID_URP16INTF:
1875                 str = "16";
1876                 max_num_aiops = 2;
1877                 rocketModel[i].model = MODEL_UPCI_RP16INTF;
1878                 strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F");
1879                 rocketModel[i].numPorts = 16;
1880                 break;
1881         case PCI_DEVICE_ID_CRP16INTF:
1882                 str = "16";
1883                 max_num_aiops = 2;
1884                 rocketModel[i].model = MODEL_CPCI_RP16INTF;
1885                 strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F");
1886                 rocketModel[i].numPorts = 16;
1887                 break;
1888         case PCI_DEVICE_ID_RP32INTF:
1889                 str = "32";
1890                 max_num_aiops = 4;
1891                 rocketModel[i].model = MODEL_RP32INTF;
1892                 strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F");
1893                 rocketModel[i].numPorts = 32;
1894                 break;
1895         case PCI_DEVICE_ID_URP32INTF:
1896                 str = "32";
1897                 max_num_aiops = 4;
1898                 rocketModel[i].model = MODEL_UPCI_RP32INTF;
1899                 strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F");
1900                 rocketModel[i].numPorts = 32;
1901                 break;
1902         case PCI_DEVICE_ID_RPP4:
1903                 str = "Plus Quadcable";
1904                 max_num_aiops = 1;
1905                 ports_per_aiop = 4;
1906                 altChanRingIndicator++;
1907                 fast_clock++;
1908                 rocketModel[i].model = MODEL_RPP4;
1909                 strcpy(rocketModel[i].modelString, "RocketPort Plus 4 port");
1910                 rocketModel[i].numPorts = 4;
1911                 break;
1912         case PCI_DEVICE_ID_RPP8:
1913                 str = "Plus Octacable";
1914                 max_num_aiops = 2;
1915                 ports_per_aiop = 4;
1916                 altChanRingIndicator++;
1917                 fast_clock++;
1918                 rocketModel[i].model = MODEL_RPP8;
1919                 strcpy(rocketModel[i].modelString, "RocketPort Plus 8 port");
1920                 rocketModel[i].numPorts = 8;
1921                 break;
1922         case PCI_DEVICE_ID_RP2_232:
1923                 str = "Plus 2 (RS-232)";
1924                 max_num_aiops = 1;
1925                 ports_per_aiop = 2;
1926                 altChanRingIndicator++;
1927                 fast_clock++;
1928                 rocketModel[i].model = MODEL_RP2_232;
1929                 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS232");
1930                 rocketModel[i].numPorts = 2;
1931                 break;
1932         case PCI_DEVICE_ID_RP2_422:
1933                 str = "Plus 2 (RS-422)";
1934                 max_num_aiops = 1;
1935                 ports_per_aiop = 2;
1936                 altChanRingIndicator++;
1937                 fast_clock++;
1938                 rocketModel[i].model = MODEL_RP2_422;
1939                 strcpy(rocketModel[i].modelString, "RocketPort Plus 2 port RS422");
1940                 rocketModel[i].numPorts = 2;
1941                 break;
1942         case PCI_DEVICE_ID_RP6M:
1943
1944                 max_num_aiops = 1;
1945                 ports_per_aiop = 6;
1946                 str = "6-port";
1947
1948                 /*  If revision is 1, the rocketmodem flash must be loaded.
1949                  *  If it is 2 it is a "socketed" version. */
1950                 if (dev->revision == 1) {
1951                         rcktpt_type[i] = ROCKET_TYPE_MODEMII;
1952                         rocketModel[i].loadrm2 = 1;
1953                 } else {
1954                         rcktpt_type[i] = ROCKET_TYPE_MODEM;
1955                 }
1956
1957                 rocketModel[i].model = MODEL_RP6M;
1958                 strcpy(rocketModel[i].modelString, "RocketModem 6 port");
1959                 rocketModel[i].numPorts = 6;
1960                 break;
1961         case PCI_DEVICE_ID_RP4M:
1962                 max_num_aiops = 1;
1963                 ports_per_aiop = 4;
1964                 str = "4-port";
1965                 if (dev->revision == 1) {
1966                         rcktpt_type[i] = ROCKET_TYPE_MODEMII;
1967                         rocketModel[i].loadrm2 = 1;
1968                 } else {
1969                         rcktpt_type[i] = ROCKET_TYPE_MODEM;
1970                 }
1971
1972                 rocketModel[i].model = MODEL_RP4M;
1973                 strcpy(rocketModel[i].modelString, "RocketModem 4 port");
1974                 rocketModel[i].numPorts = 4;
1975                 break;
1976         default:
1977                 str = "(unknown/unsupported)";
1978                 max_num_aiops = 0;
1979                 break;
1980         }
1981
1982         /*
1983          * Check for UPCI boards.
1984          */
1985
1986         switch (dev->device) {
1987         case PCI_DEVICE_ID_URP32INTF:
1988         case PCI_DEVICE_ID_URP8INTF:
1989         case PCI_DEVICE_ID_URP16INTF:
1990         case PCI_DEVICE_ID_CRP16INTF:
1991         case PCI_DEVICE_ID_URP8OCTA:
1992                 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
1993                 ConfigIO = pci_resource_start(dev, 1);
1994                 if (dev->device == PCI_DEVICE_ID_URP8OCTA) {
1995                         UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
1996
1997                         /*
1998                          * Check for octa or quad cable.
1999                          */
2000                         if (!
2001                             (sInW(ConfigIO + _PCI_9030_GPIO_CTRL) &
2002                              PCI_GPIO_CTRL_8PORT)) {
2003                                 str = "Quadcable";
2004                                 ports_per_aiop = 4;
2005                                 rocketModel[i].numPorts = 4;
2006                         }
2007                 }
2008                 break;
2009         case PCI_DEVICE_ID_UPCI_RM3_8PORT:
2010                 str = "8 ports";
2011                 max_num_aiops = 1;
2012                 rocketModel[i].model = MODEL_UPCI_RM3_8PORT;
2013                 strcpy(rocketModel[i].modelString, "RocketModem III 8 port");
2014                 rocketModel[i].numPorts = 8;
2015                 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2016                 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2017                 ConfigIO = pci_resource_start(dev, 1);
2018                 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2019                 break;
2020         case PCI_DEVICE_ID_UPCI_RM3_4PORT:
2021                 str = "4 ports";
2022                 max_num_aiops = 1;
2023                 rocketModel[i].model = MODEL_UPCI_RM3_4PORT;
2024                 strcpy(rocketModel[i].modelString, "RocketModem III 4 port");
2025                 rocketModel[i].numPorts = 4;
2026                 rcktpt_io_addr[i] = pci_resource_start(dev, 2);
2027                 UPCIRingInd = rcktpt_io_addr[i] + _PCI_9030_RING_IND;
2028                 ConfigIO = pci_resource_start(dev, 1);
2029                 rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
2030                 break;
2031         default:
2032                 break;
2033         }
2034
2035         switch (rcktpt_type[i]) {
2036         case ROCKET_TYPE_MODEM:
2037                 board_type = "RocketModem";
2038                 break;
2039         case ROCKET_TYPE_MODEMII:
2040                 board_type = "RocketModem II";
2041                 break;
2042         case ROCKET_TYPE_MODEMIII:
2043                 board_type = "RocketModem III";
2044                 break;
2045         default:
2046                 board_type = "RocketPort";
2047                 break;
2048         }
2049
2050         if (fast_clock) {
2051                 sClockPrescale = 0x12;  /* mod 2 (divide by 3) */
2052                 rp_baud_base[i] = 921600;
2053         } else {
2054                 /*
2055                  * If support_low_speed is set, use the slow clock
2056                  * prescale, which supports 50 bps
2057                  */
2058                 if (support_low_speed) {
2059                         /* mod 9 (divide by 10) prescale */
2060                         sClockPrescale = 0x19;
2061                         rp_baud_base[i] = 230400;
2062                 } else {
2063                         /* mod 4 (devide by 5) prescale */
2064                         sClockPrescale = 0x14;
2065                         rp_baud_base[i] = 460800;
2066                 }
2067         }
2068
2069         for (aiop = 0; aiop < max_num_aiops; aiop++)
2070                 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x40);
2071         ctlp = sCtlNumToCtlPtr(i);
2072         num_aiops = sPCIInitController(ctlp, i, aiopio, max_num_aiops, ConfigIO, 0, FREQ_DIS, 0, altChanRingIndicator, UPCIRingInd);
2073         for (aiop = 0; aiop < max_num_aiops; aiop++)
2074                 ctlp->AiopNumChan[aiop] = ports_per_aiop;
2075
2076         dev_info(&dev->dev, "comtrol PCI controller #%d found at "
2077                 "address %04lx, %d AIOP(s) (%s), creating ttyR%d - %ld\n",
2078                 i, rcktpt_io_addr[i], num_aiops, rocketModel[i].modelString,
2079                 rocketModel[i].startingPortNumber,
2080                 rocketModel[i].startingPortNumber + rocketModel[i].numPorts-1);
2081
2082         if (num_aiops <= 0) {
2083                 rcktpt_io_addr[i] = 0;
2084                 return (0);
2085         }
2086         is_PCI[i] = 1;
2087
2088         /*  Reset the AIOPIC, init the serial ports */
2089         for (aiop = 0; aiop < num_aiops; aiop++) {
2090                 sResetAiopByNum(ctlp, aiop);
2091                 num_chan = ports_per_aiop;
2092                 for (chan = 0; chan < num_chan; chan++)
2093                         init_r_port(i, aiop, chan, dev);
2094         }
2095
2096         /*  Rocket modems must be reset */
2097         if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) ||
2098             (rcktpt_type[i] == ROCKET_TYPE_MODEMII) ||
2099             (rcktpt_type[i] == ROCKET_TYPE_MODEMIII)) {
2100                 num_chan = ports_per_aiop;
2101                 for (chan = 0; chan < num_chan; chan++)
2102                         sPCIModemReset(ctlp, chan, 1);
2103                 msleep(500);
2104                 for (chan = 0; chan < num_chan; chan++)
2105                         sPCIModemReset(ctlp, chan, 0);
2106                 msleep(500);
2107                 rmSpeakerReset(ctlp, rocketModel[i].model);
2108         }
2109         return (1);
2110 }
2111
2112 /*
2113  *  Probes for PCI cards, inits them if found
2114  *  Input:   board_found = number of ISA boards already found, or the
2115  *           starting board number
2116  *  Returns: Number of PCI boards found
2117  */
2118 static int __init init_PCI(int boards_found)
2119 {
2120         struct pci_dev *dev = NULL;
2121         int count = 0;
2122
2123         /*  Work through the PCI device list, pulling out ours */
2124         while ((dev = pci_get_device(PCI_VENDOR_ID_RP, PCI_ANY_ID, dev))) {
2125                 if (register_PCI(count + boards_found, dev))
2126                         count++;
2127         }
2128         return (count);
2129 }
2130
2131 #endif                          /* CONFIG_PCI */
2132
2133 /*
2134  *  Probes for ISA cards
2135  *  Input:   i = the board number to look for
2136  *  Returns: 1 if board found, 0 else
2137  */
2138 static int __init init_ISA(int i)
2139 {
2140         int num_aiops, num_chan = 0, total_num_chan = 0;
2141         int aiop, chan;
2142         unsigned int aiopio[MAX_AIOPS_PER_BOARD];
2143         CONTROLLER_t *ctlp;
2144         char *type_string;
2145
2146         /*  If io_addr is zero, no board configured */
2147         if (rcktpt_io_addr[i] == 0)
2148                 return (0);
2149
2150         /*  Reserve the IO region */
2151         if (!request_region(rcktpt_io_addr[i], 64, "Comtrol RocketPort")) {
2152                 printk(KERN_ERR "Unable to reserve IO region for configured "
2153                                 "ISA RocketPort at address 0x%lx, board not "
2154                                 "installed...\n", rcktpt_io_addr[i]);
2155                 rcktpt_io_addr[i] = 0;
2156                 return (0);
2157         }
2158
2159         ctlp = sCtlNumToCtlPtr(i);
2160
2161         ctlp->boardType = rcktpt_type[i];
2162
2163         switch (rcktpt_type[i]) {
2164         case ROCKET_TYPE_PC104:
2165                 type_string = "(PC104)";
2166                 break;
2167         case ROCKET_TYPE_MODEM:
2168                 type_string = "(RocketModem)";
2169                 break;
2170         case ROCKET_TYPE_MODEMII:
2171                 type_string = "(RocketModem II)";
2172                 break;
2173         default:
2174                 type_string = "";
2175                 break;
2176         }
2177
2178         /*
2179          * If support_low_speed is set, use the slow clock prescale,
2180          * which supports 50 bps
2181          */
2182         if (support_low_speed) {
2183                 sClockPrescale = 0x19;  /* mod 9 (divide by 10) prescale */
2184                 rp_baud_base[i] = 230400;
2185         } else {
2186                 sClockPrescale = 0x14;  /* mod 4 (devide by 5) prescale */
2187                 rp_baud_base[i] = 460800;
2188         }
2189
2190         for (aiop = 0; aiop < MAX_AIOPS_PER_BOARD; aiop++)
2191                 aiopio[aiop] = rcktpt_io_addr[i] + (aiop * 0x400);
2192
2193         num_aiops = sInitController(ctlp, i, controller + (i * 0x400), aiopio,  MAX_AIOPS_PER_BOARD, 0, FREQ_DIS, 0);
2194
2195         if (ctlp->boardType == ROCKET_TYPE_PC104) {
2196                 sEnAiop(ctlp, 2);       /* only one AIOPIC, but these */
2197                 sEnAiop(ctlp, 3);       /* CSels used for other stuff */
2198         }
2199
2200         /*  If something went wrong initing the AIOP's release the ISA IO memory */
2201         if (num_aiops <= 0) {
2202                 release_region(rcktpt_io_addr[i], 64);
2203                 rcktpt_io_addr[i] = 0;
2204                 return (0);
2205         }
2206
2207         rocketModel[i].startingPortNumber = nextLineNumber;
2208
2209         for (aiop = 0; aiop < num_aiops; aiop++) {
2210                 sResetAiopByNum(ctlp, aiop);
2211                 sEnAiop(ctlp, aiop);
2212                 num_chan = sGetAiopNumChan(ctlp, aiop);
2213                 total_num_chan += num_chan;
2214                 for (chan = 0; chan < num_chan; chan++)
2215                         init_r_port(i, aiop, chan, NULL);
2216         }
2217         is_PCI[i] = 0;
2218         if ((rcktpt_type[i] == ROCKET_TYPE_MODEM) || (rcktpt_type[i] == ROCKET_TYPE_MODEMII)) {
2219                 num_chan = sGetAiopNumChan(ctlp, 0);
2220                 total_num_chan = num_chan;
2221                 for (chan = 0; chan < num_chan; chan++)
2222                         sModemReset(ctlp, chan, 1);
2223                 msleep(500);
2224                 for (chan = 0; chan < num_chan; chan++)
2225                         sModemReset(ctlp, chan, 0);
2226                 msleep(500);
2227                 strcpy(rocketModel[i].modelString, "RocketModem ISA");
2228         } else {
2229                 strcpy(rocketModel[i].modelString, "RocketPort ISA");
2230         }
2231         rocketModel[i].numPorts = total_num_chan;
2232         rocketModel[i].model = MODEL_ISA;
2233
2234         printk(KERN_INFO "RocketPort ISA card #%d found at 0x%lx - %d AIOPs %s\n",
2235                i, rcktpt_io_addr[i], num_aiops, type_string);
2236
2237         printk(KERN_INFO "Installing %s, creating /dev/ttyR%d - %ld\n",
2238                rocketModel[i].modelString,
2239                rocketModel[i].startingPortNumber,
2240                rocketModel[i].startingPortNumber +
2241                rocketModel[i].numPorts - 1);
2242
2243         return (1);
2244 }
2245
2246 static const struct tty_operations rocket_ops = {
2247         .open = rp_open,
2248         .close = rp_close,
2249         .write = rp_write,
2250         .put_char = rp_put_char,
2251         .write_room = rp_write_room,
2252         .chars_in_buffer = rp_chars_in_buffer,
2253         .flush_buffer = rp_flush_buffer,
2254         .ioctl = rp_ioctl,
2255         .throttle = rp_throttle,
2256         .unthrottle = rp_unthrottle,
2257         .set_termios = rp_set_termios,
2258         .stop = rp_stop,
2259         .start = rp_start,
2260         .hangup = rp_hangup,
2261         .break_ctl = rp_break,
2262         .send_xchar = rp_send_xchar,
2263         .wait_until_sent = rp_wait_until_sent,
2264         .tiocmget = rp_tiocmget,
2265         .tiocmset = rp_tiocmset,
2266 };
2267
2268 static const struct tty_port_operations rocket_port_ops = {
2269         .carrier_raised = carrier_raised,
2270         .dtr_rts = dtr_rts,
2271 };
2272
2273 /*
2274  * The module "startup" routine; it's run when the module is loaded.
2275  */
2276 static int __init rp_init(void)
2277 {
2278         int ret = -ENOMEM, pci_boards_found, isa_boards_found, i;
2279
2280         printk(KERN_INFO "RocketPort device driver module, version %s, %s\n",
2281                ROCKET_VERSION, ROCKET_DATE);
2282
2283         rocket_driver = alloc_tty_driver(MAX_RP_PORTS);
2284         if (!rocket_driver)
2285                 goto err;
2286
2287         /*
2288          *  If board 1 is non-zero, there is at least one ISA configured.  If controller is
2289          *  zero, use the default controller IO address of board1 + 0x40.
2290          */
2291         if (board1) {
2292                 if (controller == 0)
2293                         controller = board1 + 0x40;
2294         } else {
2295                 controller = 0;  /*  Used as a flag, meaning no ISA boards */
2296         }
2297
2298         /*  If an ISA card is configured, reserve the 4 byte IO space for the Mudbac controller */
2299         if (controller && (!request_region(controller, 4, "Comtrol RocketPort"))) {
2300                 printk(KERN_ERR "Unable to reserve IO region for first "
2301                         "configured ISA RocketPort controller 0x%lx.  "
2302                         "Driver exiting\n", controller);
2303                 ret = -EBUSY;
2304                 goto err_tty;
2305         }
2306
2307         /*  Store ISA variable retrieved from command line or .conf file. */
2308         rcktpt_io_addr[0] = board1;
2309         rcktpt_io_addr[1] = board2;
2310         rcktpt_io_addr[2] = board3;
2311         rcktpt_io_addr[3] = board4;
2312
2313         rcktpt_type[0] = modem1 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2314         rcktpt_type[0] = pc104_1[0] ? ROCKET_TYPE_PC104 : rcktpt_type[0];
2315         rcktpt_type[1] = modem2 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2316         rcktpt_type[1] = pc104_2[0] ? ROCKET_TYPE_PC104 : rcktpt_type[1];
2317         rcktpt_type[2] = modem3 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2318         rcktpt_type[2] = pc104_3[0] ? ROCKET_TYPE_PC104 : rcktpt_type[2];
2319         rcktpt_type[3] = modem4 ? ROCKET_TYPE_MODEM : ROCKET_TYPE_NORMAL;
2320         rcktpt_type[3] = pc104_4[0] ? ROCKET_TYPE_PC104 : rcktpt_type[3];
2321
2322         /*
2323          * Set up the tty driver structure and then register this
2324          * driver with the tty layer.
2325          */
2326
2327         rocket_driver->owner = THIS_MODULE;
2328         rocket_driver->flags = TTY_DRIVER_DYNAMIC_DEV;
2329         rocket_driver->name = "ttyR";
2330         rocket_driver->driver_name = "Comtrol RocketPort";
2331         rocket_driver->major = TTY_ROCKET_MAJOR;
2332         rocket_driver->minor_start = 0;
2333         rocket_driver->type = TTY_DRIVER_TYPE_SERIAL;
2334         rocket_driver->subtype = SERIAL_TYPE_NORMAL;
2335         rocket_driver->init_termios = tty_std_termios;
2336         rocket_driver->init_termios.c_cflag =
2337             B9600 | CS8 | CREAD | HUPCL | CLOCAL;
2338         rocket_driver->init_termios.c_ispeed = 9600;
2339         rocket_driver->init_termios.c_ospeed = 9600;
2340 #ifdef ROCKET_SOFT_FLOW
2341         rocket_driver->flags |= TTY_DRIVER_REAL_RAW;
2342 #endif
2343         tty_set_operations(rocket_driver, &rocket_ops);
2344
2345         ret = tty_register_driver(rocket_driver);
2346         if (ret < 0) {
2347                 printk(KERN_ERR "Couldn't install tty RocketPort driver\n");
2348                 goto err_controller;
2349         }
2350
2351 #ifdef ROCKET_DEBUG_OPEN
2352         printk(KERN_INFO "RocketPort driver is major %d\n", rocket_driver.major);
2353 #endif
2354
2355         /*
2356          *  OK, let's probe each of the controllers looking for boards.  Any boards found
2357          *  will be initialized here.
2358          */
2359         isa_boards_found = 0;
2360         pci_boards_found = 0;
2361
2362         for (i = 0; i < NUM_BOARDS; i++) {
2363                 if (init_ISA(i))
2364                         isa_boards_found++;
2365         }
2366
2367 #ifdef CONFIG_PCI
2368         if (isa_boards_found < NUM_BOARDS)
2369                 pci_boards_found = init_PCI(isa_boards_found);
2370 #endif
2371
2372         max_board = pci_boards_found + isa_boards_found;
2373
2374         if (max_board == 0) {
2375                 printk(KERN_ERR "No rocketport ports found; unloading driver\n");
2376                 ret = -ENXIO;
2377                 goto err_ttyu;
2378         }
2379
2380         return 0;
2381 err_ttyu:
2382         tty_unregister_driver(rocket_driver);
2383 err_controller:
2384         if (controller)
2385                 release_region(controller, 4);
2386 err_tty:
2387         put_tty_driver(rocket_driver);
2388 err:
2389         return ret;
2390 }
2391
2392
2393 static void rp_cleanup_module(void)
2394 {
2395         int retval;
2396         int i;
2397
2398         del_timer_sync(&rocket_timer);
2399
2400         retval = tty_unregister_driver(rocket_driver);
2401         if (retval)
2402                 printk(KERN_ERR "Error %d while trying to unregister "
2403                        "rocketport driver\n", -retval);
2404
2405         for (i = 0; i < MAX_RP_PORTS; i++)
2406                 if (rp_table[i]) {
2407                         tty_unregister_device(rocket_driver, i);
2408                         kfree(rp_table[i]);
2409                 }
2410
2411         put_tty_driver(rocket_driver);
2412
2413         for (i = 0; i < NUM_BOARDS; i++) {
2414                 if (rcktpt_io_addr[i] <= 0 || is_PCI[i])
2415                         continue;
2416                 release_region(rcktpt_io_addr[i], 64);
2417         }
2418         if (controller)
2419                 release_region(controller, 4);
2420 }
2421
2422 /***************************************************************************
2423 Function: sInitController
2424 Purpose:  Initialization of controller global registers and controller
2425           structure.
2426 Call:     sInitController(CtlP,CtlNum,MudbacIO,AiopIOList,AiopIOListSize,
2427                           IRQNum,Frequency,PeriodicOnly)
2428           CONTROLLER_T *CtlP; Ptr to controller structure
2429           int CtlNum; Controller number
2430           ByteIO_t MudbacIO; Mudbac base I/O address.
2431           ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2432              This list must be in the order the AIOPs will be found on the
2433              controller.  Once an AIOP in the list is not found, it is
2434              assumed that there are no more AIOPs on the controller.
2435           int AiopIOListSize; Number of addresses in AiopIOList
2436           int IRQNum; Interrupt Request number.  Can be any of the following:
2437                          0: Disable global interrupts
2438                          3: IRQ 3
2439                          4: IRQ 4
2440                          5: IRQ 5
2441                          9: IRQ 9
2442                          10: IRQ 10
2443                          11: IRQ 11
2444                          12: IRQ 12
2445                          15: IRQ 15
2446           Byte_t Frequency: A flag identifying the frequency
2447                    of the periodic interrupt, can be any one of the following:
2448                       FREQ_DIS - periodic interrupt disabled
2449                       FREQ_137HZ - 137 Hertz
2450                       FREQ_69HZ - 69 Hertz
2451                       FREQ_34HZ - 34 Hertz
2452                       FREQ_17HZ - 17 Hertz
2453                       FREQ_9HZ - 9 Hertz
2454                       FREQ_4HZ - 4 Hertz
2455                    If IRQNum is set to 0 the Frequency parameter is
2456                    overidden, it is forced to a value of FREQ_DIS.
2457           int PeriodicOnly: 1 if all interrupts except the periodic
2458                                interrupt are to be blocked.
2459                             0 is both the periodic interrupt and
2460                                other channel interrupts are allowed.
2461                             If IRQNum is set to 0 the PeriodicOnly parameter is
2462                                overidden, it is forced to a value of 0.
2463 Return:   int: Number of AIOPs on the controller, or CTLID_NULL if controller
2464                initialization failed.
2465
2466 Comments:
2467           If periodic interrupts are to be disabled but AIOP interrupts
2468           are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2469
2470           If interrupts are to be completely disabled set IRQNum to 0.
2471
2472           Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2473           invalid combination.
2474
2475           This function performs initialization of global interrupt modes,
2476           but it does not actually enable global interrupts.  To enable
2477           and disable global interrupts use functions sEnGlobalInt() and
2478           sDisGlobalInt().  Enabling of global interrupts is normally not
2479           done until all other initializations are complete.
2480
2481           Even if interrupts are globally enabled, they must also be
2482           individually enabled for each channel that is to generate
2483           interrupts.
2484
2485 Warnings: No range checking on any of the parameters is done.
2486
2487           No context switches are allowed while executing this function.
2488
2489           After this function all AIOPs on the controller are disabled,
2490           they can be enabled with sEnAiop().
2491 */
2492 static int sInitController(CONTROLLER_T * CtlP, int CtlNum, ByteIO_t MudbacIO,
2493                            ByteIO_t * AiopIOList, int AiopIOListSize,
2494                            int IRQNum, Byte_t Frequency, int PeriodicOnly)
2495 {
2496         int i;
2497         ByteIO_t io;
2498         int done;
2499
2500         CtlP->AiopIntrBits = aiop_intr_bits;
2501         CtlP->AltChanRingIndicator = 0;
2502         CtlP->CtlNum = CtlNum;
2503         CtlP->CtlID = CTLID_0001;       /* controller release 1 */
2504         CtlP->BusType = isISA;
2505         CtlP->MBaseIO = MudbacIO;
2506         CtlP->MReg1IO = MudbacIO + 1;
2507         CtlP->MReg2IO = MudbacIO + 2;
2508         CtlP->MReg3IO = MudbacIO + 3;
2509 #if 1
2510         CtlP->MReg2 = 0;        /* interrupt disable */
2511         CtlP->MReg3 = 0;        /* no periodic interrupts */
2512 #else
2513         if (sIRQMap[IRQNum] == 0) {     /* interrupts globally disabled */
2514                 CtlP->MReg2 = 0;        /* interrupt disable */
2515                 CtlP->MReg3 = 0;        /* no periodic interrupts */
2516         } else {
2517                 CtlP->MReg2 = sIRQMap[IRQNum];  /* set IRQ number */
2518                 CtlP->MReg3 = Frequency;        /* set frequency */
2519                 if (PeriodicOnly) {     /* periodic interrupt only */
2520                         CtlP->MReg3 |= PERIODIC_ONLY;
2521                 }
2522         }
2523 #endif
2524         sOutB(CtlP->MReg2IO, CtlP->MReg2);
2525         sOutB(CtlP->MReg3IO, CtlP->MReg3);
2526         sControllerEOI(CtlP);   /* clear EOI if warm init */
2527         /* Init AIOPs */
2528         CtlP->NumAiop = 0;
2529         for (i = done = 0; i < AiopIOListSize; i++) {
2530                 io = AiopIOList[i];
2531                 CtlP->AiopIO[i] = (WordIO_t) io;
2532                 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2533                 sOutB(CtlP->MReg2IO, CtlP->MReg2 | (i & 0x03)); /* AIOP index */
2534                 sOutB(MudbacIO, (Byte_t) (io >> 6));    /* set up AIOP I/O in MUDBAC */
2535                 if (done)
2536                         continue;
2537                 sEnAiop(CtlP, i);       /* enable the AIOP */
2538                 CtlP->AiopID[i] = sReadAiopID(io);      /* read AIOP ID */
2539                 if (CtlP->AiopID[i] == AIOPID_NULL)     /* if AIOP does not exist */
2540                         done = 1;       /* done looking for AIOPs */
2541                 else {
2542                         CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2543                         sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE);    /* clock prescaler */
2544                         sOutB(io + _INDX_DATA, sClockPrescale);
2545                         CtlP->NumAiop++;        /* bump count of AIOPs */
2546                 }
2547                 sDisAiop(CtlP, i);      /* disable AIOP */
2548         }
2549
2550         if (CtlP->NumAiop == 0)
2551                 return (-1);
2552         else
2553                 return (CtlP->NumAiop);
2554 }
2555
2556 /***************************************************************************
2557 Function: sPCIInitController
2558 Purpose:  Initialization of controller global registers and controller
2559           structure.
2560 Call:     sPCIInitController(CtlP,CtlNum,AiopIOList,AiopIOListSize,
2561                           IRQNum,Frequency,PeriodicOnly)
2562           CONTROLLER_T *CtlP; Ptr to controller structure
2563           int CtlNum; Controller number
2564           ByteIO_t *AiopIOList; List of I/O addresses for each AIOP.
2565              This list must be in the order the AIOPs will be found on the
2566              controller.  Once an AIOP in the list is not found, it is
2567              assumed that there are no more AIOPs on the controller.
2568           int AiopIOListSize; Number of addresses in AiopIOList
2569           int IRQNum; Interrupt Request number.  Can be any of the following:
2570                          0: Disable global interrupts
2571                          3: IRQ 3
2572                          4: IRQ 4
2573                          5: IRQ 5
2574                          9: IRQ 9
2575                          10: IRQ 10
2576                          11: IRQ 11
2577                          12: IRQ 12
2578                          15: IRQ 15
2579           Byte_t Frequency: A flag identifying the frequency
2580                    of the periodic interrupt, can be any one of the following:
2581                       FREQ_DIS - periodic interrupt disabled
2582                       FREQ_137HZ - 137 Hertz
2583                       FREQ_69HZ - 69 Hertz
2584                       FREQ_34HZ - 34 Hertz
2585                       FREQ_17HZ - 17 Hertz
2586                       FREQ_9HZ - 9 Hertz
2587                       FREQ_4HZ - 4 Hertz
2588                    If IRQNum is set to 0 the Frequency parameter is
2589                    overidden, it is forced to a value of FREQ_DIS.
2590           int PeriodicOnly: 1 if all interrupts except the periodic
2591                                interrupt are to be blocked.
2592                             0 is both the periodic interrupt and
2593                                other channel interrupts are allowed.
2594                             If IRQNum is set to 0 the PeriodicOnly parameter is
2595                                overidden, it is forced to a value of 0.
2596 Return:   int: Number of AIOPs on the controller, or CTLID_NULL if controller
2597                initialization failed.
2598
2599 Comments:
2600           If periodic interrupts are to be disabled but AIOP interrupts
2601           are allowed, set Frequency to FREQ_DIS and PeriodicOnly to 0.
2602
2603           If interrupts are to be completely disabled set IRQNum to 0.
2604
2605           Setting Frequency to FREQ_DIS and PeriodicOnly to 1 is an
2606           invalid combination.
2607
2608           This function performs initialization of global interrupt modes,
2609           but it does not actually enable global interrupts.  To enable
2610           and disable global interrupts use functions sEnGlobalInt() and
2611           sDisGlobalInt().  Enabling of global interrupts is normally not
2612           done until all other initializations are complete.
2613
2614           Even if interrupts are globally enabled, they must also be
2615           individually enabled for each channel that is to generate
2616           interrupts.
2617
2618 Warnings: No range checking on any of the parameters is done.
2619
2620           No context switches are allowed while executing this function.
2621
2622           After this function all AIOPs on the controller are disabled,
2623           they can be enabled with sEnAiop().
2624 */
2625 static int sPCIInitController(CONTROLLER_T * CtlP, int CtlNum,
2626                               ByteIO_t * AiopIOList, int AiopIOListSize,
2627                               WordIO_t ConfigIO, int IRQNum, Byte_t Frequency,
2628                               int PeriodicOnly, int altChanRingIndicator,
2629                               int UPCIRingInd)
2630 {
2631         int i;
2632         ByteIO_t io;
2633
2634         CtlP->AltChanRingIndicator = altChanRingIndicator;
2635         CtlP->UPCIRingInd = UPCIRingInd;
2636         CtlP->CtlNum = CtlNum;
2637         CtlP->CtlID = CTLID_0001;       /* controller release 1 */
2638         CtlP->BusType = isPCI;  /* controller release 1 */
2639
2640         if (ConfigIO) {
2641                 CtlP->isUPCI = 1;
2642                 CtlP->PCIIO = ConfigIO + _PCI_9030_INT_CTRL;
2643                 CtlP->PCIIO2 = ConfigIO + _PCI_9030_GPIO_CTRL;
2644                 CtlP->AiopIntrBits = upci_aiop_intr_bits;
2645         } else {
2646                 CtlP->isUPCI = 0;
2647                 CtlP->PCIIO =
2648                     (WordIO_t) ((ByteIO_t) AiopIOList[0] + _PCI_INT_FUNC);
2649                 CtlP->AiopIntrBits = aiop_intr_bits;
2650         }
2651
2652         sPCIControllerEOI(CtlP);        /* clear EOI if warm init */
2653         /* Init AIOPs */
2654         CtlP->NumAiop = 0;
2655         for (i = 0; i < AiopIOListSize; i++) {
2656                 io = AiopIOList[i];
2657                 CtlP->AiopIO[i] = (WordIO_t) io;
2658                 CtlP->AiopIntChanIO[i] = io + _INT_CHAN;
2659
2660                 CtlP->AiopID[i] = sReadAiopID(io);      /* read AIOP ID */
2661                 if (CtlP->AiopID[i] == AIOPID_NULL)     /* if AIOP does not exist */
2662                         break;  /* done looking for AIOPs */
2663
2664                 CtlP->AiopNumChan[i] = sReadAiopNumChan((WordIO_t) io); /* num channels in AIOP */
2665                 sOutW((WordIO_t) io + _INDX_ADDR, _CLK_PRE);    /* clock prescaler */
2666                 sOutB(io + _INDX_DATA, sClockPrescale);
2667                 CtlP->NumAiop++;        /* bump count of AIOPs */
2668         }
2669
2670         if (CtlP->NumAiop == 0)
2671                 return (-1);
2672         else
2673                 return (CtlP->NumAiop);
2674 }
2675
2676 /***************************************************************************
2677 Function: sReadAiopID
2678 Purpose:  Read the AIOP idenfication number directly from an AIOP.
2679 Call:     sReadAiopID(io)
2680           ByteIO_t io: AIOP base I/O address
2681 Return:   int: Flag AIOPID_XXXX if a valid AIOP is found, where X
2682                  is replace by an identifying number.
2683           Flag AIOPID_NULL if no valid AIOP is found
2684 Warnings: No context switches are allowed while executing this function.
2685
2686 */
2687 static int sReadAiopID(ByteIO_t io)
2688 {
2689         Byte_t AiopID;          /* ID byte from AIOP */
2690
2691         sOutB(io + _CMD_REG, RESET_ALL);        /* reset AIOP */
2692         sOutB(io + _CMD_REG, 0x0);
2693         AiopID = sInW(io + _CHN_STAT0) & 0x07;
2694         if (AiopID == 0x06)
2695                 return (1);
2696         else                    /* AIOP does not exist */
2697                 return (-1);
2698 }
2699
2700 /***************************************************************************
2701 Function: sReadAiopNumChan
2702 Purpose:  Read the number of channels available in an AIOP directly from
2703           an AIOP.
2704 Call:     sReadAiopNumChan(io)
2705           WordIO_t io: AIOP base I/O address
2706 Return:   int: The number of channels available
2707 Comments: The number of channels is determined by write/reads from identical
2708           offsets within the SRAM address spaces for channels 0 and 4.
2709           If the channel 4 space is mirrored to channel 0 it is a 4 channel
2710           AIOP, otherwise it is an 8 channel.
2711 Warnings: No context switches are allowed while executing this function.
2712 */
2713 static int sReadAiopNumChan(WordIO_t io)
2714 {
2715         Word_t x;
2716         static Byte_t R[4] = { 0x00, 0x00, 0x34, 0x12 };
2717
2718         /* write to chan 0 SRAM */
2719         out32((DWordIO_t) io + _INDX_ADDR, R);
2720         sOutW(io + _INDX_ADDR, 0);      /* read from SRAM, chan 0 */
2721         x = sInW(io + _INDX_DATA);
2722         sOutW(io + _INDX_ADDR, 0x4000); /* read from SRAM, chan 4 */
2723         if (x != sInW(io + _INDX_DATA)) /* if different must be 8 chan */
2724                 return (8);
2725         else
2726                 return (4);
2727 }
2728
2729 /***************************************************************************
2730 Function: sInitChan
2731 Purpose:  Initialization of a channel and channel structure
2732 Call:     sInitChan(CtlP,ChP,AiopNum,ChanNum)
2733           CONTROLLER_T *CtlP; Ptr to controller structure
2734           CHANNEL_T *ChP; Ptr to channel structure
2735           int AiopNum; AIOP number within controller
2736           int ChanNum; Channel number within AIOP
2737 Return:   int: 1 if initialization succeeded, 0 if it fails because channel
2738                number exceeds number of channels available in AIOP.
2739 Comments: This function must be called before a channel can be used.
2740 Warnings: No range checking on any of the parameters is done.
2741
2742           No context switches are allowed while executing this function.
2743 */
2744 static int sInitChan(CONTROLLER_T * CtlP, CHANNEL_T * ChP, int AiopNum,
2745                      int ChanNum)
2746 {
2747         int i;
2748         WordIO_t AiopIO;
2749         WordIO_t ChIOOff;
2750         Byte_t *ChR;
2751         Word_t ChOff;
2752         static Byte_t R[4];
2753         int brd9600;
2754
2755         if (ChanNum >= CtlP->AiopNumChan[AiopNum])
2756                 return 0;       /* exceeds num chans in AIOP */
2757
2758         /* Channel, AIOP, and controller identifiers */
2759         ChP->CtlP = CtlP;
2760         ChP->ChanID = CtlP->AiopID[AiopNum];
2761         ChP->AiopNum = AiopNum;
2762         ChP->ChanNum = ChanNum;
2763
2764         /* Global direct addresses */
2765         AiopIO = CtlP->AiopIO[AiopNum];
2766         ChP->Cmd = (ByteIO_t) AiopIO + _CMD_REG;
2767         ChP->IntChan = (ByteIO_t) AiopIO + _INT_CHAN;
2768         ChP->IntMask = (ByteIO_t) AiopIO + _INT_MASK;
2769         ChP->IndexAddr = (DWordIO_t) AiopIO + _INDX_ADDR;
2770         ChP->IndexData = AiopIO + _INDX_DATA;
2771
2772         /* Channel direct addresses */
2773         ChIOOff = AiopIO + ChP->ChanNum * 2;
2774         ChP->TxRxData = ChIOOff + _TD0;
2775         ChP->ChanStat = ChIOOff + _CHN_STAT0;
2776         ChP->TxRxCount = ChIOOff + _FIFO_CNT0;
2777         ChP->IntID = (ByteIO_t) AiopIO + ChP->ChanNum + _INT_ID0;
2778
2779         /* Initialize the channel from the RData array */
2780         for (i = 0; i < RDATASIZE; i += 4) {
2781                 R[0] = RData[i];
2782                 R[1] = RData[i + 1] + 0x10 * ChanNum;
2783                 R[2] = RData[i + 2];
2784                 R[3] = RData[i + 3];
2785                 out32(ChP->IndexAddr, R);
2786         }
2787
2788         ChR = ChP->R;
2789         for (i = 0; i < RREGDATASIZE; i += 4) {
2790                 ChR[i] = RRegData[i];
2791                 ChR[i + 1] = RRegData[i + 1] + 0x10 * ChanNum;
2792                 ChR[i + 2] = RRegData[i + 2];
2793                 ChR[i + 3] = RRegData[i + 3];
2794         }
2795
2796         /* Indexed registers */
2797         ChOff = (Word_t) ChanNum *0x1000;
2798
2799         if (sClockPrescale == 0x14)
2800                 brd9600 = 47;
2801         else
2802                 brd9600 = 23;
2803
2804         ChP->BaudDiv[0] = (Byte_t) (ChOff + _BAUD);
2805         ChP->BaudDiv[1] = (Byte_t) ((ChOff + _BAUD) >> 8);
2806         ChP->BaudDiv[2] = (Byte_t) brd9600;
2807         ChP->BaudDiv[3] = (Byte_t) (brd9600 >> 8);
2808         out32(ChP->IndexAddr, ChP->BaudDiv);
2809
2810         ChP->TxControl[0] = (Byte_t) (ChOff + _TX_CTRL);
2811         ChP->TxControl[1] = (Byte_t) ((ChOff + _TX_CTRL) >> 8);
2812         ChP->TxControl[2] = 0;
2813         ChP->TxControl[3] = 0;
2814         out32(ChP->IndexAddr, ChP->TxControl);
2815
2816         ChP->RxControl[0] = (Byte_t) (ChOff + _RX_CTRL);
2817         ChP->RxControl[1] = (Byte_t) ((ChOff + _RX_CTRL) >> 8);
2818         ChP->RxControl[2] = 0;
2819         ChP->RxControl[3] = 0;
2820         out32(ChP->IndexAddr, ChP->RxControl);
2821
2822         ChP->TxEnables[0] = (Byte_t) (ChOff + _TX_ENBLS);
2823         ChP->TxEnables[1] = (Byte_t) ((ChOff + _TX_ENBLS) >> 8);
2824         ChP->TxEnables[2] = 0;
2825         ChP->TxEnables[3] = 0;
2826         out32(ChP->IndexAddr, ChP->TxEnables);
2827
2828         ChP->TxCompare[0] = (Byte_t) (ChOff + _TXCMP1);
2829         ChP->TxCompare[1] = (Byte_t) ((ChOff + _TXCMP1) >> 8);
2830         ChP->TxCompare[2] = 0;
2831         ChP->TxCompare[3] = 0;
2832         out32(ChP->IndexAddr, ChP->TxCompare);
2833
2834         ChP->TxReplace1[0] = (Byte_t) (ChOff + _TXREP1B1);
2835         ChP->TxReplace1[1] = (Byte_t) ((ChOff + _TXREP1B1) >> 8);
2836         ChP->TxReplace1[2] = 0;
2837         ChP->TxReplace1[3] = 0;
2838         out32(ChP->IndexAddr, ChP->TxReplace1);
2839
2840         ChP->TxReplace2[0] = (Byte_t) (ChOff + _TXREP2);
2841         ChP->TxReplace2[1] = (Byte_t) ((ChOff + _TXREP2) >> 8);
2842         ChP->TxReplace2[2] = 0;
2843         ChP->TxReplace2[3] = 0;
2844         out32(ChP->IndexAddr, ChP->TxReplace2);
2845
2846         ChP->TxFIFOPtrs = ChOff + _TXF_OUTP;
2847         ChP->TxFIFO = ChOff + _TX_FIFO;
2848
2849         sOutB(ChP->Cmd, (Byte_t) ChanNum | RESTXFCNT);  /* apply reset Tx FIFO count */
2850         sOutB(ChP->Cmd, (Byte_t) ChanNum);      /* remove reset Tx FIFO count */
2851         sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs);      /* clear Tx in/out ptrs */
2852         sOutW(ChP->IndexData, 0);
2853         ChP->RxFIFOPtrs = ChOff + _RXF_OUTP;
2854         ChP->RxFIFO = ChOff + _RX_FIFO;
2855
2856         sOutB(ChP->Cmd, (Byte_t) ChanNum | RESRXFCNT);  /* apply reset Rx FIFO count */
2857         sOutB(ChP->Cmd, (Byte_t) ChanNum);      /* remove reset Rx FIFO count */
2858         sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs);      /* clear Rx out ptr */
2859         sOutW(ChP->IndexData, 0);
2860         sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2);  /* clear Rx in ptr */
2861         sOutW(ChP->IndexData, 0);
2862         ChP->TxPrioCnt = ChOff + _TXP_CNT;
2863         sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioCnt);
2864         sOutB(ChP->IndexData, 0);
2865         ChP->TxPrioPtr = ChOff + _TXP_PNTR;
2866         sOutW((WordIO_t) ChP->IndexAddr, ChP->TxPrioPtr);
2867         sOutB(ChP->IndexData, 0);
2868         ChP->TxPrioBuf = ChOff + _TXP_BUF;
2869         sEnRxProcessor(ChP);    /* start the Rx processor */
2870
2871         return 1;
2872 }
2873
2874 /***************************************************************************
2875 Function: sStopRxProcessor
2876 Purpose:  Stop the receive processor from processing a channel.
2877 Call:     sStopRxProcessor(ChP)
2878           CHANNEL_T *ChP; Ptr to channel structure
2879
2880 Comments: The receive processor can be started again with sStartRxProcessor().
2881           This function causes the receive processor to skip over the
2882           stopped channel.  It does not stop it from processing other channels.
2883
2884 Warnings: No context switches are allowed while executing this function.
2885
2886           Do not leave the receive processor stopped for more than one
2887           character time.
2888
2889           After calling this function a delay of 4 uS is required to ensure
2890           that the receive processor is no longer processing this channel.
2891 */
2892 static void sStopRxProcessor(CHANNEL_T * ChP)
2893 {
2894         Byte_t R[4];
2895
2896         R[0] = ChP->R[0];
2897         R[1] = ChP->R[1];
2898         R[2] = 0x0a;
2899         R[3] = ChP->R[3];
2900         out32(ChP->IndexAddr, R);
2901 }
2902
2903 /***************************************************************************
2904 Function: sFlushRxFIFO
2905 Purpose:  Flush the Rx FIFO
2906 Call:     sFlushRxFIFO(ChP)
2907           CHANNEL_T *ChP; Ptr to channel structure
2908 Return:   void
2909 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2910           while it is being flushed the receive processor is stopped
2911           and the transmitter is disabled.  After these operations a
2912           4 uS delay is done before clearing the pointers to allow
2913           the receive processor to stop.  These items are handled inside
2914           this function.
2915 Warnings: No context switches are allowed while executing this function.
2916 */
2917 static void sFlushRxFIFO(CHANNEL_T * ChP)
2918 {
2919         int i;
2920         Byte_t Ch;              /* channel number within AIOP */
2921         int RxFIFOEnabled;      /* 1 if Rx FIFO enabled */
2922
2923         if (sGetRxCnt(ChP) == 0)        /* Rx FIFO empty */
2924                 return;         /* don't need to flush */
2925
2926         RxFIFOEnabled = 0;
2927         if (ChP->R[0x32] == 0x08) {     /* Rx FIFO is enabled */
2928                 RxFIFOEnabled = 1;
2929                 sDisRxFIFO(ChP);        /* disable it */
2930                 for (i = 0; i < 2000 / 200; i++)        /* delay 2 uS to allow proc to disable FIFO */
2931                         sInB(ChP->IntChan);     /* depends on bus i/o timing */
2932         }
2933         sGetChanStatus(ChP);    /* clear any pending Rx errors in chan stat */
2934         Ch = (Byte_t) sGetChanNum(ChP);
2935         sOutB(ChP->Cmd, Ch | RESRXFCNT);        /* apply reset Rx FIFO count */
2936         sOutB(ChP->Cmd, Ch);    /* remove reset Rx FIFO count */
2937         sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs);      /* clear Rx out ptr */
2938         sOutW(ChP->IndexData, 0);
2939         sOutW((WordIO_t) ChP->IndexAddr, ChP->RxFIFOPtrs + 2);  /* clear Rx in ptr */
2940         sOutW(ChP->IndexData, 0);
2941         if (RxFIFOEnabled)
2942                 sEnRxFIFO(ChP); /* enable Rx FIFO */
2943 }
2944
2945 /***************************************************************************
2946 Function: sFlushTxFIFO
2947 Purpose:  Flush the Tx FIFO
2948 Call:     sFlushTxFIFO(ChP)
2949           CHANNEL_T *ChP; Ptr to channel structure
2950 Return:   void
2951 Comments: To prevent data from being enqueued or dequeued in the Tx FIFO
2952           while it is being flushed the receive processor is stopped
2953           and the transmitter is disabled.  After these operations a
2954           4 uS delay is done before clearing the pointers to allow
2955           the receive processor to stop.  These items are handled inside
2956           this function.
2957 Warnings: No context switches are allowed while executing this function.
2958 */
2959 static void sFlushTxFIFO(CHANNEL_T * ChP)
2960 {
2961         int i;
2962         Byte_t Ch;              /* channel number within AIOP */
2963         int TxEnabled;          /* 1 if transmitter enabled */
2964
2965         if (sGetTxCnt(ChP) == 0)        /* Tx FIFO empty */
2966                 return;         /* don't need to flush */
2967
2968         TxEnabled = 0;
2969         if (ChP->TxControl[3] & TX_ENABLE) {
2970                 TxEnabled = 1;
2971                 sDisTransmit(ChP);      /* disable transmitter */
2972         }
2973         sStopRxProcessor(ChP);  /* stop Rx processor */
2974         for (i = 0; i < 4000 / 200; i++)        /* delay 4 uS to allow proc to stop */
2975                 sInB(ChP->IntChan);     /* depends on bus i/o timing */
2976         Ch = (Byte_t) sGetChanNum(ChP);
2977         sOutB(ChP->Cmd, Ch | RESTXFCNT);        /* apply reset Tx FIFO count */
2978         sOutB(ChP->Cmd, Ch);    /* remove reset Tx FIFO count */
2979         sOutW((WordIO_t) ChP->IndexAddr, ChP->TxFIFOPtrs);      /* clear Tx in/out ptrs */
2980         sOutW(ChP->IndexData, 0);
2981         if (TxEnabled)
2982                 sEnTransmit(ChP);       /* enable transmitter */
2983         sStartRxProcessor(ChP); /* restart Rx processor */
2984 }
2985
2986 /***************************************************************************
2987 Function: sWriteTxPrioByte
2988 Purpose:  Write a byte of priority transmit data to a channel
2989 Call:     sWriteTxPrioByte(ChP,Data)
2990           CHANNEL_T *ChP; Ptr to channel structure
2991           Byte_t Data; The transmit data byte
2992
2993 Return:   int: 1 if the bytes is successfully written, otherwise 0.
2994
2995 Comments: The priority byte is transmitted before any data in the Tx FIFO.
2996
2997 Warnings: No context switches are allowed while executing this function.
2998 */
2999 static int sWriteTxPrioByte(CHANNEL_T * ChP, Byte_t Data)
3000 {
3001         Byte_t DWBuf[4];        /* buffer for double word writes */
3002         Word_t *WordPtr;        /* must be far because Win SS != DS */
3003         register DWordIO_t IndexAddr;
3004
3005         if (sGetTxCnt(ChP) > 1) {       /* write it to Tx priority buffer */
3006                 IndexAddr = ChP->IndexAddr;
3007                 sOutW((WordIO_t) IndexAddr, ChP->TxPrioCnt);    /* get priority buffer status */
3008                 if (sInB((ByteIO_t) ChP->IndexData) & PRI_PEND) /* priority buffer busy */
3009                         return (0);     /* nothing sent */
3010
3011                 WordPtr = (Word_t *) (&DWBuf[0]);
3012                 *WordPtr = ChP->TxPrioBuf;      /* data byte address */
3013
3014                 DWBuf[2] = Data;        /* data byte value */
3015                 out32(IndexAddr, DWBuf);        /* write it out */
3016
3017                 *WordPtr = ChP->TxPrioCnt;      /* Tx priority count address */
3018
3019                 DWBuf[2] = PRI_PEND + 1;        /* indicate 1 byte pending */
3020                 DWBuf[3] = 0;   /* priority buffer pointer */
3021                 out32(IndexAddr, DWBuf);        /* write it out */
3022         } else {                /* write it to Tx FIFO */
3023
3024                 sWriteTxByte(sGetTxRxDataIO(ChP), Data);
3025         }
3026         return (1);             /* 1 byte sent */
3027 }
3028
3029 /***************************************************************************
3030 Function: sEnInterrupts
3031 Purpose:  Enable one or more interrupts for a channel
3032 Call:     sEnInterrupts(ChP,Flags)
3033           CHANNEL_T *ChP; Ptr to channel structure
3034           Word_t Flags: Interrupt enable flags, can be any combination
3035              of the following flags:
3036                 TXINT_EN:   Interrupt on Tx FIFO empty
3037                 RXINT_EN:   Interrupt on Rx FIFO at trigger level (see
3038                             sSetRxTrigger())
3039                 SRCINT_EN:  Interrupt on SRC (Special Rx Condition)
3040                 MCINT_EN:   Interrupt on modem input change
3041                 CHANINT_EN: Allow channel interrupt signal to the AIOP's
3042                             Interrupt Channel Register.
3043 Return:   void
3044 Comments: If an interrupt enable flag is set in Flags, that interrupt will be
3045           enabled.  If an interrupt enable flag is not set in Flags, that
3046           interrupt will not be changed.  Interrupts can be disabled with
3047           function sDisInterrupts().
3048
3049           This function sets the appropriate bit for the channel in the AIOP's
3050           Interrupt Mask Register if the CHANINT_EN flag is set.  This allows
3051           this channel's bit to be set in the AIOP's Interrupt Channel Register.
3052
3053           Interrupts must also be globally enabled before channel interrupts
3054           will be passed on to the host.  This is done with function
3055           sEnGlobalInt().
3056
3057           In some cases it may be desirable to disable interrupts globally but
3058           enable channel interrupts.  This would allow the global interrupt
3059           status register to be used to determine which AIOPs need service.
3060 */
3061 static void sEnInterrupts(CHANNEL_T * ChP, Word_t Flags)
3062 {
3063         Byte_t Mask;            /* Interrupt Mask Register */
3064
3065         ChP->RxControl[2] |=
3066             ((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3067
3068         out32(ChP->IndexAddr, ChP->RxControl);
3069
3070         ChP->TxControl[2] |= ((Byte_t) Flags & TXINT_EN);
3071
3072         out32(ChP->IndexAddr, ChP->TxControl);
3073
3074         if (Flags & CHANINT_EN) {
3075                 Mask = sInB(ChP->IntMask) | sBitMapSetTbl[ChP->ChanNum];
3076                 sOutB(ChP->IntMask, Mask);
3077         }
3078 }
3079
3080 /***************************************************************************
3081 Function: sDisInterrupts
3082 Purpose:  Disable one or more interrupts for a channel
3083 Call:     sDisInterrupts(ChP,Flags)
3084           CHANNEL_T *ChP; Ptr to channel structure
3085           Word_t Flags: Interrupt flags, can be any combination
3086              of the following flags:
3087                 TXINT_EN:   Interrupt on Tx FIFO empty
3088                 RXINT_EN:   Interrupt on Rx FIFO at trigger level (see
3089                             sSetRxTrigger())
3090                 SRCINT_EN:  Interrupt on SRC (Special Rx Condition)
3091                 MCINT_EN:   Interrupt on modem input change
3092                 CHANINT_EN: Disable channel interrupt signal to the
3093                             AIOP's Interrupt Channel Register.
3094 Return:   void
3095 Comments: If an interrupt flag is set in Flags, that interrupt will be
3096           disabled.  If an interrupt flag is not set in Flags, that
3097           interrupt will not be changed.  Interrupts can be enabled with
3098           function sEnInterrupts().
3099
3100           This function clears the appropriate bit for the channel in the AIOP's
3101           Interrupt Mask Register if the CHANINT_EN flag is set.  This blocks
3102           this channel's bit from being set in the AIOP's Interrupt Channel
3103           Register.
3104 */
3105 static void sDisInterrupts(CHANNEL_T * ChP, Word_t Flags)
3106 {
3107         Byte_t Mask;            /* Interrupt Mask Register */
3108
3109         ChP->RxControl[2] &=
3110             ~((Byte_t) Flags & (RXINT_EN | SRCINT_EN | MCINT_EN));
3111         out32(ChP->IndexAddr, ChP->RxControl);
3112         ChP->TxControl[2] &= ~((Byte_t) Flags & TXINT_EN);
3113         out32(ChP->IndexAddr, ChP->TxControl);
3114
3115         if (Flags & CHANINT_EN) {
3116                 Mask = sInB(ChP->IntMask) & sBitMapClrTbl[ChP->ChanNum];
3117                 sOutB(ChP->IntMask, Mask);
3118         }
3119 }
3120
3121 static void sSetInterfaceMode(CHANNEL_T * ChP, Byte_t mode)
3122 {
3123         sOutB(ChP->CtlP->AiopIO[2], (mode & 0x18) | ChP->ChanNum);
3124 }
3125
3126 /*
3127  *  Not an official SSCI function, but how to reset RocketModems.
3128  *  ISA bus version
3129  */
3130 static void sModemReset(CONTROLLER_T * CtlP, int chan, int on)
3131 {
3132         ByteIO_t addr;
3133         Byte_t val;
3134
3135         addr = CtlP->AiopIO[0] + 0x400;
3136         val = sInB(CtlP->MReg3IO);
3137         /* if AIOP[1] is not enabled, enable it */
3138         if ((val & 2) == 0) {
3139                 val = sInB(CtlP->MReg2IO);
3140                 sOutB(CtlP->MReg2IO, (val & 0xfc) | (1 & 0x03));
3141                 sOutB(CtlP->MBaseIO, (unsigned char) (addr >> 6));
3142         }
3143
3144         sEnAiop(CtlP, 1);
3145         if (!on)
3146                 addr += 8;
3147         sOutB(addr + chan, 0);  /* apply or remove reset */
3148         sDisAiop(CtlP, 1);
3149 }
3150
3151 /*
3152  *  Not an official SSCI function, but how to reset RocketModems.
3153  *  PCI bus version
3154  */
3155 static void sPCIModemReset(CONTROLLER_T * CtlP, int chan, int on)
3156 {
3157         ByteIO_t addr;
3158
3159         addr = CtlP->AiopIO[0] + 0x40;  /* 2nd AIOP */
3160         if (!on)
3161                 addr += 8;
3162         sOutB(addr + chan, 0);  /* apply or remove reset */
3163 }
3164
3165 /*  Resets the speaker controller on RocketModem II and III devices */
3166 static void rmSpeakerReset(CONTROLLER_T * CtlP, unsigned long model)
3167 {
3168         ByteIO_t addr;
3169
3170         /* RocketModem II speaker control is at the 8th port location of offset 0x40 */
3171         if ((model == MODEL_RP4M) || (model == MODEL_RP6M)) {
3172                 addr = CtlP->AiopIO[0] + 0x4F;
3173                 sOutB(addr, 0);
3174         }
3175
3176         /* RocketModem III speaker control is at the 1st port location of offset 0x80 */
3177         if ((model == MODEL_UPCI_RM3_8PORT)
3178             || (model == MODEL_UPCI_RM3_4PORT)) {
3179                 addr = CtlP->AiopIO[0] + 0x88;
3180                 sOutB(addr, 0);
3181         }
3182 }
3183
3184 /*  Returns the line number given the controller (board), aiop and channel number */
3185 static unsigned char GetLineNumber(int ctrl, int aiop, int ch)
3186 {
3187         return lineNumbers[(ctrl << 5) | (aiop << 3) | ch];
3188 }
3189
3190 /*
3191  *  Stores the line number associated with a given controller (board), aiop
3192  *  and channel number.
3193  *  Returns:  The line number assigned
3194  */
3195 static unsigned char SetLineNumber(int ctrl, int aiop, int ch)
3196 {
3197         lineNumbers[(ctrl << 5) | (aiop << 3) | ch] = nextLineNumber++;
3198         return (nextLineNumber - 1);
3199 }