2 * Copyright (c) 1996-2004 Russell King.
4 * Please note that this platform does not support 32-bit IDE IO.
7 #include <linux/string.h>
8 #include <linux/module.h>
9 #include <linux/ioport.h>
10 #include <linux/slab.h>
11 #include <linux/blkdev.h>
12 #include <linux/errno.h>
13 #include <linux/ide.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/device.h>
16 #include <linux/init.h>
17 #include <linux/scatterlist.h>
21 #include <asm/ecard.h>
23 #define DRV_NAME "icside"
25 #define ICS_IDENT_OFFSET 0x2280
27 #define ICS_ARCIN_V5_INTRSTAT 0x0000
28 #define ICS_ARCIN_V5_INTROFFSET 0x0004
29 #define ICS_ARCIN_V5_IDEOFFSET 0x2800
30 #define ICS_ARCIN_V5_IDEALTOFFSET 0x2b80
31 #define ICS_ARCIN_V5_IDESTEPPING 6
33 #define ICS_ARCIN_V6_IDEOFFSET_1 0x2000
34 #define ICS_ARCIN_V6_INTROFFSET_1 0x2200
35 #define ICS_ARCIN_V6_INTRSTAT_1 0x2290
36 #define ICS_ARCIN_V6_IDEALTOFFSET_1 0x2380
37 #define ICS_ARCIN_V6_IDEOFFSET_2 0x3000
38 #define ICS_ARCIN_V6_INTROFFSET_2 0x3200
39 #define ICS_ARCIN_V6_INTRSTAT_2 0x3290
40 #define ICS_ARCIN_V6_IDEALTOFFSET_2 0x3380
41 #define ICS_ARCIN_V6_IDESTEPPING 6
44 unsigned int dataoffset
;
45 unsigned int ctrloffset
;
46 unsigned int stepping
;
49 static struct cardinfo icside_cardinfo_v5
= {
50 .dataoffset
= ICS_ARCIN_V5_IDEOFFSET
,
51 .ctrloffset
= ICS_ARCIN_V5_IDEALTOFFSET
,
52 .stepping
= ICS_ARCIN_V5_IDESTEPPING
,
55 static struct cardinfo icside_cardinfo_v6_1
= {
56 .dataoffset
= ICS_ARCIN_V6_IDEOFFSET_1
,
57 .ctrloffset
= ICS_ARCIN_V6_IDEALTOFFSET_1
,
58 .stepping
= ICS_ARCIN_V6_IDESTEPPING
,
61 static struct cardinfo icside_cardinfo_v6_2
= {
62 .dataoffset
= ICS_ARCIN_V6_IDEOFFSET_2
,
63 .ctrloffset
= ICS_ARCIN_V6_IDEALTOFFSET_2
,
64 .stepping
= ICS_ARCIN_V6_IDESTEPPING
,
70 void __iomem
*irq_port
;
71 void __iomem
*ioc_base
;
74 struct ide_host
*host
;
77 #define ICS_TYPE_A3IN 0
78 #define ICS_TYPE_A3USER 1
80 #define ICS_TYPE_V5 15
81 #define ICS_TYPE_NOTYPE ((unsigned int)-1)
83 /* ---------------- Version 5 PCB Support Functions --------------------- */
84 /* Prototype: icside_irqenable_arcin_v5 (struct expansion_card *ec, int irqnr)
85 * Purpose : enable interrupts from card
87 static void icside_irqenable_arcin_v5 (struct expansion_card
*ec
, int irqnr
)
89 struct icside_state
*state
= ec
->irq_data
;
91 writeb(0, state
->irq_port
+ ICS_ARCIN_V5_INTROFFSET
);
94 /* Prototype: icside_irqdisable_arcin_v5 (struct expansion_card *ec, int irqnr)
95 * Purpose : disable interrupts from card
97 static void icside_irqdisable_arcin_v5 (struct expansion_card
*ec
, int irqnr
)
99 struct icside_state
*state
= ec
->irq_data
;
101 readb(state
->irq_port
+ ICS_ARCIN_V5_INTROFFSET
);
104 static const expansioncard_ops_t icside_ops_arcin_v5
= {
105 .irqenable
= icside_irqenable_arcin_v5
,
106 .irqdisable
= icside_irqdisable_arcin_v5
,
110 /* ---------------- Version 6 PCB Support Functions --------------------- */
111 /* Prototype: icside_irqenable_arcin_v6 (struct expansion_card *ec, int irqnr)
112 * Purpose : enable interrupts from card
114 static void icside_irqenable_arcin_v6 (struct expansion_card
*ec
, int irqnr
)
116 struct icside_state
*state
= ec
->irq_data
;
117 void __iomem
*base
= state
->irq_port
;
121 switch (state
->channel
) {
123 writeb(0, base
+ ICS_ARCIN_V6_INTROFFSET_1
);
124 readb(base
+ ICS_ARCIN_V6_INTROFFSET_2
);
127 writeb(0, base
+ ICS_ARCIN_V6_INTROFFSET_2
);
128 readb(base
+ ICS_ARCIN_V6_INTROFFSET_1
);
133 /* Prototype: icside_irqdisable_arcin_v6 (struct expansion_card *ec, int irqnr)
134 * Purpose : disable interrupts from card
136 static void icside_irqdisable_arcin_v6 (struct expansion_card
*ec
, int irqnr
)
138 struct icside_state
*state
= ec
->irq_data
;
142 readb(state
->irq_port
+ ICS_ARCIN_V6_INTROFFSET_1
);
143 readb(state
->irq_port
+ ICS_ARCIN_V6_INTROFFSET_2
);
146 /* Prototype: icside_irqprobe(struct expansion_card *ec)
147 * Purpose : detect an active interrupt from card
149 static int icside_irqpending_arcin_v6(struct expansion_card
*ec
)
151 struct icside_state
*state
= ec
->irq_data
;
153 return readb(state
->irq_port
+ ICS_ARCIN_V6_INTRSTAT_1
) & 1 ||
154 readb(state
->irq_port
+ ICS_ARCIN_V6_INTRSTAT_2
) & 1;
157 static const expansioncard_ops_t icside_ops_arcin_v6
= {
158 .irqenable
= icside_irqenable_arcin_v6
,
159 .irqdisable
= icside_irqdisable_arcin_v6
,
160 .irqpending
= icside_irqpending_arcin_v6
,
164 * Handle routing of interrupts. This is called before
165 * we write the command to the drive.
167 static void icside_maskproc(ide_drive_t
*drive
, int mask
)
169 ide_hwif_t
*hwif
= drive
->hwif
;
170 struct expansion_card
*ec
= ECARD_DEV(hwif
->dev
);
171 struct icside_state
*state
= ecard_get_drvdata(ec
);
174 local_irq_save(flags
);
176 state
->channel
= hwif
->channel
;
178 if (state
->enabled
&& !mask
) {
179 switch (hwif
->channel
) {
181 writeb(0, state
->irq_port
+ ICS_ARCIN_V6_INTROFFSET_1
);
182 readb(state
->irq_port
+ ICS_ARCIN_V6_INTROFFSET_2
);
185 writeb(0, state
->irq_port
+ ICS_ARCIN_V6_INTROFFSET_2
);
186 readb(state
->irq_port
+ ICS_ARCIN_V6_INTROFFSET_1
);
190 readb(state
->irq_port
+ ICS_ARCIN_V6_INTROFFSET_2
);
191 readb(state
->irq_port
+ ICS_ARCIN_V6_INTROFFSET_1
);
194 local_irq_restore(flags
);
197 static const struct ide_port_ops icside_v6_no_dma_port_ops
= {
198 .maskproc
= icside_maskproc
,
201 #ifdef CONFIG_BLK_DEV_IDEDMA_ICS
205 * Similar to the BM-DMA, but we use the RiscPCs IOMD DMA controllers.
206 * There is only one DMA controller per card, which means that only
207 * one drive can be accessed at one time. NOTE! We do not enforce that
208 * here, but we rely on the main IDE driver spotting that both
209 * interfaces use the same IRQ, which should guarantee this.
213 * Configure the IOMD to give the appropriate timings for the transfer
214 * mode being requested. We take the advice of the ATA standards, and
215 * calculate the cycle time based on the transfer mode, and the EIDE
216 * MW DMA specs that the drive provides in the IDENTIFY command.
218 * We have the following IOMD DMA modes to choose from:
220 * Type Active Recovery Cycle
221 * A 250 (250) 312 (550) 562 (800)
223 * C 125 (125) 125 (375) 250 (500)
226 * (figures in brackets are actual measured timings)
228 * However, we also need to take care of the read/write active and
232 * Mode Active -- Recovery -- Cycle IOMD type
233 * MW0 215 50 215 480 A
237 static void icside_set_dma_mode(ide_drive_t
*drive
, const u8 xfer_mode
)
239 int cycle_time
, use_dma_info
= 0;
264 * If we're going to be doing MW_DMA_1 or MW_DMA_2, we should
265 * take care to note the values in the ID...
267 if (use_dma_info
&& drive
->id
[ATA_ID_EIDE_DMA_TIME
] > cycle_time
)
268 cycle_time
= drive
->id
[ATA_ID_EIDE_DMA_TIME
];
270 drive
->drive_data
= cycle_time
;
272 printk("%s: %s selected (peak %dMB/s)\n", drive
->name
,
273 ide_xfer_verbose(xfer_mode
), 2000 / drive
->drive_data
);
276 static const struct ide_port_ops icside_v6_port_ops
= {
277 .set_dma_mode
= icside_set_dma_mode
,
278 .maskproc
= icside_maskproc
,
281 static void icside_dma_host_set(ide_drive_t
*drive
, int on
)
285 static int icside_dma_end(ide_drive_t
*drive
)
287 ide_hwif_t
*hwif
= drive
->hwif
;
288 struct expansion_card
*ec
= ECARD_DEV(hwif
->dev
);
290 drive
->waiting_for_dma
= 0;
292 disable_dma(ec
->dma
);
294 /* Teardown mappings after DMA has completed. */
295 ide_destroy_dmatable(drive
);
297 return get_dma_residue(ec
->dma
) != 0;
300 static void icside_dma_start(ide_drive_t
*drive
)
302 ide_hwif_t
*hwif
= drive
->hwif
;
303 struct expansion_card
*ec
= ECARD_DEV(hwif
->dev
);
305 /* We can not enable DMA on both channels simultaneously. */
306 BUG_ON(dma_channel_active(ec
->dma
));
310 static int icside_dma_setup(ide_drive_t
*drive
, struct ide_cmd
*cmd
)
312 ide_hwif_t
*hwif
= drive
->hwif
;
313 struct expansion_card
*ec
= ECARD_DEV(hwif
->dev
);
314 struct icside_state
*state
= ecard_get_drvdata(ec
);
315 unsigned int dma_mode
;
317 if (cmd
->tf_flags
& IDE_TFLAG_WRITE
)
318 dma_mode
= DMA_MODE_WRITE
;
320 dma_mode
= DMA_MODE_READ
;
323 * We can not enable DMA on both channels.
325 BUG_ON(dma_channel_active(ec
->dma
));
328 * Ensure that we have the right interrupt routed.
330 icside_maskproc(drive
, 0);
333 * Route the DMA signals to the correct interface.
335 writeb(state
->sel
| hwif
->channel
, state
->ioc_base
);
338 * Select the correct timing for this drive.
340 set_dma_speed(ec
->dma
, drive
->drive_data
);
343 * Tell the DMA engine about the SG table and
346 set_dma_sg(ec
->dma
, hwif
->sg_table
, cmd
->sg_nents
);
347 set_dma_mode(ec
->dma
, dma_mode
);
349 drive
->waiting_for_dma
= 1;
354 static int icside_dma_test_irq(ide_drive_t
*drive
)
356 ide_hwif_t
*hwif
= drive
->hwif
;
357 struct expansion_card
*ec
= ECARD_DEV(hwif
->dev
);
358 struct icside_state
*state
= ecard_get_drvdata(ec
);
360 return readb(state
->irq_port
+
362 ICS_ARCIN_V6_INTRSTAT_2
:
363 ICS_ARCIN_V6_INTRSTAT_1
)) & 1;
366 static int icside_dma_init(ide_hwif_t
*hwif
, const struct ide_port_info
*d
)
368 hwif
->dmatable_cpu
= NULL
;
369 hwif
->dmatable_dma
= 0;
374 static const struct ide_dma_ops icside_v6_dma_ops
= {
375 .dma_host_set
= icside_dma_host_set
,
376 .dma_setup
= icside_dma_setup
,
377 .dma_start
= icside_dma_start
,
378 .dma_end
= icside_dma_end
,
379 .dma_test_irq
= icside_dma_test_irq
,
380 .dma_lost_irq
= ide_dma_lost_irq
,
383 #define icside_v6_dma_ops NULL
386 static int icside_dma_off_init(ide_hwif_t
*hwif
, const struct ide_port_info
*d
)
391 static void icside_setup_ports(hw_regs_t
*hw
, void __iomem
*base
,
392 struct cardinfo
*info
, struct expansion_card
*ec
)
394 unsigned long port
= (unsigned long)base
+ info
->dataoffset
;
396 hw
->io_ports
.data_addr
= port
;
397 hw
->io_ports
.error_addr
= port
+ (1 << info
->stepping
);
398 hw
->io_ports
.nsect_addr
= port
+ (2 << info
->stepping
);
399 hw
->io_ports
.lbal_addr
= port
+ (3 << info
->stepping
);
400 hw
->io_ports
.lbam_addr
= port
+ (4 << info
->stepping
);
401 hw
->io_ports
.lbah_addr
= port
+ (5 << info
->stepping
);
402 hw
->io_ports
.device_addr
= port
+ (6 << info
->stepping
);
403 hw
->io_ports
.status_addr
= port
+ (7 << info
->stepping
);
404 hw
->io_ports
.ctl_addr
= (unsigned long)base
+ info
->ctrloffset
;
408 hw
->chipset
= ide_acorn
;
411 static const struct ide_port_info icside_v5_port_info
= {
412 .host_flags
= IDE_HFLAG_NO_DMA
,
416 icside_register_v5(struct icside_state
*state
, struct expansion_card
*ec
)
419 struct ide_host
*host
;
420 hw_regs_t hw
, *hws
[] = { &hw
, NULL
, NULL
, NULL
};
423 base
= ecardm_iomap(ec
, ECARD_RES_MEMC
, 0, 0);
427 state
->irq_port
= base
;
429 ec
->irqaddr
= base
+ ICS_ARCIN_V5_INTRSTAT
;
432 ecard_setirq(ec
, &icside_ops_arcin_v5
, state
);
435 * Be on the safe side - disable interrupts
437 icside_irqdisable_arcin_v5(ec
, 0);
439 icside_setup_ports(&hw
, base
, &icside_cardinfo_v5
, ec
);
441 host
= ide_host_alloc(&icside_v5_port_info
, hws
);
447 ecard_set_drvdata(ec
, state
);
449 ret
= ide_host_register(host
, &icside_v5_port_info
, hws
);
456 ecard_set_drvdata(ec
, NULL
);
460 static const struct ide_port_info icside_v6_port_info __initdata
= {
461 .init_dma
= icside_dma_off_init
,
462 .port_ops
= &icside_v6_no_dma_port_ops
,
463 .dma_ops
= &icside_v6_dma_ops
,
464 .host_flags
= IDE_HFLAG_SERIALIZE
| IDE_HFLAG_MMIO
,
465 .mwdma_mask
= ATA_MWDMA2
,
466 .swdma_mask
= ATA_SWDMA2
,
470 icside_register_v6(struct icside_state
*state
, struct expansion_card
*ec
)
472 void __iomem
*ioc_base
, *easi_base
;
473 struct ide_host
*host
;
474 unsigned int sel
= 0;
476 hw_regs_t hw
[2], *hws
[] = { &hw
[0], NULL
, NULL
, NULL
};
477 struct ide_port_info d
= icside_v6_port_info
;
479 ioc_base
= ecardm_iomap(ec
, ECARD_RES_IOCFAST
, 0, 0);
485 easi_base
= ioc_base
;
487 if (ecard_resource_flags(ec
, ECARD_RES_EASI
)) {
488 easi_base
= ecardm_iomap(ec
, ECARD_RES_EASI
, 0, 0);
495 * Enable access to the EASI region.
500 writeb(sel
, ioc_base
);
502 ecard_setirq(ec
, &icside_ops_arcin_v6
, state
);
504 state
->irq_port
= easi_base
;
505 state
->ioc_base
= ioc_base
;
509 * Be on the safe side - disable interrupts
511 icside_irqdisable_arcin_v6(ec
, 0);
513 icside_setup_ports(&hw
[0], easi_base
, &icside_cardinfo_v6_1
, ec
);
514 icside_setup_ports(&hw
[1], easi_base
, &icside_cardinfo_v6_2
, ec
);
516 host
= ide_host_alloc(&d
, hws
);
522 ecard_set_drvdata(ec
, state
);
524 if (ec
->dma
!= NO_DMA
&& !request_dma(ec
->dma
, DRV_NAME
)) {
525 d
.init_dma
= icside_dma_init
;
526 d
.port_ops
= &icside_v6_port_ops
;
530 ret
= ide_host_register(host
, &d
, hws
);
539 ecard_set_drvdata(ec
, NULL
);
545 icside_probe(struct expansion_card
*ec
, const struct ecard_id
*id
)
547 struct icside_state
*state
;
551 ret
= ecard_request_resources(ec
);
555 state
= kzalloc(sizeof(struct icside_state
), GFP_KERNEL
);
561 state
->type
= ICS_TYPE_NOTYPE
;
563 idmem
= ecardm_iomap(ec
, ECARD_RES_IOCFAST
, 0, 0);
567 type
= readb(idmem
+ ICS_IDENT_OFFSET
) & 1;
568 type
|= (readb(idmem
+ ICS_IDENT_OFFSET
+ 4) & 1) << 1;
569 type
|= (readb(idmem
+ ICS_IDENT_OFFSET
+ 8) & 1) << 2;
570 type
|= (readb(idmem
+ ICS_IDENT_OFFSET
+ 12) & 1) << 3;
571 ecardm_iounmap(ec
, idmem
);
576 switch (state
->type
) {
578 dev_warn(&ec
->dev
, "A3IN unsupported\n");
582 case ICS_TYPE_A3USER
:
583 dev_warn(&ec
->dev
, "A3USER unsupported\n");
588 ret
= icside_register_v5(state
, ec
);
592 ret
= icside_register_v6(state
, ec
);
596 dev_warn(&ec
->dev
, "unknown interface type\n");
606 ecard_release_resources(ec
);
611 static void __devexit
icside_remove(struct expansion_card
*ec
)
613 struct icside_state
*state
= ecard_get_drvdata(ec
);
615 switch (state
->type
) {
617 /* FIXME: tell IDE to stop using the interface */
619 /* Disable interrupts */
620 icside_irqdisable_arcin_v5(ec
, 0);
624 /* FIXME: tell IDE to stop using the interface */
625 if (ec
->dma
!= NO_DMA
)
628 /* Disable interrupts */
629 icside_irqdisable_arcin_v6(ec
, 0);
631 /* Reset the ROM pointer/EASI selection */
632 writeb(0, state
->ioc_base
);
636 ecard_set_drvdata(ec
, NULL
);
639 ecard_release_resources(ec
);
642 static void icside_shutdown(struct expansion_card
*ec
)
644 struct icside_state
*state
= ecard_get_drvdata(ec
);
648 * Disable interrupts from this card. We need to do
649 * this before disabling EASI since we may be accessing
650 * this register via that region.
652 local_irq_save(flags
);
653 ec
->ops
->irqdisable(ec
, 0);
654 local_irq_restore(flags
);
657 * Reset the ROM pointer so that we can read the ROM
658 * after a soft reboot. This also disables access to
659 * the IDE taskfile via the EASI region.
662 writeb(0, state
->ioc_base
);
665 static const struct ecard_id icside_ids
[] = {
666 { MANU_ICS
, PROD_ICS_IDE
},
667 { MANU_ICS2
, PROD_ICS2_IDE
},
671 static struct ecard_driver icside_driver
= {
672 .probe
= icside_probe
,
673 .remove
= __devexit_p(icside_remove
),
674 .shutdown
= icside_shutdown
,
675 .id_table
= icside_ids
,
681 static int __init
icside_init(void)
683 return ecard_register_driver(&icside_driver
);
686 static void __exit
icside_exit(void)
688 ecard_remove_driver(&icside_driver
);
691 MODULE_AUTHOR("Russell King <rmk@arm.linux.org.uk>");
692 MODULE_LICENSE("GPL");
693 MODULE_DESCRIPTION("ICS IDE driver");
695 module_init(icside_init
);
696 module_exit(icside_exit
);